JP4797831B2 - Signal processing apparatus and signal processing method - Google Patents

Description

  The present invention relates to a signal processing device and a signal processing method, and more particularly to a signal processing device and a signal processing method for an analog signal for detecting a circuit fault and removing noise.

  In the field of process control including a plant, it is configured to monitor and control states of various devices included in the plant based on an input signal input from the plant side. In such a situation, for example, when an input signal from the plant does not show an accurate value due to an abnormality in a circuit (signal input unit) related to signal output, the plant can be operated normally. There is also a risk that the operation must be stopped. Therefore, conventionally, a signal processing apparatus for detecting an abnormality of a circuit related to signal output has been proposed. Hereinafter, a conventional signal processing apparatus will be described with reference to FIG.

  FIG. 10 is a block diagram showing an example of the conventional signal processing apparatus 200 described above. As shown in FIG. 10, the signal processing device 200 includes a signal source 11, signal input units 12 and 13, a multiplexer 14, an A / D converter 15, a multiplexer 16, a timing controller 17, buffer devices 18 and 19, and a comparator 20. And an alarm device 21.

  Here, the signal input unit 12 and the signal input unit 13 are resistors or the like, for example, and output an output signal obtained by performing predetermined processing on the analog signal input from the signal source 11 to the multiplexer 14. The multiplexer 14 selectively acquires one of the two output signals output from the signal input units 12 and 13 and outputs it to the A / D converter 15 as one output signal. The A / D converter 15 converts the output signal from the multiplexer 14 into a digital signal, and then outputs the digital signal to the multiplexer 16 as sampling data.

  The multiplexer 16 selectively switches to one of the two buffer devices 18 and 19 serving as the output destination of the sampling data, and outputs it. The buffer device to which the sampling data has been input temporarily holds this sampling data. The comparator 20 compares the sampling data held in the buffer devices 18 and 19, and if the comparison result does not match or the difference between the two sampling data exceeds a predetermined threshold value, the alarm device outputs a signal input unit. A notification signal for notifying the abnormality is output to the external device. Here, the timing controller 17 controls the switching operation of the multiplexers 14 and 16 and the operation of the A / D converter 15 based on the reference clock signal output from the clock signal generating means (not shown). With such a configuration, it is possible to detect a failure of the signal input unit 12 or 13. In the above configuration, since one A / D converter 15 is provided, output signals from the signal input unit 12 or 13 cannot be processed at the same time, and are processed one by one.

  Hereinafter, the operation of the signal processing apparatus 200 will be described with reference to FIG. Note that the output signal acquired from the signal input unit 12 is referred to as MAIN, and the output signal acquired from the signal input unit 13 is referred to as SUB. The multiplexer 14 controls MAIN (signal input unit 12), according to the switching timing control by the timing controller 17. It shall be acquired in the order of SUB (signal input unit 13).

FIG. 11A is a diagram illustrating a case where the analog signal input from the signal source 11 linearly changes (increases) with time. At this time, if MAIN and SUB are acquired at timings t1 and t2, respectively, a difference of “D1” occurs between the values of MAIN (data 1) and SUB (data 2) as shown in the following equation.
| MAIN-SUB | = | data 1-data 2 |
= | Data 1- (Data 1 + D1) |
= D1

Further, when the analog signal input from the signal source 11 makes a step response, as shown in FIG. 11B, it may change in a curve with time. At this time, if MAIN and SUB are acquired at timings t1 and t2, respectively, a difference of “D1” occurs between the values of MAIN (data 1) and SUB (data 2) as shown in the following equation.
| MAIN-SUB | = | data 1-data 2 |
= | Data 1- (Data 1 + D1) |
= D1

  In addition, a disturbance signal (noise) such as noise from an inverter or an AC power supply or HART (Highway Addressable Remote Transducer) may be superimposed on the analog signal from the signal source 11. In this case, as shown in FIG. 12, since the frequency component corresponding to the disturbance signal is superimposed on the analog signal, the frequency component is added as an error depending on the acquisition timing. Here, a pure analog signal A1 on which no disturbance signal is superimposed is indicated by a broken line, and an analog signal A2 on which a disturbance signal is superimposed is indicated by a solid line.

  In FIG. 12, assuming that MAIN and SUB are acquired at timings t1 and t2, respectively, MAIN (data 1) = analog signal A1-D1, SUB (data 2) = analog signal A1 + D1, and an error due to the frequency component of the disturbance signal. When viewed from the analog signal A1, the maximum ± D1 is an error. Such an error may cause a false detection for detecting the signal input units 12 and 13 in a normal state as abnormal, and thus there is a problem that the accuracy of failure determination is lowered.

Conventionally, the frequency component due to the disturbance signal is removed by the sampling data whose combination is opposite in phase, and the main data (MAIN) clock is derived from the series of sampling data strings output from the A / D converter. A technique for determining whether or not there is an abnormality in sampling data by selecting a plurality of sampling data having a certain number of shifts as sub-data (SUB) data and comparing the average of these main data and sub-data. It has been proposed (see, for example, Patent Document 1).
Japanese Patent Laid-Open No. 2003-234639

However, in the technique of Patent Document 1, only the configuration subsequent to the A / D converter 15 shown in FIG. 10 is mentioned, and an analog signal is output before the A / D converter 15 as described above. In the configuration including the two signal input units (signal input units 12 and 13), it cannot be applied immediately.
In addition, when one A / D converter is used, the minimum time of the data acquisition interval is naturally limited, and on the other hand, the number of data that can be acquired within a certain time is limited. There are some restrictions.
Further, as shown in FIGS. 11A and 11B, since the analog signal input from the signal source 11 cannot be applied when it changes with time, the accuracy of failure determination is improved. There is a problem of lowering.

  An object of the present invention is to provide a signal processing device and a signal processing method capable of accurately acquiring an analog signal input from a signal source and improving the accuracy of circuit failure determination related to the output of the analog signal. It is to be.

In order to solve the above-mentioned problem, the invention described in claim 1
A plurality of signal input units to which analog signals output from one signal source are respectively input;
A first multiplexer that selectively switches and outputs any one of a plurality of output signals respectively output from the plurality of signal input units;
An A / D converter that converts an output signal output from the first multiplexer into a digital signal and outputs the signal as sampling data;
A second multiplexer for selectively switching and outputting the sampling data to any one of the same number of output terminals as the signal input unit to which the sampling data is output;
A plurality of buffer devices connected to each of the plurality of output terminals and respectively holding sampling data output from the second multiplexer;
A plurality of adders for respectively calculating a sum or average of a plurality of sampling data respectively held in the plurality of buffer devices;
A comparator for comparing the calculated values;
The switching operation of the first multiplexer is controlled a plurality of times so that the time-series switching order of the output signals is symmetric between the first half and the second half of the order, and according to the switching operation of the first multiplexer. A timing controller for controlling the switching operation of the second multiplexer;
It is characterized by having.

Furthermore, the invention according to claim 2 is the invention according to claim 1,
The timing controller controls the switching operation of the first multiplexer so that the switching timing of the first multiplexer is symmetric between the first half and the second half of the switching order.

Furthermore, the invention according to claim 3 is the invention according to claim 1 or 2,
The timing controller controls the switching operation of the first multiplexer a plurality of times within a time interval corresponding to a half cycle of the frequency component of the analog signal or at every time interval.

Furthermore, the invention according to claim 4 is the invention according to any one of claims 1 to 3,
Further comprising a notification means,
The comparator is characterized in that the informing means is informed based on a comparison result by the comparator.

Moreover, in order to solve the said subject, invention of Claim 5 is the following.
An input step of inputting an analog signal output from one signal source to each of a plurality of signal input units;
A first switching step of selectively switching and outputting any one of a plurality of output signals respectively output from the plurality of signal input units;
An A / D conversion step of converting the output signal output in the first switching step into a digital signal and outputting it as sampling data;
A second switching step of selectively switching and outputting the sampling data to any one of the same number of output terminals as the signal input unit to which the sampling data is output;
A holding step of holding the plurality of output sampling data in a plurality of buffer devices respectively connected to the plurality of output ends;
A calculation step of calculating a total or average of a plurality of sampling data respectively held in the plurality of buffer devices;
A comparison step of comparing the calculated values;
The switching operation of the first switching step is controlled a plurality of times so that the time-series switching order of the output signals is symmetric between the first half and the second half of the order, and the switching operation of the first switching step is also performed. In response, a timing control step for controlling the switching operation of the second switching step;
It is characterized by including.

Furthermore, the invention according to claim 6 is the invention according to claim 5,
The timing control step is characterized in that the switching operation of the first switching step is controlled so that the switching timing of the first switching step is symmetric between the first half and the second half of the switching order.

Furthermore, the invention according to claim 7 is the invention according to claim 5 or 6,
The timing control step is characterized in that the switching operation of the first switching step is controlled a plurality of times within a time interval corresponding to a half cycle of the frequency component of the analog signal or every time interval.

Furthermore, the invention according to claim 8 is the invention according to any one of claims 5 to 7,
Further comprising a notification step,
The comparison step is characterized in that the notification step is notified based on the comparison result of the comparison step.

  According to the present invention, the switching operation of the first multiplexer (first switching step) is controlled so that the first half portion and the second half portion of the time-series switching order of the output signal are symmetrical, and the switching operation of the first multiplexer is performed. Accordingly, the switching operation of the second multiplexer (second switching step) is controlled. Thereby, since it is possible to suppress the influence of the frequency component superimposed on the analog signal and the influence due to the change with the passage of time, the sampling data can be obtained with high accuracy. Further, since the values of sampling data in which the influence of frequency components and the influence of changes with time are suppressed are compared, it is possible to improve the accuracy of the failure determination of the signal input unit related to the output of the analog signal.

  Further, according to the present invention, since it is possible to perform notification based on the determination result of the comparator, it is possible to notify the outside when determining the failure of the signal input unit.

  The best mode for carrying out the present invention will be described below in detail with reference to the drawings. However, the scope of the invention is not limited to the illustrated examples.

<First Embodiment>
FIG. 1 is a functional block diagram showing an embodiment of a signal processing apparatus 100 to which the present invention is applied. In addition, the same code | symbol is attached | subjected about the element which is common in the structure of FIG. 10 mentioned above, and the detailed description is abbreviate | omitted suitably. Hereinafter, the configuration of the signal processing apparatus 100 will be described.

  As shown in FIG. 1, the signal processing device 100 includes a signal source 11, a signal input unit 12 and a signal input unit 13, a multiplexer 14, an A / D converter 15, a multiplexer 16, a timing controller 17, buffer devices 18 and 19, and an addition. A device 22, an adder 23, a comparator 20, and an alarm device 21 are provided.

  In the configuration of FIG. 1, the timing controller 17 controls the switching of the multiplexer 14 a plurality of times for each half cycle of the frequency component included in the analog signal output from the signal source 11. Here, the switching frequency of the multiplexer 14 is not particularly limited, but is preferably an integer multiple of the number of signal input units. In addition, although the frequency component superimposed on the analog signal is assumed to be measured in advance, the present invention is not limited thereto, and includes a detection device (not shown) that can detect the frequency component superimposed on the analog signal from the signal source 11, It is good also as an aspect controlled based on the frequency component detected by this detection apparatus.

  The timing controller 17 controls the operations of the A / D converter 15 and the multiplexer 16 according to the switching timing of the multiplexer 14. In particular, the switching of the multiplexer 16 is controlled so that the sample data output from the A / D converter 15 is alternately held in the buffer devices 18 and 19 every even number of times of switching of the multiplexer 14. It is assumed that the buffer devices 18 and 19 have a storage capacity capable of holding the number of data input from the multiplexer 16.

  The adders 22 and 23 calculate the sum or average of a plurality of sampling data held in the buffer device 18 and the buffer device 19, respectively, and output the calculated value (data) to the comparator 20.

  The comparator 20 compares the data input from the adders 22 and 23. When the values of both data do not match or when the difference between the two data exceeds a predetermined threshold, the signal input unit 12 or the signal input It is determined that a failure has occurred in the unit 13, and the alarm device 21 notifies the alarm device 21 by outputting a notification signal to the alarm device 21 serving as a notification means. Here, the threshold value serving as an index for determining the occurrence of a failure can be set to an arbitrary value, but is preferably determined based on the output signals output from the signal input unit 12 and the signal input unit 13 during normal operation. . In this embodiment, the signal input unit 12 and the signal input unit 13 are the same. However, the present invention is not limited to this, and signal input units having different functions and configurations may be used.

Hereinafter, the operation of the signal processing apparatus 100 of the present embodiment will be described with reference to FIG.
FIG. 2 is a diagram illustrating a state of a signal in which a predetermined frequency component is superimposed on the analog signal input from the signal source 11 as a disturbance signal. In FIG. 2, an analog signal A1 indicated by a broken line indicates a pure analog signal on which a disturbance signal is not superimposed, and an analog signal A2 indicated by a solid line indicates an analog signal on which a disturbance signal is superimposed. ing.

  First, the timing controller 17 controls the switching of the multiplexer 14 every time interval T corresponding to a half cycle of the frequency component of the analog signal A2, and the time t1 and the time t2 to t4 when the time interval T sequentially passes from the time t1. And the multiplexer 14 is switched four times. The analog signal acquired here passes through the A / D converter 15 and the multiplexer 16, and data 1 and 2 (MAIN) and data 3 and 4 (SUB) are held in the buffer devices 18 and 19 as sample data, respectively. Will be.

The average values calculated by the adders 22 and 23 from the MAIN and SUB held in the buffer devices 18 and 19 are the same as the analog signal A1 from which the frequency components have been removed as shown in the following equation. Although the calculation formula for MAIN (data 1 and 2) is shown here, the same applies to SUB (data 3 and 4). D1 is a difference value between the analog signal A1 and the analog signal A2 at each time (t1, t2).
Sample data = (Data 1 + Data 2) / 2
= ((Analog signal A1 + D1) + (analog signal A1-D1)) / 2
= Analog signal A1

  In the subsequent comparator 20, the calculated values calculated by the adders 22 and 23 are compared, and when a difference greater than a predetermined value is detected, the alarm device 21 is controlled to output the analog signal A 1. The signal input unit 12 and the signal input unit 13 according to the above are notified to the outside that an abnormality has occurred.

  As described above, according to the signal processing device 100 of the present embodiment, even when the frequency component is superimposed on the analog signal from the signal source 11, sampling is performed at time intervals corresponding to half cycles of the frequency component. By acquiring a plurality of data and calculating the average of the values, the superimposed frequency components can be removed, so that the sampling data can be acquired with high accuracy. Further, by comparing the values of the sampling data from which the frequency component has been removed, it is possible to improve the accuracy of failure determination of the signal input unit 12 and the signal input unit 13 related to the output of the analog signal.

<Second Embodiment>
Next, a second embodiment of the signal processing apparatus 100 described above will be described. In addition, the same code | symbol is attached | subjected to the component similar to above-mentioned Embodiment 1, and description is abbreviate | omitted.

First, the operation of the timing controller 17 of this embodiment will be described.
The timing controller 17 controls the switching operation of the multiplexer 14 so that the time-series switching order of the output signals output from the signal input units 12 and 13 is symmetric between the first half and the second half of the order, By controlling the switching operation of the multiplexer 16 in accordance with the switching operation of the multiplexer 14, the sampling data that is symmetrical in the first half part and the second half part of the switching order is controlled to be held in the same buffer device.

  Here, “symmetric between the first half and the second half of the switching order” means that the switching order of the second half is reverse to the order of the first half. For example, the multiplexer 14 includes the signal input unit 12 and the signal input. If the output signal of the first half is acquired from each signal input unit in the order of the unit 12, the signal input unit 13, and the signal input unit 13, the second half is the signal input unit 13, the signal input unit 13, the signal input unit 12, This means that the acquisition of the output signal is controlled so as to become the input unit 12. In the present embodiment, when the frequency component is superimposed on the analog signal, the multiplexer 14 is switched a plurality of times at the same time interval TA within the time interval T corresponding to a half cycle of the frequency component. And

Hereinafter, the operation of the signal processing apparatus 100 of the present embodiment will be described.
FIG. 3 is a diagram showing a state of a signal in which a predetermined frequency component is superimposed on the analog signal input from the signal source 11 as a disturbance signal. In FIG. 3, an analog signal A1 indicated by a broken line indicates a pure analog signal on which a disturbance signal is not superimposed, and an analog signal A2 indicated by a solid line indicates an analog signal on which a disturbance signal is superimposed. ing.

  First, the multiplexer 14 is controlled by the timing controller 17 so that the switching order is symmetrical between the first half and the second half, and after passing through the A / D converter 15 and the multiplexer 16, the sample data is sent to the buffer devices 18 and 19 respectively. Will be retained.

  Here, it is assumed that the multiplexer 14 is switched to become the signal input unit 12, the signal input unit 13, the signal input unit 13, and the signal input unit 12 by the timing controller 17, and acquired based on the output signal from the signal input unit 12. If the sample data to be acquired is MAIN and the sample data acquired based on the output signal from the signal input unit 13 is SUB, MAIN1 (data 1) and MAIN2 (data 4) are held in one of the buffer devices 18 and 19. Thus, SUB1 (data 2) and SUB2 (data 3) are held in the other buffer device.

  When the multiplexer 14 is switched at the timing (t1 to t4) shown in FIG. 3, the adders 22 and 23 respectively calculate from the MAIN 1 and 2 and SUB 1 and 2 held in the buffer devices 18 and 19, respectively. The average value (MAIN average value or SUB average value) is the same value as the analog signal A1 from which the frequency component has been removed, as in the first embodiment.

In this case, the calculated values (MAIN average value and SUB average value) from the adders 22 and 23 compared by the comparator 20 match when the signal input units 12 and 13 are normal, as shown in the following equation. Based on this calculated value, it can be determined whether or not an abnormality has occurred in the signal input unit 12 and the signal input unit 13 related to the output of the analog signal A1.
｜ MAIN average value−SUB average value | = 0

Even when the above switching control is performed, the switching timing of the multiplexer 14 and the frequency component of the analog signal A2 are asynchronous, and therefore the frequency component cannot be removed from the analog signal A2 depending on the switching timing. There is. FIG. 4 shows such a case, and shows a case where the difference between the MAIN average value and the SUB average value is maximized. When the multiplexer 14 is switched at the timing (t1 to t4) shown in FIG. 4, the MAIN average value and the SUB average value calculated by the adders 22 and 23 are as shown in the following equations.
MAIN average value = analog signal A1
SUB average value = (data 2 + data 3) / 2 = analog signal A1 ± D1

Therefore, when the signal input units 12 and 13 are normal, the difference between the MAIN average value and the SUB average value compared by the comparator 20 is “± D1” as shown in the following equation.
MAIN average value−SUB average value | = ± D1

In the above-described conventional signal processing apparatus 200 of FIG. 10, only one sampling data corresponding to MAIN and SUB is acquired, so that the values of MAIN and SUB are calculated as follows.
MAIN = Analog signal A1 ± D1
SUB = Analog signal A1 ± D1

Therefore, in the operation of the conventional signal processing apparatus 200 (see FIG. 10), the maximum value of the difference between MAIN and SUB is twice the value of the present embodiment as shown in the following equation. The result is less accurate than the processing apparatus 100.
｜ MAIN-SUB | = ± D1 × 2

  As described above, according to the signal processing device 100 of the present embodiment, even when the frequency component is superimposed on the analog signal from the signal source 11, the first half and the second half of the time-series switching order of the output signal. The switching control of the multiplexer 14 is controlled so as to be symmetrical with respect to the portion, and the switching operation of the multiplexer 16 is controlled according to the switching operation of the multiplexer 14. Thereby, since it is possible to suppress the influence of the frequency component superimposed on the analog signal, the sampling data can be obtained with high accuracy. In addition, since the values of the sampling data in which the influence of the frequency component is suppressed are compared, it is possible to improve the accuracy of failure determination of the signal input unit 12 and the signal input unit 13 related to the output of the analog signal.

  The signal processing apparatus 100 according to the present embodiment is not only applicable to the analog signal on which the predetermined frequency component shown in FIGS. 3 and 4 is superimposed, but also an analog signal that changes linearly with time. The present invention can be effectively applied to an analog signal that changes in a curve with time. The operation when applied to an analog signal that changes linearly or curvedly over time will be described below with reference to FIGS.

  FIG. 5 is a diagram illustrating a case where the analog signal input from the signal source 11 changes (increases) linearly with time. Here, it is assumed that the multiplexer 14 is switched to become the signal input unit 12, the signal input unit 13, the signal input unit 13, and the signal input unit 12 by the timing controller 17, and acquired based on the output signal from the signal input unit 12. If the sample data to be acquired is MAIN and the sample data acquired based on the output signal from the signal input unit 13 is SUB, MAIN1 (data 1) and MAIN2 (data 4) are held in one of the buffer devices 18 and 19. Thus, SUB1 (data 2) and SUB2 (data 3) are held in the other buffer device.

In this case, the MAIN average value and the SUB average value calculated by the adders 22 and 23 are as shown in the following equations.
MAIN average value = (data 1 + data 4) / 2
= (Data 1+ (Data 1 + D1 + D2 + D3)) / 2
= Data 1+ (D1 + D2 + D3) / 2
SUB average value = (data 2 + data 3) / 2
= ((Data 1 + D1) + (Data 1 + D1 + D2)) / 2
Data 1+ (D1 + D1 + D2) / 2

  When the analog signal from the signal source 11 changes linearly with the passage of time, the change rates D1, D2, and D3 are D1 = D2 = D3. Therefore, when the signal input units 12 and 13 are normal, the difference between the MAIN average value compared with the comparator 20 and the SUB average value is “0”.

  Thus, even if the analog signal input from the signal source 11 changes linearly with the passage of time, it is possible to acquire sampling data from which the amount of change with the passage of time has been removed. Therefore, sampling data can be obtained with high accuracy. Further, since the values of the sampling data from which the amount of change with the passage of time is removed are compared, it is possible to improve the accuracy of the failure determination of the signal input unit 12 and the signal input unit 13 related to the analog signal output.

  FIG. 6 is a diagram illustrating a case where the analog signal input from the signal source 11 changes (increases) in a curved manner as time elapses. Here, it is assumed that the multiplexer 14 is switched to become the signal input unit 12, the signal input unit 13, the signal input unit 13, and the signal input unit 12 by the timing controller 17, and acquired based on the output signal from the signal input unit 12. If the sample data to be acquired is MAIN and the sample data acquired based on the output signal from the signal input unit 13 is SUB, MAIN1 (data 1) and MAIN2 (data 4) are held in one of the buffer devices 18 and 19. Thus, SUB1 (data 2) and SUB2 (data 3) are held in the other buffer device.

In this case, the MAIN average value and the SUB average value calculated by the adders 22 and 23 are as shown in the following equations.
MAIN average value = (data 1 + data 4) / 2
= (Data 1+ (Data 1 + D1 + D2 + D3)) / 2
= Data 1+ (D1 + D2 + D3) / 2
SUB average value = (data 2 + data 3) / 2
= ((Data 1 + D1) + (Data 1 + D1 + D2)) / 2
= Data 1+ (D1 + D1 + D2) / 2

When the signal input units 12 and 13 are normal, the difference between the MAIN average value and the SUB average value compared by the comparator 20 is “| (D1−D3) / 2 |” as shown in the following equation.
| MAIN average value−SUB average value | = | (data 1+ (D1 + D2 + D3) / 2)
− (Data 1+ (D1 + D1 + D2) / 2) |
= | (D1-D3) / 2 |

  Here, when the time for acquiring the data 1 to 4, that is, the switching timing of the multiplexer 14 is sufficiently shorter than the time for changing the analog signal, the change rate of the analog signal shown in FIG. Since it can be approximated to the linear change rate as shown, the change rates D1, D2, and D3 can be considered as D1≈D2≈D3. In this case, when the signal input units 12 and 13 are normal, the difference between the MAIN average value compared with the comparator 20 and the SUB average value is “0”.

  Thus, even if the analog signal input from the signal source 11 changes in a curve with the passage of time, it is possible to acquire sampling data from which the amount of change with the passage of time has been removed. Therefore, sampling data can be obtained with high accuracy. Further, since the values of the sampling data from which the amount of change with the passage of time is removed are compared, it is possible to improve the accuracy of failure determination of the signal input unit 12 and the signal input unit 13 related to the output of the analog signal.

  In this embodiment, the signal input units 12 and 13 are switched in the order of the signal input unit 12, the signal input unit 13, the signal input unit 13, and the signal input unit 12. For example, the signal input unit 12, the signal input unit 12, the signal input unit 13, the signal input unit 13, the signal input unit 13, the signal input unit 13, the signal input unit 12, and the signal input unit 12 are switched in this order. The signal input unit 12, the signal input unit 12, the signal input unit 13, the signal input unit 13, the signal input unit 12, the order of the signal input unit 12, the signal input unit 12, the signal input unit 13, and the signal input It is good also as an aspect switched in the order of the part 12. FIG.

  In this embodiment, the multiplexer 14 is switched at a constant time interval. However, the present invention is not limited to this, and the time interval of the switching time is switched to be symmetric between the first half and the second half of the switching order. In some cases, the same effect as described above can be obtained. For example, when the signal input unit 12, the signal input unit 13, the signal input unit 13, and the signal input unit 12 are switched in this order, the time interval from the signal input unit 12 to the signal input unit 13 in the first half and the signal in the second half If the time interval from the input unit 13 to the signal input unit 12 is equal, the time interval from the signal input unit 13 to the signal input unit 13 in the middle part is not limited.

The operation of the signal processing apparatus 100 under the above conditions will be described with reference to FIGS.
FIG. 7 is a diagram illustrating a case where the analog signal input from the signal source 11 changes (increases) linearly with time.

  Here, it is assumed that the multiplexer 14 is switched to become the signal input unit 12, the signal input unit 13, the signal input unit 13, and the signal input unit 12 by the timing controller 17, and acquired based on the output signal from the signal input unit 12. If the sample data to be acquired is MAIN and the sample data acquired based on the output signal from the signal input unit 13 is SUB, MAIN1 (data 1) and MAIN2 (data 4) are held in one of the buffer devices 18 and 19. Thus, SUB1 (data 2) and SUB2 (data 3) are held in the other buffer device. Here, it is assumed that the switching timing of the multiplexer 14 related to the acquisition of the data 1 to 4 is controlled by the timing controller 17 so as to be symmetrical between the first half and the second half of the switching order, and t1 to t2 and t3. It is assumed that the time interval of t4 is TA, and the time interval of t2 to t3 is TB (TA ≠ TB).

In this case, the rate of change at t1 to t2 and t3 to t4 are equal, and the increment values D1 and D3 are equal. Therefore, the values of the MAIN average value and the SUB average value calculated by the adders 22 and 23 are as follows: It becomes as shown in.
MAIN average value = (data 1 + data 4) / 2
= (Data 1+ (Data 1 + D1 + D2 + D3)) / 2
= Data 1 + D1 + D2 / 2
SUB average value = (data 2 + data 3) / 2
= ((Data 1 + D1) + (Data 1 + D1 + D2)) / 2
= Data 1 + D1 + D2 / 2

  Therefore, when the signal input units 12 and 13 are normal, the difference between the MAIN average value and the SUB average value compared by the comparator 20 is “0” as shown in the following equation.

  Further, as shown in FIG. 8, even when the analog signal A2 in which a predetermined frequency component is superimposed on the analog signal A1 is input, the switching timing of the multiplexer 14 is t1 to t2 and t3 to t4. As described above, when the signal input units 12 and 13 are normal, the difference between the MAIN average value and the SUB average value compared by the comparator 20 is set to −D1 ≦ 0. ≦ D1.

  Thus, since the MAIN average value = SUB average value, the sampling data can be obtained with high accuracy as in the effect of the present embodiment.

  In the present embodiment, the signal processing apparatus 100 including two signal input units is illustrated, but the number of signal input units is not limited to this, and the number is not limited as long as it is plural. In this case, the same number of buffer devices and comparators as the signal input units are provided, and the switching operation of the second switching step is controlled according to the switching operation of the first multiplexer, so that the first half of the switching order It is assumed that sampling data having a symmetrical relationship with the latter half is controlled so as to be held in the same buffer device.

  Further, in this embodiment, when a frequency component is superimposed on an analog signal, a plurality of sampling data can be obtained by controlling the switching operation of the first multiplexer a plurality of times within a time interval corresponding to a half cycle of the frequency component. However, the present invention is not limited to this. For example, as illustrated in FIG. 2, the sampling data may be acquired every time interval corresponding to a half cycle of the frequency component.

  The detailed configuration and detailed operation of the signal processing apparatus 100 in the above embodiment can be appropriately changed without departing from the spirit of the present invention.

  For example, in the above-described embodiment, the adders 22 and 23 calculate the average of a plurality of sampling data held in the buffer devices 18 and 19, respectively. It is good also as a mode which calculates each.

  In the above embodiment, the multiplexer 16, the timing controller 17, the buffer devices 18 and 19, the adders 22 and 23, and the comparator 20 are individually provided. May be realized by a processor including a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), and the like.

  FIG. 9 is a diagram illustrating a configuration example of the signal processing device 100 including the processor 30. Here, it is assumed that the multiplexer 14a and the multiplexer 14b are provided with a plurality of input channels (1ch, 2ch... Nch), and the same configuration as B in the figure is connected to each input channel. The multiplexers 14a and 14b selectively switch each input channel under the control of the processor 30, and obtain output signals from the resistors 121 and 131 as signal input units input via these input channels, respectively. After that, the data is output to the multiplexer 14c.

  The multiplexer 14 c selectively outputs the output signals from the multiplexers 14 a and 14 b under the control of the processor 30, and then outputs the signals to the A / D converter 15.

  The A / D converter 15 converts the output signal from the multiplexer 14c into a digital signal, and then outputs it to the processor 30 as sampling data.

  The processor 30 realizes the functions of the multiplexer 16, the timing controller 17, the buffer devices 18 and 19, the adders 22 and 23, and the comparator 20 in cooperation with a predetermined program stored in a ROM (not shown). . It is assumed that the functions as the buffer devices 18 and 19 are realized using a RAM storage area (not shown).

  When acquiring a plurality of sampling data from the A / D converter 15, the processor 30 calculates the average of the sampling data for each system of the multiplexer 14a and the multiplexer 14b, and compares these calculated values. When the calculated values do not match or when the difference between the calculated values exceeds a predetermined threshold value, the alarm device 21 is controlled and notified. With this configuration, it is possible to achieve the same effects as in the above embodiment.

It is a functional block diagram which shows one Embodiment of the signal processing apparatus to which this invention is applied. It is a figure for demonstrating operation | movement of the information processing apparatus in 1st Embodiment. It is a figure for demonstrating operation | movement of the information processing apparatus in 2nd Embodiment. It is a figure for demonstrating operation | movement of the information processing apparatus in 2nd Embodiment. It is a figure for demonstrating operation | movement of the information processing apparatus in 2nd Embodiment. It is a figure for demonstrating operation | movement of the information processing apparatus in 2nd Embodiment. It is a figure for demonstrating operation | movement of the information processing apparatus in 2nd Embodiment. It is a figure for demonstrating operation | movement of the information processing apparatus in 2nd Embodiment. It is a functional block diagram which shows the other aspect of this invention. It is a functional block diagram which shows an example of the conventional signal processing apparatus. It is a figure for demonstrating operation | movement of the signal processing apparatus of the conventional signal processing apparatus, Comprising: (a) It is the figure which illustrated the case where an analog signal changes linearly with progress of time, (b) Analog signal It is the figure which illustrated the case where changes in a curve with progress of time. It is a figure for demonstrating operation | movement of the signal processing apparatus of the conventional signal processing apparatus.

Explanation of symbols

100 Signal Processing Device 11 Signal Source 12 Signal Input Unit 121 Resistor 13 Signal Input Unit 131 Resistor 14 Multiplexer 14a Multiplexer 14b Multiplexer 14c Multiplexer 15 A / D Converter 16 Multiplexer 17 Timing Controller 18 Buffer Device 19 Buffer Device 20 Comparator 21 Alarm device 22 Adder 23 Adder 30 Processor 200 Signal processing device

Claims (8)

A plurality of signal input units to which analog signals output from one signal source are respectively input;
A first multiplexer that selectively switches and outputs any one of a plurality of output signals respectively output from the plurality of signal input units;
An A / D converter that converts an output signal output from the first multiplexer into a digital signal and outputs the signal as sampling data;
A second multiplexer for selectively switching and outputting the sampling data to any one of the same number of output terminals as the signal input unit to which the sampling data is output;
A plurality of buffer devices connected to each of the plurality of output terminals and respectively holding sampling data output from the second multiplexer;
A plurality of adders for respectively calculating a sum or average of a plurality of sampling data respectively held in the plurality of buffer devices;
A comparator for comparing the calculated values;
The switching operation of the first multiplexer is controlled a plurality of times so that the time-series switching order of the output signals is symmetric between the first half and the second half of the order, and according to the switching operation of the first multiplexer. A timing controller for controlling the switching operation of the second multiplexer;
A signal processing apparatus comprising:   The timing controller controls the switching operation of the first multiplexer so that the switching timing of the first multiplexer is symmetric between the first half and the second half of the switching order. Signal processing device.   The said timing controller controls the switching operation | movement of a said 1st multiplexer in multiple times within the time interval for every half period of the frequency component which the said analog signal has, or every time interval, The Claim 1 or 2 characterized by the above-mentioned. Signal processing device. Further comprising a notification means,
The signal processing apparatus according to claim 1, wherein the comparator causes the notifying unit to notify based on a comparison result by the comparator. An input step of inputting an analog signal output from one signal source to each of a plurality of signal input units;
A first switching step of selectively switching and outputting any one of a plurality of output signals respectively output from the plurality of signal input units;
An A / D conversion step of converting the output signal output in the first switching step into a digital signal and outputting it as sampling data;
A second switching step of selectively switching and outputting the sampling data to any one of the same number of output terminals as the signal input unit to which the sampling data is output;
A holding step of holding the plurality of output sampling data in a plurality of buffer devices respectively connected to the plurality of output ends;
A calculation step of calculating a total or average of a plurality of sampling data respectively held in the plurality of buffer devices;
A comparison step of comparing the calculated values;
The switching operation of the first switching step is controlled a plurality of times so that the time-series switching order of the output signals is symmetric between the first half and the second half of the order, and according to the switching operation of the first multiplexer. A timing control step for controlling the switching operation of the second switching step;
A signal processing method comprising:   The timing control step controls the switching operation of the first switching step so that the switching timing of the first switching step is symmetric between the first half and the second half of the switching order. A signal processing method according to claim 1.   7. The timing control process according to claim 5, wherein the switching operation of the first switching process is controlled a plurality of times within a time interval corresponding to a half cycle of the frequency component of the analog signal or every time interval. The signal processing method as described. Further comprising a notification step,
The signal processing method according to any one of claims 5 to 7, wherein the comparison step is caused to notify the notification step based on a comparison result of the comparison step.

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