JP2010263420A - Multiplexor circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multiplexor circuit which can correctly detect the operational abnormality of a multiplexor. <P>SOLUTION: The multiplexor circuit includes: a multiplexor for sequentially acquiring analog input signals input from a plurality of channels, and multiplexes and outputs the input signals; an AD converter for converting analog input signals output from the multiplexor into a plurality of digital output signals which respectively correspond to the plurality of channels; a processor for monitoring output values of the plurality of digital output signals, and determining that the operation of the multiplexor is in an abnormal state if a state in which all of the output values are within a predetermined range continues for a predetermined determination time; and a pulse signal generator for outputting a pulse signal whose period is shorter than the determination time to the multiplexor as one of the analog input signals. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  More specifically, the present invention relates to a multiplexer circuit that automatically detects an abnormal operation.

  2. Description of the Related Art Conventionally, various electric devices have so-called multiplexers that receive a plurality of channels of input signals and sequentially select the channels to multiplex and output the input signals of the respective channels. When a failure or abnormality occurs in such a multiplexer, a normal output signal cannot be obtained from the multiplexer, and there is a possibility that normal operation of a device that operates using the output signal may be hindered. Therefore, a technology for automatically detecting the abnormality of the multiplexer as described above has been developed.

  For example, in the digital protection relay disclosed in Patent Document 1, a calibration voltage is input to the multiplexer. Then, when the value of the output signal of the channel to which the calibration voltage is applied is within a predetermined range, the digital protection relay determines that the multiplexer is operating normally, and the value of the output signal is out of the predetermined range. If it is, it is determined that an abnormality has occurred in the operation of the multiplexer.

JP-A-8-98390

  However, since the digital protection relay disclosed in Patent Document 1 monitors only the output signal of the channel to which the calibration voltage is applied, the channel selected by the multiplexer is fixed to the channel to which the calibration voltage is applied. When an abnormal operation occurs in which switching to the other channel is not normally performed, the abnormal operation of the multiplexer cannot be detected.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a multiplexer circuit capable of accurately detecting an abnormal operation of a multiplexer.

  In order to solve the above problems, the present application adopts the following configuration. That is, according to the first invention, analog input signals input from a plurality of channels are sequentially fetched, the input signals are multiplexed and output, and the analog input signals output from the multiplexer correspond to the plurality of channels, respectively. An AD converter that converts to a plurality of digital output signals and the output values of the plurality of digital output signals are monitored, and a state where all the output values are within a predetermined range continues for a predetermined determination time. A multiplexer that includes a processing device that determines that the operation of the multiplexer is in an abnormal state and a pulse signal generator that outputs a pulse signal having a cycle shorter than the determination time to the multiplexer as one of the analog input signals. .

  According to the first invention, it is possible to detect whether or not channel switching is normally performed in the multiplexer. In addition, even if the output values of the output signals of all the channels are temporarily the same (within a predetermined range), a pulse signal whose output value changes reliably at a constant period is output. Therefore, the state does not continue longer than the determination time. Therefore, it is not erroneously detected that an abnormality has occurred in the normally operating multiplexer. That is, it is possible to accurately detect the abnormality of the multiplexer.

The figure which shows an example of a structure of a multiplexer circuit An example of a flowchart showing processing executed by the CPU 15 The figure which shows an example of the output signal of each channel The figure which shows an example of the output signal of each channel from which the waveform of the output signal Ar differs from FIG. The figure which shows an example of the output signal in the conventional multiplexer circuit which is not provided with the pulse generator 12.

  Hereinafter, a multiplexer circuit according to an embodiment of the present invention will be described. First, the configuration of the multiplexer circuit will be described with reference to FIG. FIG. 1 is a diagram illustrating an example of the configuration of the multiplexer circuit.

  The multiplexer circuit includes a multiplexer 11, a pulse generator 12, an A / D converter 13, a storage device 14, and a CPU 15.

  The multiplexer 11 is a device that sequentially receives analog input signals input from a plurality of channels by switching the channels, multiplexes the input signals, and outputs the multiplexed signals. In the following, an example in which the multiplexer 11 captures an analog input signal from four channels of channel A, channel B, channel C, and channel D will be described. The multiplexer 11 is electrically connected to the A / D converter 13 and outputs a multiplexed input signal (hereinafter referred to as a multiplexed signal) to the A / D converter 13.

  The pulse generator 12 is a device that outputs a pulse signal. The pulse generator 12 inputs a pulse signal to the channel A of the multiplexer 11. The pulse signal is converted by the AD converter into a rectangular pulse signal having a period P that alternately takes the maximum and minimum output values that each output signal can take. Further, the pulse generator 12 may be configured by a microcomputer or a conventionally known oscillation circuit as long as it can output a pulse signal.

  The A / D converter 13 is a device that converts a multiplexed signal into a digital signal and outputs the digital signal. The A / D converter 13 further divides the digital signal into a plurality of output signals respectively corresponding to the respective channels of the input signal and outputs them. That is, the A / D converter 13 has a so-called demultiplexer function. Each time the conversion period T elapses, the A / D converter 13 converts the multiplexed signal input up to that point into a digital signal and outputs the digital signal. At this time, the time required to convert the multiplexed signal into a digital signal and output the output signals of all channels is referred to as AD conversion time G. Hereinafter, output signals corresponding to channel A, channel B, channel C, and channel D are referred to as output signal Ar, output signal Br, output signal Cr, and output signal Dr, respectively.

  The storage device 14 is a device that stores the output value of the output signal of each channel output by the A / D converter 13 for each channel. The storage device 14 is typically a storage device such as a memory, and stores data indicating the output value of the output signal of each channel at a predetermined address.

  The CPU 15 is an information processing device that determines the state of operation of the multiplexer 11. The CPU 15 detects the abnormality of the multiplexer 11 by monitoring the output values of the output signal Ar, the output signal Br, the output signal Cr, and the output signal Dr from the A / D converter 13. Hereinafter, an operation abnormality in which switching to another channel is not normally performed is referred to as a sticking abnormality. A channel that is continuously selected when the sticking abnormality occurs is referred to as a sticking channel.

  Hereinafter, processing executed by the CPU 15 will be described with reference to FIG. FIG. 2 is an example of a flowchart showing processing executed by the CPU 15.

  In step A1, the CPU 15 counts up the timer value S. The timer value S is a value indicating an elapsed time from the time when Step A6 or Step A7 described later is executed. The CPU 15 adds a predetermined constant value to the timer value S. When the process of step A1 is completed, the CPU 15 advances the process to step A2.

  In step A2, the CPU 15 determines whether or not the timer value S is greater than or equal to the conversion cycle T. If the CPU 15 determines that the timer value S is equal to or greater than the conversion period T, the CPU 15 advances the process to step A3. On the other hand, if it is determined that the timer value S is less than the conversion period T, the process returns to step A1.

  According to the processing of step A1 and step A2, the following processing from step A3 to step A8 is executed every time the conversion cycle T elapses. The CPU 15 determines whether or not the operation of the multiplexer 11 is normal by the processing from step A3 to step A8 described below.

  In step A3, the CPU 15 determines whether or not the output values of the respective channels are substantially the same value. Specifically, the CPU 15 determines whether or not the value of each output signal is included in a predetermined range. First, the CPU 15 acquires the output values of the output signal Ar, the output signal Br, the output signal Cr, and the output signal Dr at the current time from the storage device 14. Then, the output values of the respective output signals are compared, and a difference value ΔE between the maximum value and the minimum value of the output values is calculated. Next, the CPU 15 determines whether or not the difference value ΔE is equal to or less than the threshold value ΔEth. The threshold value ΔEth is a predetermined constant value, and is a threshold value for determining whether or not the output value of each channel is substantially the same value. When the difference value ΔE is equal to or smaller than the threshold value ΔEth, the CPU 15 determines that the output value of each channel is substantially the same value, and advances the processing to step A4. On the other hand, when the difference value ΔE is larger than the threshold value ΔEth, the CPU 15 determines that the output values of the respective channels are not substantially the same value, and advances the processing to step A5.

The threshold value ΔEth is preferably calculated and set in advance as follows. First, the amount of change in voltage per unit time of the output signals (output signal Br, output signal Cr, and output signal Dr) of each channel other than the channel (channel A) that receives the pulse signal from the pulse generator 12 is measured. . Hereinafter, the amount of change in voltage per unit time of each output signal is referred to as voltage change rate V. The voltage change rate V is an eigenvalue determined by the characteristics of the device or circuit that generates each input signal. Here, the maximum value of the voltage change rate V of each channel is defined as the maximum change amount Vmax. Next, the threshold ΔEth is calculated from the maximum change rate Vmax and the AD conversion time G based on the following equation (1).
ΔEth = G × Vmax (1)

  Here, it is assumed that the A / D converter 13 sequentially converts the signals of channel A, channel B, channel C, and channel D from the multiplexed signal in this order. When the sticking abnormality has occurred, the output value of the output signal of each channel depends on the voltage change rate V of the sticking channel between the conversion of the channel A signal and the completion of the conversion of the channel D signal. Change. That is, the difference value ΔE varies within a range of a value obtained by multiplying the voltage change rate V of the fixed channel by the AD conversion time G. The variation range of the difference value ΔE becomes maximum when the voltage change rate of the fixed channel is the maximum change rate Vmax. Therefore, if the threshold value ΔEth is determined based on the above equation (1), ΔE is surely equal to or less than ΔEth when a sticking abnormality occurs. That is, the CPU 15 can accurately determine whether or not the output value of each channel is substantially the same without overlooking the occurrence of the sticking abnormality. Note that the processing in step A3 is merely an example, and the determination may be performed using another conventionally known method as long as it can be determined whether or not the output value of each channel is substantially the same value.

  In step A4, the CPU 15 counts up the coincidence counter value M. The coincidence counter value M is a variable indicating the number of times that the output value of each channel is determined to be substantially the same. For example, the CPU 15 adds a predetermined constant such as 1 to the coincidence counter value M. The initial value of the coincidence counter value M is set in advance to a value such as 0, for example. When the process of step A4 is completed, the CPU 15 advances the process to step A6.

  In step A5, the CPU 15 resets the coincidence counter value M. Specifically, the CPU 15 sets and resets the value of the coincidence counter value M to a predetermined initial value such as 0, for example. When the process of step A5 is completed, the CPU 15 advances the process to step A6.

  In step A6, the CPU 15 determines whether or not the coincidence counter value M is greater than or equal to the threshold value Mth. The threshold value Mth is a threshold value for determining whether or not the state in which the output value of each channel is substantially the same value continues for a certain period of time. If the CPU 15 determines that the coincidence counter value M is equal to or greater than the threshold value Mth, the process proceeds to step A7. On the other hand, if the CPU 15 determines that the coincidence counter value M is less than the threshold value Mth, the process proceeds to step A8.

  In step A7, the CPU 15 determines that an abnormality has occurred in the multiplexer 11. Specifically, the CPU 15 outputs a signal indicating that an abnormality has occurred in the multiplexer 11 to a device that performs an operation using each output signal, and notifies the device of the operation state of the multiplexer 11. When the process of step A7 is completed, the CPU 15 returns the process to step A1.

  In step A8, the CPU 15 determines that the multiplexer 11 is operating normally. Specifically, the CPU 15 outputs a signal indicating that the multiplexer 11 is operating normally to a device that performs an operation using each output signal, and notifies the device of the operation state of the multiplexer 11. When the process of step A8 is completed, the CPU 15 returns the process to step A1.

  According to the process of FIG. 2 described above, the CPU 15 determines that a sticking abnormality has occurred in the multiplexer 11 when the state where the output values of the respective output signals are substantially the same value continues.

  Next, the operation of the multiplexer circuit will be described with reference to FIG. FIG. 3 is a diagram illustrating an example of an output signal of each channel.

As shown in FIG. 3, since the above-described pulse signal is input to the channel A from the pulse generator 12, the output signal Ar is a rectangular pulse wave signal with a period P. Note that the period P is set in advance to a value satisfying at least the following expression (2).
P <T × (Mth−1) / 2 (2)

The threshold value Mth may be set in advance as a natural number that satisfies the following expression (3). The minimum value of the voltage change rates V of each channel is defined as the minimum change amount Vmin. Further, the maximum output value that each output signal can take is set as a maximum range value Emax.
Mth <Emax / (Vmin × T) +1 (3)

  Whenever the conversion cycle T elapses, the CPU 15 determines the operating state of the multiplexer 11 by executing the processing from step A3 to step A8 at time t1, time t2, time t3, and time t4. Hereinafter, an example in which the value of the threshold value Mth is set to 2 will be described.

  In FIG. 3, at the time t2, the output values of all the channels accidentally become substantially the same value, and the CPU 15 counts up the value of the coincidence counter M. At time t2, the output value of the output signal Ar takes the minimum value. However, since the period P is set in advance as described above, at time t3, the output value of the output signal Ar is inverted from the minimum value to the maximum value. Therefore, the output value of the output signal Ar does not become the same output value as the output signals of other channels at the time t3.

  As described above, according to the multiplexer circuit according to the embodiment of the present invention, since the pulse signal is input to the channel A, the CPU 15 outputs the output values of the output signals of all the channels approximately as long as no sticking abnormality occurs. If the values are the same, the number of times equal to or greater than the threshold value Mth is not continuously determined.

  If the pulse generator 12 is not provided unlike the conventional multiplexer circuit and the pulse signal is not input to the channel A, the output signals of the channel A to the channel D are accidentally omitted as shown in FIG. In some cases, the phenomenon of the same value continuously occurs from time t2 to time t3. FIG. 5 is a diagram illustrating an example of an output signal in a conventional multiplexer circuit that does not include a pulse generator. In such a case, at time t2 and time t3, the CPU 15 continuously determines that the values of the respective channels are continuously the same value, and is fixed regardless of whether the multiplexer 11 is operating normally. There is a possibility of erroneously determining that an abnormality has occurred.

  In that respect, according to the multiplexer circuit according to the present embodiment, the CPU 15 does not erroneously determine the fixing abnormality due to the fluctuation of the pulse signal as described above. Therefore, according to the multiplexer circuit according to the present embodiment, it is possible to accurately determine the operation state of the multiplexer 11.

In the above embodiment, an example in which the pulse signal input to the channel A is a signal converted by the AD converter into a rectangular pulse signal has been described. However, the pulse signal is, for example, as shown in FIG. It may be a signal converted into a triangular wave signal. FIG. 4 is a diagram illustrating an example of the output signal of each channel in which the waveform of the output signal Ar is different from that in FIG. The pulse signal may be a signal converted into a sawtooth wave or a sine wave. When the pulse wave is converted into a sawtooth triangular wave, the period P of the output signal is set in advance so as to satisfy the following expression (4).
P <T × (Mth−1) (4)

  In the above embodiment, the example in which the number of channels of the input signal received by the multiplexer 11 is four has been described. However, if the pulse signal of the pulse generator 12 is input to any channel, the multiplexer 11 receives the signal. The number of channels of the input signal is not limited to four.

  The multiplexer circuit according to the present invention is useful as a multiplexer circuit or the like that can detect an abnormal operation of the multiplexer accurately.

11 Multiplexer 12 Pulse generator 13 A / D converter 14 Storage device 15 CPU

Claims (1)

A multiplexer that sequentially takes analog input signals input from a plurality of channels, multiplexes the input signals, and outputs them,
An AD converter that converts the analog input signal output from the multiplexer into a plurality of digital output signals respectively corresponding to the plurality of channels each time a predetermined conversion period elapses;
The output values of the plurality of digital output signals output from the AD converter are monitored, and the operation of the multiplexer is abnormal if the state where the output values are substantially the same continues for a longer than a predetermined abnormality determination time. A determination processing device for determining that the state is present;
The input signal converted by the AD converter to one of the analog input signals is converted into a pulse signal that alternately takes the maximum value and the minimum value of each output signal that can be taken in a cycle shorter than the abnormality determination time. A multiplexer circuit further comprising a pulse signal generator for inputting to the multiplexer.

Images