JP4715528B2 - Semi-insulating GaAs wafer for electronic devices and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semi-insulating GaAs wafer and a manufacturing method thereof, and more particularly, in a process of manufacturing an electronic device using a GaAs wafer by defining a dislocation density (EPD) and a residual strain value of the wafer. The present invention relates to a semi-insulating GaAs wafer that eliminates the occurrence of slip dislocations in a heat treatment such as activation annealing after ion implantation and a method for manufacturing the same.

  There are two methods of manufacturing a semi-insulating GaAs wafer: LEC method (liquid sealing pulling method) and vertical melt method (vertical Bridgman method (VB method), vertical temperature gradient solidification method (VGF method)). This is a general technique. Hereinafter, each method will be described.

  A method for producing a GaAs single crystal by the LEC method will be described with reference to FIG.

  The LEC GaAs single crystal manufacturing apparatus 1 has a structure having a chamber 2 as a furnace part, a pulling-up shaft 3 for pulling up a crystal, a crucible 5 as a material container, and a crucible shaft 4 for receiving the crucible. It has become.

  Regarding a method for producing a GaAs single crystal by the LEC method, first, a crucible 5 serving as a raw material container (usually PBN is used as the material of the crucible) is used as a volatilization preventive material for Ga, As and As. Boron oxide 6 is put and set in the chamber 2. In addition, a seed crystal 7 as a crystal base is attached to the tip of the pull-up shaft 3. In general, the seed crystal 7 has a (100) plane in contact with the GaAs melt.

  After setting the raw material in the chamber 2, the inside of the chamber 2 is evacuated and filled with an inert gas. Thereafter, the resistance heater 8 installed in the chamber 2 is energized to raise the temperature in the chamber 2, and GaAs is produced by synthesizing Ga and As. Thereafter, the temperature is further raised to melt GaAs to obtain a GaAs melt 9. Subsequently, the pull-up shaft 3 and the crucible shaft 4 are rotated so that the rotation directions are reversed. In this state, the pull-up shaft 3 is lowered until the seed crystal 7 attached to the tip contacts the GaAs melt 9. Subsequently, by raising the pulling shaft 3 at a constant speed while gradually lowering the set temperature of the resistance heater 8, a crystal shoulder is formed while gradually increasing the crystal diameter from the seed crystal 7. After the formation of the crystal shoulder, if the target crystal outer diameter is reached, the GaAs single crystal 10 is manufactured while controlling the outer shape so as to keep the outer diameter constant.

  Next, a method for producing a GaAs single crystal by the vertical melt method will be described with reference to FIG.

  A vertical melt method (VB method, VGF method) GaAs single crystal manufacturing apparatus 21 has a structure having a chamber 22 as a furnace body portion and a crucible shaft 24 for receiving a crucible 25 as a raw material container. Yes.

  Regarding the method for producing a GaAs single crystal by the VB method (or VGF method), first, the crucible 25 serving as a raw material container (usually PBN is used as the material of the crucible) is used to volatilize GaAs polycrystal and As Boron trioxide 26, which is a preventive material, is added. In addition, a seed crystal 27 that is the base of the crystal is attached in the small diameter portion of the tip of the crucible 25. The seed crystal 27 generally has a (100) plane in contact with the GaAs melt. These are set in the chamber 22.

  Subsequently, the chamber 22 is evacuated and filled with an inert gas. Thereafter, the resistance heater 28 installed in the chamber 22 is energized, and the temperature in the chamber 22 is raised with the temperature gradient set so that the temperature increases from the lower part to the upper part. Is melted to obtain a GaAs melt 29. Further, seeding is performed by raising the furnace temperature until the GaAs melt 29 comes into contact with the seed crystal 27 installed at the tip of the crucible 25.

  Subsequently, in the case of the VB method, the GaAs melt 29 is solidified from the seed crystal 27 by lowering the crucible shaft 24 at a constant speed while the set value of the resistance heater 28 is fixed from this state. Manufacture of GaAs single crystal. In the case of the VGF method, the crucible shaft 24 is not moved after seeding, and the set value of the resistance heater 28 is lowered at a certain rate, so that the GaAs melt 29 is solidified from the seed crystal 27 and the GaAs single crystal is solidified. Crystal production is performed.

  The LEC method and the vertical melt method (VB method and VGF method) described above have advantages and disadvantages, respectively.

In the case of the LEC method, crystal growth is performed under conditions of a steep temperature gradient. Therefore, the cooling of the crystal is easy, and it is suitable for increasing the speed of crystal growth, which is very advantageous in terms of throughput. However, due to crystal growth under a steep temperature gradient, the in-plane dislocation density of the wafer is higher than that of the VB and VGF methods (the in-plane average dislocation density is 50 for a wafer having a diameter of φ15.24 cm (6 inches)). , 1,000 to 100,000 pieces / cm ² ). However, if an annotation is added, the effect of the dislocation density of the semi-insulating GaAs wafer on the electronic device characteristics is still in the investigation stage, and it has not been concluded that a low dislocation density is good.

On the other hand, in the case of the VB and VGF methods, crystal growth is performed under a gentle temperature gradient. Therefore, contrary to the LEC method, it is unsuitable for speeding up crystal growth, which is disadvantageous in terms of throughput. However, it is advantageous for lowering the dislocation density of the wafer (in-plane average dislocation density of about 10,000 / cm ² with a diameter of φ15.24 cm (6 inches)).

  By the way, the semi-insulating GaAs wafer is used as a substrate material for an electronic device that requires high-speed operation and low power consumption. The semi-insulating GaAs wafer supplied as an electronic device substrate to an electronic device maker is subjected to an annealing process (heating process) represented by activation annealing after ion implantation in the electronic device manufacturing process.

  The purpose of ion implantation is to improve the conductivity of the wafer by implanting, for example, Si ions on the surface of the GaAs wafer. However, the crystal lattice arrangement is disturbed by the ion implantation process, and the electrical conductivity is not improved sufficiently. Therefore, an activation annealing process is performed to neatly rearrange the crystal lattice.

  This annealing process is performed under the unique conditions of each electronic device manufacturer. Basically, a method is generally employed in which the temperature is rapidly raised to about 500 to 900 ° C. and then rapidly cooled. It is.

Regarding the annealing treatment technology, the LEC method and the vertical melt method (VB method, VGF method) have been conventionally weighed, and the dislocation density of the wafer made of GaAs crystal produced by the vertical melt method is lower than that of the LEC method. In view of the low residual strain, attempts have been made to utilize this as a substrate for ion implantation (see Patent Document 1). However, when a crystal obtained by the vertical melt method is actually used at a mass production level, stable characteristics may not be obtained as compared with a GaAs crystal (LEC crystal) by a conventional LEC method. In the case of a GaAs crystal obtained by this vertical melt method, when a heat treatment similar to that performed by a conventional GaAs crystal (LEC crystal) by the LEC method is performed, the diameter is especially 7.62 cm (3 inches). ) In the crystal having a large diameter as described above, the dislocation density and the residual strain increase, and the homogenization mechanism may be different from that of the LEC crystal. Therefore, Patent Document 1 realizes a high-quality GaAs wafer that can be actually used for production by narrowing down the manufacturing conditions of the GaAs crystal that can obtain more stable and uniform electrical characteristics and the characteristics of the crystal. Intends to newly examine optimum heat treatment conditions.
JP 11-268997 A

  By the way, as a problem of the prior art, in the manufacture of an electronic device using a GaAs crystal obtained by the LEC method or the vertical melt method (VB method, VGF method) described in the prior art as a substrate, activation after ion implantation is performed. In the annealing process, slip dislocation occurs in the GaAs wafer after the annealing process, causing a problem that it cannot be used as a product.

  The greatest cause of slip dislocation is temperature non-uniformity in the wafer surface during annealing. In this regard, each electronic device manufacturer is improving the annealing method.

  However, in recent years, the diameter of wafers has been increasing, and the mainstream of GaAs wafers is changing from the conventional diameter of 10.16 cm (4 inches) to the diameter of 15.24 cm (6 inches). In addition, a higher level of control is required to make the temperature in the wafer surface uniform during annealing, which is a greater problem than before.

  In the case of Patent Document 1 described above, a GaAs crystal having a lower dislocation density and a lower residual strain can be obtained by the vertical melt method (VB method, VGF method) than by the LEC method. I am trying to use it.

  However, the vertical melt method (VB method, VGF method) does not provide stable characteristics compared to the GaAs crystal (LEC crystal) by the LEC method, and the same heat treatment as that performed by the LEC crystal is performed. Therefore, it is necessary to newly examine optimum heat treatment conditions.

  Furthermore, this is the most important point. The fact that “the crystals of the vertical melt method (VB method, VGF method) have lower residual stress” means that less slip dislocations occur immediately. It is a point that must not be. Speaking from the results of diligent research efforts by the present inventors, the occurrence of slip dislocation after activation annealing is not simply caused by residual stress.

  Even with the conventional LEC method, if the characteristics of a GaAs crystal with a low incidence of slip dislocations, for example, the in-wafer in-plane dislocation density (EPD value) and the value of residual stress can be narrowed down, the actual ion implantation substrate A high-quality GaAs wafer that can be used for production can be realized.

  Therefore, the object of the present invention is to solve the above-mentioned problems and may be the LEC method or the vertical melt method (VB method, VGF method). An object of the present invention is to provide a semi-insulating GaAs wafer in which generation of slip dislocation is eliminated in a heat treatment such as activation annealing after ion implantation by narrowing the density (EPD value) and residual stress to a certain range, and a method for manufacturing the same.

In order to achieve the above object, a semi-insulating GaAs wafer for electronic devices according to the present invention is a semi-insulating GaAs wafer for electronic devices having a diameter of 10.16 cm (4 inches) or more manufactured by the LEC method . The residual strain value in the wafer surface (| Sr-St |) measured by using the photoelastic phenomenon in which the deflecting surface rotates depending on the size is in the range of 1.0 × 10 ⁻⁵ or less, and the dislocation within the wafer surface The density (EPD) is 50,000 / cm ² or more and 100,000 / cm ² or less.

Dislocation density (EPD) in the wafer plane is 80,000 / cm ² The above is preferable.

In order to achieve the above object, the method for producing a semi-insulating GaAs wafer for electronic devices according to the present invention has a temperature gradient in the crystal when growing a GaAs single crystal by the LEC method. When the dislocation density (EPD) in the wafer surface is set to 50,000 / cm ² or more and 100,000 / cm ² or less by growing the GaAs single crystal, the GaAs single crystal is further grown. The wafer is annealed by performing annealing on the crystal, setting the maximum temperature during annealing to 900 ° C. to 1150 ° C., and setting the temperature gradient in the GaAs single crystal to 0 ° C./cm to 12.5 ° C./cm. The in-plane residual strain value (| Sr-St |) is in the range of 1.0 × 10 ⁻⁵ or less.

  According to the present invention, in the manufacture of electronic devices using a semi-insulating GaAs wafer as a substrate, it is possible to greatly reduce product defects due to slip dislocations generated by wafer heat treatment represented by activation annealing after ion implantation. Thus, the yield in electronic device manufacturing can be improved.

(Key points of the invention)
Conventionally, the influence of the dislocation density of the semi-insulating GaAs wafer on the electronic device characteristics is still in the investigation stage, and it has not been concluded that a low dislocation density is good.

  With regard to this point, as a result of diligent research efforts by the present inventors, it has been found that GaAs crystals with many dislocations are less likely to cause slip dislocation after activation annealing if the residual stress is the same. In other words, if the residual stress is the same, slip dislocations are less likely to occur in the crystal wafer produced by the LEC method in which more dislocations are generated than in the crystal wafer produced by the vertical melt method (VB method, VGF method). .

Therefore, the present invention narrows down the characteristics of GaAs crystals with a low occurrence of slip dislocations as follows, so that a high-quality GaAs wafer that can actually be used for production of an ion implantation substrate even with the LEC method. Succeeded in manufacturing. That is, one is the dislocation density in the wafer surface (hereinafter referred to as EPD), which is in the range of 3 × 10 ⁴ / cm ² ≦ EPD ≦ 1 × 10 ⁵ / cm ² , One is the residual strain value (| Sr-St |) in the wafer surface obtained by photoelasticity measurement, which is in the range of 1.8 × 10 ⁻⁵ or less.

In Patent Document 1, the in-plane average dislocation density is 1 × 10 ⁴ cm ² or less, and the average residual strain (| Sr−St |) obtained by photoelasticity measurement is less than 1 × 10 ⁻⁵ . Therefore, as long as the comparison is made centering on the dislocation density (EPD) in the wafer plane, it is out of the scope of the present invention.

  Hereinafter, the numerical limitation of the present invention will be described in detail.

(EPD range on the wafer surface)
In the present invention, the reason why the EPD in the wafer surface is in the range of 3 × 10 ⁴ pieces / cm ² or more and 1 × 10 ⁵ pieces / cm ² or less is that as a phenomenon generally observed in all metals due to dislocations. In the dislocation generation portion, plastic deformation occurs, and the dislocation is entangled in a complicated manner due to the plastic deformation, resulting in work hardening. This is because it is considered that this increases the thermal stress applied during annealing and reduces the occurrence of slip dislocations. With respect to this work hardening, a result that an EPD value of 3 × 10 ⁴ pieces / cm ² or more was obtained by a verification experiment. The reason why the EPD value is 1 × 10 ⁵ pieces / cm ² or less is that although work hardening is obtained and there is an effect of reducing slip dislocation, when the EPD exceeds 1 × 10 ⁵ pieces / cm ² , This is because the possibility of occurrence of subgrain boundaries increases and the product cannot be used.

(Range of residual strain value in wafer surface | Sr-St |)
In the present invention, the reason why the residual strain value | Sr-St | in the wafer surface is set to 1.8 × 10 ⁻⁵ or less is that the residual strain value in the wafer surface and the occurrence of slip dislocations are found by the inventors' recent research. It has been found that there is a correlation between them, and when the residual strain value is high, the slip dislocation occurrence rate tends to increase gradually. It has also been found that when the residual strain value in the wafer surface exceeds a certain value, there is a critical point at which the rate of occurrence of slip dislocation in annealing is rapidly increased. Since the critical point is in the vicinity of | Sr-St | = 1.8 × 10 ⁻⁵ , the residual strain value is in the above range.

(Measurement method of residual strain value | Sr-St | in the wafer surface)
For the evaluation method of the residual strain, see Rev., for example. Sci. Instrum. , Vol. 64, no. 7, pp. The measurement method using the photoelastic phenomenon described in 1815-1821 July 1993 is used. As an outline of the measurement principle, an infrared light source irradiates the wafer with a light source and detects the rotation angle of the deflection surface of the transmitted light. The rotation angle of this deflection surface is determined by the residual stress of the wafer. By detecting it, the residual stress of the wafer can be measured.

(Definition of residual strain value | Sr-St |)
Next, the definition of | Sr-St | will be described. The residual strain of the wafer can be calculated from | Sr−St |, which is the absolute value of the difference between Sr, which is a radial strain in cylindrical coordinates, and St, which is a strain in the cylinder tangential direction. Here, | Sr-St | is defined by the following relational expression.

λ: wavelength of light source d: thickness of wafer n: refractive index δ: phase difference caused by birefringence of sample ψ: main vibration azimuth angles p ₁₁ , p ₁₂ , p ₄₄ : photoelastic constants δ and ψ from the above equations It is possible to calculate | Sr-St |, which is the residual stress of the wafer.

(Range of temperature gradient in crystal when growing GaAs single crystal)
In the present invention, the range of the temperature gradient in the crystal when growing a GaAs single crystal is set to 20 ° C./cm or more and 150 ° C./cm or less for the following reason.
One of the dislocations generated in the crystal is influenced by the thermal stress that the crystal receives during growth. It is believed that when a crystal is subjected to thermal stress, that is, when the crystal has a certain temperature gradient, dislocations are generated in a direction that relaxes the stress. Therefore, the present inventors provide a predetermined temperature gradient in the crystal during crystal growth so that the EPD value is 3 × 10 ⁴ pieces / cm ² or more and 1 × 10 ⁵ pieces / cm ² or less. I thought about controlling the EPD value.
For this reason, in determining the optimum range of the temperature gradient in the crystal, GaAs single crystal growth is performed using both the LEC method and the VB method (or VGF method). The gradient setting was changed, and an experiment was conducted to see what the EPD value at that time would be.

FIG. 4 shows the correlation between the temperature gradient in the crystal and the EPD of the obtained crystal.
From this figure, when the temperature gradient in the crystal during crystal growth in the range below 20 ° C. / cm or higher 0.99 ° C. / cm, with good reproducibility, EPD is 30,000 / cm ² or more 100,000 / cm ² It can be seen that the following range is satisfied.
Therefore, in the present invention, the range of the temperature gradient in the crystal when growing a GaAs single crystal for obtaining a semi-insulating GaAs wafer is set to 20 ° C./cm or more and 150 ° C./cm or less.

(Suitable range of annealing conditions)
In the present invention, when the annealing is performed after the crystal growth is performed by the temperature gradient at the time of GaAs single crystal growth, the highest temperature is 900 ° C. or higher and 1150 ° C. or lower as the annealing condition. The temperature gradient in the crystal is preferably 0 ° C./cm or more and 12.5 ° C./cm or less, for the following reason.
As described above, by setting the temperature gradient range in the crystal when growing the GaAs single crystal to 20 ° C./cm or more and 150 ° C./cm or less, the EPD value is set to the above 3 × 10 ⁴ pieces / cm 2. ^Although it can be controlled to ² or more and 1 × 10 ⁵ pieces / cm ² or less, there is one aspect that a residual stress is generated in the crystal because thermal stress is applied to the crystal.

  In this regard, the inventors extracted only the lot in which the temperature gradient setting condition was set to 20 ° C./cm to 150 ° C./cm in the crystal in which the experiment shown in FIG. The wafer was sampled in a state where the processing such as the above was not performed, and the in-plane residual strain | Sr-St |

FIG. 5 shows the relationship between the measured in-wafer residual strain and the number of lots.
As a result, the average value of | Sr-St | was 1.93 × 10 ⁻⁵ , and it was difficult to control | Sr−St | ≦ 1.8 × 10 ⁻⁵ with good reproducibility.
Therefore, as a result of sincerity, the present inventors performed the annealing treatment described above after the crystal growth even in the crystal grown by setting the temperature gradient setting condition to 20 ° C./cm or more and 150 ° C./cm or less. As a result, the strain remaining in the crystal due to thermal stress can be efficiently removed, and as a result, the residual strain value in the wafer surface can be controlled within a range of 1.8 × 10 ⁻⁵ or less. I found it possible.

In optimizing the annealing conditions, 1.9 × 10 ⁻⁵ (average value), 2.3 × 10 ⁻⁵ (maximum value), 1.5 × based on the result of residual strain measurement in FIG. Three samples of 10 ^-5 (minimum value) were prepared, and the change in residual stress was measured using the maximum temperature reached during annealing and the temperature gradient in the crystal as parameters, and the optimum conditions were grasped.
Tables 1, 2, and 3 show the value of residual stress | Sr-St | after annealing for each sample.

In Tables 1 to 3, the shaded columns indicate the annealing conditions in which a decrease was observed with respect to the residual stress value before annealing, and | Sr-St | was able to achieve a value of 1.8 × 10 ⁻⁵ or less. It is. In the table, “Not measurable” means that the crystal surface has risen to the melting point of GaAs due to overshoot of the furnace heater used for annealing, and the crystal surface has melted, making it impossible to measure. It is what has been.
From the results of Tables 1 to 3, in all samples, the annealing conditions under which the residual stress value before annealing was reduced and | Sr-St | was able to achieve 1.8 × 10 ⁻⁵ or less were as follows: The temperature was 900 ° C. or more and 1150 ° C. or less, and the temperature gradient in the crystal during annealing was 0 ° C./cm or more and 12.5 ° C./cm or less. Based on the above results, optimization of annealing conditions was determined.

  The method for producing a semi-insulating GaAs wafer according to the present invention is characterized in that a semi-insulating GaAs wafer that does not cause slip dislocation in the activation annealing treatment after ion implantation can be obtained from a GaAs single crystal produced by the LEC method. There is. Of course, from the GaAs single crystal manufactured by the vertical melt method (VB method, VGF method), the dislocation density (EPD) in the wafer surface and the residual strain value (| Sr-St |) in the wafer surface are defined as above. A semi-insulating GaAs wafer having a range can be obtained. Moreover, the size of the wafer does not necessarily need to be 15.24 cm (6 inches) or more in diameter, and it can be applied to a semi-insulating GaAs wafer having a diameter of 10.16 cm (4 inches) or more.

Using a semi-insulating GaAs wafer having a diameter of 15.24 cm (6 inches), aligning the wafer with two parameters, EPD and residual strain, and conducting an annealing experiment using these wafers, the slip generation rate was reduced. investigated. The prepared wafers were manufactured by the LEC method in the range of 30,000 to 100,000 / cm ² according to the EPD value, and were manufactured by the VGF method in the range of less than 30,000 / cm ² . A wafer was used. Further, when a wafer having an EPD value of 30,000 to 100,000 / cm ² is manufactured by the LEC method, the temperature gradient in the crystal during crystal growth is set to 20 ° C./cm or more and 150 ° C./cm or less. The EPD value was adjusted by adjusting. Further, when a wafer having an EPD value of less than 30,000 / cm ² is manufactured by the VGF method, the temperature gradient in the crystal during crystal growth is adjusted to a value of less than 20 ° C./cm. The value was adjusted. Further, as for the residual stress in the wafer surface, an experimental wafer sample was prepared by performing annealing in the above range or not performing after the crystal growth according to the residual stress value necessary for the experiment.

Hereinafter, a method for producing a GaAs crystal used in the experiment will be described.
First, a GaAs single crystal manufacturing method using the LEC method will be described with reference to FIG.
A PBN crucible was used as the crucible 5 serving as a raw material container. Ga, As, and boron trioxide 6 which is a volatilization preventive material for As were put into the crucible 5 and set in the chamber 2. The charged weight was Ga: 15,000 g, As: 16,500 g, and boron trioxide 6: 2,000 g. In addition, a seed crystal 7 as a crystal base was attached to the tip of the pull-up shaft 3.
After these raw materials were set in the chamber 2, the inside of the chamber 2 was evacuated and filled with an inert gas. Thereafter, the resistance heater 8 installed in the chamber 2 was energized to raise the temperature in the chamber 2, and Ga and As were synthesized to produce GaAs. Thereafter, the temperature was further raised to melt GaAs to obtain a GaAs melt 9. Subsequently, the pull-up shaft 3 and the crucible shaft 4 were rotated so that the rotation directions were reversed. In this state, the pulling shaft 3 was lowered until the seed crystal 7 attached to the tip contacted the GaAs melt 9. Subsequently, the pulling shaft 3 was raised at a constant speed while gradually lowering the set temperature of the resistance heater 8, thereby forming a crystal shoulder while gradually increasing the crystal diameter from the seed crystal 7. After the formation of the crystal shoulder, when the target crystal outer diameter was reached, the GaAs single crystal 10 was manufactured while controlling the outer shape so as to keep the outer diameter constant. Here, in the process of growing the crystal from the seed crystal, the temperature setting value and shape of the resistance heater 8 and further the in-furnace member structure in the chamber 2 are adjusted, so that the GaAs single crystal 10 at the time of crystal growth is adjusted. The temperature gradient in the crystal was adjusted.

Next, a method for producing a GaAs single crystal using the vertical melt method will be described with reference to FIG.
A PBN crucible was used as the crucible 25 serving as a raw material container, and boron trioxide 26, which is a volatilization preventive material for GaAs polycrystals and As, was placed in the crucible 25. The charged weight was 20,000 g of GaAs polycrystal and 2,000 g of boron trioxide 26. In addition, a seed crystal 27 serving as a crystal was attached to the tip of the crucible 25. These were set in the chamber 22. Subsequently, the chamber 22 was evacuated and filled with an inert gas. Thereafter, the resistance heater 28 installed in the chamber 22 is energized, and the temperature in the chamber 22 is raised with the temperature gradient set so that the temperature increases from the lower part to the upper part. Was melted to obtain a GaAs melt 29. In this experiment, crystal growth was performed with the temperature gradient in the furnace set to 20 ° C./cm or less. Subsequently, the furnace temperature was raised until the GaAs melt 29 contacted the seed crystal 27 installed at the tip of the crucible 25, and seeding was performed. Subsequently, the GaAs single crystal was manufactured by solidifying the GaAs melt from the seed crystal 27 by lowering the set value of the resistance heater 28 at a constant rate.
As described above, a GaAs wafer was prepared by slicing, chamfering, and polishing the GaAs single crystal obtained by the two crystal manufacturing methods.

  Next, the annealing treatment experiment was performed using a wafer annealing experimental furnace 14 shown in FIG. This wafer annealing experimental furnace 14 has a structure in which a wafer arrangement plate 16 is provided in a chamber 15 and a GaAs wafer 18 is arranged on the upper surface thereof. In addition, a three-zone structure heater 17 having three heating zones in the lateral direction is arranged below the wafer arrangement plate 16. Each zone of the three-zone structure heater 17 is arranged so as to be located at both ends and the center of the GaAs wafer 18, and the temperature distribution in the wafer surface can be freely adjusted by adjusting the heater set temperature of these three zones. It is possible to adjust.

  In this experiment, the temperature of the wafer annealing experimental furnace 14 was set to 850 ° C. at the wafer center and 830 ° C. at both ends of the wafer, and the temperature difference between the center and both ends within the wafer surface was set to 20 ° C. Then, the time to reach this temperature set value was 30 minutes, held for 5 minutes, and then cooled to room temperature in 1 hour.

Under these temperature conditions, EPD and residual strain values were taken as parameters, and several combinations of wafers were prepared and experiments were conducted. Specifically, the wafer in-plane EPD value is 0.8, 1, 3, 5, 8, 10 (× 10 ⁴ pieces / cm ² ), and the in-wafer in-plane residual strain value (| Sr−St |) As for, wafers having a combination of 0.9 to 2.0 (× 10 ⁻⁵ ) were prepared and experiments were conducted. In this experiment, ten wafers were prepared for each combination of EPD and residual strain value, and the experiment was conducted, and the occurrence rate of slip dislocation at that time was examined. The results are shown in Table 4.

As is clear from the results in Table 4 above, the EPD value in the wafer surface is in the range of 30,000 / cm ^{2 to} 100,000 / cm ² , and the residual in the wafer surface. When the strain value | Sr-St | is in the range of 1.8 × 10 ⁻⁵ or less (shaded area in Table 4), the slip dislocation occurrence rate is 20% at the maximum, and the results show the effectiveness of the present invention. It became.

It is the schematic of the apparatus with which it uses for description of the manufacturing method of the GaAs single crystal by LEC method. It is the schematic of the apparatus with which it uses for description of the manufacturing method of the GaAs single crystal by a vertical melt method (VB method, VGF method). It is the schematic which showed the experimental furnace of the wafer annealing process. It is a graph which shows the correlation with the temperature gradient in the crystal | crystallization at the time of crystal growth, and EPD. It is a graph which shows the result of having measured the residual stress in a wafer surface, without implementing annealing treatment to the crystal | crystallization grown by setting the setting conditions of a temperature gradient to 20 degreeC / cm or more and 150 degrees C / cm or less.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 GaAs single crystal manufacturing apparatus of LEC method 2 Chamber 3 Pulling shaft 4 Crucible shaft 5 PBN crucible 6 Boron trioxide 7 Seed crystal 8 Resistance heater 9 GaAs melt 10 GaAs single crystal 14 Wafer annealing experimental furnace 15 Chamber 16 Wafer arrangement Plate 17 Three-zone structure heater 18 GaAs wafer 21 Vertical melt method (VB method, VGF method) GaAs single crystal manufacturing apparatus 22 Chamber 24 Crucible shaft 25 PBN crucible 26 Boron trioxide 27 Seed crystal 28 Resistance heater 29 GaAs melt liquid

Claims (3)

A semi-insulating GaAs wafer for electronic devices having a diameter of 10.16 cm (4 inches) or more manufactured by the LEC method, and the in- plane residual by measurement using a photoelastic phenomenon in which a deflection surface rotates depending on the magnitude of stress. The strain value (| Sr-St |) is in the range of 1.0 × 10 ⁻⁵ or less, and the dislocation density (EPD) in the wafer surface is 50,000 / cm ² or more and 100,000 / cm ^{2. A} semi-insulating GaAs wafer for electronic devices, characterized by being ² or less. ^{2. The} semi-insulating GaAs wafer for electronic devices according to claim 1, wherein a dislocation density (EPD) in the wafer surface is 80,000 / cm ² or more. By making the temperature gradient in the crystal when growing a GaAs single crystal by the LEC method 20 ° C./cm or more and 150 ° C./cm or less, the dislocation density (EPD) in the wafer surface is 50,000 / cm ^2. After the GaAs single crystal is grown at a rate of 100,000 / cm ² or less, the GaAs single crystal is further annealed, and the highest temperature reached during the annealing is 900 ° C. or higher and 1150 ° C. or lower. By setting the temperature gradient in the single crystal to 0 ° C./cm or more and 12.5 ° C./cm or less, the in-wafer in-plane residual strain value (| Sr-St |) is set to a range of 1.0 × 10 ⁻⁵ or less. A method for producing a semi-insulating GaAs wafer for electronic devices.

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