JP4712601B2 - Manufacturing method of simple matrix type liquid crystal display device - Google Patents

Description

  The present invention relates to a method for manufacturing a liquid crystal display (LCD). In particular, the present invention relates to a method for manufacturing an active matrix liquid crystal display device (hereinafter referred to as AM-LCD) using a semiconductor thin film. In addition, the present invention can be applied to an electro-optical device provided with such a display device.

  Note that in this specification, “semiconductor device” refers to all devices that function by using a semiconductor. Accordingly, the display device and the electro-optical device are also included in the category of the semiconductor device. However, in the specification, terms such as a display device and an electro-optical device are used properly so that they can be easily distinguished.

  In recent years, development of a projector using an AM-LCD as a projection display has been actively promoted. There is also an increasing demand for direct-view display for mobile computers and video cameras.

  Here, an outline of a configuration of a pixel matrix circuit in a conventional active matrix display device is shown in FIGS. Note that the pixel matrix circuit is a circuit in which thin film transistors (TFTs) for controlling an electric field applied to the liquid crystal are arranged in a matrix, and constitutes an image display area of the AM-LCD.

  FIG. 2A shows the pixel matrix circuit as viewed from above. Here, a region surrounded by a plurality of gate lines 201 provided in the horizontal direction and a plurality of source lines 202 provided in the vertical direction is a pixel region. A TFT 203 is formed at each intersection of the plurality of gate lines 201 and the plurality of source lines 202. In addition, a pixel electrode 204 is connected to each TFT.

  Therefore, the pixel matrix circuit is composed of a plurality of pixel regions formed in a matrix by being surrounded by a plurality of gate lines 201 and a plurality of source lines 202, and each pixel region is provided with a TFT 203 and a pixel electrode 204. It becomes the composition.

  A cross-sectional structure of the pixel matrix circuit is shown in FIG. 2B, reference numeral 205 denotes a substrate having an insulating surface, and 206 and 207 denote pixel TFTs formed over the substrate 205, which correspond to the TFT 203 in FIG.

  Further, pixel electrodes 208 and 209 are connected to the pixel TFTs 206 and 207, respectively. The pixel electrodes 208 and 209 correspond to the pixel electrode 204 in FIG. The pixel electrodes 208 and 209 are usually obtained by patterning a single metal thin film.

  Therefore, the pixel matrix circuit having the conventional structure always has electrode boundary portions (hereinafter simply referred to as boundary portions) 210 and 211 between the pixel electrodes. That is, a step corresponding to the film thickness of the pixel electrode is inevitably formed. Such a level difference causes a poor alignment of the liquid crystal material, which causes disturbance of the display image. In addition, irregular reflection of incident light generated at the stepped portion causes a decrease in contrast and a decrease in light utilization efficiency.

  In particular, the projection type display used in projectors and the like enlarges and projects a very high-definition small display of about 1 to 2 inches, and thus the above-described problems become apparent.

  Conventionally, the contrast ratio is increased by shielding a region where an image is disturbed by a black mask (or a black matrix). In recent years, the miniaturization of elements has progressed, and controllability of a shielding region for the purpose of high aperture ratio has been demanded. Therefore, a configuration in which a black mask is provided on a TFT side substrate has become mainstream.

  However, when the black mask is provided on the TFT side substrate, various problems such as an increase in patterning process, an increase in parasitic capacitance, and a decrease in aperture ratio occur. For this reason, a technique for ensuring a contrast ratio without causing the above-described problems is desired.

  The present invention solves the above problems and discloses means for forming an extremely high-definition active matrix display device by simple means.

The configuration of the invention disclosed in this specification is as follows.
A plurality of electrodes formed on a substrate having an insulating surface;
A DLC film covering the plurality of electrodes;
An insulating layer embedded in a boundary portion of the plurality of electrodes;
It is characterized by having at least.

In addition, the configuration of other inventions is as follows:
A first substrate and a translucent second substrate;
A liquid crystal layer sandwiched between the first substrate and the second substrate;
A semiconductor device including at least
Striped electrodes formed on the first substrate and the second substrate;
A DLC film covering the striped electrode;
An insulating layer embedded in a boundary portion of the striped electrode;
It is characterized by having at least.

In addition, the configuration of other inventions is as follows:
A plurality of semiconductor elements formed in a matrix on a substrate having an insulating surface;
A plurality of pixel electrodes connected to each of the plurality of semiconductor elements;
A semiconductor device having at least
A DLC film covering the pixel electrode;
An insulating layer embedded in a boundary portion of the pixel electrode;
It is characterized by having at least.

In addition, the configuration of other inventions is as follows:
A substrate having a plurality of semiconductor elements formed in a matrix and a plurality of pixel electrodes connected to each of the plurality of semiconductor elements;
A liquid crystal layer held on the substrate;
A semiconductor device including at least
A DLC film covering the pixel electrode;
An insulating layer embedded in a boundary portion of the pixel electrode;
It is characterized by having at least.

Moreover, the configuration of the invention for obtaining the above configuration is as follows:
Forming a plurality of electrodes on a substrate having an insulating surface;
Forming a DLC film covering the surfaces of the plurality of electrodes;
Forming an insulating layer on the DLC film;
Planarizing the insulating layer such that the surface of the DLC film and the surface of the insulating layer are coplanar;
It is characterized by including at least.

In addition, the configuration of other inventions is as follows:
A first substrate and a translucent second substrate;
A liquid crystal layer sandwiched between the first substrate and the second substrate;
A method for manufacturing a semiconductor device including at least
Forming a striped electrode on the first substrate;
Forming a DLC film covering the surface of the striped electrode;
Forming an insulating layer on the DLC film;
Planarizing the insulating layer such that the surface of the DLC film and the surface of the insulating layer are coplanar;
It is characterized by including at least.

In addition, the configuration of other inventions is as follows:
Forming a plurality of semiconductor elements over a substrate having an insulating surface;
Forming a plurality of pixel electrodes electrically connected to each of the plurality of semiconductor elements;
Forming a DLC film covering the surfaces of the plurality of pixel electrodes;
Forming an insulating layer on the DLC film;
Flattening the insulating layer such that the surface of the DLC film and the surface of the insulating layer are flush with each other, and embedding boundary portions of the plurality of pixel electrodes with the insulating layer;
It is characterized by including at least.

In addition, the configuration of other inventions is as follows:
A substrate having a plurality of semiconductor elements formed in a matrix and a plurality of pixel electrodes connected to each of the plurality of semiconductor elements;
A liquid crystal layer held on the substrate;
A method for manufacturing a semiconductor device including at least
Forming a DLC film covering the surfaces of the plurality of pixel electrodes;
Forming an insulating layer on the DLC film;
Flattening the insulating layer such that the surface of the DLC film and the surface of the insulating layer are flush with each other, and embedding boundary portions of the plurality of pixel electrodes with the insulating layer;
It is characterized by including at least.

Here, DLC is an abbreviation for “Diamond Like Corbon”, which is carbon having a physical property like diamond or a thin film having high hardness mainly composed of carbon. Also referred to as i-carbon, it is mainly composed of sp ³ bonds.

The DLC film has a Vickers hardness as high as 2000 kg / mm ² or more and a friction coefficient as small as 0.4 or less, so it is used as a protective film or a lubricating film. However, if the hydrogen content is excessively high, the film quality becomes soft, so that it cannot be applied to the present invention.

The characteristic as a DLC film appears notably in Raman data. Here, FIG. 12 shows Raman data of the DLC film used in the present invention. The light source is Ar ⁺ laser, the laser beam diameter is 1 μmφ, the light source output is 1.0 mW, the slit width is 100 μm, the integration time is 300 seconds × 2, and it is measured at room temperature in the atmosphere.

As shown in FIG. 12, the Raman peaks of the DLC film appear in the vicinity of 1550 cm ^-1, the Raman distribution spreading in broad shape is obtained around the vicinity of 1550 cm ^-1. Another characteristic of the DLC film is that the Raman distribution is asymmetric around 1550 cm ⁻¹ .

In the Raman data of diamond, a steep Raman peak appears in the vicinity of 1330 cm ⁻¹ so that it can be easily distinguished. In addition, a carbon film (considered from DLC) having a soft film quality due to collapse of the crystal structure can be easily distinguished because two Raman peaks appear or no clear Raman peak appears.

  In the configuration of the present invention, as a typical example of the state in which the liquid crystal layer is held, a substrate having a plurality of pixel electrodes (first substrate) and a counter substrate (second substrate) facing the first substrate ) Between the liquid crystal layer. Note that in the case of using PDLC (polymer dispersion type liquid crystal) as the liquid crystal layer, the liquid crystal layer itself is solidified, and thus the second substrate may not be necessary.

  A thin film transistor (TFT) is typical as a semiconductor element, but an insulating gate type field effect transistor (IGFET), a thin film diode, a MIM (Metal-Insulator-Metal) element, a varistor element or the like may be used.

  A liquid crystal display device using the present invention has a configuration in which gaps between individual pixel electrodes arranged in a matrix (interval between pixels) are filled with a buried insulating layer. At this time, since the surface of the pixel electrode and the surface of the buried insulating layer substantially coincide with each other, the stepped portion generated in the gap between the pixel electrodes is almost completely flattened.

  Therefore, various problems such as poor alignment of the liquid crystal material due to the stepped portion and lowering of contrast due to irregular reflection of incident light are solved. Thereby, a liquid crystal display device having high-definition display performance can be realized.

  The buried insulating layer can be obtained by flattening a thick insulating layer. In particular, when flattening by a mechanical polishing process (CMP polishing process), the buried insulating layer is provided between the pixel electrode and the insulating film. By forming the DLC film, it is possible to prevent the pixel electrode from being unnecessarily polished.

  That is, since the CMP polishing process is substantially completed when the DLC film is exposed, the control of the processing time is greatly simplified. This is very effective in improving the manufacturing yield.

  Here, a brief description of the present invention will be given with reference to FIG. In FIG. 1A, reference numeral 101 denotes a substrate having an insulating surface, and reference numerals 102 and 103 denote pixel TFTs formed on the substrate 101. Further, pixel electrodes 105 and 106 are formed on the pixel TFTs 102 and 103 via an interlayer insulating film 104. The pixel electrodes 105 and 106 are electrically connected to the pixel TFTs 102 and 103, respectively, and the pixel electrodes are electrically insulated at the boundary portions 107 and 108.

  The feature of the present invention is that a DLC film 109 having a thickness of 10 to 50 nm is formed so as to cover the pixel electrodes 105 and 106. When the state of FIG. 1A is obtained, an insulating film 110 for embedding the boundary portions 107 and 108 of the pixel electrode is formed on the pixel electrodes 105 and 106. Note that when a thin film having a light shielding property (such as a light absorption layer) is used as the insulating layer 110, the insulating layer 110 can function as a black mask.

  Next, a planarization step of the insulating layer 110 as shown in FIG. Typically, a method of flattening by mechanical polishing is effective. A typical example of the mechanical polishing is a CMP (chemical mechanical polishing) technique. The CMP technique is a technique for flattening the surface of a thin film by chemical etching with a chemical solution and mechanical polishing with an abrasive (abrasive grains), and an excellent flat surface can be obtained.

  In addition to mechanical polishing, an etch back technique using a dry etching method can also be used. The etch-back technique is inferior to the CMP technique in terms of flatness, but has advantages such as the fact that no additional apparatus is required and particles (dust) are not generated during processing.

  In the present invention, as the insulating layer 110 is polished, the surface of the DLC film 109 appears. At this time, since the DLC film 109 has very high hardness, the progress of the mechanical polishing process stops here. That is, the planarization process is completed when the DLC film 109 is exposed.

  Therefore, the buried insulating layers 111 and 112 are formed in the state as shown in FIG. Note that a dotted line in FIG. 1B shows the shape of the insulating layer 110 before the polishing process, and shows the state in which the insulating layer 110 is scraped by the mechanical polishing process.

  In the final state as shown in FIG. 1C, the boundary portions 107 and 108 formed between the pixel electrodes are completely filled with the buried insulating layers 111 and 112. At this time, the surfaces of the pixel electrodes 105 and 106 and the surfaces of the buried insulating layers 111 and 112 are on the same plane.

  As described above, according to the present invention, the boundary between the pixel electrodes is filled with the buried insulating layer, and unnecessary steps are eliminated. By doing so, it is possible to obtain an extremely high-definition active matrix display device that does not cause problems such as conventional alignment defects of liquid crystal materials and irregular reflection of light at the stepped portions.

  In this embodiment, an example of a process for manufacturing a pixel matrix circuit of a reflective LCD using the present invention will be described with reference to FIGS. Note that since the present invention is a technique related to planarization of a pixel, the TFT structure itself is not limited to the present embodiment.

  First, a substrate 301 having an insulating surface is prepared. In this embodiment, a silicon oxide film is formed as a base film on a glass substrate. Active layers 302 to 304 made of a crystalline silicon film are formed on the substrate 301. Although only three TFTs are described in this embodiment, in reality, one million or more TFTs are formed in the pixel matrix circuit.

  In this embodiment, an amorphous silicon film is thermally crystallized to obtain a crystalline silicon film. Then, the crystalline silicon film is usually patterned by a photolithography process to obtain active layers 302 to 304. In this embodiment, a catalyst element (nickel) that promotes crystallization is added during crystallization. This technique is described in detail in Japanese Patent Application Laid-Open No. 7-130652.

  Next, a silicon oxide film having a thickness of 150 nm is formed as the gate insulating film 305, and an aluminum film (not shown) containing 0.2 wt% scandium is formed thereon, and the gate electrode is formed by patterning. A prototype island-like pattern is formed.

  In this embodiment, the technique described in Japanese Patent Laid-Open No. 7-13518 is used here. For details, refer to the publication.

  First, anodization is performed in a 3% oxalic acid aqueous solution while leaving the resist mask used for patterning on the island pattern. At this time, a formation current of 2 to 3 mV is passed using the platinum electrode as a cathode, and the ultimate voltage is 8V. Thus, porous anodic oxide films 306 to 308 are formed.

  Thereafter, after removing the resist mask, anodization is performed in a solution obtained by neutralizing an ethylene glycol solution of 3% tartaric acid with aqueous ammonia. At this time, the formation current may be 5 to 6 mV, and the ultimate voltage may be 100V. Thus, dense anodic oxide films 309 to 311 are formed.

  The gate electrodes 312 to 314 are defined by the above process. In the pixel matrix circuit, gate lines for connecting the gate electrodes are formed for each line simultaneously with the formation of the gate electrodes. (Fig. 3 (A))

Next, the gate insulating film 305 is etched using the gate electrodes 312 to 314 as a mask. Etching is performed by a dry etching method using CF ₄ gas. As a result, a gate insulating film having a shape shown by 315 to 317 is formed.

  In this state, impurity ions imparting one conductivity are added by an ion implantation method or a plasma doping method. In this case, P (phosphorus) ions may be added if the pixel matrix circuit is composed of N-type TFTs, and B (boron) ions may be added if it is composed of P-type TFTs.

  Note that the impurity ion addition step is performed in two steps. The first is performed at a high acceleration voltage of about 80 keV, and is adjusted so that the peak of impurity ions comes under the end portions (protruding portions) of the gate insulating films 315 to 317. The second time is performed with a low acceleration voltage of about 5 keV, and adjustment is made so that impurity ions are not added under the end portions (protruding portions) of the gate insulating films 315 to 317.

  In this way, TFT source regions 318 to 320, drain regions 321 to 323, low-concentration impurity regions (also referred to as LDD regions) 324 to 326, and channel formation regions 327 to 329 are formed. (Fig. 3 (B))

  At this time, it is preferable to add impurity ions to the source / drain region to such an extent that a sheet resistance of 300 to 500 Ω / □ can be obtained. Further, the low concentration impurity region needs to be optimized in accordance with the performance of the TFT. Further, after the impurity ion addition step is completed, heat treatment is performed to activate the impurity ions.

  Next, a silicon oxide film having a thickness of 400 nm is formed as the first interlayer insulating film 330, and source electrodes 331 to 333 and drain electrodes 334 to 336 are formed thereon. (Figure 3 (C))

  Next, a silicon oxide film is formed to a thickness of 0.5 to 1 μm as the second interlayer insulating film 337. Note that an organic resin film can also be used as the second interlayer insulating film 337. As the organic resin film, polyimide, polyamide, polyimide amide, acrylic, or the like can be used.

  After the second interlayer insulating film 337 is formed, an aluminum film to which 1 wt% titanium is added is formed to a thickness of 100 nm, and pixel electrodes 338 to 340 are formed by patterning. Of course, other metal materials may be used.

  Next, a DLC film 341 is formed so as to cover the pixel electrodes 338 to 340. For the DLC film, a vapor phase film forming method such as a plasma CVD method, an ECR plasma CVD method, a sputtering method, an ion beam sputtering method, or an ionized vapor deposition method can be used.

  Hydrocarbon is used as a source gas for forming the DLC film. Examples of the hydrocarbon include saturated hydrocarbons such as methane, ethane, and propane, and unsaturated hydrocarbons such as ethylene and acetylene. Alternatively, a halogenated hydrocarbon in which one or a plurality of hydrogen atoms in a hydrocarbon molecule is substituted with a halogen element may be used.

  In addition to hydrocarbons, it is effective to add hydrogen. When hydrogen is added, hydrogen radicals in the plasma increase, and the effect of improving the film quality by extracting excess hydrogen in the film can be expected. At this time, the ratio of the hydrogen gas flow rate to the total gas flow rate is 30 to 90%, preferably 50 to 70%. If this ratio is too large, the film formation rate decreases, and if it is too small, the effect of extracting excess hydrogen is lost.

  Furthermore, helium can be added as a carrier gas for diluting the source gas, and argon can be added as a sputtering gas in the case of sputtering. It is also effective to add a group 13-15 element as described in JP-A-6-208721.

The reaction pressure is 5 to 1000 mTorr, preferably 10 to 100 mTorr. High frequency power is normally 13.56MHz. At this time, RF power to be applied 0.01~1W / cm ^2, preferably between 0.05 to 0.5 / cm ^2. In addition, it is effective to add an excitation effect by microwave of 2.45 GHz to promote decomposition of the source gas, or to form an 875 Gauss magnetic field in the excitation space and use electron spin resonance.

  In this embodiment, 50 sccm of methane gas and 50 sccm of hydrogen gas are introduced into the reaction space of the plasma CVD apparatus, the deposition pressure is 10 mTorr, the RF power is 100 W, and the temperature of the reaction space is room temperature. Further, a DC bias of 200 V is applied as a substrate bias, and an electric field is formed so that particles (ions) in the plasma are incident on the surface to be formed, thereby improving the film quality and improving the hardness.

  Further, according to the experiments by the present inventors, when the DLC film is formed, the friction coefficient of the surface becomes 0.2 to 0.4 even when the center line average roughness (Ra) is 10 nm, which is smaller than the practical friction coefficient 0.4. can do. Moreover, the friction coefficient hardly changes even when the surface is repeatedly oscillated. This means that even a DLC film having a thickness of 10 nm can sufficiently function as a stopper during the CMP polishing process.

  The friction coefficient depends on the DLC film thickness, and becomes smaller as the DLC film thickness increases. Accordingly, it is sufficient that the thickness of the DLC film is 10 nm or more, but if it is too thick, the electric field applied to the liquid crystal is weakened, so about 10 to 50 nm is preferable.

  In addition, in the reflective LCD, there is a technique called an enhanced reflection process that improves the reflectance by forming a dielectric on the surface of the pixel electrode. This utilizes the phenomenon that the reflectance of the pixel electrode generally changes depending on the film thickness of the dielectric, and the film thickness of the dielectric correlates with the wavelength of incident light. Therefore, also in this embodiment, the reflectivity can be increased by optimizing the thickness of the DLC film according to the incident light.

  For further details of the DLC film forming method, film forming apparatus, and the like, it is preferable to refer to Japanese Patent Publication Nos. 3-72711, 4-27690, and 4-27191 by the present inventors. .

  After the DLC film 341 is formed as described above, an insulating layer 342 for filling the boundary (gap) of the pixel electrode is formed next. Note that when the pixel electrode is formed so that the boundary portion is formed on the source wirings 331 to 333 as in the present embodiment, the source wirings 331 to 333 function as a black mask, so that the insulating layer 342 is translucent. It does not matter.

  However, in order to ensure a more reliable light shielding function, the insulating layer 342 has a light shielding property such as an organic resin film (a solution-coated silicon oxide film such as PSG) in which a black pigment or carbon is dispersed. It is preferable to use an insulating film. By doing so, a reliable light shielding function can be achieved even when the source wiring becomes thin or light from an oblique direction.

  Further, by using a material having a relative dielectric constant as low as possible as compared with the liquid crystal material to be used, formation of a lateral electric field between the pixel electrodes can be suppressed.

  When the state shown in FIG. 4A is obtained in this way, a CMP polishing step is performed as a planarization step of the insulating layer 342 to form buried insulating layers 343 to 345 in the gaps between the pixel electrodes 338 to 340. (Fig. 4 (B))

  At this time, since the surfaces of the pixel electrodes 338 to 340 and the surfaces of the buried insulating layers 343 to 345 substantially coincide, an excellent flat surface can be obtained. Further, since the surfaces of the pixel electrodes 338 to 340 are protected by the DLC film 341, it is possible to prevent the polishing from proceeding more than necessary.

  The figure which looked at this state from the upper surface is shown in FIG. FIG. 6 is a simplified view focusing on the pixel matrix circuit, and the structure of FIG. 4B corresponds to a cross-sectional view taken along A-A ′ in FIG. 6. 6 correspond to the symbols used in FIGS. 4A and 4B.

  As shown in FIG. 6, the pixel electrodes are arranged in a matrix, and the surface thereof is covered with a DLC film 341. Further, the boundary portion of the pixel electrode is buried with buried insulating layers 343 to 345. Therefore, although the embedded insulating layers 343 to 345 are respectively provided with reference numerals, they are actually integrated in a matrix.

  As described above, the pixel matrix circuit is completed. Actually, a drive circuit for driving the pixel TFT and the like are simultaneously formed on the same substrate. Such a substrate is usually called a TFT side substrate or an active matrix substrate. In this specification, the active matrix substrate is referred to as a first substrate.

  When the first substrate is completed, a counter substrate in which a counter electrode 347 is formed is attached to a light-transmitting substrate 346 (this substrate is referred to as a second substrate in this specification), and a liquid crystal is interposed therebetween. The layer 348 is sandwiched. In this way, a reflective LCD as shown in FIG. 4C is completed.

  This cell assembling step may be performed according to a known method. It is also possible to disperse a dichroic dye in the liquid crystal layer or provide a color filter on the counter substrate. The type of the liquid crystal layer, the presence / absence of the color filter, and the like vary depending on the mode in which the liquid crystal is driven, so that the practitioner may determine as appropriate.

  In this embodiment, an example of a process for manufacturing a pixel matrix circuit of a transmissive LCD using the present invention will be described with reference to FIGS. Since the process up to the middle is the same as the manufacturing process of the reflective LCD shown in the first embodiment, only different points will be described here.

The state shown in FIG. 5A is a state in which the pixel electrodes 501, 502, the DLC film 503, and the buried insulating film 504 are formed in the same procedure as the process shown in the first embodiment. In this embodiment, a transparent conductive film (ITO, SnO ₂ or the like) is used as a material for the pixel electrodes 501 and 502. At this time, the pixel electrodes 501 and 502 are formed so as not to overlap the TFT.

  In this embodiment, polyimide or the like in which a black pigment is dispersed is used for the insulating film 504. In the case of the transmissive type, since the TFT active layer also needs to be shielded from light, it is preferable to use an insulating film having a light shielding property.

  Next, a CMP polishing process is performed to form buried insulating layers 505 and 506 that are flush with the pixel electrodes 501 and 502 (more precisely, the DLC film 503). (Fig. 5B)

  The figure which looked at this state from the upper surface is shown in FIG. FIG. 7 is a simplified view focusing on the pixel matrix circuit, and the structure of FIG. 5B corresponds to a cross-sectional view taken along B-B ′ in FIG. 7. In addition, each code in FIG. 7 corresponds to the code used in FIGS. 5 (A) and 5 (B).

  As shown in FIG. 7, the plurality of pixel electrodes are arranged in a matrix, and the surface thereof is covered with a DLC film 503. In addition, the boundary portion of the pixel electrode is embedded with integrated embedded insulating layers 505 and 506. Further, in this embodiment, since the buried insulating layers 505 and 506 are also formed on the TFT, it is possible to prevent the resistance from being changed due to light being applied to the active layer.

  As described above, the TFT side substrate of the transmissive LCD is completed. When the TFT side substrate is completed, a liquid crystal layer 509 is sandwiched between the light transmitting substrate 507 and the counter substrate made of the counter electrode 508 and the TFT side substrate by a normal cell assembling process. Thus, a transmissive LCD as shown in FIG. 5C is completed.

  In the first embodiment, it is effective to planarize the pixel electrodes 338 to 340 before forming the DLC film 341. The planarization step is preferably performed by CMP polishing.

  In the present invention, since the DLC film is used as a stopper film in the mechanical polishing process, the surface state of the pixel electrode is directly reflected in the surface state of the DLC film. Therefore, when flatness is required on the surface of the pixel electrode as in a reflective LCD, the pixel electrode needs to have a high flatness in advance.

  In this embodiment, an example in which a TFT having a structure different from the TFT shown in Embodiment 1 is used as a semiconductor element for performing active matrix driving will be described. Note that the TFT having the structure described in this embodiment can be easily applied to the second embodiment.

  In the first embodiment, a coplanar type TFT which is a typical top gate type TFT is described as an example, but a bottom gate type TFT may be used. FIG. 8 shows an example using an inverted staggered TFT, which is a typical example of a bottom gate TFT.

  In FIG. 8, 801 is a glass substrate, 802 and 803 are gate electrodes, 804 is a gate insulating film, and 805 and 806 are active layers. The active layers 805 and 806 are composed of silicon films to which impurities are not intentionally added.

  Reference numerals 807 and 808 denote source electrodes, reference numerals 809 and 810 denote drain electrodes, and reference numerals 811 and 812 denote silicon nitride films serving as channel stoppers (or etching stoppers). That is, in the active layers 805 and 806, regions located under the channel stoppers 811 and 812 substantially function as channel forming regions.

  The above is the basic structure of the inverted staggered TFT. In this embodiment, such an inverted stagger type is covered with an interlayer insulating film 813 made of an organic resin film, and pixel electrodes 814 and 815 are formed thereon. Then, a buried insulating film is formed in a state where the pixel electrodes 814 and 815 are protected by the DLC film, and planarized by a CMP polishing process. Accordingly, the gap between the pixel electrodes is filled with the buried insulating layers 817 and 818.

  Next, an example in which an insulated gate field effect transistor (IGFET) is formed as the semiconductor element of the present invention will be described. The IGFET is also called a MOSFET and refers to a transistor formed on a silicon wafer.

  In FIG. 9, 901 is a glass substrate, 902 and 903 are source regions, and 904 and 905 are drain regions. The source / drain regions can be formed by adding impurities by ion implantation and thermally diffusing. Note that reference numeral 906 denotes an element isolation oxide, which can be formed using a normal LOCOS technique.

  Next, 907 is a gate insulating film, 908 and 909 are gate electrodes, 910 is a first interlayer insulating film, 911 and 912 are source electrodes, and 913 and 914 are drain electrodes. This is covered with a second interlayer insulating film 915, and pixel electrodes 916 and 917 are formed thereon. Also in this case, the pixel electrodes 916 and 917 are protected by the DLC film 918, and buried insulating layers 919 and 920 are buried in the boundary portions.

  In addition to the IGFET, top gate type, or bottom gate type TFT shown in this embodiment, the present invention can be applied to an active matrix display using a thin film diode, an MIM element, a varistor element, or the like.

  As described above, the present invention can be applied to a reflective LCD or a transmissive LCD using a semiconductor element having any structure.

  In particular, the reflective liquid crystal LCD has an advantage that the pixel area can be maximized by flattening a semiconductor element and forming a pixel electrode thereon. The present invention is an effective technique for more effectively using the advantages. Therefore, the reflective LCD using the present invention can achieve a high resolution and a high aperture ratio.

  In Embodiment 1, it is effective to planarize the second interlayer insulating film 337 before forming the pixel electrodes 338 to 340.

  Examples of the method for planarizing the interlayer insulating film include a method by thickening the interlayer insulating film, a method by leveling using an organic resin film, a method by mechanical polishing, a method by etch back technology, etc. The most effective way to obtain a flat surface is by mechanical polishing.

  A typical example of the mechanical polishing method is a CMP (Chemical Mechanical Polishing) technique. The CMP technique is a polishing technique that combines chemical etching with a chemical solution and mechanical polishing with an abrasive.

  According to this embodiment, the pixel electrodes 338 to 340 are formed on an excellent flat surface, and a pixel electrode having a high reflectance can be obtained. That is, it is very effective when used for applications such as a projection display.

  The present invention can also be applied to a simple matrix type liquid crystal display device. In this case, striped electrodes are formed on each of the pair of substrates, and the substrates are bonded so that the electrodes are orthogonal to each other, so that the liquid crystal layer is sandwiched.

  In this case, if one is a light-transmitting substrate, the other may be light-transmitting or light-blocking. However, the striped electrode formed on the translucent substrate side needs to be formed of a transparent conductive film.

  In this embodiment, stripe electrodes are formed of aluminum or a material containing aluminum as a main component on the side of the substrate that is paired with the light-transmitting substrate, and a gap between the electrodes extending in the stripe shape is filled with an insulating layer.

  When the present invention is applied to a simple matrix LCD, an effect of reducing crosstalk between adjacent electrodes can be obtained by using a material having a lower dielectric constant (such as an organic resin material) as an insulating layer than a liquid crystal layer. .

  A reflective LCD formed by applying the present invention can utilize various liquid crystal display modes. For example, an ECB (electric field control birefringence) mode, a PCGH (phase transition guest / host) mode, an OCB mode, a HAN mode, and a PDLC guest / host mode may be mentioned.

  The ECB mode is a display mode in which the voltage applied to the liquid crystal layer is changed to change the orientation of the liquid crystal, and a change in birefringence of the liquid crystal layer that occurs at that time is detected by a pair of polarizing plates to perform color display. In this case, since a method not using a color filter is used, bright display is possible.

  The PCGH mode is a display mode in which a dichroic dye is mixed with guest molecules in a host liquid crystal, the alignment state of the liquid crystal molecules is changed by a voltage applied to the liquid crystal, and the light absorption rate of the liquid crystal layer is changed. In this case, since a method not using a polarizing plate can be taken, high contrast can be obtained.

  The PDLC mode is a display mode using a polymer dispersion type liquid crystal in which a polymer is dispersed in a liquid crystal (or a liquid crystal is dispersed in a polymer). In this case, since a polarizing plate is unnecessary, bright display is possible. Further, if a solid polymer dispersed liquid crystal is used, it is possible to adopt a configuration in which a glass substrate is not used on the opposite side.

  In these various display modes, the presence or absence of a polarizing plate and the presence or absence of a color filter can be freely set according to the characteristics. For example, in the PCGH mode, since a polarizing plate is not necessary, a bright display can be realized even as a single plate type using a color filter.

  In this embodiment, an example of an electro-optical device using the present invention as a display will be described. First, the case where the reflective LCD shown in Embodiment 1 is applied to a three-plate projector will be described with reference to FIG.

  In FIG. 10A, light including R (red), B (blue), and G (green) output from a light source 11 such as a metal halide lamp or a halogen lamp is reflected by a polarization beam splitter 12 and is a cross dichroic mirror. Proceed to step 13.

  The polarization beam splitter is an optical filter having a function of reflecting or transmitting light depending on the polarization direction of light. In this case, the light from the light source 11 is polarized so as to be reflected by the polarization beam splitter 12.

  At this time, the cross dichroic mirror 13 reflects the R component light in the direction of the liquid crystal panel 14 corresponding to R, and reflects the B component light in the direction of the liquid crystal panel 15 corresponding to B. The G component light passes through the cross dichroic mirror 13 and enters the liquid crystal panel 16 corresponding to G.

  In each liquid crystal panel, liquid crystal molecules are aligned so that when the pixels are in an off state, the liquid crystal panels are reflected without changing the polarization direction of the incident light. Further, when the pixel is in the ON state, the alignment state of the liquid crystal layer is changed, and the polarization direction of incident light is changed accordingly.

  The light reflected by these liquid crystal panels 14 to 16 is again reflected by the cross dichroic mirror 13 (only the G component light is transmitted) and is combined, and enters the polarization beam splitter 12 again.

  At this time, the light reflected by the pixel region in the on state is transmitted through the polarization beam splitter 12 because the polarization direction changes. On the other hand, the light reflected by the pixel region in the off state is reflected by the polarization beam splitter 13 because the polarization direction does not change.

  In this way, by controlling on / off of the pixel regions arranged in a matrix in the pixel matrix circuit with a plurality of semiconductor elements, only the light reflected by the specific pixel region can pass through the polarization beam splitter 12. Become. This operation is common to the liquid crystal panels 14-16.

  As described above, the light including the image information transmitted through the polarization beam splitter 12 is enlarged and projected by the optical system lens 17 constituted by a projection lens or the like and projected on the screen 18.

  A reflective LCD using the present invention realizes high resolution and high aperture ratio by embedding between pixel electrodes. Further, when the pixel electrode is flattened, a high reflectance is realized. Therefore, excellent display performance can be realized even in an electro-optical device that enlarges and projects an image like the projection type projector of FIG.

  Next, a case where the transmissive LCD shown in Embodiment 2 is applied to a three-plate projector will be described with reference to FIG.

  In FIG. 10B, 19 is a light source such as a halogen lamp, and 20 is a reflector. The light containing the RGB components first enters the dichroic mirror 21 where only the R component light is reflected. The R component light is reflected by the reflector 22 and enters the liquid crystal panel 23 corresponding to R.

  The light transmitted through the dichroic mirror 21 is incident on the dichroic mirror 24, where only the B component light is reflected. The reflected B component light is incident on the liquid crystal panel 25 corresponding to B. Further, the G component light transmitted through the dichroic mirror 24 enters the liquid crystal panel 26 corresponding to G.

  The R component light is combined with the B component light by the dichroic mirror 27 and is incident on the dichroic mirror 28. The G component light is reflected by the reflector 29 and enters the dichroic mirror 28. Here, all the component lights of the RBG are combined, enlarged and projected by the projection lens 30, and displayed on the screen 31.

  Since the transmissive LCD using the present invention also achieves a high resolution and a high aperture ratio, an electro-optical device having excellent display performance can be configured. In particular, the high aperture ratio is the greatest advantage of the transmissive LCD of the present invention.

  In this embodiment, an application product (electro-optical device) to which the liquid crystal display device according to the present invention can be applied will be described with reference to FIG. Examples of the electro-optical device using the present invention include a video camera, a still camera, a projector, a head mounted display, a car navigation, a personal computer, a portable information terminal (mobile computer, cellular phone, etc.), and the like.

  FIG. 11A illustrates a mobile computer, which includes a main body 2001, a camera unit 2002, an image receiving unit 2003, operation switches 2004, and a display device 2005. When the reflective LCD of the present invention is applied to the display device 2005, further downsizing and low power consumption can be achieved.

  FIG. 11B illustrates a head mounted display, which includes a main body 2101, a display device 2102, and a band portion 2103. By applying the reflective LCD of the present invention to the display device 2102, the size of the device can be greatly reduced.

  FIG. 11C illustrates a front projector, which includes a main body 2201, a light source 2202, a display device 2203, an optical system 2204, and a screen 2205. By adopting the transmissive LCD of the present invention for the display device 2203, a high-definition image is realized.

  FIG. 11D illustrates a mobile phone, which includes a main body 2301, an audio output portion 2302, an audio input portion 2303, a display device 2304, operation switches 2305, and an antenna 2306. By applying the present invention to the display device 2304, a display monitor with excellent visibility can be mounted.

  FIG. 11E illustrates a video camera which includes a main body 2401, a display device 2402, an audio input portion 2403, operation switches 2404, a battery 2405, and an image receiving portion 2406. By applying the present invention to the display device 2402, display performance that can sufficiently withstand outdoor shooting can be realized.

  FIG. 11F illustrates a rear projector, which includes a main body 2501, a light source 2502, a display device 2503, a beam splitter 2504, reflectors 2505 and 2506, and a screen 2507. By applying the reflective LCD of the present invention to the display device 2402, the device can be thinned and a high-definition image can be realized.

  In the case of a direct-view display as shown in FIGS. 11A, 11B, 11D, and 11E, it is effective to form irregularities on the surface of the pixel electrode. Thereby, the light scattering effect is enhanced, and the viewing angle and visibility are improved. Conversely, in the case of a projection display as shown in FIGS. 11C and 11F, the surface of the pixel electrode is preferably in a mirror state. Thereby, irregular reflection of light is reduced, and a color shift and a reduction in resolution are suppressed.

  As described above, the application range of the present invention is extremely wide and can be applied to display media in various fields. In particular, when the liquid crystal display device is used in a projection type display device such as a projector, a very high resolution is required. In such a case, the present invention is a very effective technique.

  In addition, portable information terminal devices typified by mobile computers, mobile phones, and video cameras are desired to have smaller devices and lower power consumption. In such a case, the reflective LCD of the present invention which does not require a backlight is effective.

The figure for demonstrating the outline of this invention. The figure which shows the structure of the conventional pixel matrix circuit. 10A and 10B show a manufacturing process of a reflective LCD. 10A and 10B show a manufacturing process of a reflective LCD. 10A and 10B show a manufacturing process of a transmissive LCD. The figure which looked at the pixel matrix circuit from the upper surface. The figure which looked at the pixel matrix circuit from the upper surface. The figure which shows the structure of an active matrix substrate. The figure which shows the structure of an active matrix substrate. FIG. 3 is a diagram illustrating a configuration of a projector. The figure for demonstrating an example of the applied product of this invention. The figure which shows the Raman data of a DLC film.

Explanation of symbols

101 Glass substrate 102, 103 Pixel TFT
104 Interlayer insulating films 105 and 106 Pixel electrodes 107 and 108 Boundary portion 109 DLC film 110 Insulating layers 111 and 112 for embedding Embedded insulating layers

Claims (9)

Forming a first striped electrode on a first substrate;
Forming a first DLC film covering the surface of the first stripe-shaped electrode;
Forming a first insulating layer on the first DLC film;
The first insulating layer is planarized so that the surface of the first DLC film located on the first stripe-shaped electrode and the surface of the first insulating layer are flush with each other, Burying each boundary portion of the stripe-shaped electrode with the first insulating layer,
Forming the first DLC film located on the first stripe-shaped electrode and the liquid crystal layer on the first insulating layer;
A method for manufacturing a simple matrix liquid crystal display device, comprising: Forming a first striped electrode on a first substrate;
Forming a first DLC film covering the surface of the first stripe-shaped electrode;
Forming a first insulating layer on the first DLC film;
The first insulating layer is planarized so that the surface of the first DLC film located on the first stripe-shaped electrode and the surface of the first insulating layer are flush with each other, Burying each boundary portion of the stripe-shaped electrode with the first insulating layer,
Forming a second striped electrode on the second substrate;
Forming a second DLC film covering the surface of the second stripe electrode;
Forming a second insulating layer on the second DLC film;
The second insulating layer is planarized so that the surface of the second DLC film located on the second stripe-shaped electrode and the surface of the second insulating layer are flush with each other, Burying each boundary portion of the stripe-shaped electrode with the second insulating layer;
Bonding the first substrate and the second substrate so that the first stripe electrode and the second stripe electrode are orthogonal to each other, and sandwiching the liquid crystal layer. A manufacturing method of a characteristic simple matrix type liquid crystal display device. 3. The method for manufacturing a simple matrix liquid crystal display device according to claim 2 , wherein the thickness of the second DLC film is 10 to 50 nm. According to claim 2 or claim 3, wherein the second insulating layer, a method for manufacturing a passive matrix type liquid crystal display device, characterized in that the lower dielectric constant than that of the liquid crystal layer. In any one of claims 1 to 4, wherein the first insulating layer, a method for manufacturing a passive matrix type liquid crystal display device, characterized in that the lower dielectric constant than that of the liquid crystal layer. In any one of claims 1 to 5, a simple matrix type liquid crystal, characterized in that a step of planarizing the first stripe electrodes before the step of forming the first DLC film A method for manufacturing a display device. In any one of claims 1 to 6, the method for manufacturing a passive matrix type liquid crystal display device wherein the first insulating layer, characterized in that it has a light blocking property. In any one of claims 1 to 7, a method for manufacturing a passive matrix type liquid crystal display device wherein the first insulating layer is an organic resin film. In any one of claims 1 to 8, a method for manufacturing a passive matrix type liquid crystal display device, characterized in that the thickness of the first DLC film is 10 to 50 nm.

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