JPH07230103A - Liquid crystal display device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a liquid crystal display device capable of performing high definition image display with high luminance and high contrast. CONSTITUTION:A dielectric layer 14 and a second electrode 15 are adhered by stacking sequentially on the side wall plane of a semiconductor layer 9 including the active layer of a thin film transistor element in the horizontal direction for a substrate so as to be erected perpendicularly (three-dimensionally) to the periphery circulating a picture element aperture part. In this way, since an auxiliary capacitor 16 can be formed in shape so as to be erected for the main plane of a substrate 6, the projecting occupied area of the auxiliary capacitor on the plane of the substrate 6 can be effectively decreased, and a picture element numerical aperture can be improved up to around twice as much.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a method of manufacturing the same, and more particularly, to secure a sufficient capacitance value of an auxiliary capacitance while reducing a projected occupation area of the auxiliary capacitance on a planar substrate surface. The present invention relates to a liquid crystal display device having a high display quality with good luminance characteristics, which realizes a large number of pixels and high definition of a screen and an improvement in the aperture ratio of a pixel portion for each pixel, and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, liquid crystal display devices have been studied for higher definition of image display, and have been miniaturized and highly integrated.
The display quality has been further improved. In particular, a projection-type liquid crystal display device, which is a so-called liquid crystal projector using a liquid crystal display panel as a light valve for image formation, is being studied for practical use, and some have already been commercialized.

Since such a liquid crystal projector is capable of displaying a larger screen size with a device body that is smaller and lighter than a CRT display or the like.
In particular, attempts have been made to further reduce the size and weight of a liquid crystal display panel including a display screen and a liquid crystal drive circuit system by using a thin film transistor (TFT) having excellent operating characteristics such as contrast ratio and response speed.

As a technical problem given to such a liquid crystal projector, it is necessary to achieve both high definition and high brightness of the screen.

In the active matrix type liquid crystal display device, the area ratio (aperture ratio) of the pixel openings to the entire screen becomes remarkably reduced as the device is miniaturized and the screen is made finer. Finally, there is a problem that an image enlarged and projected on a display surface such as a screen has low contrast and low brightness.

In order to improve the brightness and contrast of such a projected image, studies have been made to change the light source to a stronger one. However, this has a problem of increasing the power consumption, hindering the miniaturization of the device, and increasing the heat generation from the light source. It is practically difficult to use.

Further, in order to make the screen high-definition, it is desirable to achieve high integration of pixels without reducing the number of pixels and to improve the aperture ratio of the pixel portion. For this reason, various means for improving the aperture ratio have been studied, but as a liquid crystal projector using a so-called active matrix liquid crystal display panel, an aperture ratio of at most about 30 to 40% has been realized. What remains is the reality of the prior art.

The reason for such a low aperture ratio is not the element size of the thin film transistor itself as the switching element of the pixel portion, but rather the auxiliary capacitance provided for assisting the electrostatic capacitance to the liquid crystal layer when the liquid crystal is driven. As a result of trial calculation by the present inventors, it has been found that the outer dimensions of (Cs) are relatively large, which is a major cause of hindering the improvement of the aperture ratio.

The auxiliary capacitance is an electric capacitance (Cs) provided to assist the electric charges written in the liquid crystal layer, and is generally used by diverting the material film for forming the thin film transistor element and the first electrode and the first electrode. The two electrodes and the dielectric layer sandwiched between these two electrodes form the main part.

In the active matrix type liquid crystal display device, the electric charge for displaying at each scanning timing is held in the liquid crystal layer of each pixel. At this time, the capacitance of the liquid crystal layer alone is sufficient. In many cases, the value is small, and the amount of charge in the held state decreases during a predetermined time (such as every frame), or the charge is penetrated due to the influence of parasitic capacitance, etc. It will not be effective. As a result, the image quality of the display image is degraded.

In order to eliminate such a display defect, the above-mentioned auxiliary capacitance (Cs) is formed and the capacitance (C) of the liquid crystal layer is formed.
_LC ) and retains sufficient charge to hold the display for a period of time. As the auxiliary capacitance (Cs), two types are generally known: an additional capacitance method in which a pixel electrode and a gate wiring are overlapped and a storage capacitance method in which a dedicated auxiliary capacitance wiring is separately formed.

In the former case, since the gate wiring is also used as the electrode of the auxiliary capacitance, the aperture ratio is improved by the area occupied thereby, but the parasitic capacitance connected to the gate wiring is increased, so that the wiring delay of the scanning pulse or the like is caused. There is the inconvenience of becoming large.

On the other hand, the latter does not affect the pulse (voltage) transmitted through the gate wiring, so that it is easy to ensure display uniformity, but there is a disadvantage that the aperture ratio is poor.

Therefore, in general, the gate wiring has been made low in resistance by using a silicon compound such as silicide, and the former additional capacitance method is adopted to obtain an aperture ratio of about 30 to 40%.

[0015]

However, even in the case of the additional capacitance system, which is a system having a relatively high aperture ratio among the above conventional systems, the aperture ratio is at most 30 to 40.
%, It is extremely difficult to further improve the aperture ratio, and this aperture ratio is practically the upper limit, which hinders high brightness and high contrast as a liquid crystal display device. was there.

The present invention was made to solve such a problem, and its purpose is to determine the aperture ratio of each pixel by
In particular, it is intended to realize a liquid crystal display device which can be increased by reducing the projected occupation area of the auxiliary capacitance on the substrate, and as a result, can perform high-definition image display with high brightness and high contrast.

[0017]

In order to solve the above problems, a liquid crystal display device of the present invention has a pixel electrode formed for each pixel portion and an active layer formed using a semiconductor layer. An array substrate having a transistor element for controlling the voltage application to the pixel electrode on the main surface of the substrate, and a counter electrode facing the pixel electrode of the array substrate with a gap on the main surface of the substrate. A liquid crystal display device comprising: a counter substrate having the liquid crystal layer, and a liquid crystal layer between the array substrate and the counter substrate, the liquid crystal layer being sealed and sandwiched around the both substrates, and a semiconductor layer side including the active layer. A first electrode using a wall surface or formed on the side wall surface, a dielectric layer formed on the main surface of the first electrode, and the first electrode via the dielectric layer.
And a second electrode layer formed on the main surface of the dielectric layer so as to face the electrode of FIG.

Further, in the liquid crystal display device of the present invention, in the above liquid crystal display device, the thickness of the dielectric layer in the horizontal direction with respect to the main surface of the substrate is vertical to the substrate of the dielectric layer. It is characterized by being formed to a value smaller than the width.

Further, in the method for manufacturing a liquid crystal display device of the present invention as described above, a pixel electrode and a transistor element connected to the pixel electrode for controlling voltage application are formed on an insulating substrate to form an array substrate. Formed, and the array substrate and a counter substrate formed with a counter electrode are arranged to face each other with a gap,
In a method of manufacturing a liquid crystal display device, in which a periphery of both substrates is sealed and a liquid crystal layer is sandwiched in the gap,
A recess is formed at a position corresponding to the pixel opening on the main surface side, and at least one of P (phosphorus) and B (boron) and As (arsenic) is used as a dopant on the first main surface of the silicon substrate. A step of forming an insulating film containing impurity ions, and the insulating film and the silicon substrate are subjected to heat treatment to planarize a main surface of the insulating film opposite to an interface in contact with the silicon substrate. And a step of forming a low resistance layer by diffusing and doping impurity ions as the dopant in the thickness direction from the interface between the insulating film and the silicon substrate to the inside of the silicon substrate, and planarizing the insulating film. And a step of adhering the main surface side to an insulating substrate, and grinding the silicon substrate from a second main surface of the silicon substrate opposite to the first main surface to form a concave portion of the silicon substrate. The interface of the formed insulating film with the silicon substrate is exposed, and the height of the exposed surface of the silicon substrate is approximately equal to the height of the exposed surface of the insulating film from the insulating substrate. A step of stopping the grinding of the silicon substrate halfway to leave the silicon and obtaining a silicon layer which is element-isolated and has a low resistance layer on at least a sidewall surface; and a portion of the insulating film corresponding to the pixel portion. To form a pixel opening, a gate insulating film is formed on the main surface of the silicon layer, and a dielectric layer made of an insulating material is formed on the side wall surface, and the gate is formed. A gate electrode made of a conductive material is formed on the insulating layer so as to cover the channel region of the silicon layer, and a conductive layer is formed so as to face the low resistance layer on the sidewall surface of the silicon layer via the dielectric layer. Forming an auxiliary capacitance electrode made of a conductive material, and forming a channel region in a portion of the silicon layer covered with the gate insulating layer through the gate insulating layer, and forming a source region on one side of the channel region. A region is formed and a drain region is formed on the other side to form a transistor element, and the low resistance layer on the sidewall surface of the silicon layer is used as a first electrode and the auxiliary capacitance electrode is formed as a second electrode. Used as an electrode of the first
An insulating portion is formed between the auxiliary capacitance formed by sandwiching the dielectric layer between the electrode and the second electrode and the transistor element, and electrically insulates between the auxiliary capacitance and the transistor element. And a step of forming a pixel electrode connected to the transistor element in the pixel opening.

As the material of the semiconductor layer, a single crystal silicon substrate can be preferably used, but in addition to this, for example, amorphous silicon (a-Si) or polycrystalline silicon (p-Si). Can also be used.

[0021]

In the liquid crystal display device of the present invention, according to the conventional technique, the first electrode, the dielectric layer, and the second electrode are sequentially laminated in the direction perpendicular to the substrate surface to form a planar pattern. However, in the present invention, the storage capacitor is formed vertically (three-dimensionally) around the pixel opening.
A dielectric layer and a second electrode (auxiliary capacitance electrode) are sequentially deposited on the side wall surface including the active layer of the thin film transistor element in the horizontal direction with respect to the substrate to form a laminated auxiliary capacitance.

As a result, for example, the aspect ratio (vertical / horizontal ratio on the substrate) of the dielectric layer of the auxiliary capacitance can be formed to be 1 or more. That is, since the auxiliary capacitance is formed in a sectional shape such that it is erected on the substrate, it is possible to effectively reduce the projected occupation area of the auxiliary capacitance on the substrate surface and improve the utilization efficiency of the light source.

In particular, according to the present invention, even in a handy type liquid crystal panel having a small screen of about 2 inches, which is used in a small household liquid crystal projector,
It is possible to secure a dramatically higher aperture ratio than the conventional technology, with a high pixel count and high definition and an aperture ratio of 60% or more without reducing the number of pixels. It is possible to obtain a bright liquid crystal display device.

The capacitance value of the auxiliary capacitance Cs is Cs.
= Ε · S / d Here, ε is the dielectric constant of the dielectric layer, S is the area of the dielectric layer, and d is the thickness of the dielectric layer (or the distance between two electrodes sandwiching the dielectric layer).

At this time, in order to obtain the desired capacitance value, it is most effective to change the setting of the value of S in the above equation. That is, first, ε in the above equation is a dielectric constant that is uniquely determined by the material (here, the material for forming the gate insulating film) used as the dielectric layer of the auxiliary capacitance, and is therefore a unique constant for each material. . Further, d in the above formula is a film thickness that can be formed for each material used for the dielectric layer, and when a material for forming the gate insulating film is used, the film thickness suitable for the gate insulating film is The value is set to a value within a predetermined range. On the other hand, the thinner d is, the thinner the d is, and the smaller the projected occupation area of the auxiliary capacitance on the substrate is. However, if the breakdown voltage of the oxide film is generally set to about 8 MV / cm, there is a limit to thinning it in order to secure the gate breakdown voltage.
Is preferably 70 nm or more.

As described above, the values of ε and d are determined within a certain numerical range from the above factors other than the factor related to the auxiliary capacitance, so that the value of the area S is actually determined. A desired capacitance value (Cs) as the auxiliary capacitance may be obtained by changing the total extension of the planar pattern of the auxiliary capacitance.

At this time, the value of S is the width of the side wall surface of the semiconductor layer in which the auxiliary capacitance is formed in the vertical direction from the substrate, that is, the layer thickness of the semiconductor layer, and the horizontal of the pattern patterned on the substrate as the auxiliary capacitance. Determined by the product of the direction length (total extension). Therefore, in order to realize S with a pattern as small as possible (short) in order to improve the pixel aperture ratio, it is sufficient to form the width (that is, the thickness of the semiconductor layer) large.

Here, the width of the side wall surface in the height direction (that is, the thickness of the semiconductor layer) can be formed particularly thick when a silicon substrate having a thickness of 0.5 μm or more is used as the semiconductor layer. Is. Therefore, from this point of view, the present invention can be said to be a technique suitable for a liquid crystal display device including a transistor element using particularly single crystal silicon as a semiconductor layer. That is, as described above, in the case of a thin film transistor using, for example, a-Si for the active layer (semiconductor layer), its layer thickness is only about 50 to 100 nm. However, when the single crystal silicon substrate is used as a semiconductor layer by grinding in the thickness direction, the layer thickness can be formed to a thickness of, for example, 1 to 5 μm. It is possible to obtain a layer thickness of about 10 times or more as compared with the case. Therefore, when the single crystal silicon substrate is used as the material for forming the semiconductor layer, the horizontal length of the auxiliary capacitance pattern is formed to be 1/10 or less of the length when the a-Si film is used. However, it is possible to realize the same capacitance value as when the a-Si film is used.
Moreover, it goes without saying that a transistor element using C-Si (single crystal silicon) as an active layer capable of forming a semiconductor layer having such a large thickness has extremely good operating characteristics such as its mobility. Therefore, it is also preferable in that a high-performance transistor element can be realized, and there is a great merit in improving the definition of a liquid crystal display device.

Such a C-Si layer thickness is preferably 0.05 μm or more as a design value in order to reduce variations in element characteristics due to variations in film thickness and to facilitate the design of auxiliary capacitors. . On the other hand, it is preferable that the range of the layer thickness capable of obtaining the processing accuracy necessary for the element isolation and the like is 5 μm or less. If it is thicker than that, there arises a problem that the pattern accuracy cannot be sufficiently obtained when patterning is performed by an etching method or the like. Therefore, the C-Si layer thickness particularly suitable for the present invention is 0.05 to 5
It is preferable to set to μm.

Moreover, when such C-Si is used as the semiconductor layer according to the present invention, the region where the transistor element is formed in the semiconductor layer and the first electrode of the auxiliary capacitance according to the present invention are formed. It is necessary to isolate (electrically insulate) from the isolated area.
Since it is possible to easily form a structure such as COS element isolation for C-Si, the auxiliary capacitance according to the present invention is also formed on the side wall surface of one and the same semiconductor layer forming the transistor element. There is also an advantage that it is possible to easily prevent electrical interference and the like between the two, which is highly risky due to this.

The material particularly suitable for the semiconductor layer of the thin film transistor used in the liquid crystal display device of the present invention is C-Si as described above, but other than this, as the material of the semiconductor layer of the present invention, It goes without saying that, for example, p-Si or a-Si can be formed with a slightly thicker layer thickness than conventional ones, or a p-Si substrate or a-Si substrate can be used.

[0032]

Embodiments of the liquid crystal display device and the method of manufacturing the same according to the present invention will be described below in detail, focusing on the pixel portion of the TFT array substrate.

(Embodiment 1) The structure of the liquid crystal display device of the first embodiment will be described in detail with reference to FIGS. 1, 2 and 3 in the order of the manufacturing process.

In the liquid crystal display device of the present embodiment, the pixel portion switching element and the liquid crystal driving circuit using single crystal silicon as a semiconductor layer are formed on an array substrate of a liquid crystal display panel having a screen of diagonal 3.3 inches. It is

A width 12 is formed on the first major surface 2 side of the single crystal Si substrate 1.
Grooves are engraved in a contour pattern surrounding the pixel portion in a grid pattern of μm / pixel pitch of 35 μm, and RIE is used to correspond to the inside of the contour pattern along each lattice surrounded by the groove portion, that is, the pixel portion. A concave portion is etched (etched) to a depth of 3 μm. Then, a PSG (Phospho-Silicate Glass) oxide film 3 containing a large amount of P (phosphorus) of 6 wt% or more is deposited so as to cover almost the entire first main surface 2 including the recesses (FIG. 1A). . For this flattening, SO
G (Spin On Glass) or TEOS oxide film is used, or CMP (Chemical Mechanical) is used.
It is also possible to use a polishing method such as an alkaline polish).

Then, the whole single crystal Si substrate 1 on which the PSG oxide film 3 is deposited is subjected to a thermal process at 1050 ° C. to make PSG.
The PSG oxide film 3 is flattened by reflowing the oxide film 3, and the upper surface of the PSG oxide film 3 is flattened while filling the recesses formed on the first main surface 2 side of the single crystal Si substrate 1.

At this time, reflow is carried out at a high temperature of 1050 ° C., and a large amount of P ions contained in the PSG oxide film 3 are so-called auto-doped into single crystal Si.
By diffusing from the interface with the PSG oxide film 3 of the substrate 1 to the inside, the low resistance layer 4 can be formed in the region inside from the interface of the first main surface 2 of the single crystal Si substrate 1. The layer thickness (depth) of the low resistance layer 4 thus obtained is about 200 nm.
Became the depth of. In addition, the reason why the upper surface of the PSG oxide film 3 is flattened by reflowing in this manner is that it is also expected that the PSG oxide film 3 will act as a stopper when polishing the C-Si portion in a later step. That is. In this way, the first PSG oxide film 3 on the upper side in FIG.
The main surface 5 is flattened (FIG. 1B).

Then, as shown in FIG. 1C, the entire first substrate 5 is turned upside down so that the first main surface 5 of the flattened PSG oxide film 3 is turned downward, and the first main surface 5 is removed. Quartz substrate 6
Is bonded to the upper first main surface 7. That is, the second main surface 8 of the single crystal Si substrate 1, which has been the lower side in the figure until now, is shown in FIG.
It is located on the uppermost surface in the step shown in FIG.

The first major surface 7 of the quartz substrate 6 and the first major surface 5 of the PSG oxide film 3 are bonded to each other by cleaning the entire surface of the quartz substrate 6 having substantially the same size as the PSG oxide film 3. After the application, the first main surface 5 of the PSG oxide film 3 is attached onto the first main surface 7 of the quartz substrate 6 while being pressure-bonded in a heating atmosphere without interposing a sizing agent such as an adhesive. It was attached by the contact method. However, it goes without saying that the joining method is not limited to the direct contact method as in the present embodiment, and an adhesive or the like may be used as the sizing agent. However, as a sizing agent that is preferably used in that case, considering the transmission of light, the transmittance in the visible light region is good, and
It is preferable to use a material having a high process consistency in the subsequent steps (c), that is, a material that is not significantly affected by warpage or distortion in the heating step, or contamination due to exudation of ions or the like. Incidentally, the present inventor also tried an experiment in the case of using a sizing agent in addition to this example, and as a result,
Bonding of sufficient strength was obtained without causing other problems (inconvenience).

After the first major surface 5 of the PSG oxide film 3 is bonded to the first major surface 7 of the quartz substrate 6 in this way, FIG.
As shown in, the single crystal Si substrate 1 is ground from the surface of the first main surface 8 using diamond slurry, and finally the PSG oxide film 3 is thinned to a thickness of about 3 μm. did. In this grinding, when the PSG oxide film 3 having a high hardness is ground, the progress of the grinding is appropriately stopped by the PSG oxide film 3, and the layer thickness (the upper surface of the PSG oxide film 3 is almost equal to the layer thickness of the PSG oxide film 3 is increased. Single crystal Si so that
The polishing of the substrate 1 is also stopped. At this time, the variation in the layer thickness of the single crystal Si substrate 1 left without being ground was 0.02 μm or less, because the PSG oxide film 3 described above worked as a stopper at the time of grinding.

Then, an ammonium fluoride solution (NH
₄ F) is removed by etching the PSG oxide film 3 from the surface in the exposed using, as the pattern of the single-crystal Si substrate 1 in plan view so as to surround the outer shape of the pixel aperture shown in FIG. 3 Pattern into a pattern. In this way, about 200 n from the side wall surface of the semiconductor layer 9 made of C-Si and the interface with the PSG oxide film 3 on which an active layer is to be formed later are formed.
A structure in which the low resistance layer 4 is formed at a depth of m can be obtained (FIG. 1E).

Then, the single crystal S left as a pattern
Using a manufacturing process similar to the fabrication of a general TFT for forming a thin film transistor element on an i substrate 1, first, a gate insulating layer 10 and a P-doped p-Si film having good conductivity which is further P-doped thereon are formed. 11 is deposited (FIG. 2 (f)).

Then, the p-Si 11 is patterned to obtain the second electrode 13 deposited on the side surfaces of the gate electrode 12 and the semiconductor layer 9 (that is, laminated in the direction perpendicular to the substrate surface). At this time, the gate insulating layer 10 on the side wall surface of the semiconductor layer 9 is used as the dielectric layer 14, and the low resistance region 4 formed on the left side in the figure in contact with the dielectric layer 14 is used as the first electrode 15, The first electrode 15 and the second electrode 13 are arranged so as to face each other, and the dielectric layer 1 is provided between them.
A storage capacitor 16 formed by sandwiching 4 is formed. Then, in order to obtain electrical isolation (element isolation) from the auxiliary capacitance 16, an element isolation region 17 is formed between them by LOCOS oxidation, and then the gate electrode 12 is formed.
Main body of TFT and storage capacitor 1
6 and 6 are isolated (isolated). When the active layer is thin, element isolation may be performed in an island shape by using a dry etching method or the like.

Subsequently, as shown in FIG. 2G, both sides of the gate electrode 12 are doped with a dopant (impurity ion), and the source region 18 is formed in one region and the drain region 19 is formed in the other region. Are formed, and the active layer 20 is formed using the portion of the single crystal Si substrate 1 in the semiconductor layer 9. Thus, the main part of the thin film transistor 21 of the liquid crystal display device according to the present invention, which includes the gate electrode 12, the source region 18, and the drain region 19, is formed.

Here, needless to say, a channel region 22 is formed under the gate electrode 12 between the source region 18 and the drain region 19.

In this embodiment, a thermal oxide film having a thickness of 70 nm is formed as the gate insulating layer 10. As the p-Si film for forming the gate electrode 12 and the second electrode 13, a p-Si film having a film thickness of 400 nm was formed and patterned by anisotropic etching by RIE. Impurity ions as a dopant are implanted into the source region 18 and the drain region 19 by self-alignment using the gate electrode 12. The activation of impurities inside the active layer 20 using the single crystal Si substrate 1 was performed by passing through a heating process at 900 ° C. for about 1 hour.

After that, as shown in FIG. 2H, an interlayer insulating film 22 is formed by depositing SiO ₂ by plasma CVD so as to cover each structure (each structure) formed up to the above process. . Then, in the subsequent steps, substantially the same as the general MOS element forming step,
After planarization by resist etch back, as shown in FIG. 3, a contact hole 301 for connecting the signal wiring (not shown) and the semiconductor layer 9 is formed in the gate insulating film 10 by, for example, dry etching, and Al--Si is formed. Is formed by a sputtering method, and this is dry-etched to form a signal wiring.

Further, a light shielding film (not shown) called a black matrix is formed so as to cover the TFT 21. WSi _x was used as this light-shielding film.

Then, contact holes are formed in the interlayer insulating layer 23 and the gate insulating layer 10 so as to expose the source region 18 and the drain region 19, respectively.
Source electrodes 24 connected to the source region 18 and the drain region 19 through the contact holes,
The drain electrodes 25 are formed respectively. Then, a PSG film 26 is first formed as a passivation film so as to cover each of these structures, and then SiN is formed thereon.
Two layers of the _x film 27 are laminated in this order.

Further, a contact hole for making a connection with the drain electrode 25 is formed with the PSG film 26 and Si.
A pixel electrode 28, which is formed in the N _x film 27, is in contact with the upper surface of the drain electrode 25 through the contact hole, and forms a pixel in each pixel region of the liquid crystal display device, is formed of ITO (indium tin oxide). ) Is formed and patterned to be used for each pixel opening. Thus, main parts of the thin film transistor and the storage capacitor of the liquid crystal display device according to the present invention can be formed.

Further, although not shown, the counter substrate having the counter electrode and the TFT array substrate are arranged so as to face each other with a gap, and the periphery of the substrate is sealed with an adhesive / sealant. A liquid crystal layer is injected into the gap between the substrates, and an exterior assembly and the like are performed to complete the liquid crystal display device according to the present invention.

FIG. 3 shows the main part of the planar structure of each pixel of the liquid crystal display device according to the present invention thus obtained. In FIG. 3, the portion indicated by the dots is the second.
This is a pattern region of the electrode 13 of. As described above, the dielectric formed by using the forming material of the second electrode 13 and the gate insulating layer 10 formed of p-Si in a pattern that goes around the area corresponding to the pixel portion Body layer 1
4, the first electrode 15 formed using the low resistance region 4 forms the main part of the structure of the auxiliary capacitance 16.
Since it is necessary to secure the area S so that the capacitance value Cs of the auxiliary capacitance 16 according to the present invention becomes a value that is necessary and sufficient for performing the liquid crystal display device, its length is made as wide as possible. Therefore, the pattern is formed as shown in FIG.

Here, in the present embodiment, the TFT 21
For design reasons for making the operating characteristics of (1) preferable, the layer thickness of the semiconductor layer 9 is preferably set to 0.05 μm or more, and the layer thickness is set to have sufficient processing accuracy. It is desirable to set it to 5 μm or less. That is, the layer thickness of the semiconductor layer 9 is preferably set to 0.05 to 5 μm. If the film thickness is smaller than that, the variation in the element characteristics due to the variation in the film thickness becomes large, or it becomes difficult to design a sufficient auxiliary capacitance, so that the active layer 20 does not always function sufficiently. Can only be formed. On the other hand, if the thickness is too large, the processing accuracy is impaired, which hinders the miniaturization of the pattern of the pixel portion.

In this embodiment, a suitable value (C
As s), the auxiliary capacitance 16 was designed so that 150 × 10 ⁻¹² F could be obtained. At this time, the dielectric layer 1 of the auxiliary capacitance 16
Considering the dielectric constant of the gate insulating layer 10 used as No. 4 and its film thickness (70 nm in this embodiment), the area S of the Cs pattern that can satisfy the above value is S <(film thickness: 3 μm ) × (peripheral length: 120 to 150 μ
It is calculated that m) is required. As described above, the area S of the auxiliary capacitance 16 and the film thickness of the semiconductor layer 9 (C-Si in this embodiment) that determines the area S of the auxiliary capacitance 16 are determined in consideration of ε and d determined for each material used for the liquid crystal display device. The thickness of the semiconductor layer 9 formed from 3 μm) is calculated back to calculate a suitable length of the pattern of the auxiliary capacitance 16, and the auxiliary capacitance 16 may be designed in a pattern that can realize it.

Further, when the semiconductor layer 9 is formed of, for example, p-Si (polycrystalline silicon) in addition to C-Si by film formation, the layer thickness is considered to be thinner and generally 2 μm or less. As is clear from the above Cs calculation formula, it is necessary to set the total extension of the Cs pattern to a pattern longer than that of the present embodiment. The same applies to the case of a-Si (amorphous silicon). In addition, a wafer substrate of p-Si or a-Si is C-Si.
After sticking as in the case of the substrate, grinding and polishing may be performed to form a silicon layer.

Further, in the above-mentioned embodiment, since the merit of simplifying the manufacturing process is great, the gate insulating film 10 is
The dielectric layer 14 and the dielectric layer 14 are formed by patterning the same P-doped low resistance p-Si material film, but the present invention is not limited to this. The gate insulating film 10 and the dielectric layer 14 may be formed using different material films in different steps.

A test pattern image was displayed on the liquid crystal display device according to the present invention formed by the above manufacturing method, and its display performance was evaluated.

As a result, it was confirmed that the brightness of the screen was remarkably improved as compared with the conventional one, and the brightness was doubled or more as compared with the conventional liquid crystal display panel of the same size. This is because the projected occupation area of the auxiliary capacitance 16 on the substrate surface is reduced as described above, so that the aperture ratio of the pixel portion is 30% in the conventional case.
This is because the value of about 60% was greatly improved to about 60 to 73% in this embodiment.

In this embodiment, the PSG
The role of the oxide film 3 as an etching stopper is shown in FIG.
The single crystal S is provided in the step shown in (e).
In order to have the i-layer 1 and the PSG oxide film 3 function as a support material, as shown in FIG.
Although the first main surface 5 of No. 1 was attached to the surface of the first main surface 7 of the quartz substrate 6, the supporting material is not limited to the quartz substrate 1 which is the substrate material of the array substrate as in this embodiment. Needless to say. In addition to this, for example, at the stage of the step shown in FIG. 1A, some support substrate has already been attached (or adsorbed) to the main surface of the single crystal Si layer 1 opposite to the first main surface 2. Processing) the first main surface 2 side of the single crystal Si layer 1,
After that, the supporting substrate may be separated from the single crystal Si layer 1.

Further, in FIGS. 1 and 2, the portion of the TFT 21 and the auxiliary capacitance 16 of the pixel portion, which can be said to be the main portion of the present invention, is mainly shown, but in fact, other than this portion, the peripheral portion of the array substrate is also shown. Also, TFTs forming a so-called liquid crystal drive circuit were formed at the same time. Therefore,
Actually, both n and p channel MOS devices are formed on the array substrate. However, it is needless to say that the above-mentioned auxiliary capacitance is not formed on the side wall surface of the semiconductor layer used for the TFT for the liquid crystal drive circuit since the auxiliary capacitance is not necessary.

Further, in the above-mentioned embodiment, the PSG film 26 and the SiN _x film 27 are used as the passivation film.
Although the layer structure is adopted, this is to prevent the insulation (reliability) from being deteriorated when a film formation defect such as a pinhole defect occurs in one of the films. However, it is needless to say that the passivation film may be formed as a single layer using either one or another film when the occurrence rate of such film defects is low.

Further, in this embodiment, the gate electrode 12
A PSG oxide film containing a large amount of P as an impurity was used for autodoping the second electrode 13, the first electrode 15, and the like. The material of the film used for this autodoping is the present embodiment. In addition to the above PSG oxide film, for example, a BSG film containing B (boron) or an AsSG film containing arsenic can be used. Any of these materials may be selected depending on the design of the thin film transistor for realizing good operating characteristics as a liquid crystal display device.

Further, in the present embodiment, the implantation of P as an impurity is performed by the auto-doping and the ion implantation method, but other doping methods such as the ion shower method may be used. When such a method of forcibly implanting impurity ions is used, the PSG oxide film or the like for autodoping as in the present embodiment is not doped with impurities as an insulating film (or impurity ions are used). It is also possible to use an oxide film (which does not contain silicon), for example, a silicon compound film made of undoped SOG, a TEOS oxide film, or a polishing method such as CMP.

In the ion implantation method, in particular, when implanting by implanting impurity ions, the implanting angle is tilted by a few degrees with respect to the vertical direction of the substrate, and the implantation is performed so that the second electrode is formed. Impurity ions can be effectively implanted into 13 and the like.

Further, in the step shown in FIG. 2G, although the patterning step and the like are increased, the drain region 19 and the source region 18 are formed in order to improve the operation characteristics of the TFT 21 (reduction of the leak current of the gate drain). A so-called LDD (Lightly Doped Drain) structure may be additionally formed in the vicinity.

Although the black matrix (light-shielding film) is arranged on the array substrate side in this embodiment, it may be arranged on the counter substrate side.

In this embodiment, the screen size is 3.
An example of forming a 3-inch liquid crystal display panel is shown, but even when forming a 2-inch or smaller screen size liquid crystal display panel,
The technique according to the present invention is effective. That is, even in a smaller liquid crystal display panel, the screen size of the liquid crystal display panel can be further reduced without impairing the miniaturization of each pixel and the increase in the number of pixels. Rather, the present invention is more effective as the liquid crystal display device is downsized. According to the calculation by the present inventor, even when the same pattern design rule (line and space around 3 μm) as in the past is applied, by applying the present invention, a high-definition transmissive liquid crystal display of 2 inches or less for high-definition The panel can be manufactured. (Embodiment 2) In the second embodiment, an embodiment of a projection type liquid crystal display device using polycrystalline silicon as a semiconductor layer and a method of manufacturing the same will be described in detail with reference to FIG. In FIG. 4, the same parts as those in the first embodiment are designated by the same reference numerals as those in FIGS. 1, 2 and 3.

On the first main surface 7 of the quartz substrate 6, a-Si is added by C
The film is formed by the VD method. Then, this a-Si is further polycrystallized by a low temperature solid phase growth method to form a p-Si film. The thickness of the p-Si film was 2 μm in this embodiment. Then, using a resist 400 patterned on the p-Si film, a width of 12 μm and a pixel pitch are obtained by RIE.
A 35 μm grid pattern was patterned. The pattern thus obtained has a state in which a p-Si film is formed in an island shape on the quartz substrate 6 when viewed in cross section as shown in FIG. In this way, the p-Si film is separated into islands to form the semiconductor layer 401 (FIG. 4).
(A)).

Subsequently, without removing the resist 400, P (phosphorus) is doped by oblique ion implantation (angle of about 8 degrees) as it is. As a result, P can be doped only on the side wall. After that, the resist 400 was peeled off, and the entire array substrate was exposed to a heating process at 1050 ° C. to further diffuse P into the side wall surface of the semiconductor layer 401 as impurity ions. The side wall surface of the semiconductor layer 401 is selectively doped with impurities, and the resistance of that portion is reduced to form a low resistance layer 402.
At this time, it goes without saying that the portion of the p-Si film 403 which has been left undoped is still in the state of the undoped p-Si film 403 (FIG. 4B).

Then, a TFT similar to that of the first embodiment is formed on the semiconductor layer 401 covered with the low resistance layer 402.
In order to form the TFT 21, the TFT 21 is formed through a process substantially similar to that of the first embodiment. On the other hand, similar to the first embodiment, a part of the low resistance p-Si film which is the material for forming the gate insulating film is used as the dielectric layer 14, and the low resistance layer 402 is used.
Of the side wall surface of the TF is used as the first electrode 15, and TF
The same p-Si material film as the material film of the gate electrode 12 of T21 is patterned to form the second electrode 13, and the auxiliary capacitance 16 is formed using this.

Further, similarly to the first embodiment, the interlayer insulating layer 23, the source electrode 24, the drain electrode 25, PS
The G film 26, the SiN _x film 27, and the pixel electrode 28 are formed in this order, respectively, and the TFT of the liquid crystal display device of the present embodiment is formed.
The structure of the main part of the array substrate is formed (FIG. 4C).

Then, the TFT array substrate thus formed is arranged so as to face a counter substrate (not shown) with a gap, and the periphery of both substrates is sealed with an adhesive / sealing material, and the gap is filled in the gap. A liquid crystal layer is injected and an exterior assembly is applied to complete the liquid crystal display device of the second embodiment according to the present invention.

As described above, even when p-Si is used as the semiconductor layer as in this embodiment, the auxiliary capacitance 403 can be formed on the side wall surface of the semiconductor layer 401 made of p-Si.

At this time, the thickness of the low resistance layer 402 is 0.1
It was formed to a thickness of μm.

Further, the thickness of the semiconductor layer 401 at the stage shown in FIG. 4A in the state of polycrystallizing a-Si was formed to a layer thickness of 2 μm.

A test pattern image was displayed on the liquid crystal display device according to this example manufactured by the manufacturing method as described above, and its display performance was evaluated. As a result, it was confirmed that the brightness of the displayed image could be more than twice as high as that of the conventional liquid crystal display panel of the same size.

In each of the above-described embodiments, the pixel opening is rectangular (rectangular) and the planar pattern of the auxiliary capacitor is formed as a pattern along three of the four sides around the opening. As the pattern shape of this auxiliary capacitor, in addition to the three sides described in the above embodiment, four sides or
The pattern may be formed along two sides or one side. As described above, the planar pattern shape of the auxiliary capacitance can be variously changed so that the length of the pattern can be obtained such that the capacitance value (Cs) as the auxiliary capacitance is obtained as a sufficient value.

Further, when the side wall surface of the semiconductor layer is not always perpendicular to the substrate, that is, when there is a taper angle of about several tens of degrees, or when the side wall surface has a curved surface, etc. It goes without saying that the technique of the present invention is also effective in this case.

[0079]

As described above in detail, according to the present invention, the aperture ratio of each pixel is increased by reducing the projected occupation area of the auxiliary capacitor with respect to the substrate. It is possible to provide a liquid crystal display device capable of displaying an image with high brightness and high contrast.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing the structure and manufacturing process of a liquid crystal display device according to a first embodiment.

FIG. 2 is a cross-sectional view showing the structure and manufacturing process of the liquid crystal display device of the first embodiment.

FIG. 3 is a plan view showing the structure and manufacturing process of the liquid crystal display device of the first embodiment.

FIG. 4 is a cross-sectional view showing the structure and manufacturing process of a liquid crystal display device according to a second embodiment.

[Explanation of symbols]

 1 ... Single crystal Si substrate 2 ... First main surface 3 ... PSG oxide film 4 ... Low resistance layer 5 ... First main surface 6 ... Quartz substrate 9 ... Semiconductor layer 10: Gate insulating layer 11: p-Si film 12: Gate electrode 13: Second electrode 14: Dielectric layer 15: First electrode 16: Auxiliary capacitance

Claims (3)

[Claims] 1. A pixel electrode formed for each pixel portion,
An array substrate having a transistor element having an active layer formed by using a semiconductor layer for controlling voltage application to the pixel electrode on a main surface of the substrate, and having a gap between the pixel electrode of the array substrate A liquid crystal having a counter substrate having counter electrodes disposed on the main surface of the substrate and facing each other, and a liquid crystal layer sealed and sandwiched between the array substrate and the counter substrate by sealing the periphery of both substrates. In a display device, a first electrode using or formed on a side wall surface of a semiconductor layer including the active layer, a dielectric layer formed on a main surface of the first electrode, and A liquid crystal display device, comprising: an auxiliary capacitor having a second electrode layer formed on the main surface of the dielectric layer so as to face the first electrode via a dielectric layer. . 2. The liquid crystal display device according to claim 1, wherein the thickness of the dielectric layer in the horizontal direction with respect to the main surface of the substrate is smaller than the width of the dielectric layer in the vertical direction with respect to the substrate. A liquid crystal display device characterized by being formed in. 3. An array substrate is formed by forming a pixel electrode and a transistor element connected to the pixel electrode and controlling a voltage application on an insulating substrate to form an array substrate. Arranged opposite to the substrate with a gap,
In a method for manufacturing a liquid crystal display device, in which the peripheries of both substrates are sealed and a liquid crystal layer is sandwiched in the gap, a recess is formed at a position corresponding to a pixel opening on the first main surface side of the silicon substrate, P on the first main surface of the substrate
(Phosphorus), B (Boron), and As (Arsenic) at least one of the steps of forming an insulating film containing an impurity ion containing as a dopant, the insulating film and the silicon substrate is subjected to heat treatment, Impurity ions as the dopant are planarized in the thickness direction from the interface between the insulating film and the silicon substrate to the inside of the silicon substrate while planarizing the main surface of the insulating film opposite to the interface in contact with the silicon substrate. A step of forming a low resistance layer by diffusion doping, a step of adhering the planarized main surface side of the insulating film on an insulating substrate, and a side opposite to the first main surface of the silicon substrate. The silicon substrate is ground from the second main surface to expose the interface of the insulating film formed in the concave portion of the silicon substrate with the silicon substrate and expose the insulating film. The surface of the silicon substrate is stopped halfway so that the height of the exposed surface of the silicon substrate is substantially the same as the height of the exposed surface from the insulating substrate. A step of obtaining a silicon layer having a low resistance layer on at least a sidewall surface; a step of removing a portion of the insulating film corresponding to a pixel portion to form a pixel opening; and a step of forming a pixel opening on the main surface of the silicon layer. Forming a gate insulating film and forming a dielectric layer made of an insulating material on the side wall surface, and forming a gate electrode made of a conductive material on the gate insulating layer so as to cover the channel region of the silicon layer. Forming the auxiliary capacitance electrode made of a conductive material so as to face the low resistance layer on the side wall surface of the silicon layer through the dielectric layer; and the gate insulating layer of the silicon layer. A channel region is formed in a portion covered with the gate electrode via the source region, a source region is formed on one side of the channel region, and a drain region is formed on the other side of the channel region to form a transistor element. And a step of using the low resistance layer on the sidewall surface of the silicon layer as a first electrode and the auxiliary capacitance electrode as a second electrode to form the dielectric layer with the first electrode and the second electrode. A step of forming an insulating portion between the sandwiched auxiliary capacitance and the transistor element to electrically insulate the auxiliary capacitance and the transistor element; and a pixel electrode connected to the transistor element A method of manufacturing a liquid crystal display device, comprising the step of forming in a pixel opening.