JP4711287B2 - Semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective when applied to a device including a central processing unit (CPU) that operates with an internal voltage formed by a stabilized power supply circuit such as a regulator or an internal voltage down converter. Is.

As an example of changing the feedback signal by changing the voltage-dividing ratio of the output voltage of the voltage regulator and making it possible to change the output voltage by investigating known examples after making the present invention, JP 2003-005845 A, Japanese Patent Laid-Open No. 2004-145703 has been reported as examples in which the output voltage is adjusted by changing the feedback signal by switching the output voltage division ratio in accordance with an operation mode such as sleep / wakeup.
JP 2003-005845 A JP 2004-145703 A

  Signal processing, etc. in the development and design of regulated power supply circuits such as regulators and internal voltage down converters in system LSIs (semiconductor integrated circuit devices) that include a central processing unit (hereinafter referred to as CPU) that uses microfabricated elements We studied to reduce the power consumption of the entire system LSI by setting the sleep mode in which the current consumption of the CPU is significantly reduced by stopping the clock supplied to the CPU, etc. The return from the sleep mode is performed by an interrupt signal or the like supplied from the outside of the semiconductor integrated circuit device. Therefore, since the transition to and return from the sleep mode are performed unrelated to each other, the output voltage of the stabilized power supply circuit is used when the return from the sleep mode is performed immediately after entering the sleep mode. That is, it has been found that the problem that the internal voltage is greatly reduced occurs. In Patent Documents 1 and 2, it is effective as a technique for preventing a drop in the internal voltage when the regulator returns to standby, but the above problem cannot be solved for the reasons described later.

  An object of the present invention is to provide a semiconductor integrated circuit device including a stabilized power supply circuit that can obtain a stable output voltage even with a sudden change in load current in a short period of time. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. In other words, an output signal that makes both (the reference voltage and the feedback voltage) equal is formed by a differential amplifier circuit that depends on the reference voltage and the internal voltage and receives the feedback voltage counted by dividing the voltage. A stabilized power supply circuit such as a regulator or an internal step-down circuit is configured by controlling the MOSFET. The stabilized power supply circuit forms the internal voltage that is the operating voltage of a normal load circuit (first load circuit) such as a CPU. A dummy load circuit (second load circuit) for supplying a predetermined current is provided, the operation and stop of the normal load circuit are controlled by the first signal formed by the control circuit, and the second signal formed by the control circuit is used. In response to the normal load circuit being stopped, the predetermined current is allowed to flow through the dummy load circuit for a certain period.

  While maintaining the low power consumption operation by the current that flows only for the predetermined period, it is possible to reduce the drop in the internal voltage when the load current increases due to the re-operation of the normal load circuit.

  FIG. 1 is a schematic block diagram showing one embodiment of a semiconductor integrated circuit device according to the present invention. The semiconductor integrated circuit device of this embodiment is directed to a system LSI having a CPU or the like as a center. A stabilized power supply circuit as a regulator, an internal power supply circuit or a step-down power supply circuit receives a power supply voltage VCC as a first power supply potential and a ground potential VSS (VCC> VSS) as a second power supply potential supplied from an external terminal. Thus, for example, the lowered internal voltage VDD (VDD <VCC) is formed. A smoothing capacitor Cdd for stabilizing the internal voltage VDD is provided between the internal voltage VDD and the ground potential VSS.

  The stabilized power circuit forms the internal voltage VDD and is supplied to the normal load circuit (first load circuit), its control circuit, and the dummy load circuit (second load circuit) provided by the present invention. A load current IDDL as a first load current flows through the control circuit and the regular load circuit, and a dummy current IDDD as a second load current flows through the dummy load circuit. The control circuit switches the normal load circuit between the normal mode and the sleep mode by the first signal CN1, and controls the dummy load circuit when the normal load circuit is set to the sleep mode by the second signal CN2. Thus, the dummy current IDDD is allowed to flow for a certain period.

  The control circuit is not particularly limited, but controls the first signal CN1 for instructing the return from the sleep mode and the dummy load circuit by an operation control signal such as an interrupt control signal supplied from the external terminal INT. A second signal CN2 is generated for this purpose. In FIG. 1, the control circuit is described as being controlled by an operation control signal such as an external interrupt signal supplied from the external terminal INT. An interrupt signal from the provided timer circuit or an interrupt signal from the internal voltage fluctuation detection circuit that detects fluctuations in the internal voltage VDD can be used.

  FIG. 2 is a block diagram showing an embodiment of a semiconductor integrated circuit device according to the present invention. In the figure, one example of the internal configuration of the normal load circuit as the first load circuit is mainly specifically shown. The stabilized power supply circuit (regulator: REG) forms the internal step-down voltage VDD by the external power supply voltage VCC and the ground potential VSS. This internal voltage VDD is supplied to a dummy load circuit which is a normal load circuit and a second load circuit. Although the normal load circuit is not particularly limited, a coprocessor CPR, a digital signal processor DSP, a cache memory CacheRAM, a non-volatile memory EEPROM, a flash memory FLASH, and a dynamic memory, with a central processing unit (hereinafter referred to as CPU) as the center It consists of DRAM and input / output circuit I / O. Although not particularly limited, when the control circuit SYS-CTL is in the sleep mode, the supply of the internal clock INTCLK supplied to the circuits other than the input / output circuit I / O is stopped. As a result, all of the synchronous circuits depending on the internal clock INTCLK are stopped, so that the current consumption is greatly reduced.

  The control circuit SYS-CTL incorporates a gate controlled by the signal CN1 corresponding to FIG. 1, and selectively supplies / stops the internal clock INTCLK by controlling the gate. is there. Further, the control circuit SYS-CTL generates the signal CN2 and controls the dummy load circuit when it shifts to the sleep mode so that the predetermined current flows for a certain period. The return from the sleep mode is instructed by a control signal such as an interrupt supplied from the external terminal INT. That is, the control circuit SYS-CTL restarts the supply of the internal clock INTCLK by the control signal such as the interrupt and returns to the normal operation mode.

  FIG. 3 is a circuit diagram showing one embodiment of the stabilized power supply circuit used in the present invention. The stabilized power circuit of this embodiment is not particularly limited, but is composed of a series regulator. The series regulator (REG) is a circuit that outputs an internal voltage VDD that is an operating voltage of a normal load circuit including the CPU and the like from an external power supply voltage VCC through a P-channel output MOSFET Q1. The internal voltage VDD is divided by, for example, resistors R1 and (R2 + R3) to form a feedback voltage NFB. The feedback voltage NFB and the reference voltage VREF are input to the differential amplifier circuit AMP. The differential amplifier circuit AMP operates as an error amplifier that amplifies the difference between the two voltages VREF and NFB and controls the gate voltage of the P-channel MOSFET Q1 so as to eliminate the error. The stabilized power supply circuit of this embodiment is a series regulator that forms an internal voltage VDD controlled so that the reference voltage VREF and the feedback voltage NFB coincide with each other.

  The switch SW30 is provided to allow a certain amount of load current to flow through the resistor R4 even when the load current IDDL of the normal load circuit including the CPU or the like is small. That is, by turning on the switch SW30, a minute current flows through the resistor R4. The switch SW40 is provided to change the load current IDDD stepwise by switching the connection of the resistors R5 to R8 that prevent the internal voltage VDD from jumping (overshoot) when the normal load circuit is in the sleep state. The switch SW40 is controlled by signals s1, s2, s3, and s4 formed by the control circuit REGC, and all the switches are turned on and a maximum current flows through the resistor R5 during sleep-in. Then, the switches are sequentially turned off corresponding to the response stabilization time of the stabilized power supply circuit, and the resistors are switched to R5 + R6, R5 + R6 + R7, R5 + R6 + R7 + R8 to decrease the current step by step, and finally all the switches are turned off. Do not pass current. As a result, the increase in current consumption during sleep becomes transient, and an increase in current consumption during steady state can be suppressed.

  The switch SW50 changes the level of the internal voltage VDD during the sleep period and the specified number of clocks after returning. When the switch SW50 is turned on, both ends of the resistor R3 are short-circuited to lower the voltage dividing ratio. That is, an offset is set such that the level of the feedback voltage NFB is lowered to increase the internal voltage VDD. As described above, the internal voltage VDD is set higher than the target value in advance by the control of the switch SW50 so as to prepare for a drop in the internal voltage VDD due to a sudden increase in the load current at the return from sleep.

  The series regulator according to the present embodiment operates according to the operating state of the normal load circuit, in other words, the operation of the differential amplifier circuit AMP so as to achieve both high-speed response when the normal load circuit is active and low current consumption during standby. A current source is provided for generating a current Iamp. In this current source, the current is switched by the switch SW10 in order to achieve both a high-speed response when active and a low current consumption during standby. When the load current IDD becomes near the standby steady state, the operating current Iamp of the differential amplifier circuit AMP is decreased by the switch SW10. In this way, the switch SW10 reduces the self-consumption current at the sacrifice of the response speed of the series regulator during standby (sleeping of the normal load circuit). The switch SW20 is provided to limit the inrush current at the time of power-on reset. When the power is turned on, the switch SW20 is turned on to raise the gate voltage of the P-channel output MOSFET Q10 to the external voltage VCC side through the P-channel MOSFET Q2, thereby limiting a large inrush current generated in the MOSFET Q1.

  The series regulator control circuit REGC receives the power-on signal POR, the standby signal STBY, and the clocks sysck and c-ck, and forms a switch control signal supplied to the switches SW10 to SW50. For example, a timing signal for controlling the switch SW20 is formed when the power is turned on, and a timing signal for controlling each switch of the switch SW40 in time series as described above is formed when the sleep is in. A clock c-ck is used to generate the time series timing signal. For example, the switches SW40 and SW50 count the clock c-ck and make the level of the internal voltage VDD higher than the target value during the sleep period and the specified number of clocks after returning. In addition to digitally forming the timing signal using such a clock c-ck, a timing circuit as described above may be formed using a delay circuit.

  FIG. 4 is a circuit diagram showing one embodiment of the stabilized power supply circuit used in the present invention. In FIG. 4, a portion AMP surrounded by a dotted line corresponds to the differential amplifier circuit AMP in FIG. A reference voltage VREF is supplied to the gate of the P-channel MOSFET Q3. A feedback signal NFB is supplied to the gate of the P-channel MOSFET Q4 that is differential with the P-channel MOSFET Q3. A current source for forming an operating current Iamp is provided between the commonly connected sources of the differential MOSFETs Q3 and Q4 and the power supply voltage VCC. This current source includes the switch SW10 as shown in FIG.

  Between the drains of MOSFETs Q3 and Q4 and ground potential VSS, diode-connected N-channel MOSFETs Q5 and Q6 are provided as loads. The N-channel MOSFETs Q5 and Q6 are provided with N-channel MOSFETs Q7 and Q8 in the form of current mirrors, respectively. A P-channel MOSFET Q9 constituting a current mirror circuit is provided between the drain of the N-channel MOSFET Q7 and the power supply voltage VCC. The drain of the P-channel MOSFET Q10 that is current mirror connected to the P-channel MOSFET Q9 is connected to the drain of the N-channel MOSFET Q8.

  The mirror ratio from the MOSFETs Q3 to Q10 and the mirror ratio from the MOSFETs Q4 to Q8 in each of the current mirror circuits are set to be equal, for example, 1: 1, and the N-channel MOSFET Q8 and the P-channel MOSFET Q10 are connected. An output current corresponding to the difference between the drain currents of the differential MOSFETs Q3 and Q4 is formed from the drain to form the gate voltage of the P-channel output MOSFET Q1. The source of the output MOSFET Q1 is supplied with the power supply voltage VCC, and the internal voltage VDD is output from the drain. A phase compensation circuit including a resistor R and a capacitor C is provided between the gate and drain of the output MOSFET Q1.

  P-channel MOSFETs Q2 and Q03 connected in series are provided between the gate of the output MOSFET Q1 and the power supply voltage VCC. The MOSFET Q03 constitutes the switch SW20 of FIG. 3 and is switch-controlled by the power-on control signal por. That is, when the power is turned on, the MOSFET Q03 is temporarily turned on, and the gate of the output MOSFET Q1 is raised corresponding to the rise of the power supply voltage VCC to limit the inrush current by the MOSFET Q1. The internal voltage VDD formed by the MOSFET Q1 is divided by the resistors R1 and R2 (+ R3) to form the feedback signal NFB, which is fed back to the gate of the differential MOSFET Q4. As shown in FIG. 3, a switch SW50 is provided to prepare for a drop in the internal voltage VDD due to a sudden increase in load current upon returning from sleep, and only the resistor R2 is enabled immediately before returning from sleep as described above, so that stable operation is possible. In some cases, R3 may be selectively connected so that the resistors R2 and R3 are valid.

  FIG. 5 shows a circuit diagram of an embodiment of a series regulator which is a stabilized power circuit used in the present invention. In the figure, the differential amplifier circuit AMP is indicated by a circuit symbol, and a specific circuit configuration of a current source that forms the operating voltage Iamp is mainly shown. As described above, in the series regulator, the output signal of the differential amplifier circuit AMP is supplied to the gate of the P-channel output MOSFET Q1. The source of the MOSFET Q1 is supplied with the power supply voltage VCC, and the internal voltage VDD is formed from the drain. Then, the feedback signal NFB divided by the resistors R1 and R2 is compared with the reference voltage VREF by the differential amplifier circuit AMP, and the internal voltage VDD is formed so that the internal voltages VDD match. Further, an N-channel MOSFET Q18 corresponding to the switch SW30 of FIG. 3 is provided in the resistor R4 constituting a part of the dummy load circuit shown as an example.

  The current source includes P-channel MOSFETs Q13, Q14 and Q15 that receive a bias voltage pbias to form a constant current, and P-channel MOSFETs Q16 and Q17 as switches for enabling the operation of the MOSFETs Q13 and Q14. The switch MOSFETs Q16 and Q17 constitute the switch SW10 of FIG. The P-channel MOSFET Q15 is made to constantly flow in correspondence with the minimum current of the operating current Iamp. The switch MOSFET Q16 is switch-controlled by an output signal actvb of a CMOS inverter circuit composed of a P-channel MOSFET Q12 and an N-channel MOSFET Q11 that receives the signal actvt. The current formed by the current source MOSFET Q13 is added to the current formed by the MOSFET Q15 when the switch MOSFET Q16 is turned on. The switch MOSFET Q17 is switch-controlled by a signal stbyte. The current formed by the current source MOSFET Q14 is added to the current formed by the MOSFET Q15 when the MOSFET Q17 is turned on.

  FIG. 6 is a circuit diagram showing one embodiment of a control circuit for generating a control signal necessary for operation control of the series regulator shown in FIG. The standby signal stby changes corresponding to the delay circuit DL from the rising edge of the standby signal stby and changes corresponding to the falling edge of the standby signal stby by the inverter circuits IN1, IN2, IN3, the delay circuit DL, and the gate circuit G1. A signal is formed and the power-on signal por is combined with the gate circuits G2 and G3 to form signals stbyt and stbyb and actvt and actvb. Here, the signals stbyt and actvt represent a true signal having a high level as an active level, and the signals stbyb and actvb represent a bar signal having a low level as an active level.

  FIG. 7 is a waveform diagram for explaining the operation of the series regulator of FIG. The signals stbyt, stbyb and actvt, actvb are changed by the control circuit shown in FIG. 6 with a delay time delay of the delay circuit DL corresponding to the change of the standby signal stby to the high level as shown in FIG. To do. Due to the standby signal stby, the clock of the normal load circuit is stopped, and the load current IDD (Q1) rapidly decreases. At this time, the MOSFET Q18 is turned on by the high level of the signal stbyb, and a dummy load current of about 15 μA is passed through the resistor R1. As a result, for example, the load current IDD when active is suddenly decreased by about 4 digits from about 100 mA to about 15 μA.

  Corresponding to such a decrease in the load current IDD, the gate voltage VG (Q1) of the MOSFET Q1 is controlled to have a high gate voltage in order to reduce the load current, but an overshoot is caused by a delay in the feedback signal. appear. This overshoot is restored to a steady value by the feedback loop. Corresponding to such recovery time, the delay time of the delay circuit DL of the control circuit is set, and the signals stbyt, stbyb, and actvb change, the on-state MOSFET Q17 is off, and the off-state MOSFET Q16 is off. After turning on and recovering to a steady value, the operating current Iamp of the differential amplifier circuit is made as small as the current formed by the MOSFET Q13. Then, the MOSFET Q18 is turned off by the low level of the signal stbyb, the dummy load current is cut off, and the load current is only the leakage current. By reducing the operating current Iamp of the differential amplifier circuit AMP as described above, recovery of overshoot when the dummy load current is cut off is delayed.

  At the time of return from sleep due to the interrupt or the like, the standby signal stby is set to a low level and is not particularly limited. However, the load current IDD is divided into a first stage such as about 2 mA and a second stage of all operating states such as about 60 mA. Will be increased. When the load current IDD increases as described above, the gate voltage of the output MOSFET Q1 is increased to narrow down to the minute load current, and the overshoot state is not recovered. Since the gate voltage is increased, the undershoot of the internal voltage that occurs when the load current IDD increases increases.

  FIG. 8 shows a circuit diagram of an embodiment of the control circuit REGC of FIG. A delay pulse generation circuit combining the inverting circuit, the delay circuit DL, and the gate circuit G4 forms a pulse stbydl1t corresponding to the delay time of the delay circuit DL from the standby signal stby that is an input signal and the delay signal. The output signal stbydl1t of the gate circuit G4 is sequentially formed by the delay pulse signals stbydl2t, stbydl3t, and stbydl4t by a plurality of delay pulse generation circuits including an inverting circuit, delay circuit DL, and gate circuits G5, G6, and G7 having the same configuration. Is done. These pulse signals are supplied to the gate circuit G8, and a delay signal stbydal1t corresponding to the delay times of the three delay signals is formed. The signal stbydlt and the power-on signal por are combined by the gate circuits G9 and G10 to form the signals stbyt, stbyb, actvb, and actvt. Then, the delay signals stbydl1t, stbydl2t, stbydl3t, and stbydl4t are supplied to the logic circuit to form switch signals s1, s2, s3, and s4.

  FIG. 9 is a waveform diagram for explaining the operation of the control circuit REGC of FIG. When the standby signal stby changes to a high level, the switch signals s1, s2, s3, and s4 are all changed to a high level correspondingly, and are sequentially changed to a low level corresponding to the delayed signals stbydl1t, stbydl2t, stbydl3t, stbydl4t. . When all the switch signals s1, s2, s3 and s4 change to the low level, the signal stbyte is set to the high level. In FIG. 3, the dummy load current IDDD in the dummy load circuit is gradually reduced and finally cut off. Due to the high level of the signal stbyte, the switch MOSFET Q17 of FIG. 5 is turned off in the differential amplifier circuit AMP, and the operating current Iamp is reduced. The dummy current of the dummy load resistor R4 is also cut off by the low level of the inverted signal stbyb of the signal stbyt.

  Generally, a phase margin of 60 degrees or more is desirable for stable operation of a series regulator, but it is difficult to satisfy this due to variations in process voltage and load current, and the control signal VG supplied to the gate of the output MOSFET may overshoot. is there. The load current fluctuation is greatest when the normal load circuit shifts from the active state to the sleep state, and the overshoot of the internal voltages VDD and VP (Q1) increases.

  FIG. 10 shows a waveform diagram of sleep-in and sleep recovery in the stabilized power supply circuit according to the present invention. FIG. 11 shows sleep-in and sleep recovery when the dummy load circuit is not provided for comparison. The waveform diagram is shown. When the active state is switched to the sleep state, the operation of the normal load circuit including the CPU and the like is stopped. Without the dummy load circuit, the load current IDD rapidly decreases from 10 mA to almost 0 as shown in FIG. That is, since the discharge path of the internal voltage VDD immediately after the sleep is the load current IDD≈0, the overshoot state of the internal voltage VDD continues for a long time. For this reason, the gate voltage VG (Q1) of the P-channel output MOSFET Q1 also jumps to near the power supply voltage VCC, and the state in which the P-channel MOSFET Q1 is completely turned off continues for a long time, approximately 20 us. At this time, oscillation occurs in the internal voltage VDD and the gate voltage VG due to the delay of the feedback signal in the differential amplifier circuit AMP.

  After the internal voltage VDD returns to the steady value as indicated by the dotted line in the figure, the gate voltage VG (Q1) also returns to the steady value. When returning from sleep from this state, the fluctuation of the internal voltage VDD is about ΔVDD = V1≈0.15 × VDD and falls due to the delay of the feedback signal in the differential amplifier circuit with respect to the fluctuation of the load current. Since the minimum value of the voltage level is about 0.85 × VDD, the logic such as the CPU as the load circuit does not malfunction. That is, for example, even when the external power supply voltage VCC is 3.3V and the internal voltage (step-down voltage) VDD is 1.5V, there is no problem because the VDD is reduced only to about 1.3V.

  However, when the sleep recovery is instructed at a short timing as shown by the solid line in FIG. 11, the sleep recovery is performed at the timing when the internal voltage VDD and the gate voltage VG jump up. For this reason, the load current IDD increases at a specified timing, but the amplitude of the gate voltage VG required to return the P-channel MOSFET Q1 to the normal ON state is large, and the slew rate of the differential amplifier circuit AMP limits the P The channel MOSFET Q1 is delayed in turning on. As a result, the drop ΔVdd = V2≈0.4 × VDD of the internal voltage VDD becomes larger than that at the return from sleep after the internal voltage VDD returns to the steady value, and the minimum value of the drop voltage level is 0.6. Since the operating voltage decreases (such as CPU) and the signal delay in the logic circuit increases, the timing margin is insufficient and malfunctions occur, or the stored information in the memory circuit is lost. A problem was found that could

  The sleep recovery is generated under completely different operating conditions from the sleep-in such as the interrupt signal of the semiconductor integrated circuit device as described above, and the time from the sleep-in to the sleep recovery is set to a certain level or more. It can't be used, and if such a restriction is applied, it becomes unusable and impractical. Therefore, in this embodiment, a dummy load circuit is provided as in the embodiment described above.

  In FIG. 10, the STBY signal input at the clock stop timing causes the maximum load by the dummy load circuit controlled by the switch SW40 (s1 to s4) in accordance with the timing at which the load of the normal load circuit such as the CPU stops. It is configured to flow about 10% of the current. The change rate of the load current is not switched to 1000 times at a time, but is reduced to 10 times by using a dummy load, and the recovery from the jump of the internal voltage VDD is accelerated, so that the gate voltage VG of the P-channel MOSFET Q1 is accelerated. The overshoot of (Q1) is suppressed. Furthermore, by making the ratio of reducing the current value in the dummy load circuit for the second and subsequent times smaller than the ratio of switching from the normal load current of the CPU or the like to the dummy load circuit, such as three times, the worst overshoot amount sleeps. It becomes possible to limit to one point at the time of in, and the test becomes easy.

  That is, in FIG. 10A, this is performed after the gate voltage VG of the P-channel output MOSFET returns to the normal state at the time of return from sleep, and at the time of return, the VDD is about 0.85 × VDD as described above. There is no problem because it only decreases to Then, as shown in FIG. 10B, in the case where the time from sleep-in to sleep return due to an external interrupt or the like, that is, the standby time becomes extremely short and a dummy current is passed through the dummy load circuit, By supplying a dummy current of about 10% of the maximum load current, the recovery from the jump of the internal voltage VDD is accelerated. Furthermore, as a configuration in which the dummy current flows in a stepwise manner, the fluctuation ratio is reduced to 10 times at first, and to 3 times from the first time, for example, after the second time, thereby reducing the dummy current and reducing the steady value of VG (Q1). However, the peak of the jump of the internal voltage VDD is suppressed to be lower than the steady value when the dummy current is completely turned off.

  Therefore, the gate voltage VG of the P-channel MOSFET at the time of return from sleep in the state where the dummy load current flows is smaller by ΔV than the steady state of the gate voltage VG of FIG. 10A as shown by the dotted line. Become. Referring to the waveform diagram of FIG. 10A, the gate voltage at the third stage dummy current is smaller by ΔV than the steady voltage. As a result, the drop V2 of the internal voltage VDD at the return from sleep is always smaller than the drop voltage V1 of the internal voltage VDD in FIG. 10A because the charging time of VG (Q1) is shortened. Therefore, the worst case is the sleep recovery after the gate voltage VG of the P-channel output MOSFET returns to the normal state at the sleep recovery timing as shown in FIG. Whether the performance of the stabilized power supply is good or bad can be determined by a test with a period.

  In order to substantially reduce the drop in the internal voltage VDD when returning from the sleep mode, it is also beneficial to set the internal voltage VDD in advance by turning on the switch SW50 of FIG. 3 before returning from the sleep mode. . Since the level at which the internal voltage VDD falls causes a malfunction of a logic circuit or the like, it is effective to keep the internal voltage VDD high as described above immediately before the load current starts to flow. In this case, a delay using a clock of the CPU or the like is provided in the regulator, and the internal voltage VDD is kept high until just before the timing of switching to the maximum operating current predicted in advance by reading the CPU interrupt vector or stacking operation. It is beneficial.

  FIG. 12 shows a circuit diagram of another embodiment of the dummy load circuit of FIG. In this embodiment, an N-channel MOSFET Q20 is used as a variable resistor. That is, the drain side of the MOSFET Q20 is connected to the internal voltage VDD node via the resistor R20. The source side of MOSFET Q20 is connected to the output terminal of a CMOS inverter circuit composed of P-channel MOSFET Q27 and N-channel MOSFET Q26. The gate voltage VG of the MOSFET Q20 is changed by a time constant circuit including a capacitor CS1 and a MOSFET Q21, and a variable resistance element in which the resistance value obtained by adding the resistance value of the resistor R20 and the resistance value of the MOSFET Q20 is variable is used. In operation, the load resistance of the dummy load circuit is exponentially increased and the dummy current is correspondingly reduced.

  The circuit of FIG. 12 will be described with reference to the timing chart shown in FIG. In the active state, the signal slpin1b = VDD and the voltage VG = VDD. That is, the current path of the dummy load circuit by R20-Q20-Q26 is cut off.

(1) When the input signal stby of the series regulator changes from the low level to the high level, the signal slpin1t for detecting the initial state of the sleep switching by the delay circuit in the chip becomes the high level, and the slpin1b is set to the low level. As a result, a current path of the dummy load circuit is formed, and the maximum dummy current set by the resistor R0 starts to flow.

(2) The signal stbydlt changes from the low level to the high level, and the P-channel MOSFET Q23 that has charged the capacitor CS1 is turned off. As a result, the capacitor CS1 starts discharging through the MOSFET Q21. That is, the voltage VG decreases according to the time constant composed of the capacitor CS1 and the MOSFET Q21. Due to the decrease in the voltage VG, the on-resistance value of the MOSFET Q20 is increased and the dummy current is decreased.

(3) stbyd2t changes from the low level to the high level, and the signal slpin1t is set to the low level. As a result, the P-channel MOSFET Q27 is turned on, the N-channel MOSFET Q26 is turned off, and the signal slpin1b becomes high level (VDD) to cut off the dummy current in the dummy load circuit.

(4) The stbyd4t changes from the low level to the high level, the signal stbydallt is set to the high level, the signal stbyb is set to the low level, and the MOSFET that is flowing a small current of 10 μA in the dummy load circuit (not shown) is also turned off. Then, the signal stbyte is raised slowly, and the operating current of the differential amplifier circuit of the regulator (not shown) is slowly reduced.

  FIG. 14 shows waveform diagrams of sleep-in and sleep recovery in the stabilized power supply circuit when the dummy load circuit of FIG. 12 is used. In FIG. 14A, the return from sleep is performed after the gate voltage VG (Q1) of the output MOSFET Q1 returns to the steady state as in the case of FIG. Further, FIG. 14B shows a case where the sleep recovery is performed in a short period of time as in the case where the dummy load current is flowing from the dummy load circuit as in the case of FIG. 10B. In the dummy load circuit of FIG. 12, the load current also decreases in correspondence with the exponential resistance value change of the MOSFET Q20, so that the gate voltage without the above-described vibration due to the phase delay in the differential amplifier circuit. VG changes linearly to a normal state. As a result, the return from sleep in the steady state where the gate voltage VG is the highest as shown in FIG. 14A becomes the worst case of the drop in the internal voltage VDD, as in the previous embodiment. The worst of the amount of shoots can be limited to one point of the sleep time, and the test becomes easy.

  FIG. 15 is a block diagram showing still another embodiment of the stabilized power supply circuit according to the present invention. The stabilized power supply circuit includes a differential amplifier circuit AMP, a P-channel output MOSFET Q1, a voltage dividing circuit for forming a feedback signal NFB, and a dummy load circuit, as in the above embodiment. The normal load circuit including the CPU and the like is equivalently represented as a resistance element. In a flash memory, an EEPROM, or the like included in the normal load circuit, the internal voltage VPP is boosted and a necessary boosted voltage VPP is required for a data write operation or an erase operation. In particular, the charge pump circuit of this embodiment receives the internal voltage VDD and forms an internal voltage VPP having a polarity opposite to that of the internal voltage VDD.

  In the flash memory or the like, the charge pump circuit is controlled to operate only in an operation mode that requires the negative voltage VPP in order to reduce the power consumption of the system LSI. Therefore, even when the system is active, the charge pump circuit that has been operating for the write or erase operation of the flash memory or the like is stopped when the operation ends. At this time, as shown in the waveform diagram of FIG. 16, for example, VPP changes from −12V to 0V. This VPP voltage change acts so as to change the internal voltage VDD by the parasitic capacitance CST of FIG. In particular, the stabilized power supply circuit as described above does not substantially have a current sink capability for reducing power consumption, so that a large jump may occur as indicated by a dotted line.

  In this embodiment, the dummy load circuit is also used to prevent the internal voltage VDD jumping due to the VPP voltage change. That is, in addition to temporarily supplying a dummy load current at the time of sleep-in, the dummy load current is also given prior to the change of VPP at the timing when the VPP changes even when active, as shown by the thick line in FIG. It is intended to flow. By using the dummy load circuit even when the load fluctuates in such an active state, the internal voltage VDD can be stabilized.

Although the invention made by the present inventors has been specifically described based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and various embodiments can be adopted. For example, in a series regulator, an N-channel MOSFET may be used instead of the P-channel MOSFET. When an N-channel output MOSFET is used, the output MOSFET performs a source-forward output operation, so that a reference voltage is applied to the inverting input of the differential amplifier circuit and a feedback signal is applied to the non- inverting input.

  The generation of the feedback signal NFB of the series regulator is shown in FIG. 17 in addition to the one supplied to the inverting input of the differential amplifier circuit AMP from the connection node between the resistors R1 and R2 as shown in FIG. 3 or FIG. As described above, the drain voltage of the output MOSFET Q1, that is, the internal voltage VDD may be supplied to the inverting input of the differential amplifier circuit AMP. In this case, substantially the same potential as the reference potential VREF can be set as the potential of the internal potential VDD, and the voltage of a normal load circuit such as a CPU can be reduced.

  When the internal potential VDD is made lower than the reference potential VREF, as shown in FIG. 18, the reference potential VREF is divided using a resistor R100 and a resistor R110, and the connection node of the resistor R100 and the resistor R110 is connected. The reference potential supply portion can be configured to supply the potential as the reference potential VREF0 to the non-inverting input of the differential amplifier circuit AMP. A specific configuration of a dummy load circuit, a differential amplifier circuit, and a circuit that forms a time-series timing signal for controlling the operation thereof is a circuit that uses a decoder circuit or a shift register that decodes a counter output of a counter that forms a clock. Various embodiments can be adopted. The present invention can be widely used for a semiconductor integrated circuit device provided with a stabilized power supply circuit.

1 is a schematic block diagram showing an embodiment of a semiconductor integrated circuit device according to the present invention. 1 is a block diagram showing an embodiment of a semiconductor integrated circuit device according to the present invention. It is a circuit diagram which shows one Example of the stabilized power supply circuit used for this invention. It is a circuit diagram which shows one Example of the stabilized power supply circuit used for this invention. It is a circuit diagram which shows one Example of the series regulator used for this invention. FIG. 6 is a circuit diagram showing an embodiment of a control circuit for generating a control signal necessary for operation control of the series regulator of FIG. 5. It is a wave form diagram for demonstrating operation | movement of the series regulator of FIG. FIG. 4 is a circuit diagram illustrating an example of a control circuit REGC in FIG. 3. FIG. 9 is a waveform diagram for explaining the operation of the control circuit REGC of FIG. 8. It is a wave form diagram for demonstrating sleep in and sleep return operation | movement in the stabilized power supply circuit which concerns on this invention. It is a wave form diagram for demonstrating this invention. It is a circuit diagram which shows another Example of the dummy load circuit used for this invention. FIG. 13 is a timing diagram for explaining the operation of the dummy load circuit of FIG. 12. FIG. 13 is a waveform diagram for explaining sleep-in and sleep return operations in the stabilized power supply circuit when the dummy load circuit of FIG. 12 is used. It is a block diagram which shows another Example of the stabilized power supply circuit which concerns on this invention. It is a wave form diagram for demonstrating operation | movement of the Example of FIG. It is a circuit diagram which shows another Example of the series regulator used for this invention. It is a circuit diagram which shows another one Example of the series regulator used for this invention.

Explanation of symbols

CN1, CN2 ... Control signal, Cdd ... Smoothing capacity, REG ... Stabilized power supply circuit, CPU ... Intermediate processing device, CPR ... Coprocessor, DSP ... Digital signal processor, CacheRAM ... Cache memory, EEPROM ... Non-volatile memory, FLASH ... Flash memory, DRAM ... dynamic memory, I / O ... input / output circuit, SYS-CTL ... control circuit, SW10 to SW50 ... switch, REGC ... switch regulator control circuit, AMP ... differential amplifier circuit,
Q1-Q28 ... MOSFET, R1-R8 ... resistor, DL ... delay circuit, G1-G10 ... gate circuit, LOG ... logic circuit, CS1 ... capacitor, CST ... parasitic capacitance.

Claims (6)

A stabilized power supply circuit that receives an external power supply voltage to form an internal voltage;
A first load circuit that operates in response to the internal voltage;
A second load circuit for causing a predetermined current to flow with respect to the internal voltage;
A control circuit for controlling the operation of the first load circuit and the second load circuit,
The stabilized power supply circuit includes a differential amplifier circuit for forming an output signal as to equalize the two receives the reference voltage and the internal voltage based Dzu rather feedback voltage, receiving the output signal to the gate, source - drain The path consists of a MOSFET connected to the external power supply voltage node and the internal voltage node,
The second load circuit includes a first load current unit that controls a current amount by switching a plurality of resistance elements with a switch corresponding to a response stabilization time of the stabilized power supply circuit, a resistance element, and a switch. Including a second load current section that causes a minute current to flow through the resistor when the current flowing through the load circuit is small;
The control circuit includes a first load of the the first signal for controlling the operation state and stop state of the first load circuit, the first load circuit in response to being in the stopped state the second load circuit The current unit forms a second signal for performing control for flowing for a certain period so as to switch the connection of the plurality of resistance elements and gradually reduce the current ,
In the semiconductor integrated circuit device , the second load circuit is configured such that a current is cut off after a predetermined period of time has elapsed . In claim 1 ,
The first load current portion of the second load circuit includes a first resistance element, a parallel circuit of a plurality of resistance elements connected in series with the first resistance element, and the first resistance element and a ground potential node. A first switch provided in between, and a plurality of switch elements provided between the interconnection points of the plurality of resistance elements connected in series and the ground potential node so that the current decreases stepwise. Each of the switch elements is controlled by a semiconductor integrated circuit device. In claim 1 ,
The first load current portion of the second load circuit is composed of a series circuit of the plurality of resistance elements and a MOSFET, and the gate voltage of the MOSFET is reduced by a time constant circuit so that the predetermined current decreases with time. A semiconductor integrated circuit device controlled. In claim 2,
And a voltage dividing circuit for forming the internal voltage,
2. The semiconductor integrated circuit device according to claim 1, wherein the voltage dividing circuit includes a voltage dividing ratio switching circuit that forms a feedback voltage that increases the internal voltage when the first load circuit is stopped. In claim 2 ,
The differential amplifier circuit operates with a relatively large current when the first load circuit is activated, and operates with a relatively small operating current when the first load circuit is deactivated. A semiconductor integrated circuit device provided with such a current switching circuit. In claim 5 ,
The current switching circuit includes a current difference between the first current source MOSFET that flows the relatively large current, the second current source MOSFET that flows the relatively small operating current, and the first and second current source MOSFETs. A semiconductor integrated circuit device comprising: a switch MOSFET that supplies a differential MOSFET of a dynamic amplifier circuit.

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