JP5697777B2 - Data processing system - Google Patents

Description

  The present invention relates to a data processing system, and more particularly to a data processing system using a data processing apparatus having a central processing unit.

  In recent years, with the miniaturization of processes of data processing devices including a central processing unit (CPU: Central Processing Unit) configured on a semiconductor substrate, there are problems of lowering the withstand voltage of transistors and increasing off-leakage current.

  On the other hand, in a device using a data processing device, the operating voltage supplied to the data processing device due to external factors (communication standards, etc.) is relatively high voltage (about 5V) to relatively low voltage (3V). Are required to operate in a wide voltage range up to a low voltage (1.8 V) considering low power consumption.

  In order to operate in a wide voltage range, the data processing apparatus has a plurality of power supply circuits (regulators) inside, generates an internal operating voltage from an external supply voltage, and supplies it to an internal functional block ( The operation state of the power supply circuit is determined by a signal based on the operation mode of the central processing unit (see Patent Document 2).

  In order to reduce power consumption, the data processing apparatus uses a voltage obtained by reducing the external supply voltage as an internal voltage, and performs an intermittent operation for transitioning to a low power consumption state during a period when the operation is unnecessary. Yes. In the low power consumption state, the clock and power supplied to the functional blocks inside the data processing apparatus are controlled. Specifically, the frequency of the clock to be supplied is reduced, the power supply voltage to be supplied is reduced, or the supply of the clock and power is stopped (see Patent Document 3 and Patent Document 4).

JP 2002-83872 A Japanese Patent Laid-Open No. 2001-21640 JP-A-7-28549 JP 2010-118746 A

  When such an internal voltage is generated by incorporating such a step-down power supply circuit, self-power consumption consumed by the step-down power supply circuit itself becomes a problem in reducing power consumption.

  For example, in the step-down power supply circuit described in FIG. 2 of Patent Document 1, the driver MOS transistor 40 that lowers the external supply voltage to the internal operating voltage reduces the self-power consumption in the operating state where the power consumption is maximum. The on-resistance in the operating state is designed to be minimum.

  Further, in order to ensure driving capability even when the external supply voltage is low, the W size of the gate electrode of the MOS transistor 40 is increased, and a voltage higher than the internal operating voltage is applied to the gate electrode of the output MOS transistor 40. In order to apply, the gate insulating film pressure is increased. As a result, the gate electrode capacitance of the driver MOS transistor 40 is increased. When performing an intermittent operation, there is a problem that when the transition from the low power consumption state to the normal operation state is performed, the increase in the voltage level of the internal operation voltage supplied to the internal functional block is delayed. Further, when transitioning from the normal operation state to the low power consumption state, there is a problem that the extraction of the charge supplied to the internal functional block to the ground potential is delayed, leading to an unexpected increase in the internal supply voltage.

  Therefore, an object of the present invention is to provide a data processing system capable of quickly increasing the voltage level of an internal operating voltage supplied to an internal functional block (load circuit) when performing an intermittent operation.

  A data processing apparatus according to an embodiment of the present invention includes a central processing unit, a load circuit that operates with supplied power, a step-down power supply circuit that steps down an external power supply voltage and has an output node connected to the load circuit The step-down power supply circuit includes a first step-down unit that steps down the external power supply voltage, and a bias current control circuit that controls the magnitude of the bias current flowing through the auxiliary path from the output node to the ground. Is further provided with a controller that increases the magnitude of the bias current prior to a change in the operating state in which the amount of current consumed in the load circuit changes relatively greatly.

  According to an embodiment of the present invention, the voltage level of the internal operating voltage supplied to the internal functional block (load circuit) when performing intermittent operation can be quickly increased.

It is the figure which showed an example of the data processing system which has a data processor. It is a schematic block diagram of the data processor which has a central processing unit. It is a figure showing the step-down power supply circuit of 1st Embodiment. FIG. 6 is a diagram for describing operations when the data processing device transitions from a normal operation state to a low power consumption state and when the data processing device transitions from a low power consumption state to a normal operation state in the first embodiment. It is a figure showing the operation timing of a data processing system. It is a figure for demonstrating operation | movement at the time of a data processing system changing to a normal operation state from a low power consumption state. It is a figure for demonstrating operation | movement at the time of a data processing system changing from a normal operation state to a low power consumption state. It is a figure showing the step-down power supply circuit of 2nd Embodiment. It is a figure for demonstrating operation | movement when changing from the normal operation state of a data processor in a 2nd Embodiment to a low power consumption state, and changing from a low power consumption state to a normal operation state. It is a figure showing the step-down power supply circuit of 3rd Embodiment.

  In an embodiment of the present invention, an output driver MOS transistor of a step-down power supply circuit precedes a change in operating state accompanied by a relatively large change in the amount of current required for operation in a functional block such as a central processing unit in a data processing device. An example of controlling the magnitude of the bias current for increasing the amount of current that can be supplied will be described.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
FIG. 1 is a diagram illustrating an example of a data processing system having a data processing device.

  Referring to FIG. 1, a data processing system 1 includes a printed wiring board 18, a data processing device 2 mounted on the printed wiring board 18, a sensor 4, a communication unit 6, a timer 8, and a battery 12. including. The data processor 2 is supplied with the voltage of the battery 12 as the power supply voltage Vcc.

  FIG. 2 is a schematic configuration diagram of a data processing apparatus having a central processing unit CPU. FIG. 2 shows functional units unique to the present invention in addition to a general microcomputer configuration.

  Referring to FIG. 2, a data processing device 2 includes a central processing unit CPU, a memory 22, a bus 21 for transferring data and addresses, a data transfer unit (direct memory access controller) DMAC, and an analog / digital conversion unit. An ADC, an interrupt controller INTC, a serial communication unit SCIO, a system controller SYSC, a clock circuit 26, a power supply circuit 24, and a voltage detection unit 10 are included.

  The memory 22 includes a flash memory 23, a ROM (Read Only Memory) 30, and a RAM (Random Access Memory) 31. The memory 22 stores data and programs.

  The central processing unit CPU sequentially executes the programs stored in the memory 22 and controls the operation of the entire data processing device 2.

The serial communication unit SCIO stores data input from the outside in the memory 22.
The analog / digital converter (ADC) converts an analog signal input from the outside into a digital value and stores it in the memory 22.

  The data transfer unit DMAC controls data transfer via the bus 21 when storing the digital data of the serial communication unit SCIO and the analog / digital conversion unit ADC in the memory 22.

  The interrupt controller INTC receives an interrupt signal issued by an external or internal functional unit and issues an interrupt to the central processing unit CPU. The central processing unit CPU performs processing according to the interrupt contents.

  The clock circuit 26 includes a plurality of clock sources including a low-speed clock oscillator LOCO and a high-speed clock oscillator HOCO. The clock circuit 26 generates an operation clock CLK of the data processing device 2 and supplies an operation clock having a frequency corresponding to each function unit in the data processing device 2 to each function unit.

  The power supply circuit 24 steps down or boosts the external supply voltage Vcc and supplies it to each component in the data processing device. Power supply circuit 24 includes a step-down power supply circuit 52 that steps down external supply power supply voltage Vcc to generate internal operating voltage Vdd and the like.

  The voltage detection unit 10 includes a power-on reset circuit POR that generates a reset signal that triggers a power-on reset operation according to a voltage change of the external supply power supply voltage Vcc, and an interrupt signal according to a voltage drop of the external supply power supply voltage Vcc. Alternatively, a voltage drop detection circuit LVD that generates a reset signal is included.

  The system controller SYSC controls the operation of the entire data processing apparatus. The system controller SYSC controls supply of a clock and power to each functional block (that is, a load circuit) in the data processing device including the central processing unit CPU. Further, the system controller SYSC controls the step-down power supply circuit 52.

  With reference to FIGS. 1 and 2, the sensor 4 generates an analog signal to be input to the analog / digital conversion unit ADC.

  The communication unit 6 performs data communication control with the outside of the system via the terminal 14, and inputs data to the serial communication unit SCIO or receives data from the serial communication unit SCIO.

  The timer 8 issues an interrupt signal to the data processing device 2 as the time set by the data processing device 2 elapses.

  The data processing device 2 is supplied with an operating power supply voltage Vcc by an externally connected battery 12.

(Step-down power supply circuit)
FIG. 3 is a diagram illustrating the step-down power supply circuit according to the first embodiment.

With reference to FIG. 3, the step-down power supply circuit 52 includes a step-down unit 50.
The step-down unit 50 includes a differential operational amplifier 51.

  The differential operational amplifier 51 includes P channel MOS transistors TR1, TR2, TR5, TR7 and N channel MOS transistors TR4, TR3, TR6, TR8. Reference voltage Vref is input to the gate of N-channel MOS transistor TR6. The step-down voltage Vdd of the output node N4 of the step-down power supply circuit 52 is input to the gate of the N-channel MOS transistor TR3.

  The step-down unit 50 further includes an N-channel MOS transistor TR9 provided between a connection node N2 between the N-channel MOS transistor TR3 and the N-channel MOS transistor TR6 and the ground GND. The step-down unit 50 further includes an N-channel MOS transistor TR10 provided between the output node N4 of the step-down power supply circuit 52 and the ground GND.

  The step-down unit 50 further includes a large output MOS transistor TR40 provided between the external power supply voltage node Vcc and the output node N4 of the step-down power supply circuit 52. The output MOS transistor TR40 is an N-channel DMOS (double-diffused MOS) transistor. The output node N1 of the differential operational amplifier 51 is connected to the gate of the output MOS transistor TR40. The differential operational amplifier 51 applies a voltage corresponding to the potential difference between the reference voltage Vref and the step-down voltage Vdd to the gate of the output MOS transistor TR40.

  The output node N4 of the step-down power supply circuit 52 is connected to the load circuit 99, and the step-down voltage Vdd of the output node N4 is supplied to the load circuit 99.

  The step-down power supply circuit 52 includes a bias current control circuit 41 provided in an auxiliary path RT parallel to the path to the output node N4 and the load circuit 99. That is, the drain-source path of the output MOS transistor TR40 and the bias current control circuit 41 are connected in series between the external supply voltage node Vcc and the ground GND.

  Bias current control circuit 41 includes an N channel MOS transistor TR11 and an N channel MOS transistor TR12 connected in series between output node N4 of step-down power supply circuit 52 and ground GND.

  A bias control signal icont is input to the gate of the N-channel MOS transistor TR11. The magnitude of the bias control signal icont is activated to “H” level when transitioning from the normal operation state to the low power consumption state and when transitioning from the low power consumption state to the normal operation state.

  On the other hand, control signal vbias is input to the gate of N channel MOS transistor TR9, the gate of N channel MOS transistor TR10, and the gate of N channel MOS transistor TR12. The control signal vbias is “H” level in the first and last periods of the normal operation state and the low power consumption state, and is “L” level in the period excluding the first and last of the low power consumption state.

  Therefore, when transitioning from the normal operation state to the low power consumption state and when transitioning from the low power consumption state to the normal operation state, that is, operations involving a relatively large change in the amount of current required for operation in the load circuit 99 When the state changes, the bias current Ib flowing through the auxiliary path RT from the output node N4 to the ground GND increases through the bias current control circuit 41.

(Operation timing of step-down power supply circuit 52)
FIG. 4 is a diagram for explaining the operation of the data processing apparatus when transitioning from the normal operation state to the low power consumption state and when transitioning from the low power consumption state to the normal operation state.

  Referring to FIG. 4, in the normal operation state, the power consumption is relatively high. In the normal operation state, the central processing unit CPU operates in synchronization with a 50 MHz clock signal output from the high-speed clock oscillator HOCO. In addition, other functional blocks in the data processing device 2 also operate.

  In the low power consumption state, the power consumption is relatively small. In the low power consumption state, the supply of the clock signal to the central processing unit CPU is stopped.

(A) Transition from the normal operation state to the low power consumption state When the load circuit 99 including the central processing unit CPU transitions from the normal operation state to the low power consumption state, the system controller SYSC precedes the state transition. Activates the bias control signal Icont to the bias current control circuit 41 to the “H” level.

  The bias current control circuit 41 increases the amount of current flowing from the output node N4 of the step-down power supply circuit 52 to the ground GND in response to the activation of the bias control signal Icont.

  As a result, the voltage at the output node N4 decreases, but the amount of current flowing to the load circuit 99 including the central processing unit CPU is relatively large, and the on-resistance of the drain-source path of the output MOS transistor TR40 is sufficiently high. Since the voltage drops, this voltage drop is limited, and the voltage applied to the gate electrode of the output MOS transistor TR40 hardly changes. In this state, the load circuit 99 including the central processing unit CPU transitions to the low power consumption state. The electric charge stays at the output node N4 due to the fact that the current supply to the load circuit 99 including the central processing unit CPU becomes unnecessary, but this electric charge stay can be discharged to the ground GND via the bias current control circuit 41. Since the amount of current is increased, an increase in voltage at the output node N4 can be suppressed.

  After the load circuit 99 including the central processing unit CPU completes the transition to the low power consumption state and waits for a predetermined time required to eliminate the charge retention at the output node N4, the system controller SYSC receives the control signal vbias. The bias control signal Icont to the bias current control circuit 41 is set to “L” level and set to “L” level.

  Even if the load circuit 99 including the central processing unit CPU shifts to the low power consumption state, there is a functional block that operates the interrupt controller INTC and the like, and therefore the load circuit 99 as a whole has a predetermined amount of current. Is consumed. After deactivation of the bias control signal Icont to the bias current control circuit 41, the step-down power supply circuit 52 supplies a predetermined amount of current required by the load circuit 99 and maintains the potential Vdd of the output node N4 constant. About a voltage is applied to the gate electrode of the output MOS transistor TR40.

(B) Transition from the low power consumption state to the normal operation state When the load circuit 99 including the central processing unit CPU transitions from the low power consumption state to the normal operation state, the system controller SYSC Then, the control signal vbias is set to the “H” level, and the bias control signal Icont to the bias current control circuit 41 is activated to the “H” level.

  The bias current control circuit 41 increases the amount of current flowing from the output node N4 of the step-down power supply circuit 52 to the ground GND in response to the activation of the bias control signal Icont. Since the output MOS transistor TR40 applies a voltage to the gate electrode to supply a predetermined amount of current required by the load circuit 99 in the low power consumption state, the bias current flowing to the ground GND by the bias current control circuit 41. As Ib increases, the voltage at output node N4 decreases. In response to the voltage drop at the output node N4, the differential operational amplifier 51 increases the voltage applied to the gate electrode of the output MOS transistor TR40 to increase the amount of current flowing through the output MOS transistor TR40. Even if the load circuit 99 including the central processing unit CPU transitions to the normal operation state after entering this state, the output MOS transistor TR40 supplies the current required by the load circuit 99 including the central processing unit CPU. The voltage drop at the output node N4 can be suppressed.

(Data processing system operation timing)
FIG. 5 is a diagram showing the operation timing of the data processing system.

  2 and 5, in the first period TP1, the data processing device 2 is started by the timer 8 at regular time intervals, repeatedly performs a predetermined process, and then transitions to the low power consumption state. Yes. In the second period triggered by the occurrence of a predetermined event, processing for responding to the event is performed.

  As a data processing system that operates in this way, for example, a data processing system used in a power meter is applicable.

  That is, the data processing system records (for example, processing time 0.1 second) or notifies the power usage amount every predetermined time (for example, 24 hours). The data processing system notifies the power company of the amount of power used every month (for example, processing time is 1 second).

  In the first period TP1, the interrupt controller INTC receives the notification from the timer 8 and generates an interrupt notification to the central processing unit CPU. When receiving the interrupt notification, the central processing unit CPU transitions from the low power consumption state to the normal operation state. In this normal operation state, the central processing unit CPU performs a power consumption recording process (Process 1) and a notification process (Process 2) of the recorded power usage every few minutes.

  In the second period TP2, when a predetermined event such as a request from the user occurs, the interrupt controller INTC generates an interrupt notification to the central processing unit CPU. When receiving the interrupt notification, the central processing unit CPU transitions from the low power consumption state to the normal operation state. In this normal operation state, the central processing unit CPU performs notification processing (processing 3) of the recorded power consumption for one month, or performs control program update processing.

(Transition from low power consumption state to normal operation state)
FIG. 6 is a diagram for explaining an operation when the data processing system transitions from the low power consumption state to the normal operation state.

  First, the interrupt controller INTC receives the notification from the timer 8 (shown in (1)) and notifies the system controller SYSC to shift the central processing unit CPU from the low power consumption state to the normal operation state. (Shown in (2)).

  In response to this notification from the interrupt controller INTC, the system controller SYSC starts outputting the bias control signal Icont to the bias current control circuit 41, that is, activates to the “H” level (shown in (3)). ).

  The system controller SYSC waits for a predetermined time until the amount of current that can be supplied by the output MOS transistor TR40 of the step-down power supply circuit 52 increases, and then issues a transition instruction to the normal operation state to the central processing unit CPU. (Shown in (4)).

  The interrupt controller INTC issues an interrupt notification to the central processing unit CPU in response to the completion of the transition of the central processing unit CPU to the normal operation state (shown in (5)).

  The central processing unit CPU starts processing in response to the interrupt notification from the interrupt controller INTC (shown in (6)).

  The system controller SYSC waits for the elapse of a predetermined time until the central processing unit CPU completes the transition to the normal operation state and the occurrence of the voltage drop at the output node N4 of the step-down power supply circuit 52 can be suppressed. The output of the bias control signal Icont to the circuit 41 is stopped, that is, deactivated to the “L” level.

(Transition from normal operation state to low power consumption state)
FIG. 7 is a diagram for explaining an operation when the data processing system transits from the normal operation state to the low power consumption state.

  When the central processing unit CPU completes the process (shown in (1)), it requests the system controller SYSC to transition to the low power consumption state (shown in (2)).

  In response to this request from the central processing unit CPU, the system controller SYSC starts outputting the bias control signal Icont to the bias current control circuit 41 (that is, activated to the “H” level) to control the bias current. The amount of the bias current Ib that the circuit 41 can flow to the ground GND is increased (shown in (3)).

  Thereafter, the system controller SYSC issues a transition instruction to the low power consumption state to the central processing unit CPU (shown in (4)).

  Thereafter, the system controller SYSC stops outputting the bias control signal Icont to the bias current control circuit 41 after a predetermined time required for eliminating the charge retention caused by the stop of the operation of the central processing unit CPU. (That is, deactivated to “L” level) (shown in (5)).

  As described above, according to the first embodiment, the load circuit precedes the transition in the transition from the normal operation state to the low power consumption state and in the transition from the low power consumption state to the normal operation state. The bias current flowing in the auxiliary path different from the path to is increased, and the increase of the bias current is stopped after a predetermined time has elapsed after the transition. Thereby, the current required by the load circuit can be supplied at an appropriate timing according to the internal operation state of the load circuit, and an unexpected decrease or increase in the voltage supplied to the load circuit can be suppressed.

[Second Embodiment]
FIG. 8 is a diagram illustrating a step-down power supply circuit according to the second embodiment.

  The step-down power supply circuit 62 includes a first step-down unit 60, a second step-down unit 61, and a bias current control circuit 41.

The bias current control circuit 41 is the same as that shown in FIG.
The first step-down unit 60 has substantially the same configuration as the step-down unit 50 of FIG. The first step-down unit 60 is different from the step-down unit 50 of FIG. 3 as follows.

  First step-down unit 60 includes a P-channel MOS transistor TR21 provided between the gates of P-channel MOS transistor TR1 and P-channel MOS transistor TR2 and external power supply voltage node Vcc. Control signal / pd is input to the gate of P-channel MOS transistor TR21. When control signal / pd goes to "L" level, P channel MOS transistor TR21 is turned on. As a result, P channel MOS transistor TR1 and P channel MOS transistor TR2 are turned off and no current flows, so that power consumption can be reduced. .

  First step-down unit 60 includes a P-channel MOS transistor TR22 provided between the gates of P-channel MOS transistor TR5 and P-channel MOS transistor TR7 and external power supply voltage node Vcc. Control signal / pd is input to the gate of P-channel MOS transistor TR22. When control signal / pd goes to "L" level, P channel MOS transistor TR22 is turned on. As a result, P channel MOS transistor TR5 and P channel MOS transistor TR7 are turned off, and no current flows, so that power consumption can be reduced. .

  First step-down unit 60 includes a P-channel MOS transistor TR23 provided between external power supply voltage node Vcc and output MOS transistor TR40. A control signal pd is input to the gate of the P-channel MOS transistor TR23.

  The first step-down unit 60 includes an N-channel MOS transistor TR24 provided between the gate of the output transistor TR40 and the ground GND. A control signal pd is input to the gate of the N-channel MOS transistor TR24.

  When the control signal pd becomes “H” level, the P-channel MOS transistor TR23 is turned off and the output MOS transistor TR40 is turned off. As a result, no current flows through the output MOS transistor TR40, and power consumption can be reduced.

  In the second embodiment, the control signal vbias input to the gate of the N-channel MOS transistor TR9, the gate of the N-channel MOS transistor TR10, and the gate of the N-channel MOS transistor TR12 is the same as in the first embodiment. “H” level in the first and last periods of the normal operation state and the low power consumption state, and “L” level in the period excluding the first and last of the low power consumption state. Thus, in the low power consumption state, no current flows through these transistors, and power consumption can be reduced.

  In the first and last periods of the normal operation state and the low power consumption state, as shown in FIG. 9, the system controller SYSC sets the control signal vbias to the “H” level and the control signal pd to the “L” level. Then, the control signal / pd is set to the “H” level. As a result, the output MOS transistor TR40, the P channel MOS transistors TR1, TR2, TR5, TR7 and the N channel MOS transistors TR9, TR10, TR12 are turned on, and the step-down operation in the first step-down unit 60 is executed.

  Further, in the period excluding the first and last in the low power consumption state, the system controller SYSC sets the control signal vbias to the “L” level and the control signal pd to the “H” level as shown in FIG. The control signal / pd is set to the “L” level. As a result, the output MOS transistor TR40, the P-channel MOS transistors TR1, TR2, TR5, TR7 and the N-channel MOS transistors TR9, TR10, TR12 are turned off, and the step-down operation in the first step-down unit 60 is not performed, but the leakage current is reduced. It becomes possible to suppress.

The second step-down unit 61 includes a differential operational amplifier 54 similar to the differential operational amplifier 51 of FIG.
The second step-down unit 61 includes a small output MOS transistor TR25 provided between the external power supply voltage node Vcc and the output node N4 of the step-down power supply circuit. Output MOS transistor TR25 is formed of a P-channel MOS transistor. The output node of the differential operational amplifier 54 is connected to the gate of the output MOS transistor TR25. The differential operational amplifier 54 applies a voltage corresponding to the potential difference between the reference voltage Vref and the step-down voltage Vdd to the gate of the output MOS transistor TR25.

  The second step-down unit 61 operates constantly while external power is supplied to the data processing device, and supplies the step-down voltage Vdd to the load circuit 99. The second step-down unit 61 is a current required for the interrupt controller INTC, the system controller SYSC, and the like in the operation state included in the load circuit 99 to operate even during the period when the central processing unit CPU is in the low power consumption state. Supply.

  As described above, according to the second embodiment, similarly to the first embodiment, the voltage level of the internal operating voltage of the load circuit can be quickly increased. In the second embodiment, the step-down operation is executed by the first step-down unit and the second step-down unit in the normal operation state, and the step-down operation is executed only by the second step-down unit in the low power consumption state.

[Third Embodiment]
FIG. 10 is a diagram illustrating a step-down power supply circuit according to the third embodiment.

  Referring to FIG. 10, this step-down power supply circuit 72 is different from the step-down power supply circuit of FIG. 8 in the bias current control circuit.

  The bias current control circuit 42 of FIG. 10 includes an N-channel DMOS transistor TR31 and an N-channel MOS transistor TR12 connected in series between the output node N4 of the step-down power supply circuit 72 and the ground GND.

  A bias control signal icont is input to the gate of the N-channel MOS transistor TR12. As in the first and second embodiments, the magnitude of the bias control signal icont changes when transitioning from the normal operation state to the low power consumption state and when transitioning from the low power consumption state to the normal operation state. The signal is activated to “H” level prior to the transition to “L” level after a predetermined time elapses after the transition.

N channel DMOS transistor TR31 has its gate connected to output node N4.
When the voltage at output node N4 is high, N-channel DMOS transistor TR31 has a low on-resistance, and bias current Ib flowing through bias current control circuit 42 increases. On the other hand, when the voltage at output node N4 is low, the on-resistance of N-channel DMOS transistor TR31 increases and the bias current Ib flowing through bias current control circuit 42 decreases.

As described above, according to the third embodiment, the same effect as in the second embodiment can be obtained.
(Modification)
The present invention is not limited to the above embodiment, and includes, for example, the following modifications.

(1) Transition In the embodiment of the present invention, as a change in the operation state accompanied by a relatively large change in the amount of current required for operation in a functional block such as a central processing unit in the data processing device, power consumption is reduced from the normal operation state. The transition to the state and the transition from the low power consumption state to the normal operation state have been described. In the normal operation state, the high-speed clock oscillator HOCO is supplied to the central processing unit CPU. In the low power consumption state, the clock is not supplied to the central processing unit CPU. However, the present invention is not limited to this.

  Generally, from a relatively low power consumption state to a relatively high power consumption state as a change in operation state accompanied by a relatively large change in the amount of current required for operation in a functional block such as a central processing unit in a data processing device. Or a transition from a relatively high power consumption state to a relatively low power consumption state.

  As an example of the transition between the relatively low power consumption state and the relatively high power consumption state, in addition to the above, for example, the frequency of the clock output from the clock circuit by changing the clock division ratio May be changed. That is, by changing the clock division ratio, a high-frequency clock is supplied to the central processing unit CPU in a relatively high power consumption state, and a low-frequency clock is supplied to the central processing unit CPU in a relatively low power consumption state. May be supplied.

  As another example of such a transition, the frequency of the clock output from the clock circuit may be changed by changing the clock source. That is, in the relatively high power consumption state, the clock from the high-speed clock oscillator HOCO is supplied to the central processing unit CPU, and in the relatively low power consumption state, the clock from the low-speed clock oscillator LOCO is supplied to the central processing unit CPU. It may also be done.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  DESCRIPTION OF SYMBOLS 1 Data processing system, 2 Data processing apparatus, 4 Sensor, 6 Communication part, 8 Timer, 12 Battery, 14 terminal, 18 Printed wiring board, 21 Bus, 22 Memory, 23 Flash memory, 24 Power supply circuit, 26 Clock circuit, 30 ROM, 31 RAM, 41, 42 Bias current control circuit, 50 step-down unit, 51, 54 differential operational amplifier, 52 step-down power supply circuit, 60 first step-down unit, 61 second step-down unit, 99 load circuit, ADC analog / digital conversion Unit, CPU central processing unit, DMAC data transfer unit, INTC interrupt controller, LVD voltage drop detection circuit, POR power-on reset circuit, SCIO serial communication unit, SYSC system controller, HOCO high-speed clock oscillator, LOCO low-speed clock oscillator, TR1 T R12, TR21 to TR25, TR31, TR40 MOS transistors.

Claims (4)

A data processing system,
Battery,
A sensor,
A timer,
A communication department;
When the operation power supply voltage is supplied from the battery and intermittently started by the timer, a transition is made from a low power consumption state with a relatively small current consumption amount to a high power consumption state with a relatively large current consumption amount. A data processing device that processes the output from the sensor, supplies the processed data to the communication unit, and is then controlled to transition from the high power consumption state to the low power consumption state;
The data processing device includes:
A load circuit including a central processing unit and operating with supplied power;
A step-down power supply circuit that steps down the operating power supply voltage and has an output node connected to the load circuit;
The step-down power supply circuit includes:
A first step-down unit for stepping down the operating power supply voltage;
A bias current control circuit for controlling the magnitude of the bias current flowing through the auxiliary path from the output node to the ground,
The data processing device further precedes a transition when the load circuit transitions from the low power consumption state to the high power consumption state and from the high power consumption state to the low power consumption state. A data processing system comprising a control unit for increasing the magnitude of the bias current. The first step-down unit
A differential operational amplifier for amplifying a potential difference between a reference voltage and the output node;
The data processing system according to claim 1, further comprising: an output transistor provided between the output node and an external power supply node and having a gate connected to an output of the differential operational amplifier.   The data processing system according to claim 1, wherein the control unit decreases the magnitude of the bias current after a predetermined time has elapsed after the transition. The step-down power supply circuit further includes a second step-down unit that steps down the operating power supply voltage,
The first step-down unit operates only in the high power consumption state,
The data processing system according to claim 1, wherein the second step-down unit operates in the high power consumption state and the low power consumption state.

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