JP4707289B2 - Manufacturing method of multilayer wiring board - Google Patents

Description

【００８４】
表１の結果から明らかなように、ＵＶ−ＹＡＧレーザを用いて表面多層配線層にバイアホールを形成し、少なくともバイア導体のコア基板側における導体配線層の表面粗さ（Ｒｚ）を絶縁層との接着部よりも小さくした試料Ｎｏ．１〜７では、バイア導体１穴あたりの電気抵抗の変化率が９．７％以下であった。特に、バイア導体の最大径の小さい側に当接する導体配線層の表面粗さ（Ｒｚ）が０．９μｍ以下で、絶縁層接着部とこのバイア導体の最大径に当接する導体配線層の表面粗さ（Ｒｚ）の差が２．１μｍ以上とした試料Ｎｏ．３、５、６では、バイア導体１穴あたりの電気抵抗の変化率が６．８％以下とさらに低くなり、バイア導体と導体配線層との接続がさらに強固であった。
【００８５】
一方、ＣＯ₂レーザを用いてバイアホールを形成した試料Ｎｏ．８では、導体配線層の、バイア導体との当接部の表面粗さと絶縁層との接着部の表面粗さとが同じとなり、この試料では、バイア導体１穴あたりの電気抵抗の変化率が２１．３％と大きかった。
【００８６】
【発明の効果】
以上詳述したように、表面多層配線層に形成されたバイア導体のコア基板側における導体配線層との当接部の表面粗さを、表面多層配線層を構成する絶縁層との接着部の表面粗さよりも小さくすることにより、バイア導体と当接する部分の導体配線層の表面が平滑となり、バイア導体を構成する金属成分と導体配線層の金属箔との濡れ性が高まり接合面を大きくできることから接合部を強固にでき、バイア導体の抵抗値とバラツキを小さくし接続信頼性を向上できる。
【図面の簡単な説明】
【図１】本発明のコア基板表面に表面多層配線層を形成した多層配線基板の一例を説明するための概略断面図である。
【図２】表面多層配線層に形成されたバイア導体と導体配線層との接合部の要部拡大図である。
【図３】本発明の多層配線基板の製造方法の一例を説明するための工程図である。
【符号の説明】
Ａ・・・・・・・・・・・・コア基板
Ｂ・・・・・・・・・・・・表面多層配線層
１ａ〜１ｅ、３ａ〜３ｄ・・絶縁層
５・・・・・・・・・・・・絶縁基板
７、１１、２７、４５・・・導体配線層
８、１３、２５、４７・・・バイア導体
１５、２３、４３・・・・・バイアホール
１７・・・・・・・・・・・当接部
１９・・・・・・・・・・・接着部
２１、４１・・・・・・・・絶縁シート[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a multilayer wiring board.ofIn particular, a multilayer wiring board in which a surface multilayer wiring layer is laminated on the surface of a core substrate.ofIt relates to a manufacturing method.
[0002]
[Prior art]
In recent years, with the development of portable information terminals and the spread of mobile computing, a multilayer wiring board suitable for small size, high definition and high-speed operation has been demanded.
[0003]
2. Description of the Related Art As a multilayer wiring board for meeting such a demand for high definition and high speed operation, one manufactured by a build-up method is conventionally known.
[0004]
A multilayer wiring board formed by the build-up method forms a via hole by applying a photosensitive resin to the surface of a core substrate made of a glass epoxy composite material to form an insulating layer, and exposing and developing the insulating layer. Is formed.
[0005]
Next, after forming a plating layer such as copper on the entire surface of the insulating layer including the inner wall of the via hole, a conductive resist is applied / exposure / development / etching / resist removal on the surface of the plating layer. It is produced by forming.
[0006]
[Problems to be solved by the invention]
However, in the above build-up method in which an insulating layer is formed on the surface of the core substrate using a photosensitive resin, a via hole formed inside the insulating layer is formed by ultraviolet exposure, and thus is originally exposed under the via hole. The surface of the conductor wiring layer is not processed, and the surface roughness of the conductor wiring layer is rough, leaving an uneven shape so as to maintain the adhesiveness to the insulating layer. For this reason, thermosetting resin residues are present in the recesses on the surface of the conductor wiring layer, and since this surface is covered with an oxide film, there is no metal connection between the via conductor and the conductor wiring layer. In the reliability evaluation such as the temperature cycle test, the via conductor and the conductor wiring layer are likely to be disconnected and the reliability is lowered.
[0007]
  Accordingly, the present invention provides a multilayer wiring board that improves electrical connection between via conductors and conductor wiring layers in a surface multilayer wiring layer formed on the surface of a core substrate.ofAn object is to provide a manufacturing method.
[0017]
[Means for Solving the Problems]
  The method for producing a multilayer wiring board of the present invention includes: (a) a step of producing a core substrate formed by forming a conductor wiring layer having a roughened upper surface on at least the surface of an insulating sheet containing at least a thermosetting resin; (B) thermocompression bonding the semi-cured first insulating sheet to the surface of the core substrate; and (c) a predetermined portion of the first insulating sheet;UV-YAG with a processing output of 0.1 to 2.0 W and a unit time of 1 to 50 kHzIrradiate laser lightMaximum diameter is 75μm or lessForm a via holeWhileSmoothing the uneven surface on the upper surface of the conductor wiring layer formed on the surface of the core substrate, and filling the via hole formed in (d) and (c) with a conductor paste containing metal powder and an organic component. (E) forming a first conductor wiring layer having a roughened upper surface side on the first insulating sheet on which the via conductor is formed, and (f) (b) to (b) e) Repeat the process to make multiple layersTo form a surface multilayer wiring layerA manufacturing method comprising the steps of:
[0018]
In this manufacturing method, first, an insulating sheet is processed using a laser beam, whereby a tapered via hole with a small diameter and high shape accuracy can be easily formed. Further, the formation of the via hole and the smoothing of the uneven surface on the upper surface of the conductor wiring layer exposed at the bottom of the via hole can be performed simultaneously.
[0019]
Furthermore, according to the manufacturing method of the present invention, since the via hole for connecting the conductor wiring layers in the surface multilayer wiring layer is formed by laser light irradiation, it is not necessary to use a photosensitive resin, and the insulating layer Any insulating material having a high glass transition point and a low water absorption rate and having excellent material properties can be selected. In addition, the formation of the insulating layer and the formation of the conductor wiring layer can be performed simultaneously in parallel, and all the insulating layers can be cured at once, thereby simplifying and shortening the manufacturing process. it can.
[0020]
In the method for manufacturing a multilayer wiring board, the surface roughness (Rz) of the conductor wiring layer that abuts on the core board side of the via conductor formed on the first insulating sheet.₁) And the surface roughness (Rz) of the bonding portion between the conductor wiring layer and the insulating layer constituting the surface multilayer wiring layer₂) Is preferably 0.5 μm or more. Thus, the via conductor and the conductor wiring layer can be easily joined by making the surface of the conductor wiring layer in contact with the via conductor smoother than the part to which the insulating sheet adheres. Further, the surface roughness (Rz) of the bonding portion between the conductor wiring layer and the insulating layer constituting the surface multilayer wiring layer₂) Is 0.5 μm or more, the anchor effect of the conductor wiring layer is enhanced and the insulating layer can be firmly bonded.
[0021]
In the method for manufacturing a multilayer wiring board, the via conductors formed on the first insulating sheet have different via diameters at both ends, and the via diameter on the core board side is smaller than the via diameter on the opposite side to the core board side. It is desirable. Since the via conductor with the smaller maximum diameter is difficult to connect to the conductor wiring layer, the connection with the conductor wiring layer with the larger maximum diameter is made smoother by making the smaller diameter diameter smoother. In addition, the conductivity can be easily made the same.
[0022]
In the method for manufacturing a multilayer wiring board, the surface roughness (Rz) of the conductor wiring layer that abuts on the core substrate side of the via conductor formed on the first insulating sheet.₁) Is preferably 0.5 to 1.5 μm. When the via conductor diameter is small and the contact area with the conductor wiring layer is narrow, the surface roughness of the conductor wiring layer (Rz₁) As described above can be easily joined to the end portion side of the via conductor having a small diameter and the conductor wiring layer.
[0023]
In the method for manufacturing a multilayer wiring board, the maximum diameter of the via conductor formed on the first insulating sheet is desirably 75 μm or less. Thus, when the maximum diameter of the via conductor is as small as 75 μm, the manufacturing method of the present invention can be suitably used, and even when the via conductor diameter becomes small, the joint portion with the conductor wiring layer can be strengthened. .
[0024]
In the method for manufacturing a multilayer wiring board, the via conductor formed on the first insulating sheet preferably contains at least one metal of tin, lead, bismuth, indium, or an alloy thereof. By containing a low melting point metal, an alloy phase or an intermetallic compound can be easily formed at the joint between the via conductor and the conductor wiring layer.
[0025]
In the manufacturing method of the multilayer wiring board, it is desirable that the processing output by the laser light is 0.1 to 2.0 W, and the number of pulses per unit time is 1 to 50 kHz. By setting the laser output and the number of pulses in such a range, a via hole with high shape accuracy can be formed, and the surface of the conductor wiring layer exposed at the bottom of the via hole can be smoothed.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
(Construction)
A schematic cross-sectional view of an example of the multilayer wiring board of the present invention is shown in FIG.
[0027]
As shown in FIG. 1, in the multilayer wiring board of the present invention, a surface multilayer wiring layer B is formed on the surface 1 of the core substrate A.
[0028]
The core substrate A includes an insulating substrate 5 formed by laminating a plurality of insulating layers (1a to 1e) containing at least a thermosetting resin, and a conductor wiring layer formed on the surface and inside of the insulating substrate 5. 7 and via conductors 8 connecting the conductor wiring layers 7.
[0029]
Moreover, the surface multilayer wiring layer B laminated | stacked on the surface 1 of the core board | substrate A is comprised by several surface insulation layers (3a-3d) containing a thermosetting resin at least like the core board | substrate A, A conductor wiring layer 11 is formed on the surface and inside of the insulating layers (3a to 3d), and a via conductor 13 for connecting the conductor wiring layers 11 is further formed.
[0030]
FIG. 2 is an enlarged view of a main part showing a joint portion between the via conductor 13 and the conductor wiring layers 7 and 11 formed in the surface multilayer wiring layer B. FIG. As shown in FIG. 2, the via conductor 13 formed in the surface multilayer wiring layer B of the conductor wiring layer 11 has a tapered shape in which the via diameter on the core substrate A side is smaller than that on the opposite side.
[0031]
Thus, the via conductor 13 has different diameters at both ends, and the maximum diameter difference between both ends of the via conductor 13 is that the maximum diameter on the small diameter side is Ds and the maximum diameter on the large diameter side is D._LDs / D_LIt is desirable that it is> 0.6 or more because the connection between the via conductor 13 and the conductor wiring layers 7 and 11 is ensured and the generation of local stress in a temperature cycle test or the like is suppressed.
[0032]
Further, the maximum diameter of the via conductor 13 formed in the surface multilayer wiring layer B is preferably 75 μm or less. In particular, a high-density surface multilayer wiring layer B can be formed, and the via conductor 13 has a small maximum diameter. Even so, the maximum diameter of the via conductor 13 is desirably 40 to 60 μm because the interlayer connection of the surface multilayer wiring layer B can be ensured.
[0033]
According to the present invention, the surface roughness (Rz) of the contact portion 17 of the conductor wiring layers 7 and 11 on the core substrate A side of the via conductor 13 is determined.₁) Is the surface roughness (Rz) of the adhesion part 19 with the insulating layers 1a to 1e and 3a to 3d.₂It is important to be smaller than Thus, by smoothing the upper surfaces of the conductor wiring layers 7 and 11 in contact with the via conductor 13, the wettability between the metal components constituting the via conductor 13 and the metal foil of the conductor wiring layers 7 and 11 is increased. The joint part of both can be strengthened.
[0034]
On the other hand, the surface roughness (Rz) of the conductor wiring layers 7 and 11 adhered to the insulating layers 1a to 1e and 3a to 3d.₂) Is processed to be large, and from this, the thermosetting resin contained in the insulating layers 1a to 1e and 3a to 3d enters the recesses of the conductor wiring layers 7 and 11, thereby insulating layers 1a to 1e. 3a to 3d and the conductor wiring layers 7 and 11 can be firmly bonded. In addition, the via conductor 13 and the conductor wiring layers 7 and 11 are intimately bonded to each other at the contact portion 17, and an alloy phase of the via conductor 13 and the metal component of the conductor wiring layers 7 and 11 is formed at this interface. Alternatively, an intermetallic compound is formed.
[0035]
Further, the surface roughness (Rz) of the conductor wiring layers 7 and 11 in contact with the via conductor 13₁) Is preferably 0.5 to 1.5 [mu] m, and particularly preferably 0.7 to 1.3 [mu] m for the purpose of improving the wettability without impairing the conductivity of the conductor wiring layers 7 and 11. On the other hand, the surface roughness (Rz) of the insulating layers 3a to 3d and the bonded portion₂) Is preferably 2 μm or more, and particularly preferably in the range of 2.4 to 3.5 μm.
[0036]
Further, the surface roughness (Rz) of the contact portion 17 of the conductor wiring layers 7 and 11 with the via conductor 13 formed in the surface multilayer wiring layer B₁) And the surface roughness (Rz) of the adhesion portion 19 between the insulating layers 3a to 3d constituting the surface multilayer wiring layer B₂) Is preferably 0.5 μm or more, and in particular, the difference is 0.5 to 1.5 μm because the thickness difference between the conductor wiring layers 7 and 11 is reduced and the conductivity is stabilized. desirable. Thereby, the connection between the conductor wiring layers 7 and 11 and the via conductor 13 and the connection between the conductor wiring layers 7 and 11 and the insulating layers 3a to 3d can be further strengthened.
[0037]
On the other hand, the maximum diameter of the via conductor 8 constituting the core substrate A is desirably 300 μm or less because it is possible to form a high-density circuit. Even if the maximum diameter of the via conductor 8 is reduced, the core substrate A It is desirable that the maximum diameter of the via conductor 8 is 70 to 250 μm because the interlayer connection can be ensured.
[0038]
Further, the via conductor 8 formed on the core substrate A also has the same maximum diameter at both ends as the surface via conductor 13 formed on the surface multilayer wiring layer 3, and the maximum at both ends of the via conductor 8. For the diameter difference, the maximum diameter on the small diameter side is Dcs, and the maximum diameter on the large diameter side is Dc._LDcs / Dc_LIt is desirable that it is> 0.6 or more.
[0039]
Further, the conductor wiring layer 7 formed inside the core substrate A also has a surface roughness (a surface contacted with the via conductor 8), similarly to the conductor wiring layer 11 constituting the surface multilayer wiring layer B (see FIG. It is desirable that Rz) is smaller than the surface roughness (Rz) of the bonded portion with the insulating layers 1a to 1e because the connection between the via conductor 8 and the conductor wiring layer 7 is strengthened.
[0040]
Further, the surface roughness of the contact portion of the via conductor 8 of the conductor wiring layer 7 used for the core substrate A is the same surface roughness (Rz) as that of the conductor wiring layer 11 formed on the surface multilayer wiring layer B. It is preferably 0.5 to 1.5 μm, and more preferably 0.7 to 1.3 μm.
[0041]
On the other hand, the surface roughness (Rz) of the portion where the conductor wiring layer 7 adheres to the insulating layers 1a to 1e is preferably 2 μm or more, particularly preferably 2.4 to 3.5 μm, because the adhesive strength is increased.
[0042]
(material)
In the multilayer wiring board of the present invention, the insulating layers 3a to 3d constituting the surface multilayer wiring layer B are made of an insulating material containing at least a thermosetting resin. For example, A-PPE (polyphenylene ether resin), It consists of BT resin (bismaleidotriazine), polyimide resin, fluororesin, polyaminobismaleimide resin, and epoxy resin, and it is particularly desirable that the raw material is a thermosetting resin that is liquid at room temperature.
[0043]
In addition, as the inorganic insulating powder in the insulating layers 3a to 3d laminated on the front and back surfaces of the front surface multilayer wiring layer B, SiO 2₂, Al₂O_Three, ZrO₂TiO₂, AlN, SiC, BaTiO_Three, SrTiO_ThreeAt least one material can be used. In addition, the shape may be any shape such as a spherical shape or a needle shape. In this way, by using the inorganic insulating powder that is discontinuously present in the insulating layers 3a to 3d constituting the surface multilayer wiring layer B, the migration resistance can be enhanced, and the density of the surface multilayer wiring layer B is increased. be able to.
[0044]
On the other hand, the insulating layers 1a to 1e constituting the core substrate A are also preferably made of a thermosetting resin such as A-PPE (polyphenylene ether resin) similar to the insulating layers 3a to 3d constituting the surface multilayer wiring layer B. It is done. In addition, as the filler mixed in the insulating layers 1a to 1e, there are inorganic insulating powders and fiber bodies, and an arbitrary property such as a woven fabric or a nonwoven fabric may be used. Moreover, organic fiber bodies, such as an aramid fiber and a cellulose fiber, can also be used. In particular, as the fibrous body used for the core substrate A, glass fibers impregnated with the thermosetting resin are most desirable in terms of increasing strength.
[0045]
The conductor wiring layers 7 and 11 constituting the core substrate A and the surface multilayer wiring layer B are made of a metal suitable for forming wiring, and include, for example, at least one of gold, silver, copper, and aluminum. A low resistance metal electrolytic metal foil is preferably used. The thickness of the electrolytic metal foil is preferably 1 to 35 μm, and preferably 5 to 18 μm from the viewpoint of low conductivity and suitable for miniaturization of wiring. If the thickness of the electrolytic metal foil, in other words, the thickness of the conductor wiring layers 7 and 11 is smaller than 1 μm, the resistivity of the wiring is increased. If the thickness is larger than 35 μm, the core substrate A and the surface multilayer wiring layer B are deformed at the time of lamination. There is a problem that it becomes large, the amount of metal embedded in the insulating layers 1a to 1e, 3a to 3d increases, the distortion of the core substrate A and the surface multilayer wiring layer B increases, and the substrate is likely to be deformed after the resin is cured. is there. 1 and 2, in the core substrate A and the surface multilayer wiring layer B, the conductor wiring layers 7 and 11 are all embedded in the insulating layers 1a to 1e and 3a to 3d. As described above, since the conductor wiring layers 7 and 11 are both embedded in the surfaces of the insulating layers 1a to 1e and 3a to 3d, stacking faults due to the thickness of the conductor wiring layers 7 and 11 themselves may occur. In addition, it is possible to realize excellent adhesion between the insulating layers 1a to 1e and 3a to 3d and very excellent smoothness as the entire wiring board.
[0046]
Further, as a conductor paste filled in the via hole 15 to be the via conductors 8 and 13, a resin component such as epoxy and cellulose is added to the metal powder forming the conductor wiring layers 7 and 11, and a solvent such as butyl acetate. A kneaded mixture is used. The conductive paste is dried after the filling into the via hole 15, but it is desirable that the conductive paste is free from the beginning. In addition, in order to reduce the resistance of the via conductors 8 and 13 and to improve the connectivity with the metal foils forming the conductor wiring layers 7 and 11 at the top and bottom of the via conductors 8 and 13, at least tin, lead, bismuth, and indium are used. It is desirable to contain one type of metal or an alloy thereof, and in particular, when the metal component constituting the conductor wiring layers 7 and 11 is copper, an alloy between copper or a metal having a higher melting point than a simple substance. Tin is desirable because it can form a compound.
[0047]
Further, the average particle diameter of the metal particles used for the via conductors 8 and 13 is 1 to 15 μm, and 3 to 6 μm for improving the dispersibility of the conductive paste and the wettability and filling properties with the conductor wiring layers 7 and 11. It is desirable that
[0048]
And, in the via conductor 13 formed in the surface multilayer wiring layer B, it is more preferable that the metal components constituting the conductor wiring layers 7 and 11 are included with a thickness of 0.1 μm or more from the end side, As described above, diffusion of the metal components constituting the conductor wiring layers 7 and 11 can strengthen the bonding between the via conductor 13 and the conductor wiring layers 7 and 11. In the multilayer wiring board of the present invention, it is desirable that the metal components constituting the via conductors 8 and 13 contain the same components from the viewpoint of manufacturing the substrate by batch curing.
[0049]
(Manufacturing method)
Next, the manufacturing method of the multilayer wiring board of this invention is demonstrated based on FIG. FIG. 3 is a process diagram for fabricating the multilayer wiring board of FIG.
[0050]
First, in forming the conductor wiring layer 7 on the insulating layers 1a to 1e constituting the core substrate A, as shown in FIG. 3A, the semi-cured insulating sheet 21 is subjected to a desired laser processing. A via hole 23 is formed. Then, as shown in FIG. 3B, a via conductor 25 is formed by filling the via hole 23 with a conductor paste containing metal powder.
[0051]
Next, a conductor wiring layer 27 made of electrolytic metal foil is embedded in one surface of the via conductor 25 of the semi-cured insulating sheet 21 shown in FIG. In the present invention, the conductive wiring layer 27 is formed by transferring a pattern formed by etching a metal foil previously laminated on the resin film 29. As for the transfer conditions, the conductor wiring layer 27 is embedded and transferred on the insulating sheet 21, and the insulating sheet 21 is not deformed when pressurized and heated, and the uncured state is maintained so that subsequent lamination is possible. The temperature, pressure, and time are preferably 100 to 140 ° C, the pressure is 30 to 100 Pa, and the time is 1 to 10 minutes.
[0052]
For example, to form the conductor wiring layer 27, first, a thickness made of one or two or more alloys selected from copper, gold, silver, aluminum and the like produced by plating on the surface of an appropriate resin film 29 is used. A 1 to 35 μm thick electrolytic metal foil is bonded, a resist layer is provided on the surface of the electrolytic metal foil so as to be a mirror image pattern of a desired wiring pattern, and then a mirror image conductor of a predetermined wiring pattern is obtained by etching and resist removal. A wiring layer 27 is formed. The thickness of the conductor wiring layer 27 is preferably 5 to 18 μm because it can be miniaturized and the conductor resistance is lowered. In addition, the surface roughness (Rz) of the conductor wiring layer 27 that is normally not laser processed and is in contact with the maximum diameter side of the via conductors 8 and 13.₂) Is adjusted by the sparse processing.
[0053]
As the resin film 29, known ones such as polyethylene terephthalate, polyethylene naphthalate, polyimide, polyphenylene sulfide, vinyl chloride, and polypropylene can be used. The thickness of the resin film 29 is suitably 10 to 100 μm, preferably 25 to 50 μm. This is because if the thickness of the resin film 29 is smaller than 10 μm, the conductor wiring formed by the deformation or bending of the film tends to cause disconnection, and if the thickness is larger than 100 μm, the resin film becomes inflexible and the sheet is difficult to peel off. Because. As the adhesive for adhering the electrolytic metal foil to the surface of the resin film 29, known adhesives such as acrylic, rubber, silicon, and epoxy can be used.
[0054]
In addition, in order to form the internal conductor wiring layer 27, the thermosetting property that the insulating sheet 21 is formed by pasting an electrolytic metal foil having a surface roughness (Ra) of 0.2 μm or more to the resin film 29 in advance. Since the resin is not exposed to moisture in the etching process, the water absorption can be lowered. At this time, the conductor wiring layer 27 is more easily peeled off from the transferred film when the electrolytic metal foil coupling process is not performed.
[0055]
Next, together with the resin film 29 provided with the front-side conductor wiring layer 27 produced as described above, a resin film 29 comprising the back-side conductor wiring layer 27 produced by the same method is produced. These are laminated on both surfaces of the insulating sheet 21 on which the via conductors 25 are formed, as in the method shown in FIG. Then, as shown in FIG. 3 (d), the laminate is heated under pressure at a temperature of 60 to 150 ° C., a pressure of 1 to 50 MPa, and a time of 1 to 10 minutes, and then the resin film 29 is peeled off. As shown in FIG. 3E, the wiring sheet c in which the conductor wiring layer 27 is embedded on one surface of the insulating sheet 21 can be produced.
[0056]
Thus, when forming the wiring sheet c, the transfer process of the two layers of the conductor wiring layer 27 on the multilayer wiring board is performed simultaneously by laminating and pressing the resin film 29 having the conductor wiring layer 27 formed on both sides thereof. be able to.
[0057]
Further, of the conductor wiring layer 27 embedded in the surface of the wiring sheet c produced as described above, the conductor wiring layer 27 positioned on the surface side of the core substrate A is subjected to a roughening process, and the conductor wiring layer It is desirable that the surface roughness (Rz) of 27 is 0.5 μm or more, particularly 1.6 μm or more.
[0058]
This roughening treatment can be performed by chemical etching treatment using acid treatment such as hydrochloric acid, sulfuric acid, nitric acid, acetic acid, formic acid, etc. For example, it is desirable to spray an acid solution on the surface of the conductor wiring layer 27. Further, it is desirable to form a large number of pointed protrusions on the roughened surface (etched surface). Such pointed protrusions are, for example, 1 μm / min or more with a 10% by mass formic acid solution. It can be satisfactorily formed at the roughening rate.
[0059]
Then, as shown in FIG. 3 (e), the wiring sheets b and d produced in the same manner as in the above (a) to (e) are heated and pressurized and cured together with the wiring sheet c, and these are integrated into an insulating sheet. The core laminated body C can be produced by heating to a temperature at which the thermosetting resin therein is completely cured. In this case, the curing temperature is preferably 200 to 250 ° C. in order to re-cured together with the insulating sheet 41 to be the surface multilayer wiring layer B on the core laminate C.
[0060]
Next, as shown in FIG. 3F, an insulating sheet 41 to be a surface multilayer wiring layer B is laminated on the surface 1 of the core laminate C. The insulating sheet 41 used here is produced by the following method, for example, when a composite material of a thermosetting resin and an inorganic insulating powder is used as an insulating material.
[0061]
First, a kneader (kneader) or three of a mixture obtained by adding the above-described liquid thermosetting resin together with a solvent so that the amount of the inorganic insulating powder is 20 to 80% by volume to the appropriate inorganic insulating powder as described above. An insulating slurry is produced by mixing by means such as a roll.
[0062]
The insulating slurry is preferably prepared by adding a solvent such as toluene, butyl acetate, methyl ethyl ketone, methanol, methyl cellosolve acetate, isopropyl alcohol, methyl isobutyl ketone, dimethylformamide to the composite material of the organic resin and inorganic insulating powder as described above. It consists of a fluid that has a predetermined viscosity when added. Although the viscosity of the slurry depends on the sheet forming method, a rheometer RS100 manufactured by Hake is used, a cone having a diameter of 20 mmφ and an angle of 1 ° is used, and a shear rate of 100 s.^-11 to 30 Pa · s is appropriate under the above conditions.
[0063]
Then, the insulating slurry is formed into a sheet by a sheet forming method such as a rolling method, an extrusion method, an injection method, a die coater method, a doctor blade method, etc., and then a temperature sufficient to completely cure the thermosetting resin as desired. The insulating sheet 41 having a thickness of 25 to 50 μm can be manufactured by heating to a slightly lower temperature and semi-curing the thermosetting resin.
[0064]
After the insulating sheet 41 is bonded under conditions of a temperature of 100 to 160 ° C., a pressure of 1 to 7 MPa, and a time of 1 to 10 minutes, a via hole 43 is formed by a UV-YAG laser or the like. The via hole 43 has a structure in which the conductor wiring layer 27 embedded in the lower layer of the insulating sheet 41 is exposed. At this time, the conductor wiring layer 27 at the bottom of the via hole 43 is a matte surface when forming the metal foil or a roughened surface processed at the time of pattern formation, and the bottomed via hole 43 is formed by laser processing. In this case, the unevenness on the surface is partially smoothed by being melted or sublimated by laser processing. Rz₁Is irradiated with laser so as to be 0.5 to 1.5 μm. The laser processing conditions here are, for example, in the case of a UV-YAG laser processing machine, in which the processing energy is in the range of 0.1 to 2.0 W and the number of pulses per unit time (Rep-Rate) is in the range of 1 kHz to 50 kHz. It is. In this UV-YAG, the smaller the Rep-Rate, the larger the output energy, and the more the number of repetitions of emitting laser light, the more the metal foil is scraped. If it is lower than 0.1 W or higher than 50 kHz, resin residue tends to remain at the bottom of the via hole 43, and if it is higher than 2.0 W or lower than 1 kHz, it penetrates the metal foil at the bottom of the via hole 43. The hole to open or damage to the metal foil. Further, the more the number of repetitions of emitting the laser light, the more the number of repetitions is determined.
[0065]
Thereafter, a via conductor 47 is formed by filling the via hole 43 with a conductive paste containing metal powder in the same manner as in the core substrate A. This conductor paste contains at least one low melting point metal such as tin, lead, bismuth and indium, or an alloy thereof. This low melting point metal is formed at the top and bottom of the via hole by pressing and heating during curing. It wets the foil or diffuses into the metal foil depending on the type of metal.
Further, as in the case where the conductor wiring layer 27 is formed on the core substrate A, the wiring pattern of the metal foil prepared in advance by etching is roughened, and then transferred onto the insulating sheet 41 by transferring it onto the insulating sheet 41. A buried wiring layer 45 can be formed to form a multilayer wiring board as shown in FIG.
[0066]
Thereafter, the insulating sheet 41 and the conductor wiring layer 45 can be multilayered by repeating the above steps as necessary.
[0067]
When a solder resist layer is further formed on the surface of the surface multilayer wiring layer B, a solder resist layer such as an epoxy resin is applied to the entire surface of the multilayer wiring board, and then exposed / developed to obtain a predetermined value. By exposing the pattern at these locations, a multilayer wiring board as shown in FIG. 2 can be produced.
[0068]
【Example】
A prepreg impregnated with polyphenylene ether resin (A-PPE resin) was prepared for the insulating sheet forming the core substrate.
[0069]
Next, the insulating sheet made of this prepreg is coated with CO.₂A via hole having a diameter of 100 μmφ was formed using a laser.
[0070]
Next, this via hole was filled with a conductive paste. The conductor paste is triallyl cyanurate (TAIC) for a mixed powder of conductive particles having an average particle size of 5 μm coated with 3% by weight of silver on the surface of copper powder and tin powder having an average particle size of 7 μm as a low melting point metal powder. The viscosity of this conductor paste is 30 to 500 Pa · s (RS100 rheometer manufactured by HAAKE, cone 10 mmφ, cone angle 1 °, shear rate 100 s).^-1).
[0071]
Next, as a conductor wiring layer to be transferred to the insulating sheet, an electrolytic copper foil having a thickness of 12 μm was bonded to a polyethylene terephthalate film having a thickness of 38 μm to prepare a film with a copper foil for transfer. A dry film resist was affixed to the copper foil surface, and exposure, development by spraying with a sodium carbonate solution, and etching with ferric chloride were performed to form a conductor wiring layer having a trapezoidal formation angle of 60 °. Thereafter, the resist film was peeled off using a sodium hydroxide solution, and a wiring pattern was formed on the polyethylene terephthalate film. Thereafter, an aqueous solution of 10% by mass of formic acid was sprayed to roughen the surface of the wiring pattern to a surface roughness (Rz) of 2.9 to 3.1 μm.
[0072]
The surface roughness (Rz) of the wiring pattern surface was measured using an atomic force microscope. The number of measurement locations was 5 per wiring pattern. The wiring pattern was produced with a land diameter of 90 μm and a wiring width of 70 μm.
[0073]
Next, the wiring pattern formed on the polyethylene terephthalate film was aligned with the prepreg filled with the conductive paste, and then transferred by thermocompression bonding at 120 ° C., 5 MPa for 3 minutes.
[0074]
Next, the prepreg 4 layer on which the conductor wiring layer was formed was laminated by applying pressure and heating under the conditions of 120 ° C., 5 MPa, and 3 minutes to prepare a semi-cured core substrate. Of these wiring patterns, a wiring pattern having a conductor wiring layer formed on the surface of the core substrate and the via conductor formed on the surface multilayer wiring layer on the side with the largest maximum diameter is subjected to a de-stenosis treatment again. The roughness (Rz) was 3 μm.
[0075]
Next, an insulating sheet for the surface multilayer wiring layer was produced. As with the core substrate, this insulating sheet uses an A-PPE resin and is adjusted to 40% by volume of fused silica having an average particle size of 0.6 μm as an inorganic insulating powder. A catalyst for accelerating the curing of the resin was added in an amount of 3% by mass with respect to the thermosetting resin, and toluene was added as an organic solvent to prepare a slurry having a slurry viscosity of about 2 Pa · s. An insulating sheet having a thickness of 35 μm was produced from this using a doctor blade method.
[0076]
Next, this insulating sheet was laminated on the surface of a semi-cured core substrate prepared in advance under pressure heating conditions of 130 ° C., 5 MPa, and 3 minutes.
[0077]
Next, a via hole is formed at a predetermined position of the insulating sheet laminated on the core substrate using a UV-YAG laser device, and at the same time, the resin residue on the surface of the conductor wiring layer exposed on the bottom surface of the via hole is 0. Processed to 2 μm or less. The processing energy is 0.5 W, the number of pulses per unit time (Rep-Rate) is 8 to 10 kHz, and trepanning processing is performed. The maximum diameter on the incident side is about 60 μm and the maximum diameter on the output side is about 45 μm with 2 to 10 repetitions. Via holes (Ds / D_L= 0.75). Surface roughness of the conductor wiring layer exposed on the bottom surface of the via hole after laser processing (Rz₁), Surface roughness (Rz) of via conductor contact portion not laser processed₂) And the adhesion part (Rz) with the insulating layer were measured using an atomic force microscope and are shown in Table 1.
[0078]
Next, the conductor paste used for the core substrate was buried in the via hole to form a via conductor.
[0079]
Thereafter, in the same manner as forming the conductor wiring layer of the core substrate, for the surface wiring, the surface of the insulating sheet on which the via conductor is formed of the polyethylene terephthalate film having the wiring pattern formed of the electrolytic copper foil having a thickness of 18 μm Then, heating and pressurization at a temperature of 130 ° C., a pressure of 5 MPa, and a time of 3 minutes were performed, and only the resin film and the adhesive layer were peeled to transfer the wiring circuit layer onto the surface of the insulating sheet.
[0080]
Thereafter, the above steps are repeated again to form a surface multilayer wiring layer having two insulating layers and a conductor wiring layer on the front and back surfaces of the core substrate, respectively, and then the conditions of a temperature of 240 ° C., a pressure of 4 MPa, and an hour A multi-layer wiring board was prepared by curing at once.
[0081]
As an evaluation of the produced multilayer wiring board, a solder dip test at 240 ° C. for 2 minutes was performed on a portion where 360 via conductors were connected in series inside the multilayer wiring board, and the electrical resistance before and after that was measured. Measurements were made to evaluate the rate of change in electrical resistance per hole in the via conductor.
[0082]
(Comparative example)
As a comparative example, via holes were formed at a tip energy of 3 mJ, 5 shots, and a time interval of 92 μsec using a carbon dioxide laser as an insulating sheet constituting the surface multilayer wiring layer. In this case, except for the method for forming the via hole, the conductor paste, the resin film, the wiring pattern pasted on the surface thereof, the production method, the transfer method, and the lamination curing conditions were the same.
[0083]
[Table 1]

[0084]
As is clear from the results in Table 1, via holes are formed in the surface multilayer wiring layer using a UV-YAG laser, and at least the surface roughness (Rz) of the conductor wiring layer on the core substrate side of the via conductor is defined as the insulating layer. Sample no. In 1 to 7, the rate of change in electrical resistance per via conductor hole was 9.7% or less. In particular, the surface roughness (Rz) of the conductor wiring layer that contacts the side with the smallest maximum diameter of the via conductor is 0.9 μm or less, and the surface roughness of the insulating layer adhesion portion and the conductor wiring layer that contacts the maximum diameter of the via conductor. Sample (Rz) difference of 2.1 μm or more. In 3, 5, and 6, the rate of change in electrical resistance per via conductor hole was 6.8% or less, and the connection between the via conductor and the conductor wiring layer was even stronger.
[0085]
On the other hand, CO₂Sample No. in which a via hole was formed using a laser 8, the surface roughness of the contact portion of the conductor wiring layer with the via conductor is the same as the surface roughness of the bonded portion with the insulating layer. In this sample, the rate of change in electrical resistance per hole of the via conductor is 21. It was as large as 3%.
[0086]
【The invention's effect】
As described in detail above, the surface roughness of the contact portion of the via conductor formed on the surface multilayer wiring layer with the conductor wiring layer on the core substrate side is determined by the adhesion of the insulating layer constituting the surface multilayer wiring layer. By making it smaller than the surface roughness, the surface of the conductor wiring layer in contact with the via conductor becomes smooth, the wettability between the metal component constituting the via conductor and the metal foil of the conductor wiring layer is increased, and the bonding surface can be increased. Therefore, the joint can be strengthened, the resistance value and the variation of the via conductor can be reduced, and the connection reliability can be improved.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view for explaining an example of a multilayer wiring board in which a surface multilayer wiring layer is formed on the core substrate surface of the present invention.
FIG. 2 is an enlarged view of a main part of a joint portion between a via conductor and a conductor wiring layer formed on a surface multilayer wiring layer.
FIG. 3 is a process diagram for explaining an example of a method for producing a multilayer wiring board according to the present invention.
[Explanation of symbols]
A ... Core substrate
B ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Surface multilayer wiring layer
1a to 1e, 3a to 3d .... Insulating layer
5 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Insulating substrate
7, 11, 27, 45 ... Conductor wiring layer
8, 13, 25, 47 ... Via conductor
15, 23, 43 .. Via hole
17 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Contact part
19 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Adhesion
21, 41 ... Insulation sheet

Claims (9)

(A) producing a core substrate formed by forming a conductor wiring layer having a roughened upper surface on at least the surface of an insulating sheet containing at least a thermosetting resin;
(B) thermocompression bonding the semi-cured first insulating sheet to the surface of the core substrate;
(C) A predetermined diameter of the first insulating sheet is irradiated with UV-YAG laser light having a processing output of 0.1 to 2.0 W and a unit time pulse number of 1 to 50 kHz, and a maximum diameter of 75 μm or less. Smoothing the uneven surface on the top surface of the conductor wiring layer formed on the surface of the core substrate while forming a via hole;
(D) filling the via hole formed in (c) with a conductive paste containing a metal powder and an organic component to form a via conductor;
(E) forming a first conductor wiring layer having a roughened upper surface side on the first insulating sheet on which the via conductor is formed;
And (f) a step of repeating steps (b) to (e) to form a multi-layered surface layer by forming a surface multilayer wiring layer. A surface roughness (Rz ₁ ) of a conductor wiring layer abutting on the core substrate side of a via conductor formed on the first insulating sheet; and an insulating layer constituting the surface multilayer wiring layer of the conductor wiring layer; _{2. The} method of manufacturing a multilayer wiring board according to claim 1, wherein a difference from the surface roughness (Rz ₂ ) of the bonded portion is 0.5 μm or more.   The via conductor formed in the first insulating sheet has different via diameters at both ends, and the via diameter on the core substrate side is smaller than the via diameter on the opposite side to the core substrate side. The manufacturing method of the multilayer wiring board as described. The surface roughness (Rz ₁ ) of the conductor wiring layer that abuts on the core substrate side of the via conductor formed on the first insulating sheet is 0.5 to 1.5 μm. A method for manufacturing a multilayer wiring board.   2. The method of manufacturing a multilayer wiring board according to claim 1, wherein the via conductor formed on the first insulating sheet contains at least one metal of tin, lead, bismuth, and indium, or an alloy thereof. . The step of producing the core substrate includes:
A plurality of insulating sheets containing uncured thermosetting resin on which via conductors are formed are stacked, and the core substrate is formed by forming the conductor wiring layer on at least the surface of the uppermost insulating sheet. The method for producing a multilayer wiring board according to claim 1. The step of smoothing the uneven surface includes
The method of manufacturing a multilayer wiring board according to claim 6, wherein the via hole having a maximum diameter smaller than a via conductor of the core substrate is formed. The step of producing the core substrate includes:
The method for manufacturing a multilayer wiring board according to claim 6, wherein the core substrate in a semi-cured state is manufactured. After the step of forming the surface multilayer wiring layer,
9. The method of manufacturing a multilayer wiring board according to claim 8, further comprising a step of collectively curing the core substrate and the surface multilayer wiring layer.

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