JP2003101235A - Multilayer wiring board and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer wiring board in which the electrical connection of a via conductor to a conductor wiring layer is improved in a surface multilayer wiring layer formed on the surface of a core board. SOLUTION: The surface roughness (Rz1 ) of a contact part 17 with via conductors 8, 13 formed on the surface multilayer wiring layer B in the conductor wiring layer 11 is smaller than the surface roughness (Rz2 ) of a bonding part 19 to insulating layers 3a to 3d constituting the layer B.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board and a method for manufacturing the same, and more particularly to a multilayer wiring board having a surface multilayer wiring layer laminated on the surface of a core board and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, with the development of mobile information terminals and the widespread use of mobile computing, there has been a demand for a small-sized, high-definition multilayer wiring board suitable for high-speed operation.

As a multilayer wiring board to meet such a demand for high definition and high speed operation, there is conventionally known one manufactured by a build-up method.

In a multilayer wiring board formed by the build-up method, a photosensitive resin is applied to the surface of a core substrate made of a glass epoxy composite material to form an insulating layer, and the insulating layer is exposed and developed. Thereby forming a via hole.

Next, after forming a plated layer of copper or the like on the entire surface of the insulating layer including the inner wall of the via hole, a photosensitive resist is applied / exposed / developed / etched / resist removed on the plated layer surface. It is produced by forming a conductor wiring layer.

[0006]

However, in the above build-up method in which the insulating layer is formed on the surface of the core substrate by using the photosensitive resin, since the via hole formed inside the insulating layer is formed by ultraviolet exposure, Originally, the surface of the conductor wiring layer exposed at the bottom of the via hole was not processed, but the surface roughness of the conductor wiring layer left a concavo-convex shape so as to maintain a state of adhering to the insulating layer Has become. For this reason, a residue of the thermosetting resin exists in the concave portion of the conductor wiring layer surface, and since this surface is covered with the oxide film, the metal connection between the via conductor and the conductor wiring layer is prevented. There is a problem in that the via conductor and the conductor wiring layer are easily broken in the reliability evaluation such as the temperature cycle test, and the reliability is lowered.

Therefore, an object of the present invention is to provide a multilayer wiring board and a manufacturing method thereof for improving the electrical connection between the via conductor and the conductive wiring layer in the surface multilayer wiring layer formed on the surface of the core substrate. To do.

[0008]

In the multilayer wiring board of the present invention, a conductor wiring layer is formed on the surface and / or inside of an insulating substrate containing at least a thermosetting resin, and the above-mentioned structure is provided for connecting the conductor wiring layers. A core substrate in which a via conductor is formed inside an insulating substrate, and an insulating layer and a conductor wiring layer are laminated on the surface of the core substrate, and a via hole is formed in the insulating layer to connect the conductor wiring layers. A multi-layer wiring board formed by filling a conductive paste containing metal powder in the via hole to form a via conductor; and a via conductor formed on the front multi-layer wiring layer. The surface roughness (Rz ₁ ) of the conductor wiring layer that abuts on the core substrate side is the surface roughness (Rz of the portion where the conductor wiring layer is adhered to the insulating layer that constitutes the surface multilayer wiring layer).
z ₂ ).

According to this structure, the surface of the conductor wiring layer in contact with the via conductor is smooth,
The wettability between the metal component forming the via conductor and the metal foil of the conductor wiring layer is enhanced, and the joint can be strengthened. On the other hand, by roughening the conductor wiring layer on the side of the adhesion portion with the insulating layer, the anchor effect is enhanced and the adhesion portion can be strengthened.

In the above-mentioned multilayer wiring board, the surface roughness (Rz ₁ ) of the conductor wiring layer abutting on the core board side of the via conductor formed in the surface multilayer wiring layer and the surface multilayer wiring of the conductor wiring layer. It is desirable that the difference from the surface roughness (Rz ₂ ) of the adhesive portion with the insulating layer constituting the layer is 0.5 μm or more.

The average surface roughness (Rz) of the contact portion of the via conductor thus formed on the surface multilayer wiring layer with the conductor wiring layer on the core substrate side, and the insulating layer constituting the surface multilayer wiring layer If the difference from the average surface roughness (Rz) of the adhesive portion is 0.5 μm or more, the connection between the conductor wiring layer and the via conductor in which different joints are formed and the connection between the conductor wiring layer and the insulating layer are formed. The connection can be made even stronger at the same time.

In the above multilayer wiring board, the via conductors formed on the surface multilayer wiring layer have different via diameters at both ends, and the via diameter on the core substrate side is smaller than the via diameter on the opposite side to the core substrate side. desirable.

As described above, the surface roughness (R
By reducing z), the wettability of the metal component between the via conductor and the conductor wiring layer can be improved and the joint can be strengthened. Therefore, the surface roughness (R
By making z) smaller than that of a conductor wiring layer having a large via diameter, it is possible to obtain a uniform joint strength and electrical resistance at both ends and to obtain a stable joint.

In the above-mentioned multilayer wiring board, the surface roughness (Rz ₁ ) of the conductor wiring layer abutting on the core board side of the via conductor formed in the surface multilayer wiring layer is 0.5 to 1.5 μm. desirable. By adjusting the surface roughness (Rz ₁ ) of the conductor wiring layer to fall within such a range, the wettability with the metal component contained in the via conductor can be further enhanced, and a stronger joint can be formed. .

In the above multilayer wiring board, it is desirable that the maximum diameter of the via conductor formed in the surface multilayer wiring layer is 75 μm or less. By applying the conductor wiring layer of the present invention, even if the diameter of the via conductor is reduced, the interlayer connection of the surface multilayer wiring layer can be ensured, so that a higher density multilayer wiring layer can be formed.

In the above multilayer wiring board, it is desirable that the via conductor formed in the surface multilayer wiring layer contains at least one metal selected from tin, lead, bismuth and indium, or an alloy thereof. If the metal contained in the via conductor has a low melting point as described above, the wettability with the conductor wiring layer is further increased, and the contact portion between the via conductor and the conductor wiring layer can be formed more firmly. .

The method of manufacturing a multilayer wiring board according to the present invention comprises:
(A) a step of producing a core substrate formed by forming a conductor wiring layer having a roughened upper surface on at least the surface of an insulating sheet containing at least a thermosetting resin; and (b) semi-finishing the surface of the core substrate. Thermocompression-bonding the cured first insulating sheet; and (c) irradiating a predetermined portion of the first insulating sheet with a laser beam to form a via hole and a conductor formed on the surface of the core substrate. A step of smoothing the uneven surface of the upper surface of the wiring layer, a step of forming a via conductor by filling the via hole formed in (d) and (c) with a conductor paste containing metal powder and an organic component, and (e) A step of forming a first conductor wiring layer having a roughened upper surface on the first insulating sheet on which a via conductor is formed, and a step of repeating steps (f), (b) to (e) to form a multilayer. And a manufacturing method comprising: A.

In this manufacturing method, first, by processing the insulating sheet with laser light, it is possible to easily form a tapered via hole having a small diameter and a high shape accuracy in the irradiation direction. Further, the formation of the via hole and the smoothing of the uneven surface of the upper surface of the conductor wiring layer exposed at the bottom of the via hole can be performed simultaneously.

Further, according to the manufacturing method of the present invention, the via hole for connecting the conductor wiring layers in the surface multilayer wiring layer is formed by the irradiation of the laser beam.
It is not necessary to use a photosensitive resin, and any insulating material having excellent material properties such as a high glass transition point and a low water absorption can be selected as an insulating layer material. Moreover, the formation of the insulating layer and the formation of the conductor wiring layer can be simultaneously performed in parallel, and since all the insulating layers can be cured at once, the manufacturing process can be simplified and shortened. it can.

In the above-mentioned method for manufacturing a multilayer wiring board, the surface roughness (Rz ₁ ) of the conductor wiring layer which is in contact with the via conductor formed on the first insulating sheet on the core substrate side, and the conductor wiring layer It is preferable that the difference between the surface roughness (Rz ₂ ) of the bonded portion with the insulating layer constituting the surface multilayer wiring layer is 0.5 μm or more. Thus, the via conductor and the conductor wiring layer can be easily joined by making the surface of the conductor wiring layer in the portion in contact with the via conductor smoother than the portion in which the insulating sheet is bonded. Further, the surface roughness (Rz ₂ ) of the bonding portion of the conductor wiring layer with the insulating layer forming the surface multilayer wiring layer
By setting the difference between and to be 0.5 μm or more, the anchor effect of the conductor wiring layer is enhanced and the conductive wiring layer can be firmly bonded to the insulating layer.

In the above method for manufacturing a multilayer wiring board, the via conductors formed on the first insulating sheet have different via diameters at both ends, and the via diameter on the core substrate side is the via diameter on the opposite side to the core substrate side. It is desirable to be smaller than.
Since it is difficult to connect the via conductor with the smaller maximum diameter to the conductor wiring layer, the connection with the conductor wiring layer with the larger maximum diameter is made more smooth by making the smaller maximum diameter smoother. In addition, the conductivity can be easily made the same.

In the above-described method for manufacturing a multilayer wiring board, the surface roughness (Rz ₁ ) of the conductor wiring layer abutting on the core board side of the via conductor formed on the first insulating sheet is 0.5 to 1.
It is preferably 5 μm. When the via conductor diameter is small and the contact area with the conductor wiring layer is small, the surface roughness (Rz ₁ ) of the conductor wiring layer is smoothed as described above, and the end portion side with a smaller diameter of the via conductor and the conductor wiring. The layers can be easily joined.

In the method for manufacturing a multilayer wiring board, the via conductor formed on the first insulating sheet has a maximum diameter of 75 μm.
The following is desirable. In this way, when the maximum diameter of the via conductor is as small as 75 μm, the manufacturing method of the present invention can be preferably used, and even if the via conductor diameter becomes small, the joint portion with the conductor wiring layer can be strengthened. .

In the above-mentioned method for manufacturing a multilayer wiring board, it is desirable that the via conductor formed on the first insulating sheet contains at least one metal selected from tin, lead, bismuth and indium, or an alloy thereof. By including such a low melting point metal, an alloy phase or an intermetallic compound can be easily formed at the joint between the via conductor and the conductor wiring layer.

In the above-mentioned method for manufacturing a multilayer wiring board, it is desirable that the processing output by laser light is 0.1 to 2.0 W and the number of pulses per unit time is 1 to 50 kHz. By setting the laser output and the number of pulses in such ranges, a via hole having a high shape accuracy can be formed, and the surface of the conductor wiring layer exposed at the bottom of the via hole can be smoothed.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION (Structure) FIG. 1 is a schematic sectional view showing an example of a multilayer wiring board of the present invention.

As shown in FIG. 1, in the multilayer wiring board of the present invention, the surface multilayer wiring layer B is formed on the surface 1 of the core substrate A.

The core substrate A is an insulating substrate 5 formed by laminating a plurality of insulating layers (1a-1e) containing at least a thermosetting resin, and formed on the surface and inside of the insulating substrate 5. It is composed of a conductor wiring layer 7 and a via conductor 8 connecting the conductor wiring layers 7.

The surface multilayer wiring layer B laminated on the surface 1 of the core substrate A has a plurality of surface insulating layers (3a to 3a) containing at least a thermosetting resin, like the core substrate A.
d), a conductor wiring layer 11 is formed on the surface and inside of each insulating layer (3a to 3d), and a via conductor 13 for connecting between the conductor wiring layers 11 is formed.
Are formed.

FIG. 2 is an enlarged view of an essential part showing a joint portion between the via conductor 13 formed on the surface multilayer wiring layer B and the conductor wiring layers 7 and 11. As shown in FIG. 2, of the conductor wiring layer 11,
The via conductor 13 formed in the surface multilayer wiring layer B is
It has a tapered shape in which the via diameter on the side of the core substrate A is smaller than that on the opposite side.

As described above, the diameters of both ends of the via conductor 13 are different, and the maximum diameter difference between the both ends of the via conductor 13 is as follows: when the maximum diameter on the small diameter side is Ds and the maximum diameter on the large diameter side is D _L. In addition, Ds / D _L > 0.6 or more ensures the connection between the via conductor 13 and the conductor wiring layers 7 and 11, and suppresses the occurrence of local stress in a temperature cycle test or the like. From desirable.

The maximum diameter of the via conductor 13 formed in the surface multilayer wiring layer B is preferably 75 μm or less. In particular, a high-density surface multilayer wiring layer B can be formed, and the maximum diameter of the via conductor 13 can be increased. The maximum diameter of the via conductor 13 is preferably 40 to 60 μm because the interlayer connection of the surface multilayer wiring layer B can be ensured even if the diameter becomes small.

According to the present invention, the surface roughness (Rz ₁ ) of the contact portion 17 of the conductor wiring layers 7 and 11 of the via conductor 13 on the core substrate A side is the same as that of the insulating layers 1a to 1e and 3a to 3d. It is important that it is smaller than the surface roughness (Rz ₂ ) of the adhesive portion 19 of. By smoothing the upper surfaces of the conductor wiring layers 7 and 11 in contact with the via conductors 13 in this manner, the wettability between the metal components forming the via conductors 13 and the metal foils of the conductor wiring layers 7 and 11 is increased. It is possible to strengthen the joint between the two.

On the other hand, the surface roughness (Rz ₂ ) of the conductor wiring layers 7 and 11 bonded to the insulating layers 1a to 1e and 3a to 3d is processed to be large, which is why the insulating layer 1a is formed.
To 1e, 3a to 3d, the thermosetting resin enters into the recesses of the conductor wiring layers 7 and 11 to form the insulating layer 1a.
1e, 3a to 3d can be firmly bonded to the conductor wiring layers 7 and 11. Further, at the contact portion 17, the via conductor 13 and the conductor wiring layers 7 and 11 are intimately joined to each other, and further, the via conductor 13 and the conductor wiring layers 7 and 11 are formed at this interface.
An alloy phase or an intermetallic compound with the metal component is formed.

The surface roughness (Rz ₁ ) of the conductor wiring layers 7 and 11 contacting the via conductor 13 is 0.5 to 1.5 μm.
In particular, 0.7 to 1.3 is preferable because the conductivity of the conductor wiring layers 7 and 11 is not impaired and the wettability is improved.
μm is desirable. On the other hand, the surface roughness (Rz ₂ ) of the insulating layers 3a to 3d and the adhesive portion is preferably 2 μm or more,
In particular, the range of 2.4 to 3.5 μm is desirable.

The surface roughness (Rz ₁ ) of the contact portion 17 of the conductor wiring layers 7 and 11 with the via conductor 13 formed in the surface multilayer wiring layer B and the surface multilayer wiring layer B are formed. Surface roughness (Rz ₂ ) of the bonding portion 19 with the insulating layers 3a to 3d
Is preferably 0.5 μm or more, and in particular, the difference is preferably 0.5 to 1.5 μm for the reason of reducing the thickness difference between the conductor wiring layers 7 and 11 and stabilizing the conductivity. . Thereby, the conductor wiring layers 7 and 11 and the via conductor 1 are formed.
3, and the conductor wiring layers 7 and 11 and the insulating layers 3a to
The connection with 3d can be further strengthened.

On the other hand, it is desirable that the maximum diameter of the via conductor 8 constituting the core substrate A is 300 μm or less because a high-density circuit can be formed, and even if the maximum diameter of the via conductor 8 becomes small. The maximum diameter of the via conductor 8 is 7 because the interlayer connection of the core substrate A can be ensured.
It is preferably 0 to 250 μm.

The via conductor 8 formed on the core substrate A also has the same maximum diameter at both ends as the surface via conductor 13 formed on the surface multilayer wiring layer 3.
Maximum diameter difference at both ends of the via conductors 8, the maximum diameter of the small diameter side Dcs, when the maximum diameter of the large diameter side and the Dc _L, Dcs
It is desirable that / Dc _L > 0.6 or more.

The conductor wiring layer 7 formed inside the core substrate A also has a surface abutting against the via conductor 8 like the conductor wiring layer 11 constituting the surface multilayer wiring layer B. It is desirable that the roughness (Rz) is smaller than the surface roughness (Rz) of the bonding portion with the insulating layers 1a to 1e, because the connection between the via conductor 8 and the conductor wiring layer 7 is strengthened.

The surface roughness of the conductor wiring layer 7 used for the core substrate A at the contact portion of the via conductor 8 is the same as that of the conductor wiring layer 11 formed on the surface multilayer wiring layer B (R
z), preferably 0.5 to 1.5 μm, and more preferably 0.7 to 1.3 μm.

On the other hand, the surface roughness (Rz) of the portion where the conductor wiring layer 7 is bonded to the insulating layers 1a to 1e is preferably 2 μm or more, and particularly 2.4 to 3.5 μm for the reason of increasing the adhesive strength.

(Material) In the multilayer wiring board of the present invention,
The insulating layers 3a to 3d forming the surface multilayer wiring layer B are made of an insulating material containing at least a thermosetting resin, and include, for example, A-PPE (polyphenylene ether resin), BT resin (bismaleide triazine), It is made of a polyimide resin, a fluororesin, a polyamino bismaleimide resin, or an epoxy resin, and is preferably a thermosetting resin which is liquid at room temperature as a raw material.

As the inorganic insulating powder in the insulating layers 3a to 3d laminated on the front and back surfaces of the front surface multilayer wiring layer B, Si is used.
O ₂ , Al ₂ O ₃ , ZrO ₂ , TiO ₂ , AlN, SiC,
At least one material selected from BaTiO ₃ and SrTiO ₃ can be used. Further, the shape thereof may be any shape such as a spherical shape or a needle shape. By using the inorganic insulating powder which is discontinuously present in the insulating layers 3a to 3d constituting the surface multilayer wiring layer B as described above, the migration resistance can be enhanced and the density of the surface multilayer wiring layer B can be increased. be able to.

On the other hand, the insulating layers 1a to
1e also includes the insulating layers 3a to 3a constituting the surface multilayer wiring layer B.
A thermosetting resin such as A-PPE (polyphenylene ether resin) similar to 3d is preferably used. Further, as the filler mixed in the insulating layers 1a to 1e, there are inorganic insulating powders and fibrous bodies, and those having arbitrary properties such as woven cloth and nonwoven cloth may be used. In addition, organic fiber bodies such as aramid fiber and cellulose fiber can also be used. In particular, as the fibrous body used for the core substrate A, glass fibers impregnated with the thermosetting resin are most desirable in terms of enhancing the strength.

Further, the core substrate A and the surface multilayer wiring layer B
As the conductor wiring layers 7 and 11 constituting the above, an electro-deposited metal foil made of a metal suitable for forming wiring, for example, a low resistance metal containing at least one of gold, silver, copper and aluminum is preferably used. To be done. The thickness of this electrolytic metal foil is 1 to
The thickness is preferably 35 μm, and more preferably 5 to 18 μm because it has low conductivity and is suitable for fine wiring. If the thickness of this electrolytic metal foil, in other words, the thickness of the conductor wiring layers 7 and 11 is smaller than 1 μm, the wiring resistivity becomes high, and if it is larger than 35 μm, the core substrate A and the surface multilayer wiring layer B are deformed during lamination. Insulation layers 1a-1
e, the amount of metal embedded in 3a to 3d is increased, the distortion of the core substrate A and the surface multilayer wiring layer B is increased, and the substrate is likely to be deformed after the resin is cured. 1 and 2, in the core substrate A and the surface multilayer wiring layer B, the conductor wiring layers 7 and 11 are all buried in the insulating layers 1a to 1e and 3a to 3d. In this way, the conductor wiring layers 7 and 11 are both insulating layers 1a-
1e, 3a to 3d are buried in the surface of the conductor wiring layers 7 and 11 to prevent the occurrence of stacking failure due to the thickness of the conductor wiring layers 7 and 11 themselves, and have excellent adhesion between the insulating layers 1a to 1e and 3a to 3d. Thus, it is possible to realize extremely excellent smoothness of the wiring board as a whole.

As the conductor paste filled in the via holes 15 to be the via conductors 8 and 13, resin components such as epoxy and cellulose are added to the metal powder forming the conductor wiring layers 7 and 11, and butyl acetate is added. What is kneaded with a solvent such as is used. The conductor paste is dried after the solvent is filled in the via holes 15, but it is preferable that the conductor paste is solvent-free from the beginning. Also, via conductors 8 and 1
In order to lower the resistance of No. 3 and to improve the connectivity with the metal foil forming the conductor wiring layers 7 and 11 at the top and bottom of the via conductors 8 and 13, at least one metal of tin, lead, bismuth, and indium, or It is desirable to contain these alloys, and particularly when the metal component forming the conductor wiring layers 7 and 11 is copper, it is possible to form an alloy with copper or an intermetallic compound having a higher melting point than a simple substance. To tin is preferred.

The average particle diameter of the metal particles used for the via conductors 8 and 13 is set to 1 to 15 μm in order to improve the dispersibility of the conductive paste and the wettability and filling with the conductor wiring layers 7 and 11. It is desirable that it is 3 to 6 μm.

The via conductor 13 formed on the front surface multilayer wiring layer B contains the metal component forming the conductor wiring layers 7 and 11 with a thickness of 0.1 μm or more from the end side thereof. More preferably, the metal component forming the conductor wiring layers 7 and 11 is diffused in this way, whereby the bond between the via conductor 13 and the conductor wiring layers 7 and 11 can be strengthened. In the multilayer wiring board of the present invention, it is desirable that the metal components composing the via conductors 8 and 13 contain the same component from the viewpoint of manufacturing the substrate by batch curing.

(Manufacturing Method) Next, a method of manufacturing the multilayer wiring board of the present invention will be described with reference to FIG. FIG. 3 is a process diagram for manufacturing the multilayer wiring board of FIG.

First, the insulating layers 1a to 1a constituting the core substrate A.
When the conductor wiring layer 7 is formed on 1e, as shown in FIG.
As shown in (a), desired via holes 23 are formed in the semi-cured insulating sheet 21 by laser processing. Then, as shown in FIG. 3 (b), the via hole 23 is filled with a conductor paste containing a metal powder to form a via conductor 25.

Next, a conductor wiring layer 27 made of electrolytic metal foil is embedded on one surface of the via conductor 25 of the semi-cured insulating sheet 21 of FIG. 3B by transfer by heating and pressing. In the present invention, the conductor wiring layer 27 is formed by transferring a pattern prepared by etching a metal foil laminated on the resin film 29 in advance. The transfer conditions are such that the conductor wiring layer 27 is embedded and transferred on the insulating sheet 21, and the insulating sheet 21 is not deformed when pressurized and heated, and the uncured state is maintained so that it can be laminated thereafter. The temperature, pressure, and time to be applied are desirable, the temperature is 100 to 140 ° C., the pressure is 30 to 100 Pa, and the time is 1
10 minutes is suitable.

For example, in the formation of the conductor wiring layer 27, first, one or more alloys selected from copper, gold, silver, aluminum, etc., which are formed on the surface of a suitable resin film 29 by a plating method or the like. Thickness of 1-35 μm
After adhering the electro-deposited metal foil, a resist layer is attached to the surface of the electro-deposited metal foil so as to form a mirror image pattern of a desired wiring pattern, and then a conductor wiring layer 27 having a mirror image of a predetermined wiring pattern is formed by etching and resist removal. Form. The thickness of the conductor wiring layer 27 is preferably 5 to 18 μm because the conductor resistance can be reduced and the conductor resistance can be reduced. Further, normally, the surface roughness (Rz ₂ ) of the conductor wiring layer 27 that is not laser processed and is in contact with the maximum diameter side of the via conductors 8 and 13 is adjusted by the sparse treatment.

As the resin film 29, known materials such as polyethylene terephthalate, polyethylene naphthalate, polyimide, polyphenylene sulfide, vinyl chloride and polypropylene can be used. Resin film 29
The thickness of 10 to 100 μm is suitable, and preferably 2
5 to 50 μm is preferable. This is because if the thickness of the resin film 29 is smaller than 10 μm, the conductor wiring formed by the deformation or bending of the film is likely to cause disconnection, and if the thickness is larger than 100 μm, the flexibility of the resin film is lost and peeling of the sheet becomes difficult. This is because. Further, as the adhesive for adhering the electrolytic metal foil to the surface of the resin film 29, acrylic, rubber, silicon,
A known adhesive such as an epoxy type adhesive can be used.

In order to form the inner conductor wiring layer 27, the insulating sheet 21 is formed by previously bonding an electrolytic metal foil having a surface roughness (Ra) of 0.2 μm or more to the resin film 29. Since the thermosetting resin is not exposed to water during the etching process, the water absorption rate can be lowered. At this time, if the electrolytic metal foil is not subjected to the coupling treatment, the conductor wiring layer 27 is easily peeled from the film after transfer.

Next, together with the resin film 29 having the conductor wiring layer 27 for the front surface manufactured as described above, the resin film 29 having the conductor wiring layer 27 for the back surface manufactured by the same method is prepared. It is produced, and these are laminated on both surfaces of the insulating sheet 21 on which the via conductor 25 is formed in the same manner as in the method shown in FIG. And FIG.
As shown in (d), the laminate is heated to a temperature of 60 to 150.
After heating under pressure at 1 ° C., a pressure of 1 to 50 MPa, and a time of 1 to 10 minutes, the resin film 29 is peeled off, so that the conductor wiring layer 27 is formed on one surface of the insulating sheet 21 as shown in FIG. It is possible to produce a wiring sheet c in which is embedded.

As described above, when the wiring sheet c is formed, the resin film 29 having the conductor wiring layers 27 formed on both sides thereof is laminated and pressure-bonded, so that a step of transferring the two conductor wiring layers 27 in the multilayer wiring board is performed. Can be done at the same time.

Of the conductor wiring layers 27 embedded on the surface of the wiring sheet c manufactured as described above, the conductor wiring layer 27 located on the front surface side of the core substrate A is subjected to a roughening treatment, The surface roughness (Rz) of the conductor wiring layer 27 is 0.5.
It is desirable that the thickness be at least μm, particularly at least 1.6 μm.

This roughening treatment can be performed by a chemical etching treatment using an acid treatment with hydrochloric acid, sulfuric acid, nitric acid, acetic acid, formic acid, etc. For example, an acid solution is applied to the conductor wiring layer 2
It is desirable to spray on the surface of No. 7. Further, it is desirable to form a large number of pointed protrusions on the roughened surface (etching surface), and such pointed protrusions are, for example,
A 10 mass% formic acid solution can favorably be formed at a roughening rate of 1 μm / min or more.

Then, as shown in FIG. 3 (e), the wiring sheets b and d produced in the same manner as in the above (a) to (e) are heated and pressure-cured together with the wiring sheet c to be integrated. The core laminated body C can be produced by heating to a temperature at which the thermosetting resin in the insulating sheet is completely cured. The curing temperature in this case is the core laminate C
The temperature is preferably 200 to 250 ° C. in order to be re-cured together with the insulating sheet 41 to be the surface multilayer wiring layer B on the upper side.

Next, as shown in FIG. 3 (f), an insulating sheet 41 to be a surface multilayer wiring layer B is laminated on the surface 1 of the core laminate C. The insulating sheet 41 used here is
For example, when a composite material of thermosetting resin and inorganic insulating powder is used as the insulating material, it is produced by the following method.

First, the liquid thermosetting resin described above is added to the suitable inorganic insulating powder as described above in an amount of 2 times.
The mixture added together with the solvent so as to be 0 to 80% by volume is mixed by means of a kneader (kneader), three rolls or the like to prepare an insulating slurry.

The insulating slurry is preferably a composite material of the above-mentioned organic resin and inorganic insulating powder, toluene,
A fluid having a predetermined viscosity is obtained by adding a solvent such as butyl acetate, methyl ethyl ketone, methanol, methyl cellosolve acetate, isopropyl alcohol, methyl isobutyl ketone, and dimethylformamide. Although the viscosity of the slurry depends on the sheet forming method, a rheometer RS100 manufactured by Haake Co. is used, a cone having a diameter of 20 mm and an angle of 1 ° is used, and the shear rate is 1 to 30 at a shear rate of 100 s ^-1.
Pa · s is suitable.

After the insulating slurry is formed into a sheet by a sheet forming method such as a rolling method, an extrusion method, an injection method, a die coater method, a doctor blade method,
If desired, the thermosetting resin can be semi-cured by heating to a temperature slightly lower than a temperature sufficient for the thermosetting resin to be completely cured, and the insulating sheet 41 having a thickness of 25 to 50 μm can be manufactured.

The insulating sheet 41 is heated to a temperature of 100 to 160.
After the bonding is performed under the conditions of a temperature of 1 ° C., a pressure of 1 to 7 MPa, and a time of 1 to 10 minutes, a via hole 43 is formed by UV-YAG laser or the like. The via hole 43 has a structure in which the conductor wiring layer 27 embedded in the lower layer of the insulating sheet 41 is exposed. At this time, the surface of the conductor wiring layer 27 at the bottom of the via hole 43 is a matte surface at the time of forming the metal foil or a roughened surface processed at the time of pattern formation, and the bottomed via hole 43 is formed by laser processing. In doing so, the unevenness of the surface is partly melted or sublimated by laser processing and smoothed. Laser irradiation is performed so that Rz ₁ is 0.5 to 1.5 μm. Here, the laser processing conditions are, for example, in the case of a UV-YAG laser processing machine, the processing energy is 0.1 to 2.0 W and the number of pulses per unit time (Rep-Ra).
It is suitable that te) is in the range of 1 kHz to 50 kHz. The UV-YAG has a larger output energy as the Rep-Rate is smaller, and scrapes the metal foil as the number of repetitions of emitting the laser light is larger. And when it is lower than 0.1W, or 50k
If it is higher than Hz, the resin residue is likely to remain on the bottom of the via hole 43, and if it is higher than 2.0 W or lower than 1 kHz, a hole penetrating the metal foil at the bottom of the via hole 43 is opened or the metal foil is damaged. Remain. Further, the more the number of repetitions of emitting the laser light is, the more the metal foil is scraped, so the optimum number is determined by its output.

Thereafter, the via hole 43 is filled with a conductor paste containing a metal powder in the same manner as in the core substrate A to form a via conductor 47. This conductor paste is one containing at least one low melting point metal such as tin, lead, bismuth, indium, or an alloy thereof. The low melting point metal is a metal at the top and bottom of the via hole due to pressure and heat during curing. It will either wet the foil or, depending on the type of metal, diffuse into the metal foil. Further, similarly to the case where the conductor wiring layer 27 is formed on the core substrate A, the wiring pattern of the metal foil prepared in advance is roughened by etching, and then transferred to the laminated insulating sheet 41 to be transferred onto the insulating sheet 41. The embedded conductor wiring layer 45 can be formed to form a multilayer wiring board as shown in FIG.

After that, the insulating sheet 41 and the conductor wiring layer 45 can be multi-layered by repeating the above steps as needed.

When a solder resist layer is further formed on the surface of the surface multi-layer wiring layer B, a solder resist layer such as an epoxy resin is applied over the entire surface of the multi-layer wiring substrate and then exposed / developed. By exposing the pattern at a predetermined location, a multilayer wiring board as shown in FIG. 2 can be manufactured.

[0068]

Example A prepreg impregnated with a polyphenylene ether resin (A-PPE resin) was prepared as an insulating sheet forming a core substrate.

Then, a CO ₂ laser was used to form a via hole having a diameter of 100 μmφ on the insulating sheet made of this prepreg.

Next, the via holes were filled with a conductive paste. The conductor paste is a triallyl cyanurate (TAIC) with respect to a mixed powder of conductive particles having an average particle size of 5 μm coated with 3% by mass of silver on the surface of copper powder and tin powder having an average particle size of 7 μm as a low melting point metal powder. It is prepared by mixing the organic component consisting of
00 Pa · s (RS100 rheometer manufactured by Haake, cone 10 mmφ, cone angle 1 °, shear rate 100
s ^-1 ).

Next, as a conductor wiring layer to be transferred to the insulating sheet, a film having a copper foil for transfer was prepared by adhering an electrolytic copper foil having a thickness of 12 μm to a polyethylene terephthalate film having a thickness of 38 μm. A dry film resist was attached to the surface of the copper foil, exposed, developed by spraying a sodium carbonate solution, and etched with ferric chloride to form a conductor wiring layer having a trapezoid formation angle of 60 °.
Then, the resist film was peeled off using a sodium hydroxide solution to form a wiring pattern on the polyethylene terephthalate film. After that, an aqueous solution of 10% by mass of formic acid is sprayed and the surface of the wiring pattern has a surface roughness (Rz) of 2.
It was roughened to 9 to 3.1 μm.

The surface roughness (Rz) of the wiring pattern surface was measured using an atomic force microscope. The number of measurement points was 5 per one wiring pattern. The wiring pattern was manufactured with a land diameter of 90 μm and a wiring width of 70 μm.

Next, after aligning the wiring pattern formed on the polyethylene terephthalate film with the prepreg filled with the conductive paste, 120
Transfer was carried out by thermocompression bonding at 5 ° C., 5 MPa for 3 minutes.

Next, a prepreg 4 having a conductor wiring layer formed thereon.
The layers were stacked under pressure and heating under the conditions of 120 ° C., 5 MPa, and 3 minutes to produce a semi-cured core substrate. Of these wiring patterns, the wiring pattern having the conductor wiring layer formed on the surface of the core substrate and on the side where the maximum diameter of the via conductor formed in the surface multilayer wiring layer is large is subjected to the surface sparse treatment again. The roughness (Rz) was 3 μm.

Next, an insulating sheet for the surface multilayer wiring layer was prepared. This insulating sheet, like the core substrate, is made of A-PP.
Using E resin, the average particle size of the inorganic insulating powder is 0.6μ
The fused silica of m is adjusted to a volume ratio of 40% by volume, and a catalyst for promoting curing of the thermosetting resin is added to the thermosetting resin in an amount of 3% by mass, and toluene is further used as an organic solvent. In addition, a slurry having a slurry viscosity of about 2 Pa · s was prepared. An insulating sheet having a thickness of 35 μm was produced by the doctor blade method.

Next, this insulating sheet was laminated on the surface of a pre-prepared semi-cured core substrate under pressure and heating conditions of 130 ° C., 5 MPa, and 3 minutes.

Next, an insulating sheet laminated on the core substrate
At a predetermined position of the via using a UV-YAG laser device.
A hole was formed and at the same time exposed on the bottom of the via hole.
Resin residue on the surface of the conductor wiring layer is 0.2 μm or less
Processed as follows. Processing energy 0.5W, unit time
Pulse number (Rep-Rate) of 8 to 10 kHz,
Repanning processing is performed on the incident side after repeating 2 to 10 times.
Has a maximum diameter of about 60 μm and a maximum diameter on the output side of about 45 μm
Via holes are formed (Ds / D_L= 0.75). Les
Of the conductor wiring layer exposed on the bottom surface of the via hole after laser processing
Surface roughness (Rz ₁), Via conductors not laser processed
Surface roughness of contact area (Rz₂) And an adhesive layer (R
z) was measured using an atomic force microscope and is shown in Table 1.

Next, the conductor paste used for the core substrate was embedded in this via hole to form a via conductor.

After that, in the same manner as forming the conductor wiring layer of the core substrate, the thickness for the surface wiring is 18 μm.
The electro-deposited copper foil of 1. is laminated on the surface of the insulating sheet on which the via conductor is formed, and the polyethylene terephthalate film on which the wiring pattern is formed is laminated at a temperature of 130 ° C. and a pressure of 5 MPa
By heating and pressing for 3 minutes, only the resin film and the adhesive layer were peeled off to transfer the wiring circuit layer to the surface of the insulating sheet.

After that, the above steps are repeated again,
After forming a surface multilayer wiring layer having two insulating layers and two conductive wiring layers on the front surface and the back surface of the core substrate, the multilayer wiring board was manufactured by batch curing under conditions of a temperature of 240 ° C. and a pressure of 4 MPa for 1 hour. .

For evaluation of the manufactured multilayer wiring board, a solder dip test at 240 ° C. for 2 minutes was performed on a portion where 360 via conductors were connected in series inside the multilayer wiring board, and before and after that. The electrical resistance was measured and the rate of change of the electrical resistance value per hole of the via conductor was evaluated.

(Comparative Example) As a comparative example, via holes were formed in the insulating sheet constituting the surface multilayer wiring layer using a carbon dioxide gas laser at a tip energy of 3 mJ, 5 shots, and a time interval of 92 μsec. In this case, other than the method of forming the via hole, the conductor paste, the resin film and the wiring pattern pasted on the surface thereof and the method of producing the same, the transfer method,
The lamination curing conditions were the same.

[0083]

[Table 1]

As is clear from the results of Table 1, UV-Y
Sample No. 1 in which via holes were formed in the surface multilayer wiring layer using an AG laser, and at least the surface roughness (Rz) of the conductor wiring layer on the core substrate side of the via conductor was made smaller than that of the bonding portion with the insulating layer. In Nos. 1 to 7, the rate of change in electric resistance per hole of the via conductor was 9.7% or less. In particular, the surface roughness (Rz) of the conductor wiring layer abutting on the side with the smallest maximum diameter of the via conductor is 0.9 μm or less, and the surface roughness of the insulating layer adhesion portion and the conductor wiring layer abutting the maximum diameter of this via conductor. (Rz) difference of 2.1 μm or more 3,
In Nos. 5 and 6, the change rate of the electric resistance per hole of the via conductor was further lowered to 6.8% or less, and the connection between the via conductor and the conductor wiring layer was further strengthened.

On the other hand, sample No. 1 having a via hole formed using a CO ₂ laser. 8, the surface roughness of the contact portion of the conductor wiring layer with the via conductor was the same as the surface roughness of the adhesive portion with the insulating layer, and in this sample, the rate of change in electrical resistance per hole of the via conductor was 21. It was as large as 0.3%.

[0086]

As described above in detail, the surface roughness of the contact portion of the via conductor formed in the surface multilayer wiring layer with the conductor wiring layer on the core substrate side is determined by the insulating layer forming the surface multilayer wiring layer. By making it smaller than the surface roughness of the adhesion part with, the surface of the conductor wiring layer in contact with the via conductor becomes smooth, and the wettability between the metal components forming the via conductor and the metal foil of the conductor wiring layer increases. Since the joint surface can be made large, the joint portion can be strengthened, the resistance value and variation of the via conductor can be reduced, and the connection reliability can be improved.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view for explaining an example of a multilayer wiring board in which a surface multilayer wiring layer is formed on the surface of a core substrate of the present invention.

FIG. 2 is an enlarged view of an essential part of a joint portion between a via conductor formed in a surface multilayer wiring layer and a conductor wiring layer.

FIG. 3 is a process drawing for explaining an example of the method for manufacturing a multilayer wiring board according to the present invention.

[Explanation of symbols]

A: Core substrate B ..... Multilayer surface wiring layer 1a to 1e, 3a to 3d ... Insulating layer 5 ... Insulating substrate 7, 11, 27, 45 ... Conductor wiring layer 8, 13, 25, 47 ... Via conductor 15, 23, 43 ... Via hole 17 ... Abutment part 19 --- Adhesive part 21, 41 ... Insulation sheet

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H05K 3/00 H05K 3/00 N 3/38 3/38 B 3/40 3/40 K F term (reference) ) 5E317 AA24 BB12 CC25 CD05 CD27 CD32 GG03 GG14 5E343 AA02 BB12 BB24 BB71 BB72 DD02 EE41 EE43 GG01 GG04 GG04 5E346 AA06 AA12 AA15 AA22 AEEGGEEEE38EE15 EE18EE18 CC18 CC19EE09EE18 CC19 CC09 DD06EE12 CC31 CC09 DD06 DD12 DD12 HH07 HH11

Claims (13)

[Claims] 1. A core comprising a conductor wiring layer formed on the surface and / or the inside of an insulating substrate containing at least a thermosetting resin, and a via conductor formed inside the insulating substrate for connecting between the conductor wiring layers. An insulating layer and a conductor wiring layer are laminated on the surface of a substrate and the core substrate, a via hole is formed in the insulating layer for connecting the conductor wiring layers, and the via hole contains a metal powder. In a multilayer wiring board comprising a surface multilayer wiring layer formed by filling a conductor paste with a via conductor, a conductive wiring layer abutting on the core substrate side of the via conductor formed in the surface multilayer wiring layer. multilayer wiring substrate surface roughness (Rz ₁₎ is, of the conductor interconnect layer, wherein the surface wiring layer constituting the adhesive portion surface roughness of the insulating layer (Rz ₂₎ less than. 2. A surface roughness (R) of a conductor wiring layer abutting on a core substrate side of a via conductor formed in a surface multilayer wiring layer.
z ₁ ) and the surface roughness (Rz ₂ ) of the bonding portion between the conductor wiring layer and the insulating layer forming the surface multilayer wiring layer are 0.5 μm or more. 1. The multilayer wiring board according to 1. 3. The via conductor formed on the surface multilayer wiring layer has different via diameters at both ends, and the via diameter on the core substrate side is smaller than the via diameter on the opposite side to the core substrate side. Item 3. The multilayer wiring board according to Item 1 or 2. 4. A surface roughness (R) of a conductor wiring layer abutting on a core substrate side of a via conductor formed in a surface multilayer wiring layer.
The multilayer wiring board according to any one of claims 1 to 3 z ₁₎ is characterized in that it is a 0.5 to 1.5 [mu] m. 5. The maximum diameter of the via conductor formed in the surface multilayer wiring layer is 75 μm or less.
5. The multilayer wiring board according to any one of 4 to 4. 6. The via conductor formed in the surface multilayer wiring layer contains at least one metal selected from the group consisting of tin, lead, bismuth and indium, or an alloy thereof. The multilayer wiring board according to any one of the above. 7. (a) A step of producing a core substrate in which a conductor wiring layer having a roughened upper surface is formed on at least the surface of an insulating sheet containing at least a thermosetting resin, and (b).
Thermocompression-bonding a semi-cured first insulating sheet to the surface of the core substrate; A step of smoothing the uneven surface of the upper surface of the conductor wiring layer formed on the surface of the above, and filling the via hole formed in (d) and (c) with a conductor paste containing metal powder and an organic component to form a via conductor. And (f) a step of forming a first conductor wiring layer having a roughened upper surface on the first insulating sheet having the via conductor formed thereon, (f)
A method for manufacturing a multilayer wiring board, comprising the steps of: (b) to (e) being repeated to form a multilayer. 8. The surface roughness (Rz ₁ ) of a conductor wiring layer of the via conductor formed on the first insulating sheet, which abuts on the core substrate side, and the surface multilayer wiring layer of the conductor wiring layer. 8. The method for manufacturing a multilayer wiring board according to claim 7, wherein the difference between the surface roughness (Rz ₂ ) of the bonding portion with the constituent insulating layer is 0.5 μm or more. 9. The via conductor formed on the first insulating sheet has different via diameters at both ends, and the via diameter on the core substrate side is smaller than the via diameter on the opposite side to the core substrate side. The method for manufacturing a multilayer wiring board according to claim 7 or 8. 10. A surface roughness (R) of a conductor wiring layer abutting on a core substrate side of a via conductor formed on a first insulating sheet.
z ₁₎ is a method for manufacturing a multilayer wiring board according to any one of claims 7 to 9, characterized in that a 0.5 to 1.5 [mu] m. 11. The method for manufacturing a multilayer wiring board according to claim 7, wherein the via conductor formed on the first insulating sheet has a maximum diameter of 75 μm or less. 12. The via conductor formed on the first insulating sheet contains at least one metal selected from tin, lead, bismuth, and indium, or an alloy thereof. The method for manufacturing a multilayer wiring board according to any one of the above. 13. A processing output by laser light is 0.1-2.
The method for manufacturing a multilayer wiring board according to any one of claims 7 to 12, wherein 0 W and the number of pulses per unit time are 1 to 50 kHz.