JP4696596B2 - Image sensor and image sensor manufacturing method - Google Patents

Description

  The present invention relates to an image sensor such as a CMOS image sensor, and more particularly to a well tap for applying a potential to a well layer formed on a semiconductor substrate.

  Conventional solid-state image sensors are roughly classified into two types, a CCD system and a CMOS sensor system. In the CCD system, charges generated in a photodiode are directly transferred to the outside by a charge transfer element (CCD). On the other hand, in the CMOS sensor system, potential information due to electric charges generated in the photodiodes is output to the outside of the pixel through an amplifier provided corresponding to each photodiode (see Patent Document 1). In the CMOS image sensor, as shown in the cross-sectional view of FIG. 6, a potential is applied to the P well layer 2 formed on the N-type semiconductor silicon substrate 1 through a well tap (P +) 3. The well tap 3 has a structure in which the photodiode portion having the N − -type region layer 4 is separated by a field region (insulating region) 5. FIG. 7 is a plan view of the above-described CMOS image sensor. The CMOS image sensor includes a photodiode portion 6, a transfer gate 7 made of polysilicon, a reset gate 8 made of polysilicon, and an amplifier gate 9 made of polysilicon, and a field between the photodiode portions 6. A well dup 3 is formed in the region 5. Accordingly, in this case, the area of the photodiode portion 6 occupying one pixel is reduced by the field region 5 separating the well tap 3 and the photodiode portion 6 as shown in FIG. The sensor characteristics of the image sensor are deteriorated, which is disadvantageous in terms of characteristics.

Therefore, in order to enlarge the area of the photodiode portion occupying one pixel, as shown in the cross-sectional and plan views of FIGS. 8 and 9, the field region 5 that separates the well tap (P−) 3 and the photodiode portion 6 is used. The CMOS image sensor characteristics such as saturation output and sensitivity are improved by adjusting the concentration of the well tap 3 (P-type impurity concentration).
JP 2003-224249 A

  However, in the configuration in which the field region 5 that separates the well tap 3 and the photodiode portion 6 is eliminated, sensor characteristics such as saturation output and sensitivity can be improved. However, as shown in FIG. Since the N-type region layer 4 and the P-type impurity layer of the well tap 3 are close to each other, there is a possibility that a PN junction is formed at the boundary between them, and there is a concern that a white spot may be generated due to junction leakage due to this. . For this reason, the well tap (N− region layer) 3 is formed with an N-type impurity concentration that is one digit lower than the diffusion layer concentration required for the well tap 3 in consideration of junction leakage between the photodiode portion 6 and the N− type region layer 4. It must be formed. As a result, the resistance of the well tap 3 is increased, and there is a concern about the occurrence of problems such as shading due to floating of the well potential. Further, in the configuration shown in FIG. 8, the boundary between the photodiode portion 6 and the well tap 3 is determined by two masks and is formed by a photolithographic process. Due to this variation, the above-described PN junction may be formed.

  The present invention has been devised in view of the above circumstances, and an object of the present invention is to provide an image pickup element and an image pickup element that have no white spots or shading and have sensor characteristics such as good saturation output and sensitivity. It is in providing the manufacturing method of.

In order to achieve the above object, the present invention provides a semiconductor substrate, a well layer formed on the semiconductor substrate, a plurality of photoelectric conversion regions formed in the well layer, and the wells between adjacent photoelectric conversion regions. A region partition formed on the surface of the layer and surrounding a region where the well tap region is formed, the region partition formed by polysilicon and the region surrounded by the region partition And a well tap region formed by injecting an impurity of the same conductivity type as that of the well layer from the surface of the well layer toward the inside thereof.

The present invention also relates to a method for manufacturing an imaging device having a plurality of photoelectric conversion regions formed in a well layer formed on a semiconductor substrate, the surface of the well layer formed in the well layer a plurality of photoelectric conversion region that is, between the adjacent photoelectric conversion region, so as to surround the region c Erutappu region is formed, and forming a region partition wall with polysilicon, surrounded by the region partition wall And the step of implanting impurities of the same conductivity type as the well layer from the surface of the well layer to form the well tap region.

  As described above, in the present invention, when the gate electrode is formed, the region partition portion that determines the formation position of the well tap region is formed of polysilicon that can be finely processed, and the region partition portion (polysilicon partition wall) formed of this polysilicon is formed. The well tap region is formed from the surface of the well layer inside the portion) toward the inside, so that the formation position is between the two photoelectric conversion regions (photodiode portions) and the charge storage layer of these photoelectric conversion regions. It can be accurately defined at a position not close to the (N-type region layer). At this time, since the polysilicon can be finely processed, the photodiode portion can be made as large as possible, and the well tap can be formed at a position where the well tap layer therebetween is not close to the charge storage layer. As a result, the area of the photodiode portion per pixel is not reduced, so that favorable characteristics such as saturation output and sensitivity can be obtained, and the P + type region of the well tap forms the photodiode portion. Since it is arranged with high precision so as not to be close to the N − -type region layer, it is possible to eliminate the possibility of white spots and the like, and the impurity concentration of the well tap can be increased, thereby preventing the well potential from floating. Thus, problems such as shading can be prevented from occurring.

  According to the present invention, the region partition wall portion that determines the formation position of the well tap region is formed of polysilicon that can be finely processed when forming the gate electrode, and the well layer inside the region partition wall portion formed of this polysilicon is formed. By forming the well tap region from the surface to the inside, the photodiode portion is made as large as possible, and the well tap region between the two photodiode portions is not close to the charge storage region layer of the photodiode portion. Well tap regions can be formed at various positions. As a result, the area of the photodiode portion per pixel is not reduced, so that characteristics such as saturation output and sensitivity are good, and problems such as white spots and shading can be prevented from occurring. An image sensor having excellent characteristics can be obtained.

  The purpose of obtaining an image sensor with no white spots or shading, and good sensor output characteristics such as saturation output and sensitivity, is to finely define the area partition that determines the well tap area formation position when forming the gate electrode. This was realized by forming the well tap region in the inner direction from the surface of the well layer inside the region partition wall portion formed of polysilicon.

  FIG. 1 is a block diagram showing a configuration of a CMOS image sensor according to an embodiment of the present invention. However, the same parts as those in the prior art will be described with the same reference numerals, and description thereof will be omitted as appropriate. The CMOS image sensor includes an N-type semiconductor silicon substrate 1, a P well layer 2 formed on the N-type semiconductor silicon substrate 1, a well tap 3 for applying a potential to the P well layer 2, and an N- When the P + region of the mold region layer (charge storage layer) 4 and the well tap 3 is formed, it has a polysilicon partition wall portion 10 that defines the region.

  FIG. 2 is a plan view of the above-described CMOS image sensor. The CMOS image sensor includes a photodiode portion 6, a transfer gate 7 made of polysilicon, a reset gate 8 made of polysilicon, and an amplifier gate 9 made of polysilicon. Between the photodiode portions 6, In addition, the well tap 3 is disposed in a region surrounded by the polysilicon partition wall 10.

  Next, a method for forming the well tap 3 will be described with reference to FIGS. First, a polysilicon partition wall portion 10 that defines a region for forming the well tap 3 is formed in a mask pattern used when the transfer gate 7, the reset gate 8, and the amplifier gate 9 are formed of polysilicon by photolithography. Add a pattern for As a result, as shown in FIG. 3, the polysilicon partition 10 is formed when the gate electrodes (transfer gate 7, reset gate 8, and amplifier gate 9) are formed.

  Next, as shown in FIG. 4, the inside of the polysilicon partition wall 10 is covered with a photoresist (PR) 11, and an N-type impurity (such as arsenic) is implanted by ion implantation as indicated by an arrow to form an N-type. A photodiode is formed by forming the region layer 4.

  Finally, as shown in FIG. 5, the photodiode portion is covered with a photoresist 11, and a P-type impurity (boron) is ion-implanted as shown by an arrow to form a P + type region (well tap 3). . As a result, the P + type region of the well tap 3 is formed in the P well layer 2 inside the polysilicon partition wall 10.

  According to this embodiment, the range of the P + type region of the well tap 3 is defined by the polysilicon partition wall 10, and the P + type region of the well tap 3 is close to the N− type region layer 4 that forms the photodiode portion 6 ( The well tap 3 can be formed at a position where the PN junction is not generated). However, since the polysilicon can be finely processed, the photodiode portion 6 is made as large as possible and the wells between them are formed. The well tap 3 can be formed at a position where the tap 3 does not approach the N − type region layer 4 that forms the photodiode portion 6.

  Accordingly, since the area of the photodiode portion 6 per pixel is hardly reduced, good characteristics such as saturation output and sensitivity can be obtained. Moreover, since the P + type region of the well tap 3 is arranged with high precision so as not to be close to the N− type region layer 4 forming the photodiode portion 6, it is possible to eliminate the possibility of white spots and the like. Since the P-type impurity concentration of No. 3 can be increased, the well potential can be prevented from being lifted, and problems such as shading can be prevented from occurring.

  In addition, this invention is not limited to the said embodiment, In the range which does not deviate from the summary, it can implement also with another various form in a concrete structure, a function, an effect | action, and an effect. In the present embodiment, a polar N-type CMOS image having a P-type well layer formed on an N-type silicon substrate and having an N-type region layer 4 and a P + well tap 3 for forming a photodiode portion 6 there. Although the example in which the present invention is applied to the sensor has been described, the same effect can be obtained even if the present invention is applied to a P-type CMOS image sensor having the opposite polarity.

It is the block diagram which showed the structure of the CMOS image sensor which concerns on one Embodiment of this invention. It is a top view of the CMOS image sensor shown in FIG. It is a figure explaining the formation method of the well tap shown in FIG. It is a figure explaining the formation method of the well tap shown in FIG. It is a figure explaining the formation method of the well tap shown in FIG. It is sectional drawing which showed the structural example of the conventional CMOS image sensor. FIG. 7 is a plan view of the CMOS image sensor shown in FIG. 6. It is sectional drawing which showed the other structural example of the conventional CMOS image sensor. FIG. 9 is a plan view of the CMOS image sensor shown in FIG. 8.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... N-type semiconductor silicon substrate, 2 ... P well layer, 3 ... Well tap, 4 ... N- type area | region layer (charge storage layer), 6 ... Photodiode part, 7 ... Transfer gate, 8 ...... Reset gate, 9 ... Amplifier gate, 10 ... Polysilicon barrier.

Claims (4)

A semiconductor substrate;
A well layer formed on the semiconductor substrate;
A plurality of photoelectric conversion regions formed in the well layer;
A region partition formed on the surface of the well layer between adjacent photoelectric conversion regions and formed to surround a region where the well tap region is formed, and a region partition formed of polysilicon ;
A well tap region formed by injecting an impurity of the same conductivity type as the well layer from the surface of the well layer toward the inside of the region surrounded by the partition wall portion; An imaging device as a feature. 2. The well tap region is formed between the charge storage layers of two adjacent photoelectric conversion regions at positions separated from these charge storage layers so as not to form a PN junction. Image sensor. A method for manufacturing an imaging device having a plurality of photoelectric conversion regions formed in a well layer formed on a semiconductor substrate,
A surface of the well layer, among the plurality of photoelectric conversion region formed in the well layer, between adjacent photoelectric conversion region, so as to surround the region c Erutappu region is formed, a region partition wall Forming with polysilicon;
Injecting impurities of the same conductivity type as the well layer from the surface of the well layer into the region surrounded by the region partition wall , and forming the well tap region;
An image pickup device manufacturing method comprising: 4. The method of manufacturing an image pickup device according to claim 3, wherein the step of forming the region partition wall portion using polysilicon is the same step as the step of forming the gate electrode.

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