JP2006269546A - Solid-state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the occurrence of shading even if pixels are microfabricated in a CMOS solid-state imaging device. <P>SOLUTION: The solid-state imaging device includes a pixel region where a plurality of pixels 26 are arranged each including a photoelectric converter PD and a transistor 25. In this device, a semiconductor well region 28 common to all the pixels 26 is formed, and a plurality of well contacts 31 (31A and 31B) for applying reference voltage to the common semiconductor well region 28 are formed in each pixel 26. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device such as a CMOS image sensor.

  In a solid-state imaging device, particularly a CMOS image sensor, a large number of pixels are arranged in an array (an area where a large number of pixels are arranged in an array is referred to as a pixel region), and a common p-type semiconductor well region ( In the case where the well potential is applied from just outside the pixel region periphery, that is, from just outside the outermost peripheral pixel, the pixel region periphery near the contact (referred to as a well contact) for supplying the reference well potential; The time constant is different at the center of the distant pixel region. In such a case, if the power is supplied to each pixel through the entire drain wiring, when the drain voltage changes, the well potential of the p well varies due to the coupling between the entire drain wiring and the p well. As a result, the well potential fluctuates for a long time in the central portion of the pixel region having a large time constant compared to the peripheral portion of the pixel region. For this reason, a so-called shading phenomenon in which the output is different between the central portion of the pixel region and the peripheral portion of the pixel region may be seen.

  This shading phenomenon will be described with reference to the drawings. FIG. 12 shows a pixel configuration in a general CMOS image sensor. The unit pixel 1 of this CMOS image sensor is composed of a photodiode PD which is a photoelectric conversion unit, and three MOS transistors, that is, a transfer transistor 2, a reset transistor 3 and an amplification transistor 4 for reading signal charges from the photodiode PD. The The source of the transfer transistor 2 is connected to the photodiode PD, and the drain thereof is connected to the source of the reset transistor 3. A transfer wiring 5 is connected to the gate of the transfer transistor 2, and a reset wiring 6 is connected to the gate of the reset transistor 3. On the other hand, the floating diffusion (FD) between the transfer transistor 2 and the reset transistor 3 is connected to the gate of the amplification transistor 4, and the source of the amplification transistor is connected to the vertical signal line 7. Further, the drain of the reset transistor 3 and the drain of the amplification transistor 4 are connected to the drain terminal t. In the CMOS image sensor having such a pixel 1, the drain terminal t has a variable voltage and changes between a low level and a high level.

  FIG. 13B shows a dark output distribution in the ab cross section of the pixel region (for example, a pixel array of about 1.3 million pixels in the horizontal direction and about 1000 pixels in the vertical direction) 11 shown in FIG. 13A. Note that no well contact is arranged in each pixel. When the well contact is not arranged, it can be seen that the output changes greatly in the central portion as compared with the peripheral portion. This is dark shading caused by the well potential fluctuation of the common p-well.

As a method for preventing the reference potential of the common p-well that causes shading as described above from being different in the pixel region, there is a method of forming a well contact in the pixel (see Patent Document 1). By providing the well contact in the pixel in this manner, the well potential is stabilized even when the voltage of the drain terminal changes, the reference voltage becomes the same in the pixel region, and shading can be suppressed.
Japanese Patent Publication No. 8-21704

  As a more specific method for forming a well contact, there has been proposed a method in which one well contact is formed in the same active region (active region) as a photoelectric conversion portion, that is, a photodiode (Japanese Patent Application No. 2003-375202). reference). By using this method, it is possible to suppress shading without increasing the pixel size.

  By the way, with the advancement of MOS microfabrication technology, CMOS image sensors are also miniaturized by using the microfabrication technology. In short, the wiring becomes thinner and the contact size becomes smaller. That is, as the miniaturization progresses, the wiring resistance tends to increase. Conventionally, a wiring is drawn from the outside of the pixel region, a contact is formed in each pixel, and a reference voltage is supplied to the common p-well (this wiring is called a well wiring).

  However, as the miniaturization proceeds as described above, the wiring resistance increases, and a situation occurs in which the wiring resistance of the well wiring is larger than the resistance of the p-well. In this case, although the well contact is formed, there is a concern that the well potential becomes unstable and shading occurs due to the time constant of the well wiring. The conventional well contact is based on the premise that the resistance value of the well wiring is smaller than that of the common p-well, and is assumed to be used in a situation where the time constant of the wiring itself does not affect the p-well. Was.

  In order to solve such a problem, it is necessary to reduce the time constant of the well wiring. In normal pixel cell design, wiring related to pixels is often laid out with a line width and space close to the minimum value of the design rule. If the wiring is thickened, the photodiode is wired and the sensitivity is increased. Incurs a decline. Therefore, the countermeasures related to wiring are too disadvantageous.

  On the other hand, when the well wiring is made thin, it has been found that, in the resistance component of the well wiring, not the resistance of the wiring portion but the contact resistance of the well contact has a great influence.

  In view of the above-described points, the present invention provides a solid-state imaging device that can suppress the occurrence of shading even when pixels are miniaturized.

  A solid-state imaging device according to the present invention includes a pixel region in which a plurality of pixels including a photoelectric conversion unit and a transistor are arranged, a common semiconductor well region is formed in each pixel, and a reference voltage is applied to the common semiconductor well region. A plurality of well contacts to be provided are provided in each pixel.

  In the solid-state imaging device of the present invention, even when the well wiring is made narrower as the pixels are miniaturized by providing each pixel with a plurality of well contacts for applying a reference voltage to a common semiconductor well region. The contact resistance of the well contact is reduced, and the resistance component of the well wiring can be reduced.

  According to the solid-state imaging device of the present invention, by providing a plurality of well contacts for each pixel, an increase in the resistance component of the well wiring is suppressed, and even when the pixel is miniaturized, the occurrence of shading is suppressed. can do.

  When the well wiring is thinned, the contact component occupies most of the resistance component of the well wiring, not the wiring portion. That is, it has been found that contact resistance occupies a large amount. If the contact resistance from the well wiring to the common p-well can be reduced, the well potential stabilizing ability of the well contact is improved.

  In order to solve this problem, a plurality of well contacts may be simply formed. The biggest reason why this simple method has been avoided is because it has been regarded as a problem that white spots in the dark (hereinafter simply referred to as white spots) will occur frequently due to well contacts. However, by taking some countermeasures, white spots due to well contacts are drastically reduced. By utilizing this measure, it is possible to suppress shading due to well potential fluctuations in the common p-well while suppressing an increase in white spots.

  In the CMOS image sensor having such a pixel 1 shown in FIG. 12 described above, the drain terminal t has a variable voltage and changes between a low level and a high level. In the present embodiment, when the drain voltage changes when the drain wiring extends over the entire pixel region, the well potential of the p-well is prevented from fluctuating due to coupling with the common p-well. This is to prevent various phenomena that lead to image quality degradation such as shading caused by fluctuations in potential.

  What has been described so far is the case where one well contact is disposed in the same active region as the photodiode PD, but as described in the problem, as the resistance of the well wiring increases, the well contact increases. A decrease in the well potential stabilization capability of the contact is expected. Therefore, in this embodiment, a plurality of well contacts are arranged for each pixel.

  Embodiments of a solid-state imaging device according to the present invention will be described below in detail with reference to the drawings.

  FIG. 1 shows a first embodiment of a solid-state imaging device, that is, a CMOS image sensor according to the present invention. FIG. 1 shows a pixel portion. In the CMOS image sensor 21 of the present embodiment, a photodiode PD serving as a photoelectric conversion unit and a plurality of transistors (in the illustrated case, only a transfer transistor 25 having a transfer gate 23 and source / drain regions 24 are shown, and other resets are shown. A pixel region including a plurality of pixels 26 including a transistor and an amplifying transistor, and a first conductivity type semiconductor well region common to each pixel 26, in this example, a p-type semiconductor well region (hereinafter referred to as “p-type semiconductor well region”). 28) (referred to as a common p-well).

  A plurality of, in this example, two well contacts 31 (31A, 31B) are arranged in the same active region 29 as the photodiode PD. Here, the photodiode PD is formed in such a shape that a part of the depression 33 is formed, and two well contacts 31 (31A, 31) are formed in the active region 29 corresponding to the depression 33. . The number of well contacts 31 may be three or more. However, since the area of the photodiode PD is reduced and the saturation signal amount is reduced, a preferable number is determined by the balance. The well wiring 34 is formed so as to partially cross the photodiode PD so as to be connected to both well contacts 31A and 31B arranged in the horizontal direction. In the pixel 26 of FIG. 1, a portion other than the active region 29 and the transistor 25 is formed as an element isolation region 35.

  FIG. 7 shows an example of a cross-sectional structure of the well contact 31 portion. A common p-well 28 is formed in the silicon semiconductor substrate 37, and a photodiode PD is formed in a portion corresponding to the active region of the common p-well 28. The common p-well 28 is provided with a well contact 31 for supplying a reference voltage for the purpose of stabilizing the well potential. The well contact 31 includes an electrode 39 for supplying a reference voltage formed in the interlayer insulating film 38, a p-type impurity introduction region 41 formed in the surface layer of the common p well 28, and a p-type impurity introduction region 41. The contact portion 42 is formed and connected to the electrode 39 and has a higher concentration than the p-type impurity introduction region 41.

The p-type impurity introduction region 41 is formed so that at least the impurity concentration thereof is 1 × 10 ¹⁹ cm ⁻³ or less. The electrode 39 is made of, for example, a tungsten plug 43, and a barrier metal layer 44 made of three layers of titanium, titanium nitride, and titanium is formed on the side surface thereof. Further, a well wiring is connected on the electrode 39 (not shown).

  Here, the p-type impurity introduction region 41 is a p-type region having a depth of about 0.1 μm from the silicon surface extending under and around the electrode 39. The p-type impurity introduction region is formed before the contact hole for the electrode 39 is opened in the manufacturing process, and is widened by at least a minimum misalignment (about 0.05 μm) below and around the electrode 39. It becomes the formed region. On the side where the photodiode PD is not provided, it is usual to form up to an element isolation region (not shown). The p-type impurity introduction region 41 is constituted by a total of impurity components near the surface of the common p-well 28 and impurity components additionally ion-implanted therein.

Next, the impurity concentration distribution in the depth direction of the p-type impurity introduction region 41 and the contact portion 42 will be described with reference to FIG. As shown in FIG. 10, on the side close to the surface, the impurity concentration of the contact portion 42 is approximately 10 ²⁰ cm −3, and the impurity concentration of the p-type impurity introduction region 41 corresponding to the periphery thereof is approximately 10 ¹⁹ cm −. 3.

Next, FIG. 11 shows the relationship between the impurity concentration of the p-type impurity introduction region 41 and the number of white spots. As shown in FIG. 11, when the impurity concentration is about 10 ¹⁹ cm −3 rather than about 10 ²⁰ cm −3, the number of white spots is reduced by about one digit over the entire white point output level. In particular, in the vicinity of the white spot output level of 3 mV, it decreases by almost two digits.

This is presumably because implantation damage such as crystal defects due to ion implantation is reduced, and unintended atom implantation is reduced.
Incidentally, since it is not a good idea to reduce the impurity concentration of the contact portion 42 in order to make an ohmic contact, the impurity concentration is set to about 10 ²⁰ cm −3. Therefore, the photodiode PD is arranged away from the contact portion 42 as shown in FIG. For example, the n-type impurity forming the photodiode PD is not introduced in the range from the contact portion 42 to the margin width w = 0.1 μm. When these are close to each other, a strong electric field portion is generated, and a white spot due to this portion is generated with a probability. Here, the photodiode PD, which is an n-type region, is formed separately from the contact portion 42, which is a high-concentration p-type region, so that the influence of a strong electric field is reduced, so that the number of white spots is reduced. There is. Of course, the number of white spots can be reduced from the viewpoint of suppressing crystal defects caused by impurity implantation around the well contact 31 and preventing unintended diffusion of atoms. Here, the margin width w set to 0.1 μm is not limited to 0.1 μm, but it is currently about 0.1 μm in consideration of mask misalignment, line width variation, and the like. Due to future process technology improvements, the margin width w may be narrower.
Since the concentration of the p-type impurity introduction region 41 is low, it can be adjacent to the photodiode PD. It is important that the concentration of the p-type impurity introduction region is thinner than before.

  FIG. 8 shows another example of the cross-sectional structure in the well contact 31 portion. A common p-well 28 is formed in the silicon semiconductor substrate 37, and a photodiode PD is formed in a portion corresponding to the active region of the common p-well 28. The common p-well 28 is provided with a well contact 31 for supplying a reference voltage for the purpose of stabilizing the well potential. The well contact 31 includes an electrode 43 for supplying a reference voltage and a contact portion 42 having a higher concentration than that of the common p well 28 formed in the surface layer of the common p well 28 as described above. The feature of this example is that the p-type impurity introduction region 41 as shown in FIG. 7 does not have an impurity distribution clearly distinguished from the periphery, and impurities near the surface of the common p-well 28 are p-type in the above-described sense. That is, the impurity introduction region 41 is formed. The electrode 39 is made of, for example, a tungsten plug 43, and a barrier metal layer 44 made of a three-layer film of titanium, titanium nitride, and titanium is formed on a side surface of the electrode 39. Further, although not shown, a well wiring is connected on the electrode 39.

  Unlike the well contact shown in FIG. 7, the well contact 31 shown in FIG. 8 does not perform ion implantation in addition to the common p well 28 as the p-type impurity introduction region 41. Boron (B) and boron difluoride (BF2) are not ion-implanted into the substrate, crystal defects are hardly induced in the common p-well 28, and heavy metal atoms are not mixed and diffused in the process. Therefore, the number of white spots can be further reduced.

In this case, the contact portion 42 is formed by ion implantation after opening the contact hole. However, if the contact portion 42 has substantially the same structure, the formation process of the contact portion 42 is the same as that of the p-type impurity region described above. It may be before opening. An example is shown in FIG. 8 is the same as the case of FIG. 8 in that the contact portion is formed so as to have an impurity concentration of about 10 ²⁰ cm −3 and further separated from the n-type region of the photodiode PD by about 0.1 μm. The difference is that the order and forming range in the forming process are larger than the electrode width. In this case, in consideration of misalignment or the like, the contact portion may be formed to be about 0.05 μm or more wide and separated from the photodiode PD by about 0.1 μm under and around the electrode. Note that the number of white spots is about the same as in FIG.

According to the first embodiment described above, the well potential of the common p well 28 is provided by arranging a plurality of, in this example, two well contacts 31 (31A, 31B) in the same active region 29 as the photodiode PD. Can be stabilized. Even when the well wiring 34 is thinned due to miniaturization, the contact resistance is reduced by the two well contacts connected in parallel to the well wiring, so that a substantial increase in resistance component of the well wiring is suppressed. . Therefore, dark shading in the dark can be suppressed. Shading can be suppressed when light is incident, and saturation shading can be suppressed when saturated. Moreover, fixed pattern noise can be suppressed. Furthermore, the conventional technique can be used as it is, and the cost is not higher than the conventional one. When the number of well contacts 31 is two, the well contacts 31 can be arranged without greatly reducing the area of the photodiode PD.
On the other hand, by configuring the well contact 31 as shown in FIG. 7, FIG. 8, or FIG. 9, even if the number of well contacts increases, an increase in white spots due to the well contacts can be suppressed.

  FIG. 2 shows a second embodiment of a CMOS image sensor according to the present invention. In the CMOS image sensor 51 of the present embodiment, when the same active region 29 as the photodiode PD serving as a photoelectric conversion unit is connected between the pixels 26 in the vertical direction, the horizontal direction, or the diagonal direction in the drawing, in this example, When the active region 29 is connected between the pixels 26 in the vertical direction, a plurality of, in this example, two well contacts 31 (31D, 31E) are provided in the active region 29 connected between the pixels 26 in the vertical direction. Arranged and configured. At this time, since the well contact 31 is disposed at a position away from the photodiode PD, the area of the photodiode PD is not affected by the well contact 31. The well wiring 34 is formed along the horizontal direction so as to be connected to both well contacts 31D and 31E arranged in the vertical direction. At this time, the well wiring 34 can be arranged without crossing the photodiode PD. Alternatively, the well wiring 34 is formed so as to cross an extremely small area even when the photodiode PD is crossed. For example, the cross-sectional structure of the well contact 31 is the same as that shown in FIG. 7, FIG. 8, or FIG. Other configurations are the same as those described in the first embodiment.

According to the CMOS image sensor 51 of the second embodiment, a plurality of (two in this example) well contacts 31D and 31E are arranged in the active region 29 connecting the pixels 26. An increase in the resistance component of the wiring 34 can be suppressed. Therefore, the well potential of the common p-well 28 can be stabilized and shading can be suppressed. In this case, a plurality of well contacts are arranged in the same active region 29 as the photodiode PD, but the influence on the photodiode PD can be minimized. For this reason, shading can be suppressed without substantially reducing the saturation signal amount.
On the other hand, by configuring the well contact 31 as shown in FIG. 7, FIG. 8, or FIG. 9, even if the number of well contacts increases, an increase in white spots due to the well contacts can be suppressed.

  FIG. 3 shows a third embodiment of a CMOS image sensor according to the present invention. In the CMOS image sensor 52 of the present embodiment, one or more well contacts 31, in this example, one well contact 31 A are arranged in the same active region 29 as the photodiode PD that is a photoelectric conversion unit of each pixel 26, At least one other well contact 31, in this example one well contact 31 C, is provided in another active region (active region formed outside the active region 29 including the photodiode PD) 29 ′ in the same pixel 26. Arranged and configured. In this example, a total of two well contacts 31A and 31C are arranged corresponding to each pixel 26.

  In other words, the photodiode PD is formed in a shape in which a partially recessed portion 33 is formed, and one well contact 31A is formed in the active region 29 corresponding to the recessed portion 33. In addition, one well contact 31C is formed in another active region 29 'located on a horizontal line passing through the active well contact 31A. The well wiring 34 is formed so as to partially cross the photodiode PD so as to be connected to both well contacts 31A and 31C arranged on the horizontal line. The cross-sectional structure of the well contacts 31A and 31C adopts the configuration of FIG. 7, FIG. 8, or FIG. Other configurations are the same as those described in the first embodiment.

According to the CMOS image sensor 52 of the third embodiment, a plurality of, in this example, two well contacts 31A and 31C are arranged in each pixel 26. Therefore, the resistance of the well wiring 34 due to the miniaturization. An increase in components can be suppressed. Therefore, the well potential of the common p-well 28 can be stabilized and shading can be suppressed. In this case, a well contact 31C is added to another active region 29 'in the same pixel 26 with respect to the well contact 31A that was originally in the same active region 29 as the photodiode PD. It is possible to obtain exactly the same pixel characteristics. Since the well wiring 34 partially crosses the photodiode PD, the sensitivity is somewhat sacrificed. However, since the area of the photodiode PD can be secured sufficiently, a sufficient saturation signal amount can be secured.
On the other hand, by configuring the well contact 31 as shown in FIG. 7, FIG. 8, or FIG. 9, even if the number of well contacts increases, an increase in white spots due to the well contacts can be suppressed.

  FIG. 4 shows a fourth embodiment of a CMOS image sensor according to the present invention. In the CMOS image sensor 53 of the present embodiment, when the active region 29 including the photodiode PD is connected between the pixels 26 in the vertical direction, the horizontal direction, or the diagonal direction in the figure, in this example, the vertical region 26 is connected between the pixels 26. In this example, one well contact 31D is disposed in the active region 29 connected between the pixels 26 and the same active region as the photodiode PD of each pixel. One or more well contacts 31A are arranged in this example. In this example, a total of two well contacts 31A and 31C are arranged corresponding to each pixel 26.

  In other words, the photodiode PD is formed in a shape in which a partially recessed portion 33 is formed, and one well contact 31A is formed in the active region 29 corresponding to the recessed portion 33. The well contact 31D is formed on the boundary between the pixels. Therefore, two or more well contacts 31 are arranged in this example, substantially two or more from any pixel. Well wiring 34 is formed so as to be connected to both well contacts 31A and 31D. For example, the cross-sectional structure of the well contacts 31A and 31D adopts the configuration shown in FIG. 7, FIG. 8, or FIG. Other configurations are the same as those described in the first embodiment.

According to the CMOS image sensor 53 of the fourth embodiment, a plurality of, in this example, two well contacts 31A and 31D are arranged corresponding to each pixel 26. Therefore, the resistance component of the well wiring 34 accompanying the miniaturization. Can be suppressed. Therefore, the well potential of the common p-well 28 can be stabilized and shading can be suppressed. This embodiment is effective when the active area 29 between the pixels 26 is narrow. Further, each pixel shares one well contact 31D, and an active region between the pixels is simply added to the well contact in the same active region 29 as that of the conventional photodiode PD. Very small.
On the other hand, by configuring the well contacts 31A and 31D as shown in FIG. 7, FIG. 8, or FIG. 9, even if the number of well contacts increases, an increase in white spots due to the well contacts can be suppressed.

  FIG. 5 shows a fifth embodiment of a CMOS image sensor according to the present invention. In the CMOS image sensor 54 of the present embodiment, when the active region 29 including the photodiode PD is connected between the pixels 26 in the vertical direction, the horizontal direction, or the diagonal direction in the figure, in this example, the pixels 26 in the vertical direction are connected. In the present example, one well contact 31D is disposed in the active region 29 connected between the pixels 26, and another active region ( One or more other well contacts 31 (in this example, one well contact 31C) are arranged in an active region) 29 'formed in a region outside the active region 29 including the photodiode PD. In this example, a total of two well contacts 31A and 31C are arranged corresponding to each pixel 26.

  That is, the well contact 31D is formed on the boundary between the pixels. The well contact 31C is formed in another active region 29 'formed in a region corresponding to the element isolation region of each pixel. Therefore, two or more well contacts 31 are arranged in this example, substantially two or more from any pixel. The well wiring 34 is formed so as to be connected to both the well contacts 31D and 31C. The cross-sectional structure of the well contacts 31D and 31C has the same configuration as that shown in FIG. 7, FIG. 8, or FIG. 9, for example. Other configurations are the same as those described in the first embodiment.

According to the CMOS image sensor 54 of the fifth embodiment, a plurality of, in this example, two well contacts 31A and 31D are arranged corresponding to each pixel 26. Therefore, the resistance component of the well wiring 34 accompanying the miniaturization. Can be suppressed. Therefore, the well potential of the common p-well 28 can be stabilized and shading can be suppressed. In this embodiment, the influence of the well contacts 31D and 31C on the photodiode PD is minimized. This is also effective when the active area 29 between the pixels 26 is narrow. Further, each pixel shares one well contact 31D, and an active region between the pixels is simply added to the well contact in the same active region 29 as that of the conventional photodiode PD. Very small.
On the other hand, by configuring the well contacts 31D and 31C as shown in FIG. 7, FIG. 8, or FIG. 9, even if the number of well contacts increases, an increase in white spots due to the well contacts can be suppressed.

  FIG. 6 shows a sixth embodiment of a CMOS image sensor according to the present invention. The CMOS image sensor 55 according to the present embodiment includes a plurality of, in this example, two, active regions 29 ′ formed in a region different from the same active region 29 as the photodiode PD serving as a photoelectric conversion unit of each pixel. The well contacts 31 (31C, 31F) are arranged. This active region 29 'is formed in a region corresponding to the element isolation region. Well wiring 34 is formed so as to be connected to both well contacts 31F and 31G. For example, the cross-sectional structure of the well contacts 31F and 31G has the same configuration as that shown in FIG. 7, FIG. 8, or FIG. Other configurations are the same as those described in the first embodiment.

According to the sixth embodiment, since a plurality of well contacts 31F and 31G in this example are arranged in each pixel, an increase in resistance component of the well wiring 34 due to miniaturization is suppressed. Can do. Therefore, the well potential of the common p-well 28 can be stabilized and shading can be suppressed. In this case, since the two well contacts 31F and 31G are arranged in the active region 29 'at a position away from the photodiode PD, the saturation signal amount is sufficiently secured without affecting the area of the photodiode PD. be able to.
On the other hand, by configuring the well contacts 31D and 31C as shown in FIG. 7, FIG. 8, or FIG. 9, even if the number of well contacts increases, an increase in white spots due to the well contacts can be suppressed.

1 is a schematic composition of a main part showing a first embodiment of a solid-state imaging device according to the present invention. It is a schematic composition of the important section showing a 2nd embodiment of the solid-state image sensing device concerning the present invention. It is a schematic composition of the principal part which shows 3rd Embodiment of the solid-state imaging device concerning this invention. It is a schematic composition of the principal part which shows 4th Embodiment of the solid-state imaging device concerning this invention. It is a schematic structure of the principal part which shows 5th Embodiment of the solid-state imaging device which concerns on this invention. It is a schematic structure of the principal part which shows 6th Embodiment of the solid-state imaging device which concerns on this invention. It is sectional drawing which shows an example of the well contact structure which concerns on this invention. It is sectional drawing which shows the other example of the well contact structure which concerns on this invention. It is sectional drawing which shows the further another example of the well contact structure which concerns on this invention. This is an impurity concentration distribution in the depth direction of the p-type impurity introduction region and the contact portion in the well contact. FIG. 6 is a relationship diagram between the impurity concentration of a p-type impurity introduction region in a well contact and the number of white spots. It is an equivalent circuit diagram which shows the structure of the general pixel of a CMOS image sensor. FIG. 4 is a schematic configuration diagram of A and B pixel regions and an output distribution diagram at dark time for explaining shading.

Explanation of symbols

21, 51, 52, 53, 54, 55..Solid-state imaging device (CMOS image sensor), PD..photodiode (photoelectric conversion unit), 23..transfer gate, 25..transfer transistor, 26..pixel, 28 ·· Common p-well, 29, 29 '· · Active region, 31 (31A, 31B, 31C, 31D, 31E, 31F, 31G) · · Well contact, 33 · · Recessed portion, 34 · · Well wiring, 35 ..Element isolation region 37..Semiconductor substrate 38..Interlayer insulating film 39..Electrode 41..P-type impurity introduction region 42..Contact part 43..Tungsten plug 44..Barrier metal layer

Claims (13)

A pixel region in which a plurality of pixels including a photoelectric conversion unit and a transistor are arranged,
A common semiconductor well region is formed in each of the pixels;
A solid-state imaging device, wherein a plurality of well contacts for applying a reference voltage to the common semiconductor well region are provided in each pixel. The solid-state imaging device according to claim 1, wherein the number of well contacts in each pixel is two. The solid-state imaging device according to claim 1, wherein a plurality of the well contacts are provided in the same active region as the photoelectric conversion unit of each pixel. The solid-state imaging device according to claim 3, wherein the number of well contacts in each pixel is two. One or more well contacts are provided in the same active region as the photoelectric conversion portion of each pixel,
The solid-state imaging device according to claim 1, further comprising one or more well contacts in another active region in the same pixel. The solid-state imaging device according to claim 7, wherein the number of well contacts in each pixel is two. An active region including a photoelectric conversion unit is connected between the pixels in the vertical direction, the horizontal direction, or the diagonal direction,
The solid-state imaging device according to claim 1, wherein a plurality of the well contacts are provided in the active region connected between the pixels. The solid-state imaging device according to claim 7, wherein the number of well contacts between the pixels is two. An active region including a photoelectric conversion unit is connected between the pixels in the vertical direction, the horizontal direction, or the diagonal direction,
One or more well contacts are provided in the active region connected between the pixels;
The solid-state imaging device according to claim 1, wherein one or more well contacts are provided in an active region of each pixel. An active region including a photoelectric conversion unit is connected between the pixels in the vertical direction, the horizontal direction, or the diagonal direction,
One or more well contacts are provided in the active region connected between the pixels;
The solid-state imaging device according to claim 1, wherein one or more well contacts are provided in an active region different from the same active region as the photoelectric conversion unit in each pixel. The solid-state imaging device according to claim 1, wherein a plurality of well contacts are provided in an active region different from the same active region as the photoelectric conversion unit in each pixel. The well contact is
An electrode for supplying a reference voltage;
A first impurity introduction region of the first conductivity type formed in a surface layer of the common first conductivity type semiconductor well region;
The first conductivity type contact portion formed in the first impurity introduction region so as to be connected to the electrode and having a higher concentration than the first impurity introduction region. The solid-state imaging device according to claim 1. The well contact is
An electrode for supplying a reference voltage;
A first conductivity type contact portion formed in a surface layer of the common first conductivity type semiconductor well region and having a higher concentration than the common first conductivity type semiconductor well region so as to be connected to the electrode; The solid-state imaging device according to any one of claims 1 to 11, wherein the solid-state imaging device is formed.

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