JP4689700B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko gaming machine, and in particular, when a game medium is launched into a game area by a player's operation and the game medium wins a prize area provided in the game area, a predetermined value is given to the player. A gaming machine that can be given and a special game value can be given to a player based on the result of the special game being in a predetermined mode by entering the game medium into the specific winning portion. .

  As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a prize area such as a prize opening provided in the game area, a predetermined number of prize balls are paid out to the player. There is something to be done. Further, a variable display unit capable of changing the display state is provided, and is configured to give a predetermined game value to the player when the display result of the variable display unit becomes a predetermined specific display mode There is.

  The variable display section has a plurality of display areas, and is usually configured to display the display results of the plurality of variable displays at different times. For example, a plurality of pieces of identification information such as symbols are variably displayed on the variable display section. That the display result of the variable display unit is a combination of specific display modes determined in advance is usually referred to as “big hit”. Note that the game value is the right that the state of the variable winning ball device provided in the gaming area of the gaming machine is advantageous for a player who is likely to win a ball, or the advantageous state for a player. It is to generate. When a “hit” occurs, for example, a player is given a value such as a large number of prize balls.

  In game control in such a gaming machine, a random number is generated when a predetermined condition (for example, a start prize that becomes a variable display start condition) is satisfied, and a “big hit” when the random number value matches a predetermined value. It becomes. In addition, a circuit portion that performs game control for reasons such as noise countermeasures is reset and activated at predetermined time intervals. Since the generation of the random number value is performed in the circuit portion that performs the game control, it must be synchronized with the activation time interval of the circuit portion that performs the game control.

  Then, when the activation time interval is detected by some means, the random value generation timing is recognized. Furthermore, the timing at which a random value that is a “big hit” is recognized is recognized. Then, it becomes possible to frequently generate a “hit” by aiming for a start winning prize at a timing when a random value that becomes a “hit” is generated.

  An illegal board may be attached to the gaming machine in order to detect the start timing of the circuit portion that performs game control. Such a fraudulent board introduces a signal that is output to the outside from the circuit part that performs game control, detects the start timing of the circuit part that performs game control based on the signal, and generates a random value that becomes a "big hit" The timing to do is detected. Then, the illegal board can illegally generate a “hit” by sending a start winning signal to the circuit portion that controls the game at that timing.

  Since various components such as a variable display device, a decorative lamp, and a sound generator are present in the gaming machine, it is not possible to eliminate signal lines from the circuit portion that performs game control to those components. Accordingly, there remains a room where the illegal board as described above is attached and illegal gaming acts are performed. Therefore, how to prevent an illegal gaming act using an illegal board is an important issue in the gaming machine.

  In view of the above, an object of the present invention is to provide a gaming machine that can effectively prevent an attack against a game by an unauthorized board.

The gaming machine according to the present invention performs a special game based on the fact that the start port switch is turned on by winning a game medium in the specific winning section, and the player is based on the result of the special game being in a predetermined mode. A gaming machine that can be given a predetermined game value, and executes periodic processing including switch determination processing that determines whether or not the start port switch is turned on at predetermined intervals according to the game control program, and from the start port switch The game control means having an input port for receiving the detection signal and the game control means are provided separately, and an external counter whose numerical value is updated at an interval shorter than a predetermined interval and the game control means are provided separately. And a latch circuit that latches a numerical value updated by the external counter. The external counter has a configuration in which a plurality of multi-bit counters are connected in series. A clock signal from the outside is input to the clock input terminal of the first-stage multi-bit counter of the multi-bit counters, and the multi-bit counter is carried to the clock input terminals of the multi-bit counters other than the first stage among the multi-bit counters The detection signal from the start port switch is branched and input to the latch circuit and the input port of the game control means. The latch circuit is based on the detection signal from the start port switch being input. The value updated by the external counter is latched, and the game control means determines whether or not the detection signal from the start port switch is input to the input port in a predetermined period in the switch determination process executed in the regular process. and, starting opening switch is surely turned on when it is determined that the detection signal has been input a predetermined number of times to the input port Judgment, when it is determined that the start hole switch is certainly turned on, it is determined whether or not there is an empty space in start winning storage, latched by the latch circuit when it is judged that there is a space in the start winning storage numeric Is read from the latch circuit, and a lottery process is performed to determine whether or not the result of the special game is in a predetermined mode using the numerical value read from the latch circuit.

Here, the numerical value acquisition means is provided outside the game control means. The configuration provided outside is, for example, a configuration in which an output value that changes at high speed is latched in hardware by a signal from a switch that detects a winning of a game medium to a specific winning portion.
In addition, the output of the switch for detecting the winning of the game medium to the specific winning portion is input to the game control means and the numerical value acquisition means, respectively.

According to the present invention, the gaming machine performs periodic processing including switch determination processing for determining whether or not the start port switch is turned on at a predetermined interval according to the game control program, and a detection signal from the start port switch is input. The game control means having the input port and the game control means are provided separately, and an external counter whose numerical values are updated at intervals shorter than a predetermined interval and the game control means are provided separately from each other. The game control means determines whether or not the detection signal from the start port switch is input to the input port in a predetermined period in the switch determination process executed in the periodic process. determination, the starting opening switch when the detection signal is determined to have been input a predetermined number of times to the input port is determined to certainly turned on, starting opening switch is turned on It is determined whether or not there is an empty start prize memory when it is determined, and when it is determined that there is an empty start prize memory, the value latched by the latch circuit is read from the latch circuit and read from the latch circuit. Since the lottery process for determining whether or not the result of the special game is in a predetermined mode is executed using a numerical value, the output of the external counter that generates a random number that is not synchronized with the start cycle of the game control program Since it is possible to perform a lottery process based on this, even when observing various signals output from the game control means in synchronization with a predetermined activation timing, it is impossible to estimate the extraction timing of the random number for jackpot determination, The effect of effectively preventing illegal gaming acts by not being able to give a signal to illegally generate a big hit from outside the game control means A.

  When the numerical value acquisition means is provided outside the game control means, and when the output of the switch for detecting the winning of the game medium to the specific winning portion is input to the game control means and the numerical value acquisition means, respectively. Has the effect of reducing the burden on the random number acquisition of the game control means.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
First, the overall configuration of a pachinko gaming machine that is an example of a gaming machine will be described. FIG. 1 is a front view of the pachinko gaming machine 1 as seen from the front. Here, a pachinko gaming machine is shown as an example of a gaming machine, but the present invention is not limited to a pachinko gaming machine, and may be, for example, a coin gaming machine or the like. This is applicable to all gaming machines that can give a player a predetermined game value based on the result of the special game being in a predetermined mode.

  As shown in FIG. 1, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2 is a hitting ball supply tray 3. Below the hitting ball supply tray 3, there are provided an extra ball receiving tray 4 for storing prize balls overflowing from the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing the hitting ball. A game board 6 is detachably attached to the rear side of the glass door frame 2. A game area 7 is provided in front of the game board 6.

  Near the center of the game area 7, a variable display device 8 including an image display unit 9 for displaying game contents and a variable display 10 using 7 segment LEDs is provided. A passing gate 11 for guiding a hit ball is provided on the side of the variable display device 8. The hit ball that has passed through the passing gate 11 is guided to the start winning opening 14 through the ball outlet 13. In the passage between the passage gate 11 and the ball exit 13, there is a gate switch 12 that detects a hit ball that has passed through the passage gate 11. The winning ball that has entered the start winning opening 14 is guided to the back of the game board 6 and detected by the start opening switch 17.

  A variable winning ball device 15 that opens and closes is provided below the start winning opening 14. The variable winning ball device 15 is opened by a solenoid 16. An open / close plate 20 that is opened by a solenoid 21 in a specific gaming state (big hit state) is provided below the variable winning ball device 15. Of the winning balls guided from the opening / closing plate 20 to the back of the game board 6, the winning ball entering one (V zone) is detected by the V count switch 22. A winning ball from the opening / closing plate 20 is detected by the count switch 23. At the bottom of the variable display device 8, a start winning memory display 18 having four display units for displaying the number of winning balls that have entered the start winning opening 14 is provided. In this example, with the upper limit being four, each time there is a start prize, the start prize storage display 18 increases the number of lit display units one by one. Each time variable display on the image display unit 9 is started, the number of display units that are lit is reduced by one.

  The game board 6 is provided with a plurality of winning openings 19, 24. Decorative lamps 25 blinking during the game are provided around the left and right sides of the game area 7, and an outlet 26 for absorbing a hit ball that has not won a prize is provided below. Two speakers 27 that emit sound effects are provided on the left and right upper portions outside the game area 7. A game effect lamp / LED 28 is provided on the outer periphery of the game area 7. In this example, a prize ball lamp 51 is provided in the vicinity of one speaker 27 so as to be turned on when the prize ball is paid out, and a ball-out lamp 52 that is turned on when the supply ball is cut out is provided in the vicinity of the other speaker 27. Is provided. Further, FIG. 1 also shows a card unit 50 that is installed adjacent to the pachinko gaming machine 1 and enables ball lending by inserting a prepaid card.

  The hit ball fired from the hit ball launching device enters the game area 7 through the hit ball rail, and then descends the game area 7. When the hit ball is detected by the gate switch 12 through the passing gate 11, the display number of the variable display 10 changes continuously. Further, when the hit ball enters the start winning opening 14 and is detected by the start opening switch 17, a predetermined variable display image is displayed in the image display unit 9 if variable display can be started. If variable display cannot be started, the start winning memory is incremented by one. The start winning memory will be described in detail later.

  The variable display in the image display unit 9 ends when a certain time has elapsed or when a predetermined condition is satisfied. When the condition is satisfied, the game shifts to a big hit gaming state. That is, the opening / closing plate 20 is opened until a predetermined time (for example, 29.5 seconds) elapses or until a predetermined number (for example, 10) of hit balls wins. When the hit ball enters the specific winning area while the opening / closing plate 20 is opened and is detected by the V count switch 22, a right to continue is generated and the opening / closing plate 20 is opened again. The generation of the continuation right is allowed a predetermined number of times (for example, 15 rounds).

  When the combination of images in the variable display section 9 at the time of stop is a combination of jackpot symbols with probability fluctuations, the probability of the next jackpot increases. That is, it becomes a more advantageous state for the player in a high probability state. Further, when the stop symbol on the variable display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the high probability state, the probability that the stop symbol in the variable display 10 becomes a winning symbol is increased, and the opening time and the number of times of opening of the variable winning ball device 15 are increased.

Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG.
On the back surface of the variable display device 8, as shown in FIG. 2, a prize ball tank 38 is provided above the mechanism plate 36, and the prize ball is placed from above in a state where the pachinko gaming machine 1 is installed on the gaming machine installation island. It is supplied to the prize ball tank 38. The prize balls in the prize ball tank 38 pass through the guide rod 39 and reach the ball dispensing device.

  The mechanism plate 36 includes a variable display control unit 29 for controlling the variable display unit 9 via the relay board 30, a game control board (main board) 31 covered with a board case 32 and mounted with a game control microcomputer, etc. A relay board 33 for relaying signals between the variable display control unit 29 and the main board 31, and a prize ball board 37 on which a payout control microcomputer for performing payout control of prizes is mounted. . Further, on the mechanism plate 36, a ball hitting device 34 that launches a hit ball to the game area 7 by using the rotational force of the motor, and a lamp control for sending signals to the speaker 27 and the game effect lamps / LEDs 28a, 28b, 28c. A substrate 35 is installed.

  FIG. 3 is a rear view of the game board of the pachinko gaming machine 1 as seen from the back. On the back surface of the game board 6, as shown in FIG. 3, a winning ball collective cover 40 is provided for guiding the winning balls that have won the winning holes and the winning ball devices along a predetermined winning path. Among the winning balls led to the winning ball collective cover 40, those that win through the opening / closing plate 20 are controlled so that the ball paying device 97 pays out a relatively large number of prize balls (for example, 15). What is won through the start winning opening 14 is controlled such that a ball payout device (not shown in FIG. 3) pays out a relatively small number of prize balls (for example, 6). And what was won through the other winning opening 24 and the winning ball device is controlled such that the ball payout device pays out a relatively medium number of prize balls (for example, 10). In FIG. 3, the relay board 33 is illustrated.

  In order to perform the winning ball payout control, signals from the winning ball detection switch 99, the start port switch 17 and the V count switch 22 are sent to the main board 31. When the ON signal of the winning ball detection switch 99 is sent to the main board 31, a winning ball number signal is sent from the main board 31 to the winning ball board 37. The winning ball detection switch 99 detects that there has been a winning. In this case, a prize ball number signal is given from the main board 31 to the winning ball board 37. For example, when the winning ball detection switch 99 is turned on in response to the start port switch 17 being turned on, “6” is output to the winning ball number signal, and in response to the turning on of the count switch 23 or the V count switch 22, winning ball detection is performed. When the switch 99 is turned on, “15” is output as the prize ball number signal. Then, if the winning ball detection switch 99 is turned on when those switches are not turned on, “10” is output as the winning ball number signal.

  FIG. 4 is a block diagram illustrating an example of a circuit configuration in the main board (main board) 31. FIG. 2 also shows a prize ball board 37, a lamp control board 35, a sound control board 70, a display control board 80, a launch control board 91, and the like. The main circuit board 31 has a basic circuit 53 for controlling the pachinko gaming machine 1 in accordance with a game control program, and a switch circuit for supplying signals to the basic circuit 53 from the gate switch 12, the start port switch 17, the V count switch 22 and the count switch 23. 58, a solenoid circuit 59 for driving the solenoid 16 for opening / closing the variable winning ball apparatus 15 and the solenoid 21 for opening / closing the opening / closing plate 20 in accordance with a command from the basic circuit 53, and turning on and off the start memory display 18. According to the data supplied from the lamp / LED circuit 60 for driving the variable display 10 by 7 segment LED and blinking the decoration lamp 25 and the data provided from the basic circuit 53, the jackpot information indicating the occurrence of the jackpot, the image of the image display unit 9 Effective start information indicating the number of start winning balls used to start display The probability variation information indicating that the probability change occurs and an information output circuit 64 for outputting to the host computer such as a hall management computer.

  The basic circuit 53 includes a ROM 54 that stores a game control program and the like, a RAM 55 that is used as a work memory, a CPU 56 that performs a control operation according to a control program, and an I / O port unit 57. Note that the ROM 54 and RAM 55 may be built in the CPU 56.

  An initial reset circuit 65 for resetting the basic circuit 53 when the power is turned on is applied to the main board 31, and a reset pulse is given to the basic circuit 53 periodically (for example, every 2 ms) to start a game control program from the top again. A periodic reset circuit 66 for execution and an address decoding circuit for decoding an address signal given from the basic circuit 53 and outputting a signal for selecting any I / O port of the I / O port unit 57 67.

  Furthermore, the main board 31 is also equipped with an oscillation circuit 75, a 16-bit counter 76, and a random number determination register 77 that constitute external random number generation means for generating random numbers at high speed.

Embodiment 1 FIG.
FIG. 5 is a block diagram showing the oscillation circuit 75, 16-bit counter 76 and random number determination register 77 together with the CPU 56. In this embodiment, the oscillation circuit 75 generates a clock signal at 20 MHz. A clock signal from the oscillation circuit 75 is input to the 16-bit counter 76. The 16-bit counter 76 is configured, for example, by connecting four 4-bit counters (here, 74HC161) 76a to 76d in series. That is, the clock signal from the oscillation circuit 75 is input to the clock input terminal of the 4-bit counter 76a, and the carry signal of the 4-bit counter 76a is input to the clock input terminal of the 4-bit counter 76b. The carry signal of the 4-bit counter 76b is input to the clock input terminal of the 4-bit counter 76c, and the carry signal of the 4-bit counter 76c is input to the clock input terminal of the 4-bit counter 76d. Accordingly, the outputs of the four 4-bit counters 76a to 76d are 16-bit counter outputs.

  In this example, a D flip-flop (74HC574) having two eight circuits is used as the latch circuits 77a and 77b constituting the random number determination register 77. The latch circuits 77a and 77b receive the counter output of the 16-bit counter 76, and latch the counter output when a latch signal is input. In the example shown in FIG. 5, the latch signal is output from the CPU 56. Then, the latched 16-bit value is output to the CPU 56 in response to the read signal (RD). The outputs of the latch circuits 77a and 77b are input to the CPU 56 via the bus of the CPU 56. The output of the start port switch 17 is connected to the interrupt input terminal of the CPU 56. When the output of the start port switch 17 is turned on, the interrupt process is started. The output of the start port switch 17 is also input to the CPU 56 via the switch circuit 58 and the I / O port 57 as shown in FIG.

  Since the oscillation frequency of the oscillation circuit 75 is 20 MHz, one clock is generated in 0.05 μs. The 16-bit counter 76 outputs a value in the range of 0 to 65535. Therefore, the random number cycle is 0.05 μs × 65535 = 3.2768 ms.

Next, the operation will be described.
FIG. 6 is a flowchart showing the operation of the basic circuit 53 on the main board 31. As described above, this processing is started, for example, every 2 ms by a reset pulse generated by the periodic reset circuit 66. When the basic circuit 53 is activated, the basic circuit 53 first performs a stack setting process for setting a designated address of the stack pointer (step S1). Next, initialization processing is performed (step S2). In the initialization process, the basic circuit 53 determines whether or not an error is included in the RAM 55. If the error is included, the basic circuit 53 performs a process such as initializing the RAM 55. And after performing the process which sets the command code sent to the display control board 80 to the predetermined area | region of RAM55 (step S3), the process which outputs a command code as display control data is performed (step S4).

  Next, processing for transmitting a predetermined command for generating sound and controlling LED lighting is performed on the lamp control board 35 and the sound control board 70, and the jackpot information is started to the hall management computer via the information output circuit 64. Processing for transmitting data such as information and probability variation information is performed (data output processing: step S5). Further, various abnormality diagnosis processes are performed by the self-diagnosis function provided in the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error process: step S6).

Next, a process of updating each counter indicating each determination random number used for game control is performed (step S7). In step S7, the basic circuit 53 counts up (adds 1) the jackpot symbol determination random number (random 3) as the determination random number.
FIG. 7 is an explanatory diagram showing each random number. Each random number is used as follows.
(1) Random 1: Decide whether or not to generate a big hit (for big hit judgment)
(2) Random 2-1-2-3: For left / right centered symbol determination (3) Random 3: Determines the symbol combination at the time of jackpot (for jackpot symbol determination = for specific symbol determination)
(4) Random 4: Decide whether or not to reach when falling off (for reach determination)
(5) Random 5: Reach type is determined (for reaching operation determination)

In order to enhance the game effect, random numbers other than the random numbers (1) to (5) are also used. In addition, in order to enhance the gaming effect, the variable display unit 9 also displays images other than symbols, such as a background or a character that performs a predetermined movement.
In step S7, the basic circuit 53 counts up (1) the random number for jackpot symbol determination of (3). The big hit determination random number in (1) is also a determination random number, but the big hit determination random number is not updated in the main process.

  Next, the basic circuit 53 performs a special symbol process (step S8). In the special symbol process control, corresponding processing is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state. Also, normal symbol process processing is performed (step S9). In the normal symbol process, the corresponding process is selected and executed in accordance with the normal symbol process flag for controlling the variable display 10 using the 7-segment LED in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state. Further, the basic circuit 53 inputs the states of the gate switch 12, the start port switch 17, and the count switch 23 through the switch circuit 58, and determines whether or not each winning port or winning device has been won (step S10). .

  The basic circuit 53 further performs a process of updating the display random number (step S11). That is, (2) random number for determining symbols, (4) random number for reach determination, and (5) random number for reach operation (1 addition) are counted up. However, the random 2-2 is counted up when the carry of the random 2-1 occurs, that is, when the value of the random 2-1 becomes “15” and is returned to “0”. Random 2-3 is counted up when a carry of random 2-2 occurs, that is, when the value of random 2-2 becomes “15” and returns to “0”.

  The basic circuit 53 performs signal processing with the prize ball substrate 37 (step S12). That is, when a predetermined condition is satisfied, a prize ball number signal is output to the prize ball substrate 37. The prize ball control CPU mounted on the prize ball substrate 37 drives the ball payout device 97 according to the prize ball number signal. Thereafter, the basic circuit 53 repeats the display random number update process in step S13 until the next reset pulse is given from the periodic reset circuit 66.

  FIG. 8 is a flowchart showing an interrupt process of the CPU 56 activated by an interrupt based on the start port switch 17 being turned on. When the start port switch 17 is turned on, an interrupt process is started. In the interrupt process, the CPU 56 first outputs a latch pulse to the random number determination register 77 (step S21). Then, the random number determination register 77 latches the output of the 16-bit counter 76 at that time. The CPU 56 inputs the counter value latched in the random number determination register 77 (step S22). Then, the CPU 56 stores the input value in the random 1 storage area (step S23). The random 1 storage area is a predetermined area in the RAM 55.

  FIG. 9 is a timing chart showing an example of the relationship between the normal process (main process) of the CPU 56 activated by the periodic reset signal and the interrupt process based on the start-up switch 17 being turned on. As shown in FIG. 9, the normal processing of the CPU 56 is restarted every 2 ms. However, since the start-up switch 17 is turned on based on the winning of the hit ball in the game by the player, the 2 ms cycle is completely different. Asynchronous. The 20 MHz clock signal that drives the 16-bit counter 76 that generates a counter value that is based on random 1 is also completely asynchronous with the 2 ms period. Therefore, if the count value of the 16-bit counter 76 is extracted as random 1 (a big hit determination random number) based on the start switch 17 being turned on, a random 1 value that is not synchronized with the 2 ms cycle can be obtained.

  Then, even if the signal output from the main board 31 is observed outside the main board 31, the period of random 1 cannot be known. That is, it becomes impossible to observe a signal output from the main board 31 and give a signal that illegally generates a big hit to the main board 31.

  Next, a method for determining a symbol that is variably displayed on the image display unit 9 based on a winning (start winning) in the start winning opening 14 will be described with reference to the flowcharts of FIGS. FIG. 10 shows a process for determining that the hit ball has won the start winning opening 14, FIG. 11 shows a process for determining a symbol, and FIG. 12 is a flowchart showing a process for determining a big hit. 11 and 12 is executed in the special symbol process (step S8) in the main process shown in FIG.

  When the hit ball wins the start winning opening 14 provided in the game board 6, the start opening switch 17 is turned on. When the start port switch 17 is turned on and off, chattering (flapping of the on waveform and the off waveform) occurs. In addition, noise may get on the cable from the start port switch 17 to the main board 31. Therefore, if it is immediately detected whether the start port switch 17 is turned on, a detection error may occur. Therefore, in this embodiment, as a countermeasure against chattering and noise, the CPU 56 recognizes that the start port switch 17 has been turned on when detecting that it has been turned on twice consecutively. Since the process shown in FIG. 10 is executed once every 2 ms, the CPU 56 recognizes that the start port switch 17 is turned on when the start port switch 17 outputs an ON signal continuously for at least 2 ms. Note that in a gaming machine having a long chattering period, it may be recognized that the start port switch 17 is turned on when it is detected that the turn-on is continuously performed three times or more.

  Further, in the process shown in FIG. 10, chattering countermeasures and noise countermeasures are taken, but in the interrupt process shown in FIG. 8, chattering countermeasures and noise countermeasures are not taken. Therefore, for example, due to the flickering of the signal when the start port switch 17 is turned on, the interrupt process may be started many times when the start port switch 17 is turned on. However, since the value of the random 1 storage area is used when it is determined by the processing shown in FIG. 10 that the start port switch 17 is reliably turned on (step S47), the CPU 56 detects the start prize at the time. The random number value acquired by the immediately preceding interrupt process is stored in the random value storage area.

  In the switch process of step S10, the CPU 56 of the basic circuit 53 detects that the start port switch 17 is turned on via the switch circuit 58 and the I / O port 57 as shown in FIG. 10 (step S41). It is confirmed whether or not the on flag is set (step S42). The switch-on flag is a flag that is set when the first on-state is detected. Therefore, when it is detected that the start port switch 17 is turned on and the switch-on flag is not set, the CPU 56 sets the switch-on flag (step S43).

  When it is detected that the start port switch 17 is turned on and the switch on flag is set, the CPU 56 resets the switch on flag (step S44), and whether or not the start winning memory number has reached the start memory upper limit value. Confirm (step S45). If the starting winning memory number does not reach the starting memory upper limit value, the starting winning memory number is increased by 1 (step S46). In this embodiment, the starting storage upper limit value = 4.

And the value stored in the random 1 storage area in the random number storage area provided corresponding to each start winning storage number n (n = 1, 2, 3,..., Start storage upper limit value). Is stored (step S47). Note that if the start winning memory number has reached the start memory upper limit value, the processing of steps S46 to S47 is not performed.
Further, in the switch process in step S10, a detection process for switches other than the start port switch 17 is also performed.

The basic circuit 53 performs the processing shown in the flowchart of FIG. 11 when the variable display on the image display unit 9 can be started.
First, the value of the start winning memory number is confirmed (step S50). If the starting winning memory number is not 0, the value stored in the random number value storage area corresponding to the starting winning memory number = 1 is read (step S51), the value of the starting winning memory number is decreased by 1, and each The value in the random value storage area is shifted (step S52). That is, the value stored in the random number value storage area corresponding to the starting winning memory number = n (n = 2, 3,...) Is stored in the random number value storing area corresponding to the starting winning memory number = n−1. Store.

  Then, the basic circuit 53 determines the winning / losing based on the value read in step S51, that is, the extracted value of the jackpot determination random number (step S53). In this embodiment, the jackpot determination random number takes a value in the range of 0 to 65535. Then, as shown in FIG. 12, when the probability is low (when a probability variation flag described later is not set), for example, when the value is one of 188 predetermined values, ", And if it is any other value, it is determined to be" out of range ". At the time of high probability, for example, when the value is any of 9440 values determined in advance, it is determined as “big hit”, and when it is other than that value, it is determined as “loss”.

  Since the jackpot determination random number takes a value in the range of 0 to 65535, and 188 of them are winning values (values determined as “big hit”), in this example, the jackpot probability at low probability is 188 / 65536 = 1 / 348.60. Moreover, the jackpot probability at the time of high probability is 940/65536 = 1 / 69.19.

  When it is determined that the game is a big hit, the basic circuit 53 determines a stop symbol based on the value of the special symbol determination random number (random 3). Here, if the limiter is not operating, the stop symbol is determined from the table including all symbols (steps S54 and S55). When the limiter is operating, a stop symbol is determined from a table that does not include a special symbol (probability variation symbol) in which probability variation is performed (steps S54 and S56). The limiter is intended to limit the occurrence of big hits due to the probability variation pattern, that is, the continuous high probability state. For example, when the high probability state continues four times, the limiter is activated. Therefore, in the limiter operating state, a stop symbol is determined from a table that does not include a special symbol for which probability variation is performed.

  Further, the basic circuit sets a probability variation flag if the determined symbol is a probability variation symbol, and resets the probability variation flag otherwise (steps S71, S72, S73). Then, the reach type is determined according to the value of random 5 (step S74), and whether or not to make a big hit, the symbol and the reach type in the case of the big win are set in a predetermined storage area (step S75). The storage area is provided in the RAM 55 in the basic circuit 53.

  If it is determined in step S53 that there is a divergence, the basic circuit 53 determines whether or not to reach (step S59). For example, when the value of the reach determination random number shown in FIG. 7 is any one of “0” to “104”, the reach is determined. When it is determined to reach, the basic circuit determines a stop symbol. In this embodiment, the left and right symbols are determined according to the value of random 2-1 (step S60). Further, the medium symbol is determined according to the value of random 2-2 (step S61). Here, when the determined middle symbol matches the left and right symbols, the symbol corresponding to the value obtained by adding 1 to the random number value corresponding to the middle symbol is set as the determined symbol of the middle symbol so as not to match the jackpot symbol To do.

  Further, the basic circuit determines the reach type according to the value of random 5 (step S62). Then, “reach”, reach design, and reach type are set in a predetermined storage area (step S63). If the lottery result in step S59 is out of place, the predetermined storage area is set to be out (step S64).

  As described above, in this embodiment, the value of the external random number that circulates between 0 and 65535 without synchronizing with the periodic reset interval (2 ms) given to the CPU 56 in the basic circuit 53 is the periodic reset interval. It is latched by a start winning that occurs asynchronously, and the latched value is used as the extracted jackpot determination random number.

  Then, even if various signals output from the main board 31 synchronized with the start timing of 2 ms are observed, the extraction timing of the big hit determination random number cannot be estimated. Therefore, a signal for illegally generating a big hit cannot be given to the main board 31 from the outside of the main board 31.

  In this embodiment, the count value of the 16-bit counter 76 is fetched in the interrupt process, and whether or not the start winning is determined is determined by the switch process (step S10) in the main process. You may make it perform to determination whether it was a start winning prize. In that case, in the interruption process, measures for chattering and noise are taken when it is determined whether or not a start win has been won. For example, if the ON state is confirmed several times continuously, it is determined that there has been a start prize. In such a configuration, when the start port switch 17 is turned on while the main process is being executed, the CPU 56 performs a switch process including a chattering countermeasure, a noise countermeasure, and a high-speed external random number latch process. Prioritized execution. In such a configuration, the difference between the start winning detection time and the random number acquisition timing is further shortened.

Embodiment 2. FIG.
In the first embodiment, the signal from the start port switch 17 is connected to the interrupt terminal of the CPU 56 together with the I / O port 57, and the external random number is latched by the interrupt process of the CPU 56. Instead, the external random number may be latched. FIG. 13 is a block diagram showing the oscillation circuit 75, the 16-bit counter 76, and the random number determination register 77 for performing such processing together with the CPU 56. In this embodiment, the external random number is latched based on the start-up switch 17 being turned on, but unlike the first embodiment, the CPU 56 turns on the start-up switch 17 for latching the external random number. This is recognized using the state of the start port switch 17 input via the / O port 57.

  FIG. 14 is a flowchart showing the main processing of the basic circuit 53 in this embodiment. In this case, in the main process that is restarted every 2 ms, the start port switch processes (steps S15a, S15b, and S15c) are executed at a plurality of locations (three locations in this example).

  FIG. 15 is a flowchart showing the start port switch process (steps S15a, S15b, S15c). When detecting that the start port switch 17 is turned on via the switch circuit 58 and the I / O port 57 (step S81), the CPU 56 checks whether or not the switch-on counter is 10 (step S82). The switch-on counter is a counter for counting the number of continuous on detections of the start port switch 17. Therefore, when it is detected that the start port switch 17 is turned on and the switch-on counter has not reached 10, the CPU 56 increments the switch-on counter by 1 (step S83).

  If the switch-on counter is 10, the switch-on counter is cleared (step S84), and a latch pulse is output to the random number determination register 77 (step S85). Then, the CPU 56 inputs the counter value latched in the random number determination register 77 (step S86), and stores the input value in the random 1 storage area (step S87). Further, the start port on flag is set (step S88).

  As described above, when it is detected that the start port switch 17 is turned on ten times consecutively, the CPU 56 latches the count value of the 16-bit counter 76 and determines that the start port switch 17 is turned on without fail. Set the on flag. In this embodiment, since the start port switch process (steps S15a, S15b, S15c) is executed three times during one main process, the engine is started over (10 ÷ 3) × 2 ms, that is, over 6 ms. It is detected that the mouth switch 17 is definitely turned on.

  In this embodiment, the number of continuous times is 10. However, the number of continuous times is set in accordance with the chattering characteristics of the start port switch 17 of the gaming machine to which it is applied. In this embodiment, the start port switch process is executed three times during one main process, but the number of start port switch processes is not limited to three.

  FIG. 16 is a flowchart showing the jackpot determination random number extraction processing corresponding to the hitting winning of the hit ball executed in the switch processing of step S10 in this embodiment. As shown in FIG. 16, when detecting that the start port switch-on flag has been set (step S41a), the CPU 56 of the basic circuit 53 resets the start port switch-on flag (step S48), and also stores the number of start winning prizes stored. It is confirmed whether or not the start memory upper limit value has been reached (step S45). If the starting winning memory number does not reach the starting memory upper limit value, the starting winning memory number is increased by 1 (step S46). In this embodiment, the starting storage upper limit value = 4.

And the value stored in the random 1 storage area in the random value storage area provided corresponding to each start winning memory number n (n = 1, 2, 3,..., Start memory upper limit value). Is stored (step S47). Note that if the start winning memory number has reached the start memory upper limit value, the processing of steps S46 to S47 is not performed.
Further, in the switch process in step S10, a detection process for switches other than the start port switch 17 is also performed.

  Thereafter, when the CPU 56 is ready to start variable display on the image display unit 9, the CPU 56 performs the process shown in the flowchart of FIG. 11 in the special symbol process of step S8.

  As described above, in this embodiment, since the plurality of start port switch processes (steps S15a, S15b, and S15c) are performed during the main process, it is determined that the start port switch 17 is turned on reliably. Sometimes, the jackpot determination random number value generated by the external random number generating means that counts up at high speed is extracted.

  The start-up switch 17 is turned on completely asynchronously with the 2 ms cycle of the main process. In this embodiment, random 1 (a big hit determination random number) is extracted based on the start-up switch 17 being turned on. Therefore, random 1 that is not synchronized with the 2 ms period can be obtained.

  In this embodiment, the count value of the 16-bit counter 76 is latched when it is determined that the start port switch 17 has been reliably turned on, so that the random value at the time when the CPU 56 detects the start winning is not random. Stored in the numeric storage area. That is, there is no difference between the start winning detection time and the random number acquisition timing.

  However, if a certain amount of deviation is allowed between the start winning detection time and the random number acquisition timing, as in the case of the first embodiment, immediately after the start port switch 17 indicates the on state, The count value of the bit counter 76 may be input and stored in the random 1 storage area. In such a configuration, in the plurality of start port switch processes (steps S15a, S15b, and S15c) during the main process, the switch-on counter is not used. The count value of the 16-bit counter 76 is input via 77 and stored in the random 1 storage area.

  Then, instead of the process shown in FIG. 16, the process shown in FIG. 10 is executed. In such a configuration, the count value of the 16-bit counter 76 is always changed when the start port switch 17 indicates the ON state in a plurality of start port switch processes (steps S15a, S15b, S15c) during the main process. Since it is input, the same processing as in the first embodiment is performed without using the interrupt processing as in the first embodiment. Therefore, with this configuration, the stored value of the random 1 storage area can be updated at any time without depending on the interrupt process. Therefore, the interrupt process is already used as another process, or the interrupt process is performed for some reason. Useful when not available.

Embodiment 3 FIG.
FIG. 17 is a block diagram illustrating the oscillation circuit 75, the 16-bit counter 76, and the random number determination register 77 according to the third embodiment together with the CPU 56. As shown in FIG. 17, in this embodiment, the output of the start port switch 17 is also connected to the latch input of the random number determination register 77, and when the start port switch 17 is turned on, the count value of the 16-bit counter 76 is changed to a random number. It is latched in the confirmation register 77.

  In this embodiment, the main process is executed as shown in FIG. Then, in the switch process in step S10, the process shown in the flowchart of FIG. That is, when the CPU 56 of the basic circuit 53 detects that the start port switch 17 is turned on via the switch circuit 58 and the I / O port 57 (step S41), it confirms whether or not the switch-on flag is set (step S41). Step S42). When it is detected that the start port switch 17 is turned on and the switch-on flag is not set, the CPU 56 sets the switch-on flag (step S43).

  When it is detected that the start port switch 17 is turned on and the switch on flag is set, the CPU 56 resets the switch on flag (step S44), and whether or not the start winning memory number has reached the start memory upper limit value. Confirm (step S45). If the starting winning memory number does not reach the starting memory upper limit value, the starting winning memory number is increased by 1 (step S46). In this embodiment, the starting storage upper limit value = 4.

Then, the CPU 56 inputs the counter value latched in the random number determination register 77 (step S22). Further, the CPU 56 stores the input value in a random value storage area provided corresponding to each start winning memory number n (n = 1, 2, 3,..., Start memory upper limit value) ( Step S47a). Note that if the start winning memory number has reached the start memory upper limit value, the processing of steps S46 to S47a is not performed.
Further, in the switch process in step S10, a detection process for switches other than the start port switch 17 is also performed.
Thereafter, when the CPU 56 is ready to start variable display on the image display unit 9, the CPU 56 performs the process shown in the flowchart of FIG. 11 in the special symbol process of step S8.

  As described above, in this embodiment, the output of the start port switch 17 is input to the I / O port 57 and also input to the random number determination register 77 as a latch signal. Therefore, the random number determination register 77 latches the count value of the 16-bit counter 76 at any time based on the output of the start port switch 17. When the CPU 56 determines that the output of the start port switch 17 input via the I / O port 57 is on, the counter value latched in the random number determination register 77 is input. Therefore, there is no difference between the start winning detection time and the random number acquisition timing. In addition, since the latch in the random number determination register 77 is performed by hardware, the burden on the basic circuit 53 for extracting the big hit determination random number is reduced.

  Also in this embodiment, the external random number that circulates between 0 and 65535 without synchronizing with the periodic reset interval (2 ms) given to the CPU 56 in the basic circuit 53 is generated asynchronously with the periodic reset interval. The winning value is latched, and the latched value is set as the extracted jackpot determination random number. Therefore, even if various signals output from the main board 31 synchronized with the activation timing of 2 ms are observed, it is impossible to estimate the extraction timing of the big hit determination random number. Therefore, a signal for illegally generating a big hit cannot be given to the main board 31 from the outside of the main board 31.

  Note that in the gaming machines of the above-described embodiments, that is, the pachinko gaming machine shown in the front view of FIG. 1, a special symbol that is variably displayed on the image display unit 9 based on the start winning prize has a predetermined symbol. The first type pachinko gaming machine that can be given a predetermined game value to a player when it is a combination of the above, but if there is a prize in a predetermined area of the electric game that is released based on the start prize, the predetermined game value When there is a prize for a predetermined electric combination that is released when a combination of a predetermined symbol and a stop symbol of a symbol variably displayed based on a start winning prize is granted. The present invention can also be applied to a third type pachinko gaming machine in which a predetermined right is generated or continues.

It is the front view which looked at the pachinko game machine from the front. It is a block diagram which shows an example of the circuit structure in a main board | substrate, and a peripheral board | substrate. It is a block diagram which shows the principal part among the peripheral circuits of CPU. It is a flowchart which shows operation | movement of the basic circuit in a main board | substrate. It is a block diagram which shows the structure of the external random number generation means in 1st Embodiment. It is a flowchart which shows the main process of a basic circuit. It is explanatory drawing which shows each random number. It is a flowchart which shows an interruption process. It is a timing diagram which shows an example of the relationship between a main process and an interruption process. It is a flowchart which shows the process which determines that the hit ball in 1st Embodiment won the start winning opening. It is a flowchart which shows the process which determines a symbol. It is a flowchart which shows the process of jackpot determination. It is a block diagram which shows the structure of the external random number generation means in 2nd Embodiment. It is a flowchart which shows the main process in 2nd Embodiment. It is a flowchart which shows a starting port switch check process. It is a flowchart which shows the process which determines that the hit ball in 2nd Embodiment won the start winning opening. It is a block diagram which shows the structure of the external random number generation means in 3rd Embodiment. It is a flowchart which shows the process which determines that the hit ball in 3rd Embodiment won the start winning opening.

Explanation of symbols

8 Variable display device 31 Main board 53 Basic circuit 56 CPU
75 Oscillator circuit 76 16-bit counter 77 Random number determination register

Claims (2)

A special game is played based on the fact that the start switch is turned on when a game medium is awarded to a specific winning section, and a predetermined game value can be given to the player based on the result of the special game being in a predetermined mode. A gaming machine
Game control having an input port for executing a periodic process including a switch determination process for determining whether or not the starter switch is turned on at a predetermined interval in accordance with a game control program, and to which a detection signal from the starter switch is input Means,
An external counter which is provided separately from the game control means and whose numerical value is updated at an interval shorter than the predetermined interval;
A latch circuit that is provided separately from the game control means and latches a numerical value updated by the external counter;
The external counter has a configuration in which a plurality of multi-bit counters are connected in series, and an external clock signal is input to a clock input terminal of a first-stage multi-bit counter among the plurality of multi-bit counters, The carry signal of the preceding multi-bit counter is input to the clock input terminal of the multi-bit counter other than the first stage of the bit counter,
The detection signal from the start port switch is branched and input to the latch circuit and the input port of the game control means,
The latch circuit latches a numerical value updated by the external counter based on the input of the detection signal from the start port switch,
The game control means includes
In the switch determination process executed in the periodic process, it is determined every predetermined period whether or not the detection signal from the start port switch is input to the input port, and the detection signal is input to the input port a predetermined number of times. When it is determined that it has been input, it is determined that the start switch has been turned on,
When it is determined that the start opening switch is surely turned on, it is determined whether or not there is an empty start winning memory,
When it is determined that there is a vacancy in the start winning memory, the numerical value latched by the latch circuit is read from the latch circuit,
A gaming machine, wherein a lottery process for determining whether or not the result of the special game is in the predetermined mode is executed using a numerical value read from the latch circuit. The frequency of the clock signal is set so that the time required for updating all the numerical values within the update range by the external counter is an asynchronous time that is not an integral multiple of the predetermined interval.
The gaming machine according to claim 1.

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