JP4672290B2 - Circuit board, package board manufacturing method, and package board - Google Patents

Description

The present invention relates to a circuit board, a method for manufacturing a package substrate, and a package substrate , and more particularly to reduce the warpage of the substrate due to thinning that occurs in the substrate manufacturing stage or the warpage of the substrate due to heat treatment accompanying element mounting. The present invention relates to a circuit board having a characteristic configuration, a method for manufacturing a package board, and a package board .

  In recent years, as electronic components to be mounted on a substrate are highly integrated or densified, it is also necessary to increase the density of wiring provided on the mounting substrate. Have been developed (see, for example, Patent Document 1 or Patent Document 2).

Here, with reference to FIG. 12 and FIG. 13, an example of the manufacturing process of the conventional buildup board | substrate is demonstrated.
See FIG.
FIG. 12 is a flowchart of a conventional build-up board manufacturing process.
a. A core substrate made of BT resin or the like for forming a plurality of multilayer circuit boards is introduced, and then
b. After forming through vias in the core substrate, predetermined first wiring patterns (L ₃ , L ₄ ) are formed on both surfaces of the core substrate. Then
c. After forming the first insulating layer on both sides, predetermined vias (V ₃ , V ₄ ) are formed. D. Forming a second wiring pattern (L ₂ , L ₅ ) on the first insulating layer;
e. After forming the second insulating layer on both surfaces, predetermined vias (V ₂ , V ₅ ) are formed. F. Third wiring patterns (L ₁ , L ₆ ) are formed on the second insulating layer.
In this case, the first wiring pattern (L ₃ , L ₄ ) and the third wiring pattern (L ₁ , L ₆ ) are, for example, signal wiring, and the second wiring pattern (L ₂ , L ₅ ) is a power wiring and GND wiring.

Then
g. After forming a solder resist around the third wiring pattern (L ₁ , L ₆ ),
h. Gold plating is applied to the surface of the third wiring pattern (L ₁ , L ₆ ). Then
i. After engraving the product number, etc.
j. A pre-solder layer for connecting the electronic component chip is formed on the surface of the third wiring pattern (L ₁ , L ₆ ) subjected to gold plating.

Then
k. After performing the appearance inspection such as warping of the formed build-up board and electrical specific inspection such as disconnection and short circuit,
l. Cut the build-up board into individual multilayer circuit boards,
m. Ship the board to the user.

See FIG.
FIG. 13 is a schematic cross-sectional view of the multilayer circuit board formed as described above, and has a structure in which build-up layers 72 to 75 are formed on both sides of the core board 71.
In this case, the buildup layer 72 includes, for example, a first insulating layer provided with a via V ₃ and a second wiring pattern L ₂ , and the buildup layer 74 includes, for example, a second insulating layer provided with a via V ₂ and and a third wiring pattern L _1.

The user then
n. In a state where the obtained multilayer circuit board is pressed with a warp suppression jig,
o. An electronic component chip such as a semiconductor integrated circuit device is mounted and mounted on the multilayer circuit board using the pre-solder layer formed in step j.

  However, as the speed of electronic devices increases, the wiring length cannot be ignored, and the thickness of the core substrate becomes a problem. Therefore, a coreless substrate that does not use a core has been proposed as the next multilayer circuit board (for example, And Patent Document 3).

See FIG.
FIG. 14 is a schematic cross-sectional view of a conventional coreless substrate having a multilayer thin film structure in which build-up layers 81 to 85 with wiring layers and connection vias are sequentially stacked.

A multilayer circuit board using such a build-up method can form a wiring pattern using semiconductor technology, so that the density of the wiring pattern can be increased. In particular, in the case of a coreless board, a thin layer Since the wiring length can be shortened as the speed increases, it is possible to cope with the higher speed.
Japanese Patent Laid-Open No. 11-233937 Japanese Patent Laid-Open No. 11-289025 Japanese Patent Laid-Open No. 2002-026171

  However, in the case of the coreless substrate as described above, or when the core substrate in the multilayer circuit substrate is made thinner, there is a problem that warpage occurs in the substrate manufacturing stage. There is a problem that it becomes difficult to mount.

  In addition, when a warp suppressing jig is used to prevent warping as in the conventional mounting process, the stress and strain generated in the solder at the C4 portion due to the temperature cycle becomes a problem.

  Therefore, an object of the present invention is to reduce substrate warpage that occurs as the substrate becomes thinner.

FIG. 1 is a diagram illustrating the basic configuration of the present invention. Means for solving the problems in the present invention will be described with reference to FIG.
To solve the above-described problem, the present invention provides a circuit board in which a wiring layer and a ground layer are laminated via an insulating layer, and a first region in which a wiring pattern is formed in the wiring layer (Element mounting substrate part 2) and the ground layer, connected to the ground wiring pattern (7) formed in a region overlapping the first region in the stacking direction, and the ground wiring pattern (7), a ground wiring pattern conductor solid pattern 3 formed on the periphery (7), have a bridge wiring pattern for connecting the conductor solid pattern and the ground wiring pattern, separation between the bridge wiring patterns adjacent separation An insulating layer is provided on the surface of the circuit board on the side of the center layer of the circuit board .
Alternatively, it is a circuit board, in which the wiring pattern (6) is formed (element mounting substrate portion 2), and the wiring pattern (6) is provided in the same layer as the wiring pattern (6). a conductive solid pattern 3 which is connected to the 6), said to have a wiring pattern and the conductor bridge connecting the solid pattern wiring pattern, the separation unit for separation between the bridge wiring patterns adjacent said circuit board An insulating layer is provided on the surface on the center layer side .
In this case, the conductive solid pattern 3 is preferably formed so as to surround the wiring pattern (6) or the ground wiring pattern (7).

As described above, the conductive solid pattern 3 to be removed in the final mounting state is provided so as to surround the element mounting substrate portion 2 , particularly the wiring pattern (6) or the ground wiring pattern (7). 3 can suppress the warpage of the element mounting board portion 2.

Further, it is desirable to connect the conductor solid pattern 3 and a part of the wiring pattern (6) or a part of the ground wiring pattern (7) by the bridge portion 4 integrated with the conductor solid pattern 3, and after the element 5 is mounted. When the conductive solid pattern 3 is removed, only the bridge portion 4 needs to be cut, and the conductive solid pattern 3 can be removed without applying stress to the mounted element.

In this case, the conductor solid pattern 3 may be provided in the same layer as all the wiring layers 6 and 7, or only one of the wiring layers 6 and 7 may be provided. It is desirable to provide them symmetrically. The circuit board in this case is typically a multilayer circuit board having a multilayer wiring structure, and in particular, a coreless board having a multilayer wiring structure.

  In addition, as the wiring layers 6 and 7 that become the conductor solid pattern 3, either the power supply wiring and the ground wiring in which the internal wiring pattern is a solid pattern, or one of the power supply wiring and the ground wiring is used. Therefore, it is possible to efficiently transmit the suppression effect due to the rigidity of the conductor solid pattern 3 to the element mounting board portion 2.

Further, the conductive solid pattern 3 may be provided as a non-uniform pattern around the element mounting substrate unit 2 so as to cancel out the pattern density of the multilayer wiring of the element mounting substrate unit 2. Warpage can be effectively suppressed. For example, the conductor solid pattern 3 may be partially provided around the element mounting substrate unit 2 or may be provided so that the width is nonuniform over the entire periphery of the element mounting substrate unit 2. It ’s good.

The present invention also relates to a package substrate and a method for manufacturing the same, wherein the wiring layer and the ground layer are stacked via an insulating layer, and the wiring pattern is formed in the wiring layer. A ground wiring pattern formed in a region overlapping with the first region in the stacking direction in the ground layer, and a conductor solid connected to the ground wiring pattern and formed around the ground wiring pattern possess a pattern, the bridge wiring pattern for connecting the conductor solid pattern and the ground wiring pattern on the surface of the central layer side of the circuit board of the separation unit for separation between the bridge wiring patterns adjacent an insulating layer The circuit board includes a step of mounting an element in the first region, and a step of cutting out the first region. In this way, after mounting the element 5 on the element mounting board 2, the element mounting board 2 is separated from the surroundings by a method such as cutting the bridge 4, thereby causing a warp due to the influence of thermal strain in the mounting process. Implementation is possible without making it.

The present invention also relates to a package substrate and a method for manufacturing the same, and a conductor connected to the wiring pattern provided in the periphery of the region in the same layer as the wiring pattern and in the same layer as the wiring pattern. and the solid pattern, the have a wiring pattern and the conductor bridge connecting the solid pattern wiring pattern on the surface of the central layer side of the circuit board of the separation unit for separation between the bridge wiring patterns adjacent the insulating layer The circuit board includes a step of mounting an element in the region and a step of cutting out the region.

  According to the present invention, since the conductor solid pattern is formed around the mounting substrate portion, it is possible to suppress the warp that occurs in the substrate manufacturing stage, and finally the mounting structure by cutting off the solid pattern portion after mounting the chip. While being the same, it is possible to suppress substrate warpage in the mounting process.

  The present invention provides a solid copper foil pattern around the actual device mounting board portion after the final mounting process, and connects the copper foil solid pattern and the device mounting board portion with a bridge made of a conductor connected to the wiring pattern. After the element is mounted in the state, the bridge is separated from the element mounting board part.

Here, the manufacturing process of the coreless substrate according to the first embodiment of the present invention will be described with reference to FIG. 2 to FIG. 5. As the manufacturing process of the wiring pattern and the via, etc., the microfabrication used in the semiconductor manufacturing process is described. Apply technology.
See Figure 2
FIG. 2 is a flowchart of the manufacturing process of the coreless substrate according to the first embodiment of the present invention.
a. Put the base substrate as the base, then
b. A first wiring pattern (S ₁ ) made of Cu serving as a signal wiring is formed. At this time, a Cu solid pattern is provided on the periphery of the base substrate, and a Cu solid pattern and the first wiring pattern (S ₁ ) are provided. A Cu bridge for connecting the device mounting substrate portion is simultaneously formed.

Then
c. After forming a first insulating layer made of polyimide resin on the entire surface, a via hole is formed at a predetermined position, and the via hole is filled with Cu to form a via (V ₁ ).
d. A second wiring pattern (G) made of Cu serving as a GND wiring is formed on the first insulating layer. In this case as well, a Cu solid pattern is provided around the base substrate, and the Cu solid pattern and the second wiring pattern are also provided. A Cu bridge for connecting the element mounting substrate portion provided with (G) is simultaneously formed so as to overlap with the previously formed Cu bridge.

Then
e. After forming the second insulating layer made of polyimide resin on the entire surface, a via hole is formed at a predetermined position, and the via hole is filled with Cu to form a via (V ₂ ).
f. A third wiring pattern (S ₂ ) made of Cu serving as a signal wiring is formed on the second insulating layer at the same time as the Cu solid pattern in the peripheral portion and a Cu bridge for connecting both in the same manner as in step d.

Then
g. After a third insulating layer made of polyimide resin is formed on the entire surface, via holes are formed at predetermined positions, and vias (V ₃ ) are formed by filling the via holes with Cu.
h. On the third insulating layer, a fourth wiring pattern (V) made of Cu serving as a power supply wiring is formed simultaneously with a Cu solid pattern in the peripheral portion and a Cu bridge connecting the both in the same manner as in step d.

Then
i. After the fourth insulating layer made of polyimide resin is formed on the entire surface, via holes are formed at predetermined positions, and vias (V ₄ ) are formed by filling the via holes with Cu.
j. On the fourth insulating layer, the fifth wiring pattern (S ₃ ) made of Cu serving as the signal wiring is formed simultaneously with the Cu solid pattern in the peripheral portion and the Cu bridge for connecting both in the same manner as in step d.

  Next, as in the prior art, solder resist formation, gold plating formation, product number marking, pre-solder layer formation, and base substrate peeling are performed.

Then
k. After conducting visual inspections such as warping of the coreless substrate formed and electrical specific inspections such as disconnection and short circuit,
l. Cut the coreless board into individual multilayer circuit boards,
m. Ship the board to the user.

See FIG. 3 to FIG.
3 is an explanatory view of the state of individual piece cutting in step l, FIG. 4 is a plan view of the coreless substrate formed in this way, and FIG. 5 is a schematic cross-sectional view of the coreless substrate. It is. As shown in the figure, the element mounting board portion 20 is connected to the solid pattern portion 40 via the bridge portion 30.

The element mounting substrate unit 20 includes a first wiring pattern (S ₁ ) 21, a first insulating film 22, a second wiring pattern (G) 23, a second insulating film 24, a third wiring pattern (S ₂ ) 25, The third insulating film 26, the fourth wiring pattern (V) 27, the fourth insulating film 28, and the fifth wiring pattern (S ₃ ) 29 are configured.
The vias connecting the wiring layers are not shown.

  The bridge portion 30 includes a first Cu bridge layer 31, a first insulating film 22, a second Cu bridge layer 32, a second insulating film 24, a third Cu bridge layer 33, a third insulating film 26, a fourth Cu bridge layer 34, a first 4 insulating film 28 and fifth Cu bridge layer 35.

  The solid pattern portion 40 includes a first Cu solid pattern layer 41, a first insulating film 22, a second Cu solid pattern layer 42, a second insulating film 24, a third Cu solid pattern layer 43, a third insulating film 26, and a fourth Cu solid. The pattern layer 44, the fourth insulating film 28, and the fifth Cu solid pattern layer 45 are configured.

The user then
n. After mounting and mounting an electronic component chip such as a semiconductor integrated circuit device on the obtained multilayer circuit board using a pre-formed pre-solder layer,
o. The mounting process is completed by cutting the bridge portion and separating the solid pattern portion from the element mounting substrate portion.

Next, with reference to FIG. 6 thru | or FIG. 9, the effect of the coreless board | substrate of Example 1 of this invention is demonstrated.
See FIG.
FIG. 6 is an analysis model of the present invention used for the simulation performed for confirming the effect. The upper diagram is a plan view, and the lower diagram is a sectional view. Here, the thickness of the polyimide resin is 60 μm. A solid Cu power supply wiring 52 having a thickness of 40 μm on the first insulating layer 51, a second insulating layer 53 having a thickness of 60 μm made of polyimide resin, a Cu signal wiring 54 having a thickness of 40 μm, and a polyimide resin The third insulating layer 55 has a five-layer structure with a thickness of 60 μm, and a Cu solid pattern 56 is provided around it. The Cu solid pattern portion 56 is connected to a Cu power supply wiring 52 and a Cu signal wiring 54 via a Cu bridge portion 57. And connected to the system.

The analysis was performed on the assumption that a chip 59 having a thickness of 300 μm was mounted through a solder 58 having a thickness of 100 μm corresponding to the pre-solder layer in the center of the substrate having the five-layer structure.
In the figure, for the sake of simplicity of illustration, a quarter of the whole is shown, and the lacking portion of the Cu signal wiring pattern in the cross-sectional view is a space, but an actual substrate is filled with polyimide resin. It becomes.

See FIG.
FIG. 7 is an analysis model of a conventional example used for a simulation performed for comparison, the upper diagram is a plan view, and the lower diagram is a cross-sectional view. In this case as well, the thickness of the polyimide resin is 60 μm. A solid Cu power supply wiring 62 having a thickness of 40 μm on the first insulating layer 61, a second insulating layer 63 having a thickness of 60 μm made of polyimide resin, a Cu signal wiring 64 having a thickness of 40 μm, and a polyimide resin The analysis was performed on the assumption that a third insulating layer 65 having a thickness of 60 μm was formed, and a chip 67 having a thickness of 300 μm was mounted in the center via a solder 66 having a thickness of 100 μm corresponding to the pre-solder layer.
FIG. 7 also shows a quarter of the whole for the sake of simplicity.

Further, the physical property values of the respective materials employed in the simulation in this case are as shown in Table 1.

See FIG.
FIG. 8 shows the results of simulating warpage due to thermal deformation or the like in the case of performing heat treatment at 150 ° C. → 221 ° C. assuming the soldering process at the time of chip mounting for these models. Shows an analysis model of the present invention, and the following figure shows a conventional analysis model.

  As a result of this simulation, the warpage amount in the analysis model of the conventional example was 0.33435 mm, whereas the warpage amount in the analysis model of the present invention was 0.15578 mm, and the warpage amount was reduced by about 53%. It was confirmed.

Thus, in Example 1 of this invention, since the element mounting board | substrate part is pressed down by the solid pattern part via the bridge | bridging part, the curvature by the deformation | transformation accompanying heat processing can be reduced significantly.
Further, warpage due to deformation caused by stress applied in the manufacturing process can be reduced.

Next, a second embodiment of the present invention will be described with reference to FIG. 9. Since the basic configuration is the same as that of the first embodiment, only a sectional view is shown. / 2 is shown.
See FIG.
The upper diagram of FIG. 9 shows a fifth Cu solid pattern portion 40 that connects the solid pattern portion 40 to the fifth wiring pattern (S ₃ ) 29 that is the uppermost signal wiring and the first wiring pattern (S ₁ ) that is the lowermost signal wiring. In addition to the pattern layer 45 and the first Cu solid pattern layer 41, the bridge portion 30 is composed of the fifth Cu bridge layer 35 and the first Cu bridge layer 31.

  The middle stage diagram shows a second Cu solid pattern layer 42 and a fourth Cu solid pattern that connect the solid pattern portion 40 to the second wiring pattern (G) 23 that is the GND wiring and the fourth wiring pattern (V) 27 that is the power wiring. The bridge portion 30 is constituted by the second Cu bridge layer 32 and the fourth Cu bridge layer 34 while being constituted by the layer 44.

Further, the lower diagram is configured by the third Cu solid pattern layer 43 connected to the third wiring pattern (S ₂ ) 25 which is the central signal wiring, and the bridge portion 30 is configured by the third Cu bridge layer 33. .

  As described above, in the second embodiment, the rigidity of the warp of the substrate can be adjusted to the optimum rigidity by selectively providing the solid pattern layer and the bridge layer.

Next, a third embodiment of the present invention will be described with reference to FIG. 10. Since the basic configuration is the same as that of the first embodiment, only a plan view is shown.
See FIG.
As shown in the figure, a solid pattern portion 40 is selectively provided at a position where the wiring pattern is point-symmetric with respect to the dense pattern dense portion 70 in order to cancel out the deviation of the patterns of the first to third signal wirings. It is a thing.
In this case, the position where the solid pattern portion 40 is provided is not point-symmetric in a strict sense, and the length thereof is appropriately set according to the deviation of the wiring pattern density.

  Thus, in Example 3, it is possible to effectively suppress the warpage of the substrate by selectively providing the solid pattern layer 40 and the bridge layer 30 according to the deviation of the wiring pattern density.

Next, a fourth embodiment of the present invention will be described with reference to FIG. 11. Since the basic configuration is the same as that of the first embodiment, only a plan view is shown.
See FIG.
As shown in the figure, the width of the solid pattern portion 40 at the position where the wiring pattern is point-symmetric with respect to the dense pattern dense portion 70 is selectively selected in order to cancel the pattern deviation of the first to third signal wirings. It is thickened.
Also in this case, the position where the solid pattern portion 40 is thickened is not point-symmetric in a strict sense, and the length thereof is appropriately set according to the deviation of the wiring pattern density.

  Thus, in Example 4, since the width of the solid pattern is changed according to the deviation of the wiring pattern density, it is possible to effectively suppress the warpage of the substrate.

  The embodiments of the present invention have been described above. However, the present invention is not limited to the conditions and configurations described in each embodiment, and various modifications are possible. For example, the substrate described in each embodiment The size of each layer, the thickness of each layer, the number of layers, the number of bridges, and the like are appropriately changed.

  In the second embodiment, the solid pattern portion and the bridge portion are provided symmetrically in the vertical direction. However, the solid pattern portion and the bridge portion may be provided asymmetrically or may be provided in only one layer.

Further, in each of the above-described first embodiments, the element mounting substrate portion and the solid pattern portion are connected by the bridge portion, but the bridge portion is not necessarily required, and the element mounting substrate portion and the solid pattern portion are May be formed so as to be directly connected.
However, there is a disadvantage that the cutting process takes time.

  Further, in each of the above embodiments, the bridge portion is already formed in a bridge shape in each wiring layer forming step, but in the stacking step, it is formed in a solid shape like the solid pattern portion, and all the stacking steps are completed. Then, the bridge portion may be formed by punching out the solid portion.

  In each of the above embodiments, the wiring layer is made of Cu and the insulating layer is made of polyimide. However, the wiring layer is not limited to these materials, and the wiring layer may be made of other good materials such as Ag or Al. A conductor may be used, and another insulating material such as an epoxy resin may be used for the insulating layer.

  In each of the above embodiments, it is assumed that each wiring layer is patterned by etching. However, it may be formed by an electrolytic plating method or an electroless plating method using a plating frame pattern.

  In each of the above-described embodiments, the coreless buildup method is described in which the base substrate is sequentially stacked on the base substrate. However, the coreless buildup method is not necessarily limited to the coreless buildup method. Even when forming a substrate, an insulating thin film made of polyimide resin or the like is provided on one surface of a base substrate having a large opening on the inside, and this is used as a substitute for the core layer, and a build-up process is performed as in the conventional example. May be used to form a coreless substrate.

  The present invention is not limited to a coreless substrate, but can be applied to a build-up substrate using a core substrate, and is an effective technique particularly when the core substrate is thinned.

Here, the detailed features of the present invention will be described again with reference to FIG.
Again see Figure 1
(Supplementary Note 1) A part of at least one wiring layer 6, 7 constituting the multilayer wiring of the element mounting substrate 2 is formed around the element mounting substrate 2 and is integrated with the wiring layers 6, 7. A multilayer circuit board provided with a conductive solid pattern 3.
(Additional remark 2) The said conductive solid pattern 3 is connected with a part of said wiring layers 6 and 7 via the bridge | bridging part 4 integrated with the conductive solid pattern 3, The additional description 1 characterized by the above-mentioned. Multilayer circuit board.
(Additional remark 3) The multilayer circuit board of Additional remark 1 or 2 characterized by providing the said conductor solid pattern 3 symmetrically with respect to the lamination direction of a multilayer wiring structure.
(Additional remark 4) The wiring layers 6 and 7 used as the said conductor solid pattern 3 are any one of a power supply wiring and a ground wiring, or a power supply wiring or a ground wiring. The multilayer circuit board according to any one of the above.
(Supplementary Note 5) The conductive solid pattern 3 is provided as a non-uniform pattern around the element mounting substrate portion 2 so as to offset the pattern density of the multilayer wiring of the element mounting substrate portion 2. The multilayer circuit board according to any one of 1 to 4.
(Supplementary note 6) The multilayer circuit board according to supplementary note 5, wherein the conductor solid pattern 3 is partially provided around the element mounting substrate portion 2.
(Additional remark 7) While providing the said conductor solid pattern 3 in the perimeter of the said element mounting substrate part 2, the width | variety of the said conductor solid pattern 3 was made non-uniform | heterogenous, The multilayer circuit board of Additional remark 5 characterized by the above-mentioned .
(Additional remark 8) After mounting the element 5 in the element mounting board | substrate part 2 of the multilayer circuit board 1 of any one of Additional remarks 1 thru | or 7, the said element mounting board | substrate part 2 is cut off from the circumference | surroundings. .

  As an application example of the present invention, a multilayer wiring flexible substrate is typical, but it can also be applied to other mounting substrates such as an interposer.

It is explanatory drawing of the fundamental structure of this invention. It is a flowchart of the manufacturing process of the coreless board | substrate of Example 1 of this invention. It is explanatory drawing of the condition of the piece cutting of process l. It is a top view of the coreless board | substrate of Example 1 of this invention. It is a schematic sectional drawing of the coreless board | substrate of Example 1 of this invention. It is an analysis model of the present invention used for simulation. It is the analysis model of the prior art example used for simulation. It is explanatory drawing of the simulation result of the curvature by the thermal deformation etc. at the time of performing heat processing. It is a schematic sectional drawing of the coreless board | substrate of Example 2 of this invention. It is a top view of the coreless board | substrate of Example 3 of this invention. It is a top view of the coreless board | substrate of Example 4 of this invention. It is a flowchart of the manufacturing process of the conventional buildup board | substrate. It is a schematic sectional drawing of the conventional multilayer circuit board. It is a schematic sectional drawing of the conventional coreless board | substrate.

Explanation of symbols

1 the multilayer circuit board 2 element mounting board unit 3 conductor solid pattern 4 bridge portions 5 element 6 wiring layer 7 wiring layer 20 element mounting board unit 21 first wiring pattern (S ₁₎
22 1st insulating film 23 2nd wiring pattern (G)
24 Second insulating film 25 Third wiring pattern (S ₂ )
26 3rd insulating film 27 4th wiring pattern (V)
28 Fourth insulating film 29 Fifth wiring pattern (S ₃ )
30 bridge portion 31 first Cu bridge layer 32 second Cu bridge layer 33 third Cu bridge layer 34 fourth Cu bridge layer 35 fifth Cu bridge layer 40 solid pattern portion 41 first Cu solid pattern layer 42 second Cu solid pattern layer 43 third Cu solid pattern layer 44 4th Cu solid pattern layer 45 5th Cu solid pattern layer 50 Element mounting board part 51 1st insulating layer 52 Cu power supply wiring 53 2nd insulating layer 54 Cu signal wiring 55 3rd insulating layer 56 Cu solid pattern part 57 Cu bridge part 58 Solder 59 Chip 60 Element mounting substrate portion 61 First insulating layer 62 Cu power supply wiring 63 Second insulating layer 64 Cu signal wiring 65 Third insulating layer 66 Solder 67 Chip 70 Pattern dense portion 71 Core substrate 72 Buildup layer 73 Buildup layer 74 Build-up layer 75 Build-up layer 8 The build-up layer 82 build-up layer 83 build-up layer 84 build-up layer 85 build-up layer

Claims (10)

A circuit board in which a wiring layer and a ground layer are laminated via an insulating layer,
A first region in which a wiring pattern is formed in the wiring layer;
In the ground layer, a ground wiring pattern formed in a region overlapping with the first region in the stacking direction;
A conductive solid pattern connected to the ground wiring pattern and formed around the ground wiring pattern;
Possess a bridge wiring pattern for connecting the conductor solid pattern and the ground wiring pattern,
A circuit board comprising an insulating layer on a surface on a central layer side of the circuit board of a separation part that separates adjacent bridge wiring patterns .   The circuit board according to claim 1, wherein the conductive solid pattern is formed so as to surround the ground wiring pattern. A region where a wiring pattern is formed; and
A conductor solid pattern connected to the wiring pattern provided in the periphery of the region in the same layer as the wiring pattern;
Wherein possess a wiring pattern and a bridge wiring pattern for connecting the conductor solid pattern, characterized in that the surface of the central layer side of the circuit board of the separation unit for separation between the bridge wiring patterns adjacent an insulating layer A circuit board.   The circuit board according to claim 3, wherein the conductive solid pattern is formed so as to surround the wiring pattern.   5. The circuit board according to claim 1, wherein the circuit board is a multilayer circuit board having a multilayer wiring structure.   The circuit board according to claim 5, wherein the multilayer circuit board is a coreless board. A circuit board in which a wiring layer and a ground layer are stacked via an insulating layer, wherein a first region in which a wiring pattern is formed in the wiring layer, and a stack in the ground layer with respect to the first region A ground wiring pattern formed in a region overlapping in a direction, a conductor solid pattern connected to the ground wiring pattern and formed around the ground wiring pattern, and connecting the ground wiring pattern and the conductor solid pattern. possess a bridge wiring pattern, the circuit board having an insulating layer on the surface of the central layer side of the circuit board of the separation unit for separation between the bridge wiring patterns adjacent the element to the first domain implementation And a process of
A method of manufacturing the package substrate, comprising: cutting out the first region. A circuit board in which a wiring layer and a ground layer are stacked via an insulating layer, wherein a first region in which a wiring pattern is formed in the wiring layer, and a stack in the ground layer with respect to the first region A ground wiring pattern formed in a region overlapping in a direction, a conductor solid pattern connected to the ground wiring pattern and formed around the ground wiring pattern, and connecting the ground wiring pattern and the conductor solid pattern. possess a bridge wiring pattern, the circuit board having an insulating layer on the surface of the central layer side of the circuit board of the separation unit for separation between the bridge wiring patterns adjacent the element to the first domain implementation And a process of
A package substrate manufactured by cutting out the first region. An area in which a wiring pattern is formed, a conductive solid pattern connected to the wiring pattern provided in the periphery of the area in the same layer as the wiring pattern, and the wiring pattern and the conductive solid pattern are connected to each other. It possesses a bridge wiring pattern, the circuit board having an insulating layer on the surface of the central layer side of the circuit board of the separation unit for separating the adjacent said bridge wiring pattern, a step of mounting the element to the region ,
A method of manufacturing the package substrate, comprising: cutting out the region. An area in which a wiring pattern is formed, a conductive solid pattern connected to the wiring pattern provided in the periphery of the area in the same layer as the wiring pattern, and the wiring pattern and the conductive solid pattern are connected to each other. It possesses a bridge wiring pattern, the circuit board having an insulating layer on the surface of the central layer side of the circuit board of the separation unit for separating the adjacent said bridge wiring pattern, a step of mounting the element to the region ,
A package substrate manufactured by cutting the region.

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