JP4658721B2 - Manufacturing method of display device - Google Patents

Description

The present invention relates to a method for manufacturing a flat panel display device , and is particularly suitable for manufacturing a display device such as a liquid crystal panel having a thin film wiring formed using a liquid process such as an ink jet method.

  A so-called active matrix type flat panel display device that controls lighting for each pixel has a large number of switching elements such as thin film transistors (hereinafter described as thin film transistors) and pixel electrodes driven by the thin film transistors. The pixels are arranged in a matrix in rows and columns on one insulating substrate. A plurality of gate wirings (one thin film wiring pattern) for supplying a scanning signal for selecting a plurality of thin film transistors arranged in a matrix for each row and a plurality of thin film transistors connected to the selected gate wirings for supplying display data The data wiring (the other thin film wiring pattern) is arranged so as to intersect in a matrix corresponding to the above rows and columns. A pixel is arranged in each of the intersecting regions of the thin film wiring patterns (gate wiring pattern and data wiring pattern). Some display devices have a thin film wiring pattern necessary for the display method of the display device in addition to the gate wiring and the data wiring.

The above-mentioned gate wiring pattern and data wiring pattern are generally formed by a photolithography ( exposure and development process abbreviated as photolithography) method using a photomask, but in recent years, a liquid process such as an inkjet method has been used. A method for forming the used wiring pattern or the like has been proposed. For example, Non-Patent Document 1 discloses a pattern forming technique using the ink jet method . Further, “Patent Document 1” discloses a film forming technique in which a groove is formed in a bank on an insulating substrate and a thin film material liquid is filled in the groove by an ink jet method to form a thin film.

  In a film forming technique in which a groove is formed on a surface of an insulating substrate by a bank and a wiring material ink (thin film material liquid) is dropped and filled into the groove by an ink jet method to form a thin film, the bank applies a photoresist and a photomask. It is formed by the exposure / development process used. The surface of this bank is liquid repellent and the bottom of the groove is lyophilic. Patent Document 2 describes a method for calculating the amount of wiring material ink to be incorporated from the bank shape and contact angle.

And patent document 3 discloses the method of discharging a resist pattern to the main surface of a glass substrate by the inkjet method, exposing from the back surface of a substrate, and forming a channel protective layer.
“Nikkei Electronics” (issued 2002.6.17, pages 67 to 78) JP 2000-353594 A JP 2002-131529 A JP 2004-241769 A

  Here, a liquid crystal display device that is a typical example of the flat display device will be described as an example. A liquid crystal display device is configured by sandwiching a liquid crystal between a pair of substrates. This one substrate (first substrate) is generally called a thin film transistor substrate (TFT substrate) because a thin film transistor is widely adopted as the pixel selection element. The other substrate (second substrate) is generally called a color filter substrate (CF substrate) because a color filter is formed.

  FIG. 4 is a diagram for explaining a configuration example of one pixel formed on the TFT substrate constituting the flat panel display device. 4A shows a plane, and FIG. 4B shows a cross section taken along the line A-A ′ of FIG. On the TFT substrate 1 which is preferably made of glass as the first substrate, a gate electrode 2 protruding from the gate wiring 20, a gate insulating film 3, a silicon semiconductor layer 4, a contact layer 5, a source electrode (drain electrode) 61, A stacked structure of the drain electrode (source electrode) 62, the protective layer 7, and the pixel electrode 8 is formed. A source electrode (drain electrode) 61 of the thin film transistor TFT protrudes from the data wiring 60 to the pixel region, and a pixel electrode 8 is connected to the drain electrode (source electrode) 62. The pixel electrode 8 on the protective layer 7 is connected to a drain electrode (source electrode) 62 through a through hole 11 provided in the protective layer 7. In this configuration, the auxiliary capacitance line 50 is formed on the TFT substrate 1.

  The pixel region is a portion surrounded by a pair of data lines 60 and 60 and a pair of gate lines 20 and 20. The thin film transistor TFT connected to the selected gate line 20 applies display data supplied from the data line 60 to the pixel electrode 8 and forms an electric field for display between the counter electrode on the other substrate (not shown). To do. The orientation of liquid crystal molecules is changed according to the formed electric field, and the amount of light transmitted is controlled.

  5 and 6 are diagrams for explaining a conventional manufacturing process of a thin film transistor substrate. In FIG. 5, three metal layers (gate metals 1, 2 and 3) for gate wiring and gate electrodes (and auxiliary capacitance lines) are sequentially formed in processes 1 to 5. A resist is applied thereon (process 6), and the first exposure and development for forming a gate pattern are performed using a first mask (photomask) (process 7).

After resist development, the exposed gate metal is dry-etched in the order of 3, 2 and 1 (processes 8 to 10). Thereafter, the remaining resist is peeled off (process 11), washed (process 12), and silicon nitride SiN _x for a gate insulating film is formed (process 13). A silicon semiconductor film ( a- Si) is formed on the gate insulating film (process 14), and an n ⁺ semiconductor film (contact layer) is further formed (process 15).

A resist is applied to cover the n ⁺ semiconductor film (process 16), and the second exposure and development for forming a semiconductor island are performed using the second mask (process 17). After developing the resist, dry etching of the n ⁺ semiconductor film and the silicon semiconductor film is sequentially performed (processes 18 and 19), and the resist is removed (process 20).

  Next, cleaning is performed before film formation (process 21), and metal films (denoted as source metals 1, 2, and 3 in FIG. 5) to be data wiring and source electrodes (drain electrodes) are sequentially formed (processes 22 to 24). ). A resist is applied on the source metal (process 25), and the third exposure and development for pattern formation of the data wiring and the source electrode (drain electrode) are performed using the third mask (process 26). ).

After the resist development, the exposed source metals 3, 2, and 1 are sequentially dry etched (processes 27 to 29), and the n ⁺ semiconductor film (contact layer) is etched (process 30). Thereafter, the remaining resist is peeled off (process 31), washed (process 32), and a protective film is formed (process 33).

  Conventionally, after that, resist coating shown in process 34 of FIG. 6 is performed, and a fourth exposure and development for forming a contact hole (through hole) are performed using a fourth mask (process 35). The protective film exposed by this development is dry-etched to form a contact hole reaching the drain electrode (source electrode) (process 36).

  The resist is peeled off and washed (processes 37 and 38), and an ITO film to be a pixel electrode is formed (process 39). At this time, ITO is connected to the drain electrode (source electrode) through the contact hole. A resist is applied to cover the ITO (process 40), and the fifth exposure and development for forming the pixel electrode pattern are performed using the fifth mask (process 41). The ITO exposed by this development is wet etched to form a pixel pattern (process 42). Thereafter, the resist is stripped (process 43). An alignment film is formed on the thin film transistor substrate so as to cover the image electrode, and this is provided with alignment ability by rubbing or the like.

Thus, in the conventional thin film transistor manufacturing process, five exposures and developments are performed using five photomasks. Therefore, the number of manufacturing processes is large and the cost is high. An object of the present invention is to reduce the number of photomask, to reduce the number of manufacturing processes, it is to provide a method of manufacturing a display equipment with reduced costs.

  In the present invention, the process before the contact hole formation shown in FIG. 5 is similarly performed by exposure and development using three masks to form a pixel electrode and connect the drain electrode (source electrode) to the pixel electrode. An ink jet method is used.

  A display device according to the present invention includes a gate wiring and a data wiring on a first substrate, and a gate electrode and a semiconductor layer that are connected to the gate wiring in the vicinity of the intersection of the gate wiring and the data wiring, and A thin film transistor including a source electrode (or drain electrode) and a drain electrode (or source electrode) connected to the data wiring; and a pixel electrode connected to the drain electrode (or source electrode). It is characterized by being composed of ITO connected to a part of the electrode (or source electrode) by inkjet discharge. Note that in a thin film transistor, a drain electrode and a source electrode are alternately switched during operation, and thus are expressed as a source electrode (or drain electrode) and a drain electrode (or source electrode).

The display device manufacturing method of the present invention includes a gate wiring on a first substrate 1, a gate electrode connected to the gate wiring, a gate insulating film, a silicon semiconductor layer (a-Si), an n ⁺ semiconductor film, a data wiring, A thin film transistor processing process for forming a source electrode (or drain electrode) and a drain electrode (or source electrode) connected to the data wiring, and a protective film is formed to cover the entire surface of the first substrate on which the thin film transistor is processed. Protective film formation process, the gate wiring and the gate electrode connected to the gate wiring, the data wiring and the upper layer of the source electrode (or drain electrode) connected to the data wiring, and a part of the drain electrode (or source electrode) A resist discharge process in which a resist is applied to the upper layer except ink by an inkjet, and a portion where the resist is applied The protective film removing process for removing the protective film except the ITO, and discharging the ITO into the region surrounded by the pair of the gate wiring and the pair of the data wiring from which the protective film has been removed by ink jetting the drain electrode ( Or a pixel electrode formation process for forming a pixel electrode connected to a part of the source electrode).

  According to the present invention, the number of photomasks is reduced, the number of manufacturing processes is reduced, and a high-quality display device can be manufactured at low cost.

  Hereinafter, embodiments of a display device and a manufacturing method thereof according to the present invention will be described in detail with reference to the drawings of the examples.

FIG. 1 is a main part view of a thin film transistor substrate for explaining a first embodiment of a manufacturing method of a display device according to the present invention. FIGS. 1 (a), (c), (e), (g), (i) FIGS. 1B, 1D, 1F, 1H, and 1J show the AA ′ cross section of FIG. In FIGS. 1A and 1B, FIGS. 5A and 5B show the process 32 of FIG. 5, that is, the process 30 after dry etching the n + semiconductor film, and then the remaining resist is stripped (process 31). Indicates the state. On the glass substrate 1, a gate electrode 2, a gate insulating film 3, a silicon semiconductor layer (a-Si) 4, an n + semiconductor film 5, a source electrode (drain electrode) 61, and a drain electrode (source electrode) 62 are formed. FIGS. 1C and 1D show a state in which the protective film 7 is formed on the entire surface (process 33) .

In the first embodiment, as shown in FIGS. 1E and 1F, a resist 8 is discharged by ink jet onto a portion where the protective film 7 is left. FIG. 1E shows the outline of the ink droplet immediately after ejection. At this time, the resist is not discharged to the connection portion 62 ′ of the drain electrode (source electrode) 62 connected to the pixel electrode. The resist 8 is also discharged onto the data wiring connected to the source electrode (drain electrode) and the gate wiring connected to the gate electrode. The n + semiconductor film 5 is also removed and exposed to fill the silicon semiconductor layer (a-Si) 4 that forms a channel.

Next, as shown in FIGS. 1G and 1H, the protective film 7 of the connection portion 62 ′ of the drain electrode (source electrode) 62 connected to the pixel electrode which is the portion exposed from the resist 8 is etched. Then, the portion 9 of the drain electrode (source electrode) is exposed (terminal extraction, process 35). FIGS. 1G to 1J show the connecting portion 9. The resist discharged to the data wiring and the gate wiring is cured by exposure from the back surface of the glass substrate to form a bank for forming an electrode film (ITO) for the pixel electrode (process 36). Then, a pixel electrode connected to the drain electrode (source electrode) is formed by forming an electrode film (ITO) for the pixel electrode in the bank (processes 37 and 38). The pixel electrode is formed inside the pixel region by a bank formed by being discharged on the data wiring and the gate wiring. Therefore, there is no need for exposure or development using a mask for patterning the pixel electrodes. FIG. 1 (i) shows a pixel electrode 10 similar to that shown in FIG. 3 (b).

Figure 2 is a diagram illustrating collectively a manufacturing process of the first embodiment, is a manufacturing process diagram subsequent to the process 33 in FIG. After the formation of the protective film in FIG. 5, a resist is applied by inkjet ((process 34), the resist ejection described in ( e ) and ( f ) in FIG. 1). The protective film is etched to expose the terminal portion, that is, the connection portion with the pixel electrode (terminal extraction (process 35), FIG. 1 ( g ), ( h )). A resist other than the resist on the data wiring and the gate wiring is exposed and developed by backside exposure, and a bank is formed (process 36).

ITO is ejected into the bank by inkjet (process 37), dried (temporarily baked) (process 38), the resist is peeled off (process 39), and then baked to form the pixel electrode 10 (process 40 , FIG. 1). (I), (j) ). According to the first embodiment, the number of photomasks is only three as described with reference to FIG. 5, and the number of masks and the number of processes can be reduced.

  As Example 2, the configuration of the display device of the present invention will be described. FIG. 3 is an explanatory diagram of one pixel portion in the thin film transistor substrate constituting the display device according to the present invention. FIG. 3A is a plan view, and FIG. 3B is an enlarged view of the thin film transistor portion of FIG. As in FIG. 4, one pixel is formed in a region surrounded by the pair of gate lines 20 and 20 and the pair of data lines 60 and 60. A thin film transistor TFT is disposed at the intersection of the gate line 20 and the data line 60. The thin film transistor TFT includes a gate electrode 2, a semiconductor layer 4 (contact layer is not shown), a source electrode (drain electrode) 61, and a drain electrode (source electrode) 62. The drain electrode (source electrode) 62 is formed with the portion 9 described above, and the pixel electrode 10 is connected to the thin film transistor TFT at the connecting portion 9.

  Here, the connecting portion 9 shown in FIGS. 3A and 3B is arranged farther from the edge of the gate wiring 20 than the connecting portion 9 shown in FIGS. 4A and 4B. . This is for the following reason. Conventionally, the gate wiring 20 and the connecting portion 9 are usually separated from each other by about 6 to 7 μm in the current design. In this case, if the resist is ejected onto the gate wiring 20 by the ink jet method, the resist may be ejected onto the connecting portion 9 due to the flying bend of the ink droplets and the like, which may cause a contact failure. Therefore, for example, if the ink droplet landing accuracy is ± 5 μm, it is preferable that the gate wiring 20 and the connecting portion 9 be separated from each other by at least about 10 μm.

  The present invention is not only applied to the wiring formation of a TFT substrate for a liquid crystal panel, but can also be applied to an organic EL panel, a panel of another similar display device, and a wiring formation substrate of another electronic device.

It is a principal part figure of the thin-film transistor substrate explaining Example 1 of the manufacturing method of the display apparatus of this invention. 6 is a diagram for further explaining the manufacturing process of Example 1. FIG. It is explanatory drawing of 1 pixel part in the thin-film transistor substrate which comprises the display apparatus by this invention. It is a figure explaining the structural example of 1 pixel formed in the TFT substrate which comprises a flat type display apparatus. It is a figure explaining the conventional manufacturing process of a thin-film transistor substrate. It is a figure following FIG. 5 explaining the conventional manufacturing process of a thin-film transistor substrate.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Glass substrate, 2 ... Gate wiring, 3 ... Gate insulating layer, 4 ... Semiconductor layer, 5 ... Contact layer, 6 ... Data wiring, 7 ... Protective layer, 8... Resist, 9.

Claims (2)

On the first substrate, a gate line, a gate electrode connected to the gate line, a gate insulating film, a silicon semiconductor layer, and the n + semiconductor layer, and the data line, a source electrode and a drain electrode, of which A thin film transistor processing process for forming the source electrode and the drain electrode, one of which is connected to the data wiring and the other of which is connected to the pixel electrode in part .
A protective film forming process for forming a protective film covering the entire surface of the first substrate obtained by processing the thin film transistor;
The above-mentioned gate wiring and the gate electrode connected to the gate wiring, the data wiring and the upper layer of the source electrode (or drain electrode) connected to the data wiring, and the upper layer excluding a part of the drain electrode (or source electrode) by inkjet A resist discharge process for applying a resist;
A protective film removing process for removing the protective film except for a portion where the resist is applied;
The protective film by discharging the ITO by an inkjet in the area having a pair of the pair and the data line of the gate wiring is removed, and the pixel electrode of the ITO is the source electrode and the drain electrode And a pixel electrode forming process for forming a pixel electrode connected to the other part to be connected. The resist, the pixel of the n + semiconductor layer is also discharged on the silicon semiconductor layer to form a channel and exposed by removing the data line, the gate line, and the source electrode and the drain electrode the other with the exception of the part to be connected is discharged over the drain electrode and the source electrode and, upon exposure of the resist discharged from the back surface of the first substrate, the said data line gate method of manufacturing a display device according to claim 1, by exposing the resist other than the resist on the wiring removed by development, thereby forming the bank.

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