JP2008129303A - Liquid crystal display device and method for manufacturing the same - Google Patents

Liquid crystal display device and method for manufacturing the same Download PDF

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JP2008129303A
JP2008129303A JP2006313871A JP2006313871A JP2008129303A JP 2008129303 A JP2008129303 A JP 2008129303A JP 2006313871 A JP2006313871 A JP 2006313871A JP 2006313871 A JP2006313871 A JP 2006313871A JP 2008129303 A JP2008129303 A JP 2008129303A
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liquid crystal
common electrode
crystal display
electrode
display device
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JP4252595B2 (en
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Keiko Nakano
敬子 中野
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Japan Display Inc
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Hitachi Displays Ltd
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<P>PROBLEM TO BE SOLVED: To form a common electrode with high precision in a liquid crystal display panel with a system which has the common electrode for each pixel solidly formed on a principal surface of an insulating substrate, and has a comb-shaped pixel electrode arranged on the common electrode via an insulating film, without using sputter deposition and a photolithography step. <P>SOLUTION: A bank 50 for the common electrode is formed simultaneously with a gate wire/electrode 3 and a common electrode wire 10 to be formed on the principal surface of a glass substrate 1, and the common electrode 2 is formed with high precision by inkjet-applying conductive ink to the inside surrounded by the bank 50. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、液晶表示装置とその製造方法に関し、特に横電界方式におけるコモン透明導電膜の形成工程を削減して全体のコスト低減を図った横電界型の液晶表示装置に好適なものである。   The present invention relates to a liquid crystal display device and a method of manufacturing the same, and is particularly suitable for a horizontal electric field type liquid crystal display device in which the step of forming a common transparent conductive film in the horizontal electric field method is reduced to reduce the overall cost.

フラット・パネル・ディスプレイ(FPD)の典型として液晶表示装置が広く用いられている。液晶表示装置は、基本的には二枚の基板の一方に画素電極を、他方の基板に共通電極(対向電極、コモン電極)を形成し、両電極間に電界を形成して液晶分子の配向方向を制御する、所謂縦電界方式(一般的に、TN方式などと呼ばれる)、二枚の基板の一方の基板に画素電極と共通電極(対向電極)を当該基板の基板面に略平行に配列させて形成し、両電極間に形成される電界で液晶分子の配向方向を制御する、所謂横電界方式(IPS方式とも称する)とに大別される。これらの方式には、さらに、多くの派生的な方式が提案されて、実用化がなされている。   A liquid crystal display device is widely used as a typical flat panel display (FPD). In a liquid crystal display device, a pixel electrode is basically formed on one of two substrates, a common electrode (opposite electrode, common electrode) is formed on the other substrate, and an electric field is formed between both electrodes to align liquid crystal molecules. The so-called vertical electric field method (generally called the TN method) for controlling the direction, a pixel electrode and a common electrode (counter electrode) are arranged substantially parallel to the substrate surface of one of the two substrates The so-called transverse electric field method (also referred to as IPS method), in which the orientation direction of liquid crystal molecules is controlled by an electric field formed between the electrodes. Many of these methods have been proposed and put into practical use.

これらの各方式の液晶表示装置の中で、横電界方式は視野角が広く、また、画素電極と共通電極の両方を一方の基板(通常は、薄膜トランジスタを形成した側の基板、薄膜トランジスタ基板:TFT基板)に形成することで、他方の基板(通常は、カラーフィルタを形成することで、カラーフィルタ基板:CF基板)との位置合わせ裕度が大きい、などから製造歩留まりが良い、などの特徴を有する。   Among these types of liquid crystal display devices, the horizontal electric field method has a wide viewing angle, and both the pixel electrode and the common electrode are provided on one substrate (usually the substrate on which the thin film transistor is formed, the thin film transistor substrate: TFT The substrate has a feature that the manufacturing yield is good because the alignment tolerance with the other substrate (usually the color filter substrate: CF substrate) is large because the color filter is formed. Have.

横電界方式の液晶表示装置は、その一方の基板であるTFT基板の主面に薄膜トランジスタからなる多数の画素回路をマトリクス配置した有効表示領域と、この有効表示領域の外側に画素の点灯・非点灯を制御する駆動回路を含む外部回路が設置または形成される。一方、CF基板の主面には、通常はR(赤),G(緑),B(青)の3色のカラーフィルタが形成され、TFT基板と主面同士を対向させて貼り合わせ、貼り合わせた間隙に液晶を封止して構成される。本発明は、横電界方式の液晶表示装置の、特にTFT基板に設ける共通電極とその形成に関連する。カラーフィルタをTFT基板側に設けたものもあるが、本発明はカラーフィルタに直接関連しないので、詳しい説明はしない。   The horizontal electric field type liquid crystal display device has an effective display area in which a large number of pixel circuits made of thin film transistors are arranged in a matrix on the main surface of a TFT substrate, which is one of the substrates, and lighting / non-lighting of pixels outside the effective display area An external circuit including a driving circuit for controlling the circuit is installed or formed. On the other hand, color filters of three colors R (red), G (green), and B (blue) are usually formed on the main surface of the CF substrate. The liquid crystal is sealed in the combined gap. The present invention relates to a liquid crystal display device of a horizontal electric field type, and particularly to a common electrode provided on a TFT substrate and its formation. Although some color filters are provided on the TFT substrate side, the present invention is not directly related to the color filters and will not be described in detail.

図10は、従来のTFT基板の構造例を説明する1画素の断面図である。このTFT基板は、ガラス等の無機基板、あるいは耐熱プラスチックスなどの有機フィルムを用い、その主面(TFT等を構成するための内面)に薄膜トランジスタや画素電極、共通電極が形成される。ここでは、基板に透明ガラス基板を用いるものとして説明する。図13において、TFT部分TFTには、ガラス基板1の主面に金属膜(アルミニウム(Al)等)膜3の積層構造を有する。又、画素開口部PXには共通電極2としてのITO膜が下部ゲート電極/ゲート配線3Aと同層に有する。共通配線部(共通電極給電部)CLには、共通電極2を形成するITO膜の上に金属膜(アルミニウム(Al)等)からなる上部共通電極2Aが積層されている。   FIG. 10 is a cross-sectional view of one pixel for explaining an example of the structure of a conventional TFT substrate. As this TFT substrate, an inorganic substrate such as glass or an organic film such as heat-resistant plastics is used, and a thin film transistor, a pixel electrode, and a common electrode are formed on its main surface (inner surface for constituting a TFT or the like). Here, it demonstrates as what uses a transparent glass substrate for a board | substrate. In FIG. 13, the TFT partial TFT has a laminated structure of a metal film (aluminum (Al) or the like) film 3 on the main surface of the glass substrate 1. The pixel opening PX has an ITO film as the common electrode 2 in the same layer as the lower gate electrode / gate wiring 3A. In the common wiring portion (common electrode power feeding portion) CL, an upper common electrode 2A made of a metal film (aluminum (Al) or the like) is laminated on the ITO film forming the common electrode 2.

金属膜3、ITO膜3Aからなるゲート配線/電極、共通電極2としてのITO膜、上部共通電極2Aを覆ってゲート絶縁膜4が形成されている。このゲート絶縁膜4としては窒化シリコン(SiN)が好適であるが、他の適当な絶縁材であってもよい。ゲート絶縁膜4の上層で、TFT部分TFTには半導体膜5がパターニングされている。この半導体膜5はアモルファスシリコン、ポリシリコン等5Bと、その上層に不純物半導体層5Aを有する積層構造である。   A gate insulating film 4 is formed to cover the gate wiring / electrode comprising the metal film 3 and the ITO film 3A, the ITO film as the common electrode 2, and the upper common electrode 2A. The gate insulating film 4 is preferably silicon nitride (SiN), but may be another appropriate insulating material. A semiconductor film 5 is patterned on the TFT partial TFT above the gate insulating film 4. The semiconductor film 5 has a laminated structure having an amorphous silicon, polysilicon, etc. 5B, and an impurity semiconductor layer 5A as an upper layer.

半導体膜5の上部には、チャネルを挟んでソース電極6とドレイン電極7が形成されている。これらソース電極6とドレイン電極7はアルミニウムを好適とする金属膜をパターニングして形成される。このソース電極6とドレイン電極7の上層を含むゲート絶縁膜4を覆って、保護絶縁膜8が成膜されている。保護絶縁膜8はパッシベーション膜(PAS膜)とも称し、ゲート絶縁膜4と同様の窒化シリコンが好適である。しかし、他の適当な絶縁材であってもよい。なお、ソース電極6とドレイン電極7は動作中に切り替わるが、説明の便宜上、図示のように固定したものとする。   A source electrode 6 and a drain electrode 7 are formed on the semiconductor film 5 with a channel interposed therebetween. The source electrode 6 and the drain electrode 7 are formed by patterning a metal film suitable for aluminum. A protective insulating film 8 is formed so as to cover the gate insulating film 4 including the upper layers of the source electrode 6 and the drain electrode 7. The protective insulating film 8 is also called a passivation film (PAS film), and silicon nitride similar to the gate insulating film 4 is suitable. However, other suitable insulating materials may be used. Although the source electrode 6 and the drain electrode 7 are switched during operation, it is assumed that they are fixed as shown for convenience of explanation.

保護絶縁膜8の上には、ITOからなる画素電極9がパターニングされている。画素電極9は櫛歯形であり、その一部は保護絶縁膜8に開けたコンタクトホールを通してTFTのドレイン電極7と接続している。また、共通配線部CLでは、共通配線10が保護絶縁膜8とゲート絶縁膜4を通して開けられたスルーホールを通して上部共通電極2Aに接続している。   A pixel electrode 9 made of ITO is patterned on the protective insulating film 8. The pixel electrode 9 has a comb shape, and a part thereof is connected to the drain electrode 7 of the TFT through a contact hole opened in the protective insulating film 8. In the common wiring portion CL, the common wiring 10 is connected to the upper common electrode 2A through a through hole opened through the protective insulating film 8 and the gate insulating film 4.

このTFT基板は、その主面の最上層を覆って配向膜が成膜され、ラビング等の処理で配向制御能が付与される。その後、このTFT基板にCF基板を貼り合わせ、両者の間に液晶を封入して液晶表示パネルが構成される。液晶表示パネルを構成するTFT基板の周囲には、駆動回路チップ等の外部回路が実装され、あるいは当該基板面に作り込まれる。この液晶表示パネルに、バックライトなどの機構部品、表示信号制御回路を搭載したプリント基板などを組み込んで液晶表示装置とする。   In this TFT substrate, an alignment film is formed so as to cover the uppermost layer of the main surface, and an alignment control ability is imparted by a process such as rubbing. Thereafter, a CF substrate is bonded to the TFT substrate, and a liquid crystal is sealed between them to form a liquid crystal display panel. An external circuit such as a drive circuit chip is mounted on or around the TFT substrate constituting the liquid crystal display panel. A liquid crystal display device is formed by incorporating mechanical parts such as a backlight and a printed circuit board on which a display signal control circuit is mounted on the liquid crystal display panel.

図11は、図10における共通電極の形成プロセスを説明する図である。また、図12は、図11における各プロセスに対応したTFT基板の断面図である。そして、図13は、図12におけるITOエッチング後のTFT基板の平面図、図14は、図12における金属(以下、メタルとも言う)エッチング後のTFT基板の平面図である。   FIG. 11 is a diagram illustrating a process for forming the common electrode in FIG. FIG. 12 is a cross-sectional view of a TFT substrate corresponding to each process in FIG. 13 is a plan view of the TFT substrate after ITO etching in FIG. 12, and FIG. 14 is a plan view of the TFT substrate after metal (hereinafter also referred to as metal) etching in FIG.

図11、図12、図13、図14を参照して、共通電極の形成プロセスを説明する。先ず、図11のプロセス31(以下、P−31のように表記する)では、ガラス基板1の主面にITO膜20を成膜する(図12の(a))。この上に感光性レジスト21を塗布し、ホトリソグラフィー工程(図では、単に、ホトと表記)で共通電極のパターンにパターニングする(P−32、(図12の(b))。パターニングした感光性レジスト21をマスクとしてITO膜20をエッチングした後、感光性レジスト21を除去する(P−33、図12の(c)、図13)。図13にエッチング後のITOパターンの平面形状を示す。図13のA−B線に沿った断面が図12の(c)に対応する。この上に金属薄膜としてアルミニウム(Al)30をスパッタし(P−34、図12の(d))、感光性レジストを塗布した後、マスク露光でゲート配線/電極3と上部共通電極配線(共通配線)2Aの部分にレジスト41を残す(P−35、図12の(e))。これにエッチングを施してレジスト41の下層以外のメタルを除去して共通電極2を露出させる(P−36、図12の(f)、図14)。   The formation process of the common electrode will be described with reference to FIGS. 11, 12, 13, and 14. First, in the process 31 of FIG. 11 (hereinafter referred to as P-31), the ITO film 20 is formed on the main surface of the glass substrate 1 (FIG. 12A). A photosensitive resist 21 is applied thereon, and is patterned into a common electrode pattern by a photolithography process (simply referred to as “photo” in the drawing) (P-32, (b) in FIG. 12). After etching the ITO film 20 using the resist 21 as a mask, the photosensitive resist 21 is removed (P-33, (c) in FIG. 12, FIG. 13), and the planar shape of the ITO pattern after etching is shown in FIG. 13 corresponds to (c) of Fig. 12. Aluminum (Al) 30 is sputtered as a metal thin film on this (P-34, (d) of Fig. 12), and the photosensitive film is exposed. After the resist is applied, the resist 41 is left on the gate wiring / electrode 3 and the upper common electrode wiring (common wiring) 2A by mask exposure (P-35, FIG. 12 (e)). The Exposing the common electrode 2 by removing the metal other than the underlying resist 41 (P-36, in FIG. 12 (f), FIG. 14).

このように、従来は,ITOのパターニングとゲート電極/配線のメタルのパターニングとの2回のホトリソ工程を必要としている。なお、TFT基板の製造におけるスパッタ成膜とホトリソ工程に換えて、TFTを構成する絶縁膜、導電膜、半導体膜の何れか、もしくは全部をインクジェット塗布による直接パターニングで形成するものが引用文献1に開示されている。
特許第3725169号公報
As described above, conventionally, two photolithography processes of ITO patterning and gate electrode / wiring metal patterning are required. In addition to the sputter film formation and the photolithography process in the manufacture of the TFT substrate, the one in which any or all of the insulating film, the conductive film, and the semiconductor film constituting the TFT are formed by direct patterning by ink-jet coating is disclosed in Reference Document 1. It is disclosed.
Japanese Patent No. 3725169

大形TV用の液晶表示装置を構成する液晶表示パネルでは低コスト化が重要である。スパッタ成膜とホトリソ工程によるパターニングは、スパッタ用の真空装置、露光マスク、露光装置、現像装置、等の高価かつ大型の製造設備を要するため、スパッタ成膜やホトリソ工程の削減は製造コストの低減に直接寄与する。   Cost reduction is important for a liquid crystal display panel constituting a liquid crystal display device for a large TV. Sputter deposition and patterning by the photolithography process require expensive and large manufacturing facilities such as sputtering vacuum equipment, exposure masks, exposure equipment, and development equipment, so reducing sputter deposition and photolithography processes reduces manufacturing costs. Contribute directly to

引用文献1に開示のインクジェット塗布での薄膜の直接パターニングでは、精度が10μmのパターンまで形成可能としている。TV用の液晶表示パネルの1画素のサイズは500μm×170μm程度と大きいので、理論上は画素電極等をインクジェット塗布で直接形成できると考えられる。しかし、インクジェット用のインクは薄膜材料を分散した溶液であり、ノズルから滴下されたインク滴は滴下表面上を濡れ広がるため、塗布端の外縁を精度よく制御することは困難である。   In direct patterning of a thin film by inkjet coating disclosed in the cited document 1, it is possible to form a pattern with a precision of 10 μm. Since the size of one pixel of a liquid crystal display panel for TV is as large as about 500 μm × 170 μm, it is theoretically considered that a pixel electrode or the like can be directly formed by inkjet coating. However, the ink for inkjet is a solution in which a thin film material is dispersed, and the ink droplets dropped from the nozzle spread wet on the dropping surface, so that it is difficult to accurately control the outer edge of the coating end.

ガラス基板の主面に、画素毎にべた形成した共通電極を有し、その上に絶縁膜を介して櫛歯状の画素電極を設ける形式の液晶表示パネルの製造のためのスパッタ成膜とホトリソ工程数を削減するために、画素電極よりも面積の広い共通電極をインクジェット塗布で形成できれば、低コスト化に大きく貢献することが可能である。しかし、配線間ショートや層間の浮遊コンダクタンスを発生させないためには、共通電極のパターニング精度は5μm以下が必要であり、このような高精度パターニングを引用文献1に記載のインクジェット塗布では形成できない。   Sputter deposition and photolithography for the manufacture of liquid crystal display panels with a common electrode formed on every principal pixel on the main surface of the glass substrate and a comb-like pixel electrode on the common electrode. If a common electrode having a larger area than the pixel electrode can be formed by inkjet coating in order to reduce the number of processes, it is possible to greatly contribute to cost reduction. However, in order not to generate a short circuit between wirings or a floating conductance between layers, the patterning accuracy of the common electrode is required to be 5 μm or less, and such high-accuracy patterning cannot be formed by inkjet coating described in the cited document 1.

本発明の目的は、ガラス等の絶縁基板の主面に、画素毎にべた形成した共通電極を有し、その上に絶縁膜を介して櫛歯状の画素電極を設ける形式の液晶表示パネルにおける当該共通電極のパターニングを、スパッタ成膜とホトリソ工程を用いずに高精度に形成した液晶表示装置とその製造方法を得ることにある。   An object of the present invention is to provide a liquid crystal display panel having a common electrode formed for each pixel on the main surface of an insulating substrate such as glass, and a comb-like pixel electrode provided thereon via an insulating film. An object of the present invention is to obtain a liquid crystal display device and a manufacturing method thereof in which the common electrode is patterned with high accuracy without using sputter deposition and a photolithography process.

上記目的は、ガラス基板の主面に形成するゲート配線/電極および共通電極配線と同時に共通電極用バンク(堤)を形成し、このバンクで囲まれた内側に導電性インクをインクジェット塗布し、焼成することで、高精度に共通電極を形成することで達成される。ゲート配線/電極および共通電極配線とバンクは、同時に形成されるため、絶縁基板面からの高さは略同じとなる。また、共通電極は塗布したインクを焼成して得られるため、その絶縁基板面からの高さはゲート配線/電極および共通電極配線とバンクのそれよりも低くなる。   The purpose is to form a common electrode bank (bank) at the same time as the gate wiring / electrode and common electrode wiring formed on the main surface of the glass substrate, apply conductive ink to the inner side surrounded by the bank, and bak This is achieved by forming the common electrode with high accuracy. Since the gate wiring / electrode and common electrode wiring and the bank are formed at the same time, the height from the surface of the insulating substrate is substantially the same. Further, since the common electrode is obtained by baking the applied ink, the height from the insulating substrate surface is lower than that of the gate wiring / electrode, the common electrode wiring and the bank.

すなわち、ゲート配線/電極と同時に共通電極の外形を規制するバンクを精度の良いホトリソ工程で形成し、このバンクで囲まれた内側にITOを好適とする透明導電膜材料を溶液に分散したインクをインクジェット塗布する。塗布された透明導電膜材料の周縁(外縁)はバンクで規制される。これを焼成することで高精度の共通電極が形成される。その後、絶縁膜を成膜し、ITOを好適とする画素電極用の透明導電膜材料をスパッタ成膜し、ホトリソ工程で櫛歯状にパターニングして画素電極とする。   That is, a bank that regulates the outer shape of the common electrode simultaneously with the gate wiring / electrode is formed by an accurate photolithography process, and an ink in which a transparent conductive film material suitable for ITO is dispersed in a solution surrounded by the bank is used. Apply inkjet. The peripheral edge (outer edge) of the applied transparent conductive film material is regulated by the bank. By firing this, a high-precision common electrode is formed. Thereafter, an insulating film is formed, and a transparent conductive film material for pixel electrodes, preferably made of ITO, is formed by sputtering, and patterned into a comb-teeth shape in a photolithography process to form pixel electrodes.

本発明の代表的な構成を記述すれば、以下のとおりであるが、本発明はこの記述および後述する実施の形態の記述に限定されるものではなく、本発明の技術思想を逸脱することなく、種々の変更が可能であることはいうまでもない。   A typical configuration of the present invention will be described as follows. However, the present invention is not limited to this description and the description of embodiments described later, and does not depart from the technical idea of the present invention. Needless to say, various modifications are possible.

絶縁基板の主面に薄膜トランジスタからなる多数の画素をマトリクス配置した有効表示領域と、この有効表示領域の外側に画素の点灯・非点灯を制御する駆動回路を含む外部回路を設けた液晶表示パネルを有する液晶表示装置において、本発明は、
前記絶縁基板の主面に形成されたゲート配線/電極と、このゲート配線/電極と同一層に共通電極配線および該共通電極配線の一部と共に共通電極の外縁を規制するバンクを有し、
前記バンクの内側に塗布型導電膜で形成された共通電極を有することを特徴とする。
A liquid crystal display panel provided with an effective display area in which a large number of pixels made of thin film transistors are arranged in a matrix on the main surface of an insulating substrate, and an external circuit including a drive circuit for controlling lighting / non-lighting of pixels outside the effective display area In the liquid crystal display device having the present invention,
A gate wiring / electrode formed on the main surface of the insulating substrate, and a bank for regulating the outer edge of the common electrode together with the common electrode wiring and a part of the common electrode wiring in the same layer as the gate wiring / electrode;
A common electrode formed of a coating-type conductive film is provided inside the bank.

また、本発明の液晶表示装置は、前記バンクの前記絶縁基板面からの高さが、前記共通電極の同高さよりも高いことを特徴とする。   In the liquid crystal display device of the present invention, the height of the bank from the insulating substrate surface is higher than the height of the common electrode.

また、本発明の液晶表示装置は、前記ゲート配線/電極と前記共通電極配線および前記共通電極の前記絶縁基板面からの高さが略等しいことを特徴とする。   The liquid crystal display device of the present invention is characterized in that the gate wiring / electrode, the common electrode wiring, and the common electrode have substantially the same height from the surface of the insulating substrate.

また、本発明の液晶表示装置は、前記共通電極の上層に、絶縁膜を介して画素電極を有することを特徴とする。   The liquid crystal display device of the present invention is characterized in that a pixel electrode is provided on an upper layer of the common electrode through an insulating film.

また、本発明の液晶表示装置は、前記画素電極は櫛歯状であることを特徴とする。   The liquid crystal display device according to the present invention is characterized in that the pixel electrode has a comb shape.

また、本発明の液晶表示装置は、前記画素電極は前記薄膜トランジスタに接続していることを特徴とする。   In the liquid crystal display device of the present invention, the pixel electrode is connected to the thin film transistor.

そして、本発明の前記液晶表示装置を製造する方法は、前記液晶表示パネルを構成する前記絶縁基板の前記画素の開口部に、ゲート配線/電極および共通電極配線と同時に共通電極用のバンクを形成し、
前記バンクで囲まれた内側に塗布型導電性溶液を塗布し、これを焼成して、前記共通電極を形成することを特徴とする。
In the method of manufacturing the liquid crystal display device according to the present invention, a bank for a common electrode is formed simultaneously with a gate wiring / electrode and a common electrode wiring at an opening of the pixel of the insulating substrate constituting the liquid crystal display panel. And
A coating-type conductive solution is coated on the inner side surrounded by the bank, and is baked to form the common electrode.

また、本発明の前記液晶表示装置を製造する方法は、前記バンクを金属膜のスパッタとホトリソグラフィーでパターニングすることを特徴とする。   The method of manufacturing the liquid crystal display device of the present invention is characterized in that the bank is patterned by sputtering of a metal film and photolithography.

また、本発明の前記液晶表示装置を製造する方法は、前記塗布型導電性溶液の塗布をインクジェットで行うことを特徴とする。   Further, the method for producing the liquid crystal display device of the present invention is characterized in that the coating type conductive solution is applied by ink jetting.

本発明では、共通電極の形成にスパッタ成膜や、それ自体のホトリソ工程を必要としないため、TFT基板の製造におけるコストが削減され、設備、装置の投資を抑制して、全体として低コスト化を実現できる。   The present invention does not require sputter deposition or its own photolithography process to form the common electrode, thereby reducing the cost of manufacturing the TFT substrate, reducing investment in equipment and equipment, and reducing the overall cost. Can be realized.

以下、本発明の最良の実施形態を実施例の図面を参照して詳細に説明する。本発明は、透明な導電膜で構成される共通電極をTFT基板の主面の最下層にある構造とした液晶表示パネルに適用されるが、これに限定されるものではなく、同様の機能と精度が要求される薄膜の形成にも同様に適用可能である。   The best mode for carrying out the present invention will be described below in detail with reference to the accompanying drawings. The present invention is applied to a liquid crystal display panel having a structure in which a common electrode composed of a transparent conductive film is in the lowermost layer of the main surface of the TFT substrate. However, the present invention is not limited to this. The present invention can be similarly applied to formation of a thin film that requires accuracy.

図1は、本発明の実施例1の要部プロセスを説明する工程図である。また、図2は、図1に示す工程図の要部プロセスに対応したTFT基板の断面図である。図2の(a)、(b)、(c)、(d)、(e)は、図1のプロセス(P−1)、(P−3)、(P−4)、(P−5)、(P−6)に対応する。そして、図3は、ゲート配線/電極と共通電極形成用のバンクおよびこのバンクの一部も構成する共通電極配線を形成した状態の平面図、図4は、共通電極形成用のバンクにより形状規制された共通電極が形成された状態の平面図である。   FIG. 1 is a process diagram for explaining a main process of the first embodiment of the present invention. FIG. 2 is a cross-sectional view of the TFT substrate corresponding to the main process of the process diagram shown in FIG. (A), (b), (c), (d), and (e) of FIG. 2 are the processes (P-1), (P-3), (P-4), and (P-5) of FIG. ), (P-6). FIG. 3 is a plan view of a state in which a gate wiring / electrode and a bank for forming a common electrode and a common electrode wiring that also constitutes a part of the bank are formed. FIG. It is a top view of the state in which the made common electrode was formed.

図1のプロセス(P−1)では、洗浄したガラス基板1の表面に金属(メタル)膜30としてアルミニウムAlをスパッタで成膜する。金属膜はアルミニウム・ネオジム等の合金でもよく、また、後述する各種金属も用いることができる。この金属膜30の上に感光性レジストを塗布し(P−2)、マスク露光と現像を含むホトリソ工程でゲート配線/電極およびバンク(共通配線の部分も含む)部分にレジスト41を残す(P−3)。レジスト41をエッチングマスクとして金属膜30をウエットエッチングし、図3にも示すようにゲート配線/電極3およびバンク(共通配線10の部分も含む)50の部分に金属膜30を残す(P−4)。バンク(共通配線10の部分も含む)50部分の内側に塗布形の透明導電膜材料としてITO(の微粒子)を溶液に分散した導電性インク20をインクジェットで塗布する(P−5)。これを乾燥し、焼成して透明な共通電極2を得る(P−6)。共通電極2はバンク50で周縁が規制される。バンク50はホトリソ工程で高精度にパターニングされているため、このバンク50で外縁が規定される共通電極は前記した5μm以下の精度で形成される。   In the process (P-1) of FIG. 1, aluminum Al is formed on the surface of the cleaned glass substrate 1 as a metal (metal) film 30 by sputtering. The metal film may be an alloy such as aluminum or neodymium, and various metals described later can also be used. A photosensitive resist is applied on the metal film 30 (P-2), and the resist 41 is left in the gate wiring / electrode and bank (including the common wiring portion) portion by a photolithography process including mask exposure and development (P -3). The metal film 30 is wet-etched using the resist 41 as an etching mask to leave the metal film 30 in the gate wiring / electrode 3 and the bank (including the common wiring 10) 50 as shown in FIG. ). Conductive ink 20 in which ITO (particulates) is dispersed in a solution as a coating-type transparent conductive film material is applied to the inside of the bank (including the common wiring 10 portion) 50 by inkjet (P-5). This is dried and baked to obtain a transparent common electrode 2 (P-6). The peripheral edge of the common electrode 2 is regulated by the bank 50. Since the bank 50 is patterned with high accuracy in the photolithography process, the common electrode whose outer edge is defined by the bank 50 is formed with the accuracy of 5 μm or less.

ここでは、エッチングをウェットプロセスとしたが、ガスを用いたドライエッチングでも構わない。使用するメタルは、アルミニウム(Al)、アルミニウム・ネオジム(Al・Nd)以外に、銅(Cu)、チタン(Ti)、クロム(Cr)、モリブデン(Mo)、ニッケル(Ni)、タングステン(W)、銀(Ag)、金(Au)などを単独または合金で用いることができ、必要に応じて複数層で形成する。膜厚は30nm〜500nmに形成し、抵抗値は10μΩcm以下とする。   Here, etching is a wet process, but dry etching using a gas may be used. Metals to be used are copper (Cu), titanium (Ti), chromium (Cr), molybdenum (Mo), nickel (Ni), tungsten (W) in addition to aluminum (Al) and aluminum / neodymium (Al / Nd). , Silver (Ag), gold (Au), or the like can be used alone or in an alloy, and a plurality of layers are formed as necessary. The film thickness is 30 nm to 500 nm, and the resistance value is 10 μΩcm or less.

バンクのパターンは画素領域を囲む形状とする。ゲート配線/電極およびバンクと共に共通電極配線(共通配線)も形成され、この共通配線がバンクの一部を形成する。ガラス基板1の上でバンクで囲まれる領域は1画素の透過部に当たる。このバンクの内側を満たすように、塗布形の透明導電膜材料をインクジェットで塗布する。なお、インクジェットに限らず、例えばオフセット印刷など、他の塗布方法で透明導電膜材料をバンク内側に塗布してもよい。   The bank pattern has a shape surrounding the pixel region. A common electrode wiring (common wiring) is formed together with the gate wiring / electrode and the bank, and this common wiring forms a part of the bank. A region surrounded by the bank on the glass substrate 1 corresponds to a transmissive portion of one pixel. A coating type transparent conductive film material is applied by ink jet so as to fill the inside of the bank. The transparent conductive film material may be applied to the inside of the bank by other application methods such as offset printing, not limited to inkjet.

塗布形の透明導電膜材料の溶液としては、ITOなどの透明導電材料の前駆体(ここでの前駆体は塗布後加熱や光照射などのエネルギーを与えることでITOとなるものを指す)を溶媒に溶かしたものでもよく、大きさ平均粒径が5〜50nmの微粒子を溶媒中に分散させたものでもよい。この微粒子を分散する溶媒としては、アルコール類、ケトン類、グリコールエーテル類、非環状炭化水素類、芳香族炭化水素類などを用いることができ、分散剤や安定剤を加えて用いる。この種の溶媒としては、例えば、住友金属鉱山社製の商品名「DX−400シリーズ」などが市販されている。   As a solution of the coating type transparent conductive film material, a precursor of a transparent conductive material such as ITO (herein, the precursor refers to a substance that becomes ITO by applying energy such as heating or light irradiation after coating) It may be dissolved in water, or may be obtained by dispersing fine particles having a size average particle diameter of 5 to 50 nm in a solvent. As a solvent for dispersing the fine particles, alcohols, ketones, glycol ethers, acyclic hydrocarbons, aromatic hydrocarbons, and the like can be used, and a dispersant and a stabilizer are added. As this type of solvent, for example, trade name “DX-400 series” manufactured by Sumitomo Metal Mining Co., Ltd. is commercially available.

透明導電膜材料の溶液をインクジェットで平坦なガラス基板上に単に塗布した場合、基板面との濡れ性(基板面と溶液の表面エネルギーの関係)により塗布パターンの端部(外縁の位置)は正確に規定できない。しかし、本実施例によれば、バンクを形成するメタルの段差によりインクが堰きとめられるので、バンクのパターンに従った形状で形成できる。バンクのパターン精度はメタルのホトリソによるパターニングの精度である±2μmで形成可能である。   When a transparent conductive film material solution is simply applied onto a flat glass substrate by inkjet, the edge of the coating pattern (the position of the outer edge) is accurate due to the wettability with the substrate surface (the relationship between the substrate surface and the surface energy of the solution). Cannot be specified. However, according to this embodiment, the ink is blocked by the level difference of the metal forming the bank, so that it can be formed in a shape according to the bank pattern. The pattern accuracy of the bank can be formed with ± 2 μm, which is the accuracy of patterning by metal photolithography.

そして、透明導電材料の溶液を滴下塗布した後、200℃以下で仮焼成して溶剤をある程度除去し、200〜450℃で焼成する。これにより、ITOの導電性薄膜が形成される。このITOの薄膜は、膜厚100nmでのシート抵抗が、例えば0.1〜50kΩ/□程度となる。また、透過率が、90%以上となる。   And after apply | coating the solution of a transparent conductive material by dripping, temporary baking is performed at 200 degrees C or less, a solvent is removed to some extent, and baking is carried out at 200-450 degreeC. Thereby, a conductive thin film of ITO is formed. This ITO thin film has a sheet resistance of about 0.1 to 50 kΩ / □ at a film thickness of 100 nm. Further, the transmittance is 90% or more.

また、従来のスパッタによるITO等の透明導電膜の成膜では、スパッタ用ターゲットとしてのITO等の材料使用効率が最大50%で、かつパターニングにより成膜後にその20〜40%を除去していたのに比べ、本発明の実施例1のようにインクジェット塗布を用いることで、材料の80〜90%を有効に使用可能となり、材料効率の観点からも低コスト化を図ることができる。   Further, in the conventional film formation of a transparent conductive film such as ITO by sputtering, the material use efficiency of ITO or the like as a sputtering target is 50% at the maximum, and 20 to 40% is removed after film formation by patterning. In contrast, by using ink jet coating as in Example 1 of the present invention, 80 to 90% of the material can be used effectively, and cost can be reduced from the viewpoint of material efficiency.

図5は、共通電極の形成後のTFT基板の形成プロセスを工程順に説明する断面図である。なお、ここでは、共通電極を実施例1で形成したものを用いている。図6は、図4と同様の図5の(a)に対応する1画素部分の平面図、図7は、図5の(e)に対応する1画素部分の平面図、図8は、図5の(h)に対応する1画素部分の平面図である。   FIG. 5 is a cross-sectional view illustrating the process of forming the TFT substrate after forming the common electrode in the order of steps. Here, the common electrode formed in Example 1 is used. 6 is a plan view of one pixel portion corresponding to (a) of FIG. 5 similar to FIG. 4, FIG. 7 is a plan view of one pixel portion corresponding to (e) of FIG. 5, and FIG. FIG. 6 is a plan view of one pixel portion corresponding to 5 (h).

図5〜図8において、共通電極2を形成したTFT基板(図5の(a)、図6)にゲート絶縁膜4としてSiNをCVDで形成する(図5の(b))。このゲート絶縁膜4の形成のための反応ガスは、SiH4、NH3で、バッファガスに窒素ガスN2を用いる。ゲート絶縁膜4は300〜500nmの膜厚に形成する。その後、半導体膜5としてアモルファスシリコン(a−Si)5B、n型不純物をドープしたアモルファスシリコン(a−Si)5AをCVDで成膜する(図5の(b))。半導体層5のみをホトリソプロセスとドライエッチングでパターニングする(図5の(c))。 5 to 8, SiN is formed by CVD as the gate insulating film 4 on the TFT substrate (FIGS. 5A and 6) on which the common electrode 2 is formed (FIG. 5B). The reaction gas for forming the gate insulating film 4 is SiH 4 or NH 3 , and nitrogen gas N 2 is used as a buffer gas. The gate insulating film 4 is formed to a thickness of 300 to 500 nm. Thereafter, amorphous silicon (a-Si) 5B and amorphous silicon (a-Si) 5A doped with n-type impurities are deposited by CVD as the semiconductor film 5 (FIG. 5B). Only the semiconductor layer 5 is patterned by a photolithography process and dry etching ((c) of FIG. 5).

次に、ソース・ドレイン配線用メタル60をスパッタで成膜し(図5の(d))、ソース電極6(及びソース配線、あるいはデータ線)12、ドレイン電極7をパターン形成する(図5の(e)、図7)。ソース・ドレイン配線用メタルは、アルミニウム(Al)、アルミニウム・ネオジム合金(Al―Nd)以外に、銅(Cu)、チタン(Ti)、クロム(Cr)、モリブデン(Mo)、ニッケル(Ni)、タングステン(W)、銀(Ag)、金(Au)などを単独または合金で用い,必要に応じて複数層で形成する。   Next, a source / drain wiring metal 60 is formed by sputtering (FIG. 5D), and the source electrode 6 (and source wiring or data line) 12 and the drain electrode 7 are patterned (FIG. 5). (E), FIG. 7). In addition to aluminum (Al) and aluminum-neodymium alloy (Al—Nd), the metal for source / drain wiring is copper (Cu), titanium (Ti), chromium (Cr), molybdenum (Mo), nickel (Ni), Tungsten (W), silver (Ag), gold (Au), or the like is used alone or in an alloy, and formed as a plurality of layers as necessary.

この上に、保護絶縁膜(PAS膜)8としてSiNをCVDで300〜500nmの膜厚に形成し(図5の(f))、画素電極とドレイン線をつなぐように保護絶縁膜8にスルーホールをホトリソで形成する(図5の(g))。   On this, SiN is formed as a protective insulating film (PAS film) 8 to a thickness of 300 to 500 nm by CVD ((f) in FIG. 5), and is passed through the protective insulating film 8 so as to connect the pixel electrode and the drain line. Holes are formed with photolithography (FIG. 5 (g)).

さらに、画素電極9としての透明導電膜を30〜200nmの膜厚に形成し,横電界を発生させるために櫛歯形状にパターニングする(図5の(h)、図5の(i)、図8)。透明導電膜9はスパッタで形成し、材料には、ITO、SnO2、ZnO、AlドープZnO、などが使用できる。図8の線E―Fに沿った断面が図5の(h)に、線G―Hに沿った断面が図5の(i)に対応する。 Further, a transparent conductive film as the pixel electrode 9 is formed to a thickness of 30 to 200 nm and patterned into a comb-teeth shape to generate a lateral electric field (FIG. 5 (h), FIG. 5 (i), FIG. 8). The transparent conductive film 9 is formed by sputtering, and materials such as ITO, SnO 2 , ZnO, and Al-doped ZnO can be used. The cross section along line EF in FIG. 8 corresponds to (h) in FIG. 5, and the cross section along line GH corresponds to (i) in FIG.

図9は、本発明による液晶表示装置の液晶表示パネルを構成するTFT基板の構造例を説明する1画素の断面図である。このTFT基板1には、ガラス等の無機基板、あるいは耐熱プラスチックスなどの有機フィルムを用い、その主面に薄膜トランジスタTFTや画素電極、共通電極が形成される。ここでは、基板1に透明ガラス基板を用いるものとして説明する。図9において、TFT部分TFTには、ガラス基板1の主面に金属膜のゲート電極3を有する。又、画素開口部PXには共通電極2としてのITO膜がゲート電極3と同層で有する。共通配線部(共通電極給電部)CLには、金属膜からなる共通電極配線10が形成されている。この共通電極配線10はバンク50の一部(一辺)を構成している。   FIG. 9 is a cross-sectional view of one pixel for explaining a structural example of a TFT substrate constituting the liquid crystal display panel of the liquid crystal display device according to the present invention. As this TFT substrate 1, an inorganic substrate such as glass or an organic film such as heat-resistant plastics is used, and a thin film transistor TFT, a pixel electrode, and a common electrode are formed on the main surface. Here, it demonstrates as what uses a transparent glass substrate for the board | substrate 1. FIG. In FIG. 9, the TFT partial TFT has a gate electrode 3 of a metal film on the main surface of the glass substrate 1. The pixel opening PX has an ITO film as the common electrode 2 in the same layer as the gate electrode 3. A common electrode wiring 10 made of a metal film is formed in the common wiring portion (common electrode feeding portion) CL. The common electrode wiring 10 constitutes a part (one side) of the bank 50.

ゲート配線/電極3、共通電極2としてのITO膜、共通電極配線10を覆ってゲート絶縁膜4が形成されている。このゲート絶縁膜4としては窒化シリコンSiNが好適であるが、他の適当な絶縁材であってもよい。ゲート絶縁膜4の上層で、TFT部分TFTには半導体膜5がパターニングされている。この半導体膜5はアモルファスシリコン(ポリシリコン等でも可)5Bと、その上層に不純物半導体層5Aを有する積層構造である。   A gate insulating film 4 is formed to cover the gate wiring / electrode 3, the ITO film as the common electrode 2, and the common electrode wiring 10. The gate insulating film 4 is preferably silicon nitride SiN, but may be another appropriate insulating material. A semiconductor film 5 is patterned on the TFT partial TFT above the gate insulating film 4. The semiconductor film 5 has a laminated structure having amorphous silicon (or polysilicon or the like) 5B and an impurity semiconductor layer 5A as an upper layer.

半導体膜5の上部には、チャネルを挟んでソース電極6とドレイン電極7が形成されている。これらソース電極6とドレイン電極7はアルミニウムを好適とする金属膜をパターニングして形成される。このソース電極6とドレイン電極7の上層を含むゲート絶縁膜4を覆って、保護絶縁膜(PAS膜)8が成膜されている。保護絶縁膜8はゲート絶縁膜4と同様の窒化シリコンで形成するのが好適である。しかし、他の適当な絶縁材であってもよい。   A source electrode 6 and a drain electrode 7 are formed on the semiconductor film 5 with a channel interposed therebetween. The source electrode 6 and the drain electrode 7 are formed by patterning a metal film suitable for aluminum. A protective insulating film (PAS film) 8 is formed so as to cover the gate insulating film 4 including the upper layers of the source electrode 6 and the drain electrode 7. The protective insulating film 8 is preferably formed of silicon nitride similar to the gate insulating film 4. However, other suitable insulating materials may be used.

保護絶縁膜8の上には、ITOからなる画素電極9がパターニングされている。画素電極9は櫛歯形であり、その一部は保護絶縁膜8に開けたコンタクトホールを通してTFTのドレイン電極7と接続している。また、共通配線部CLでは、共通配線10が保護絶縁膜8とゲート絶縁膜4を通して開けられたスルーホールのコンタクト11を通して図示しない共通電極給電線に接続している。   A pixel electrode 9 made of ITO is patterned on the protective insulating film 8. The pixel electrode 9 has a comb shape, and a part thereof is connected to the drain electrode 7 of the TFT through a contact hole opened in the protective insulating film 8. In the common wiring portion CL, the common wiring 10 is connected to a common electrode power supply line (not shown) through a contact 11 of a through hole opened through the protective insulating film 8 and the gate insulating film 4.

このTFT基板は、その主面の最上層を覆って図示しない配向膜が成膜され、ラビング等の処理で配向制御能が付与される。その後、このTFT基板にCF基板を貼り合わせ、両者の間に液晶を封入して液晶表示パネルが構成される。液晶表示パネルを構成するTFT基板の周囲には、駆動回路チップ等の外部回路が実装され、あるいは当該基板面に作り込まれる。この液晶表示パネルに、バックライトなどの機構部品、表示信号制御回路を搭載したプリント基板などを組み込んで液晶表示装置とする。   In this TFT substrate, an alignment film (not shown) is formed so as to cover the uppermost layer of the main surface, and an alignment control ability is imparted by a process such as rubbing. Thereafter, a CF substrate is bonded to the TFT substrate, and a liquid crystal is sealed between them to form a liquid crystal display panel. An external circuit such as a drive circuit chip is mounted on or around the TFT substrate constituting the liquid crystal display panel. A liquid crystal display device is formed by incorporating mechanical parts such as a backlight and a printed circuit board on which a display signal control circuit is mounted on the liquid crystal display panel.

本発明の実施例1の要部プロセスを説明する工程図である。It is process drawing explaining the principal part process of Example 1 of this invention. 図1に示す工程図の要部プロセスに対応したTFT基板の断面図である。It is sectional drawing of the TFT substrate corresponding to the principal process of the process drawing shown in FIG. ゲート配線/電極と共通電極形成用のバンクおよびこのバンクの一部も構成する共通電極配線を形成した状態の平面図である。FIG. 3 is a plan view of a state where a gate wiring / electrode and a bank for forming a common electrode and a common electrode wiring that also constitutes a part of the bank are formed. 共通電極形成用のバンクにより形状規制された共通電極が形成された状態の平面図である。It is a top view of the state in which the common electrode by which the shape control was carried out by the bank for common electrode formation was formed. 共通電極の形成後のTFT基板の形成プロセスを工程順に説明する断面図である。It is sectional drawing explaining the formation process of the TFT substrate after formation of a common electrode to process order. 図4と同様の図8の(a)に対応する1画素部分の平面図である。It is a top view of the 1 pixel part corresponding to (a) of FIG. 8 similar to FIG. 図5の(e)に対応する1画素部分の平面図である。It is a top view of the 1 pixel part corresponding to (e) of FIG. 図5の(h)に対応する1画素部分の平面図である。FIG. 6 is a plan view of one pixel portion corresponding to (h) of FIG. 5. 本発明による液晶表示装置の液晶表示パネルを構成するTFT基板の構造例を説明する1画素の断面図である。It is sectional drawing of 1 pixel explaining the structural example of the TFT substrate which comprises the liquid crystal display panel of the liquid crystal display device by this invention. 従来のTFT基板の構造例を説明する1画素の断面図である。It is sectional drawing of 1 pixel explaining the structural example of the conventional TFT substrate. 図10における共通電極の形成プロセスを説明する図である。It is a figure explaining the formation process of the common electrode in FIG. 図11における各プロセスに対応したTFT基板の断面図である。It is sectional drawing of the TFT substrate corresponding to each process in FIG. 図12におけるITOエッチング後のTFT基板の平面図である。It is a top view of the TFT substrate after ITO etching in FIG. 図12における金属エッチング後のTFT基板の平面図である。It is a top view of the TFT substrate after metal etching in FIG.

符号の説明Explanation of symbols

1・・・ガラス基板、2・・・共通電極、3・・・ゲート配線/電極、4・・・ゲート絶縁膜、5・・・シリコン半導体膜、6・・・ソース電極、7・・・ドレイン電極、8・・・保護絶縁膜、9・・・画素電極、10・・・共通電極配線、11・・・コンタクト、12・・・データ線、20・・・ITO,21,41・・・レジスト、50・・・バンク。   DESCRIPTION OF SYMBOLS 1 ... Glass substrate, 2 ... Common electrode, 3 ... Gate wiring / electrode, 4 ... Gate insulating film, 5 ... Silicon semiconductor film, 6 ... Source electrode, 7 ... Drain electrode, 8 ... Protective insulating film, 9 ... Pixel electrode, 10 ... Common electrode wiring, 11 ... Contact, 12 ... Data line, 20 ... ITO, 21, 41 ...・ Resist, 50 ... bank.

Claims (9)

絶縁基板の主面に薄膜トランジスタからなる多数の画素をマトリクス配置した有効表示領域と、この有効表示領域の外側に画素の点灯・非点灯を制御する駆動回路を含む外部回路を設けた液晶表示パネルを有する液晶表示装置であって、
前記絶縁基板の主面に形成されたゲート配線/電極と、このゲート配線/電極と同一層に共通電極配線および該共通電極配線の一部と共に共通電極の外縁を規制するバンクを有し、
前記バンクの内側に塗布型導電膜で形成された共通電極を有することを特徴とする液晶表示装置。
A liquid crystal display panel provided with an effective display area in which a large number of pixels made of thin film transistors are arranged in a matrix on the main surface of an insulating substrate, and an external circuit including a drive circuit for controlling lighting / non-lighting of pixels outside the effective display area A liquid crystal display device comprising:
A gate wiring / electrode formed on the main surface of the insulating substrate, and a bank for regulating the outer edge of the common electrode together with the common electrode wiring and a part of the common electrode wiring in the same layer as the gate wiring / electrode;
A liquid crystal display device having a common electrode formed of a coating-type conductive film inside the bank.
請求項1において、
前記バンクの前記絶縁基板面からの高さが、前記共通電極の同高さよりも高いことを特徴とする液晶表示装置。
In claim 1,
The liquid crystal display device, wherein a height of the bank from the surface of the insulating substrate is higher than a height of the common electrode.
請求項1又は2において、
前記ゲート配線/電極と前記共通電極配線および前記共通電極の前記絶縁基板面からの高さが略等しいことを特徴とする液晶表示装置。
In claim 1 or 2,
The liquid crystal display device, wherein the gate wiring / electrode, the common electrode wiring, and the common electrode have substantially the same height from the insulating substrate surface.
請求項1乃至3の何れかにおいて、
前記共通電極の上層に、絶縁膜を介して画素電極を有することを特徴とする液晶表示装置。
In any one of Claims 1 thru | or 3,
A liquid crystal display device having a pixel electrode on an upper layer of the common electrode through an insulating film.
請求項4において、
前記画素電極は櫛歯状であることを特徴とする液晶表示装置。
In claim 4,
The liquid crystal display device, wherein the pixel electrode has a comb shape.
請求項4又は5において、
前記画素電極は前記薄膜トランジスタに接続していることを特徴とする液晶表示装置。
In claim 4 or 5,
The liquid crystal display device, wherein the pixel electrode is connected to the thin film transistor.
絶縁基板の主面に薄膜トランジスタからなる多数の画素をマトリクス配置した有効表示領域と、この有効表示領域の外側に画素の点灯・非点灯を制御する駆動回路を含む外部回路を設けた薄膜トランジスタ基板で構成した液晶表示パネルを有する液晶表示装置の製造方法であって、
前記液晶表示パネルを構成する前記絶縁基板の前記画素の開口部に、ゲート配線/電極および共通電極配線と同時に共通電極用のバンクを形成し、
前記バンクで囲まれた内側に塗布型導電性溶液を塗布し、これを焼成して、前記共通電極を形成することを特徴とする液晶表示装置の製造方法。
Consists of a thin film transistor substrate in which an effective display region in which a large number of pixels made of thin film transistors are arranged in a matrix on the main surface of the insulating substrate and an external circuit including a drive circuit for controlling lighting / non-lighting of the pixels outside the effective display region A method of manufacturing a liquid crystal display device having a liquid crystal display panel,
Forming a bank for the common electrode simultaneously with the gate wiring / electrode and the common electrode wiring at the opening of the pixel of the insulating substrate constituting the liquid crystal display panel,
A method of manufacturing a liquid crystal display device, comprising: applying a coating-type conductive solution to an inner side surrounded by the bank, and baking the coating-type conductive solution to form the common electrode.
請求項7において、
前記バンクを金属膜のスパッタとホトリソグラフィーでパターニングすることを特徴とする液晶表示装置の製造方法。
In claim 7,
A method of manufacturing a liquid crystal display device, wherein the bank is patterned by sputtering of a metal film and photolithography.
請求項7又は8において、
前記塗布型導電性溶液の塗布をインクジェットで行うことを特徴とする液晶表示装置の製造方法。
In claim 7 or 8,
A method of manufacturing a liquid crystal display device, wherein the application type conductive solution is applied by inkjet.
JP2006313871A 2006-11-21 2006-11-21 Liquid crystal display device and manufacturing method thereof Expired - Fee Related JP4252595B2 (en)

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