WO2013102372A1 - Array substrate, method for manufacturing same, and display device - Google Patents

Array substrate, method for manufacturing same, and display device Download PDF

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Publication number
WO2013102372A1
WO2013102372A1 PCT/CN2012/084463 CN2012084463W WO2013102372A1 WO 2013102372 A1 WO2013102372 A1 WO 2013102372A1 CN 2012084463 W CN2012084463 W CN 2012084463W WO 2013102372 A1 WO2013102372 A1 WO 2013102372A1
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Prior art keywords
thin film
film transistor
gate
array substrate
layer
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PCT/CN2012/084463
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French (fr)
Chinese (zh)
Inventor
张学辉
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京东方科技集团股份有限公司
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Publication of WO2013102372A1 publication Critical patent/WO2013102372A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K39/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic radiation-sensitive element covered by group H10K30/00
    • H10K39/30—Devices controlled by radiation
    • H10K39/32—Organic image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device. Background technique
  • Organic Thin Film Transistor has advantages such as being suitable for large-area processing and being suitable for flexible substrates, and has shown application prospects in the field of flat panel display. Therefore, research and development of OTFT array substrates have received extensive attention. It is common to perform a plurality of patterning processes in the fabrication of an OTFT array substrate to form a patterned layer structure.
  • An ink jet printing process has recently appeared to prepare the source/drain of an OTFT.
  • the ink jet printing process is a process of forming a desired pattern by printing a melt (i.e., ink droplet) of a material used for pattern production on a region where a pattern is to be formed. Since this process is a direct patterning method, the process can be simplified, cost reduction and production efficiency can be improved.
  • an array substrate including: a substrate; and a pixel structure formed on the substrate, the pixel structure including: a gate line, a data line, a thin film transistor, and a pixel electrode
  • the thin film transistor includes a gate, a gate insulating layer, an active layer, a source and a drain, wherein the gate is electrically connected to the gate line, and the source is electrically connected to the data line
  • the drain electrode is electrically connected to the pixel electrode
  • the pixel structure further includes: an organic insulating layer, the organic insulating layer is located above the gate insulating layer, and has a "W" shape at a position of the thin film transistor a structure, and a source and a drain of the thin film transistor are respectively located at two low recesses of the "W"-shaped structure, and an active layer of the thin film transistor covers the thin film crystal The source and drain of the tube.
  • a display device in another embodiment, includes the array substrate described above.
  • a method of fabricating an array substrate including: forming a gate metal film on a substrate, and forming a gate metal layer by a patterning process; wherein the gate metal layer includes a gate line And a gate of the thin film transistor; forming a gate insulating layer on the substrate to cover the gate metal layer; depositing an organic material thin film on the substrate on which the gate insulating layer is formed, and using a patterning process on the thin film transistor Forming the organic material film into a "W"-shaped structure to form an organic insulating layer; respectively printing ink droplets at two low concave portions of the "W"-shaped structure by an inkjet printing process to form the film a source and a drain of the transistor; forming an active layer of the thin film transistor by a patterning process, the active layer covering a source and a drain of the thin film transistor; in the forming the active layer Forming a passivation layer on the substrate, and forming a via at the same position of the active
  • FIG. 1 is a schematic diagram 1 of a manufacturing process of an array substrate according to an embodiment of the present invention.
  • FIG. 2 is a second schematic diagram of a manufacturing process of an array substrate according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram 3 of a manufacturing process of an array substrate according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram 4 of a manufacturing process of an array substrate according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram 5 of a manufacturing process of an array substrate according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram 6 of a manufacturing process of an array substrate according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram 7 of a manufacturing process of an array substrate according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram 8 of a manufacturing process of an array substrate according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram 9 of a manufacturing process of an array substrate according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram 10 of a manufacturing process of an array substrate according to an embodiment of the present invention
  • FIG. 11 is a schematic diagram of a manufacturing process of an array substrate according to an embodiment of the present invention
  • FIG. 12 is a schematic structural diagram of a manufactured array substrate according to an embodiment of the present invention.
  • an array substrate and a method of fabricating the same are provided for precisely controlling the shape of a source/drain of a thin film transistor formed by an inkjet printing process.
  • a display device including the above array substrate is also provided.
  • an array substrate may include: a substrate 1 (eg, a transparent substrate) and a plurality of pixel structures formed on the substrate 1, each pixel structure including: a gate line, a data line, Thin film transistor and pixel electrode l la.
  • the thin film transistor includes a gate 3a, a gate insulating layer 4, an active layer 9, a source 6 and a drain 7, wherein the gate 3a is electrically connected to the gate line, the source 6 is electrically connected to the data line, and the drain 7 and the pixel
  • the electrode 11a is electrically connected.
  • the pixel structure may further include: an organic insulating layer 5 on the gate insulating layer 4 and having a "mountain” shape structure or a "W" shape structure at the position of the thin film transistor (which has “mountain” or "" W”" cross-sectional shape), the source 6 and the drain 7 of the thin film transistor are respectively located at two low recesses of the "W"-shaped structure, and the active layer 9 of the thin film transistor covers the source 6 and the drain 7 of the thin film transistor .
  • the active layer 9 may be formed of an organic semiconductor, an oxide semiconductor, a silicon semiconductor or the like.
  • the array substrate is an organic thin film transistor array substrate (ie, an OTFT array substrate).
  • the "W"-shaped structure of the organic insulating layer 5 includes the side wall convex portion 51 and the central convex portion 52, and a low concave portion is formed between the side wall convex portion 51 and the central convex portion 52.
  • the source 6 and the drain 7 of the thin film transistor are respectively located at the two low recesses of the "W"-shaped structure, and the upper surfaces of the source 6 and the drain 7 are lower than the upper surface of the central boss 52.
  • the "W"-shaped structure of the organic insulating layer 5 may be a structure with a middle height and a low side on both sides, or a structure with a low middle and two sides high (as shown in FIG. 12), or may be in the middle.
  • the structure equal to the height of the two sides may also be a structure on the left side higher than the right side, the right side is higher than the middle side, etc., but in the embodiment of the present invention, the "W"-shaped structure is not limited to the above list, and may be other possible combination.
  • the upper left portion can be used as a spacer.
  • the shape of the "W" shaped structure can be reasonably set by other means to achieve its additional function as a spacer, that is, the "W" shaped structure can simultaneously serve as a spacer.
  • the material of the organic insulating layer 5 may be an organic photosensitive material or a common organic material, but the embodiment of the invention is not limited thereto.
  • the organic insulating layer 5 having a "W"-shaped structure on the above array substrate provided by the embodiment of the present invention can prevent the flow of ink droplets during the inkjet printing process, thereby accurately controlling the size of the ink droplets. That is, the shape of the source/drain formed by the inkjet printing process is precisely controlled.
  • the "W"-shaped structure of the organic insulating layer 5 is a "W"-shaped structure having a low middle and a high height on both sides, that is, the height of the side wall convex portion 51 is larger than the central convex portion 52.
  • the height, and the active layer 9 of the thin film transistor is disposed inside the "W"-shaped structure, for example, the active layer 9 may be formed of an organic semiconductor material.
  • the above-mentioned low-low, high-side "W"-shaped structure allows the source 6 and the drain 7 to be formed not only by the ink-jet printing process, but also the active layer 9 can be formed by an ink-jet printing process, and "W The raised portion of the glyph structure can be used to prevent the flow of organic semiconductor material. Since the inkjet printing process is simpler than the conventional photolithographic patterning process, the process can be simplified and the manufacturing cost can be reduced.
  • the "W"-shaped structure of the organic insulating layer 5 is a structure in which the middle is low, the two sides are high, and the left side is higher than the right side and the right side is higher than the middle, at this time, the upper portion of the left side can be used as a partition. Use the mat. In this case, the process can be further simplified and the manufacturing cost can be reduced.
  • the pixel structure may further include: a common electrode 2a, the common electrode 2a It is located below the gate insulating layer 4 and is disposed in the same layer as the gate 3a.
  • the same layer arrangement means that the common electrode 2a and the gate electrode 3a are in the same layer of the array substrate, and the thickness of the same is not limited; and both may be formed of the same material or may be formed of different materials.
  • the common electrode 2a, the gate 3a, and the gate line are fabricated using a one-time patterning process.
  • the one-time patterning process refers to a process of patterning using a mask.
  • a transparent conductive material (a material for forming a common electrode) may be deposited on the transparent substrate 1 to form the first transparent conductive film 2, and then one of a metal material such as molybdenum or copper may be deposited (for forming a gate).
  • the material of the line and the gate) is formed to form the gate metal film 3 (see FIG. 1); then, the above two films are formed into the common electrode 2a, the gate electrode 3a, and the gate line by a halftone exposure patterning process (see FIG. 2).
  • the array substrate may not be provided with the pixel electrode 2a. In this case, the array substrate is generally used for a TN type liquid crystal display or an OLED display panel or an electronic paper display panel or the like.
  • the pixel structure may further include: a passivation layer 10 covering the active layer 9, and a pixel electrode 11a formed on the passivation layer 10.
  • the drain electrode 7 of the thin film transistor is electrically connected to the pixel electrode 11a.
  • the drain electrode 7 is electrically connected to the pixel electrode 11a via the passivation layer 10 and the via hole at the same position of the active layer 9.
  • the pixel electrode may be strip-shaped and the common electrode may also be strip-shaped.
  • the common electrode may not be provided, and the pixel electrode is provided in a plate shape or a strip shape.
  • the fact that the pixel electrode (or the common electrode) is strip-shaped means that the pixel electrode (or the common electrode) in one pixel unit is composed of a plurality of strip electrodes.
  • an organic insulating layer is formed on the gate insulating layer, and the organic insulating layer has a "W"-shaped structure at the position of the thin film transistor, and the source of the thin film transistor
  • the drains are respectively located at the two low recesses of the "w"-shaped structure, so the low recess of the "W"-shaped structure can prevent the flow of ink droplets in the inkjet printing process, thereby precisely controlling the size of the ink droplets, that is, precise control The shape of the TFT source/drain formed by the inkjet printing process.
  • the organic insulating layer has a "W"-shaped structure with a low middle and high sides at the position of the thin film transistor, and the active layer of the thin film transistor is disposed inside the "W"-shaped structure, "W"
  • the inner side of the glyph structure prevents the flow of the organic semiconductor material, so that the active layer can be formed by an inkjet printing process, and the inkjet printing process is simpler than the conventional photolithographic patterning process; in addition, the gate metal layer and the common electrode This is done in a patterning process, which simplifies the manufacturing process, reduces manufacturing costs, and increases productivity.
  • a display device comprising any of the array substrates of the above embodiments.
  • the display device provided by the embodiment of the present invention may be a product or component having any display function such as a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, or the like.
  • the display device provided by the embodiment of the present invention includes the above array substrate, it is also possible to precisely control the shape of the TFT source/drain formed by the inkjet printing process and the shape of the active layer formed by the inkjet printing process; It can also be done using a patterning process when forming the gate and the common electrode.
  • a method for fabricating the above array substrate comprising: forming a gate metal film 3 on the substrate 1, and forming a gate metal layer by a patterning process, the gate metal layer comprising: a gate line And a gate 3a of the thin film transistor;
  • the method further includes: depositing a first transparent conductive film 2 on the substrate 1 to form a common electrode 2a, wherein the gate is formed
  • the patterning process of the metal layer and the common electrode 2a is the same halftone exposure patterning process.
  • a first transparent conductive film 2 and a gate metal film 3 are sequentially deposited on a substrate 1, and a photoresist 8 is coated on the gate metal film 3.
  • the photoresist 8 is exposed by a halftone mask, and then developed to obtain a photoresist mask, wherein the region A is a photoresist completely removed region, and the region B is light.
  • the photoresist is completely reserved, and the region C is a photoresist partial retention region; then, the portion of the first transparent conductive film 2 and the gate metal film 3 in the photoresist completely removed region A is removed by etching or the like, A pattern of the gate 3a and the gate line.
  • the etched array substrate shown in FIG. 2 is subjected to ashing treatment, To completely remove the photoresist of the photoresist portion retaining region c, and partially retain the photoresist of the photoresist completely remaining region B; thereafter, etching the gate metal film 3 in the photoresist by an etching process A portion of the portion C is reserved to obtain the common electrode 2a of the OTFT array substrate; then, it is also necessary to strip off the photoresist on the gate 3a and the gate line, that is, the photoresist in the photoresist completely remaining region B.
  • a gate insulating layer 4 is formed on the substrate 1 to cover the gate metal layer; in the embodiment of the present invention, plasma enhanced chemical vapor deposition (plasma enhanced chemical Vapor) may be utilized in this step.
  • PECVD plasma enhanced chemical vapor deposition
  • an organic photosensitive material film 5 is deposited on the substrate 1 on which the gate insulating layer 4 is formed, and the organic photosensitive material film 5 is formed into a "W"-shaped structure in the thin film transistor region by a patterning process. Forming an organic insulating layer 5;
  • the patterning process employed in this step is a halftone exposure patterning process.
  • the "W" glyph structure here may be a structure with a middle height and a low side on both sides, or a structure with a low middle and a high height on both sides. It should be noted, however, that in the embodiment of the present invention, referring to FIG. 5, the "W"-shaped structure is, for example, a structure having a low middle and a high height on both sides.
  • this step may also be as follows: depositing an organic material film 5 on the substrate 1 on which the gate insulating layer 4 is formed, applying a photoresist, and using a halftone mask A patterning process (including exposure, development, etching, ashing, etching, etc.) forms the organic material film 5 into a "W"-shaped structure in the thin film transistor region to form an organic insulating layer 5.
  • a halftone mask A patterning process including exposure, development, etching, ashing, etching, etc.
  • A4 referring to FIG. 6, using inkjet printing process, respectively, printing ink droplets at two low recesses of the "W"-shaped structure of the organic insulating layer 5 to form the source 6 and the drain 7 of the thin film transistor;
  • A5 refer to FIG. 7, forming a active layer of the thin film transistor by using one patterning process, and the active layer 9 covers the source 6 and the drain 7 of the thin film transistor;
  • this step may be, for example, printing ink on the inner side of the "W"-shaped structure by an inkjet printing process.
  • the active layer is an organic semiconductor layer.
  • the active layer 9 can be formed by a conventional photolithography process.
  • the active layer film may also be formed by deposition, sputtering, coating, or the like, and the pattern of the active layer is formed by a patterning process.
  • the active layer may be a silicon semiconductor material, an oxide semiconductor material, or an organic semiconductor material.
  • a passivation layer 10 is formed on the substrate 1 on which the active layer 9 is formed, and a via hole penetrating the active layer 9 and the passivation layer 10 is formed over the drain electrode 7 of the thin film transistor. ;
  • an organic photosensitive material (which may be a common organic material or an organic photosensitive material) may be used on the OTFT array substrate shown in FIG. 7, and the embodiment of the present invention does not.
  • the passivation layer 10 is formed, and a via hole is formed over the drain electrode 7 of the thin film transistor by a patterning process.
  • the passivation layer 10 with vias can also be formed directly by an ink jet printing process.
  • the active layer 9 under the via hole in Fig. 8 is etched away so that the drain electrode 7 of the thin film transistor is exposed to be electrically connected to the pixel electrode 11a.
  • a second transparent conductive film 11 is deposited on the passivation layer 10, and a pixel electrode 11a is formed by a patterning process, and the pixel electrode 11a is electrically connected to the drain 7 of the thin film transistor through the via hole. connection.
  • the second transparent conductive film 11 may be formed by sputtering; as shown in FIG. 11, a photoresist is coated on the second transparent conductive film 11. 8.
  • the photoresist 8 is exposed and developed by a photolithography process to form a photoresist mask; as shown in FIG. 12, the second transparent conductive film 11 in the completely removed region of the photoresist is removed by etching to form The pixel electrode l la.
  • the halftone exposure patterning process can be implemented by a Half Tone Mask (HTM) or a GrayTone Mask (GTM).
  • HTM Half Tone Mask
  • GTM GrayTone Mask
  • the organic photosensitive material film in the thin film transistor region is formed into a "W" by forming an organic photosensitive material film on the gate insulating layer and using a halftone exposure patterning process.
  • the organic insulating layer of the glyph structure makes it possible to print the ink droplets at the two low recesses of the "W"-shaped structure by the ink jet printing process to precisely control the size of the source/drain; further, in some embodiments of the present invention,
  • the active layer (which is an organic semiconductor material) is grown on the inner side of the "W"-shaped structure of the organic insulating layer, which is more advantageous for the fabrication of the active layer than the prior art; in addition, the gate metal layer and the common electrode are once This is done in the patterning process, which simplifies the manufacturing process, reduces manufacturing costs and increases productivity.

Abstract

Disclosed in the embodiments of the present invention are an array substrate, method for manufacturing same, and a display device. The array substrate comprises a substrate, and a pixel structure formed on the substrate. The pixel structure comprises a gate line, a data line, a thin film transistor and a pixel electrode. The thin film transistor comprises a gate, a gate insulation layer, an active layer, a source and a drain and wherein, the gate and the gate line are electrically connected, the source and the data line are electrically connected, and the drain and the pixel electrode are electrically connected. The pixel structure also comprises an organic insulation layer, which is located on the gate insulation layer, with W-shaped structure in the position of the thin film transistor. And the source and drain of the thin film transistor are located in two recessed portions of the W-shaped structure respectively. And the active layer of the thin film transistor covers the source and drain of the thin film transistor.

Description

阵列基板及其制造方法和显示装置 技术领域  Array substrate, manufacturing method thereof and display device
本发明的实施例涉及一种阵列基板及其制造方法和显示装置。 背景技术  Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device. Background technique
有机薄膜晶体管（ Organic Thin Film Transistor, OTFT )具有适合大面积 加工、适用于柔性基板等优点，在平板显示领域显现出应用前景。因此， OTFT 阵列基板的研究与开发受到广泛关注。 通常在 OTFT阵列基板的制造中需要 执行多次构图工艺， 以形成图案化的层结构。 目前出现一种喷墨打印工艺， 用以制备 OTFT的源 /漏极。喷墨打印工艺是通过将制造图案所用材料的熔浆 (即墨滴）打印在需要制造图案的区域以形成所需图案的工艺。 由于这种工 艺是一种直接图案化的方法， 故可简化工艺， 降低成本和提高生产效率。  Organic Thin Film Transistor (OTFT) has advantages such as being suitable for large-area processing and being suitable for flexible substrates, and has shown application prospects in the field of flat panel display. Therefore, research and development of OTFT array substrates have received extensive attention. It is common to perform a plurality of patterning processes in the fabrication of an OTFT array substrate to form a patterned layer structure. An ink jet printing process has recently appeared to prepare the source/drain of an OTFT. The ink jet printing process is a process of forming a desired pattern by printing a melt (i.e., ink droplet) of a material used for pattern production on a region where a pattern is to be formed. Since this process is a direct patterning method, the process can be simplified, cost reduction and production efficiency can be improved.
在实现上述利用喷墨打印工艺形成 OTFT的源 /漏极的过程中，发明人发 现现有技术中存在问题。 例如，在打印过程中， 由于墨滴的表面张力等原因， 难以精确控制墨滴的尺寸， 这就导致利用喷墨打印工艺所形成的 OTFT 源 / 漏极的形状难以精确控制， 从而影响到 OTFT的质量， 进而会影响到 OTFT 液晶显示器的质量。 当然， 其他类型的阵列基板（即非 OTFT阵列基板） ， 在利用打印工艺制造源 /漏电极时， 也会出现上述问题。 发明内容  In carrying out the above-described process of forming the source/drain of the OTFT by the ink-jet printing process, the inventors have found problems in the prior art. For example, in the printing process, it is difficult to precisely control the size of the ink droplets due to the surface tension of the ink droplets, etc., which causes the shape of the OTFT source/drain formed by the inkjet printing process to be difficult to precisely control, thereby affecting the OTFT. The quality, which in turn affects the quality of OTFT LCDs. Of course, other types of array substrates (i.e., non-OTFT array substrates) may also have the above problems when the source/drain electrodes are fabricated by a printing process. Summary of the invention
在本发明的一个实施例中， 提供了一种阵列基板， 其包括： 基板； 以及 在所述基板上形成的像素结构， 所述像素结构包括： 栅线、 数据线、 薄膜晶 体管和像素电极， 所述薄膜晶体管包括栅极、 栅绝缘层、 有源层、 源极和漏 极， 其中， 所述栅极与所述栅线电连接， 所述源极与所述数据线电连接， 所 述漏极与所述像素电极电连接， 其中， 所述像素结构还包括： 有机绝缘层， 所述有机绝缘层位于所述栅绝缘层上方， 并且在所述薄膜晶体管的位置处具 有 "W" 字形结构， 以及所述薄膜晶体管的源极和漏极分别位于所述 "W" 字形结构的两个低凹部处， 并且所述薄膜晶体管的有源层覆盖所述薄膜晶体 管的源极和漏极。 In an embodiment of the present invention, an array substrate is provided, including: a substrate; and a pixel structure formed on the substrate, the pixel structure including: a gate line, a data line, a thin film transistor, and a pixel electrode, The thin film transistor includes a gate, a gate insulating layer, an active layer, a source and a drain, wherein the gate is electrically connected to the gate line, and the source is electrically connected to the data line, The drain electrode is electrically connected to the pixel electrode, wherein the pixel structure further includes: an organic insulating layer, the organic insulating layer is located above the gate insulating layer, and has a "W" shape at a position of the thin film transistor a structure, and a source and a drain of the thin film transistor are respectively located at two low recesses of the "W"-shaped structure, and an active layer of the thin film transistor covers the thin film crystal The source and drain of the tube.
在本发明的另一个实施例中， 提供了一种显示装置， 其包括上述阵列基 板。  In another embodiment of the invention, a display device is provided that includes the array substrate described above.
在本发明的另一个实施例中，提供了一种阵列基板的制造方法，其包括： 在基板上形成栅金属薄膜， 并通过构图工艺形成栅金属层； 其中， 所述栅金 属层包括栅线和薄膜晶体管的栅极； 在所述基板上形成栅绝缘层以覆盖所述 栅金属层； 在形成有所述栅绝缘层的所述基板上沉积有机材料薄膜， 并利用 一次构图工艺在薄膜晶体管区域将所述有机材料薄膜制成 "W" 字形结构， 以形成有机绝缘层； 利用喷墨打印工艺分别在所述 "W" 字形结构的两个低 凹部处打印墨滴， 以形成所述薄膜晶体管的源极和漏极； 利用一次构图工艺 形成所述薄膜晶体管的有源层， 所述有源层覆盖所述薄膜晶体管的源极和漏 极； 在形成有所述有源层的所述基板上形成钝化层， 并在所述薄膜晶体管的 漏极上方的所述有源层和所述钝化层的同一位置处形成过孔； 在所述钝化层 上沉积第二透明导电薄膜， 并通过构图工艺形成像素电极， 所述像素电极通 过所述过孔而与所述薄膜晶体管的漏极电连接。 附图说明  In another embodiment of the present invention, a method of fabricating an array substrate is provided, including: forming a gate metal film on a substrate, and forming a gate metal layer by a patterning process; wherein the gate metal layer includes a gate line And a gate of the thin film transistor; forming a gate insulating layer on the substrate to cover the gate metal layer; depositing an organic material thin film on the substrate on which the gate insulating layer is formed, and using a patterning process on the thin film transistor Forming the organic material film into a "W"-shaped structure to form an organic insulating layer; respectively printing ink droplets at two low concave portions of the "W"-shaped structure by an inkjet printing process to form the film a source and a drain of the transistor; forming an active layer of the thin film transistor by a patterning process, the active layer covering a source and a drain of the thin film transistor; in the forming the active layer Forming a passivation layer on the substrate, and forming a via at the same position of the active layer and the passivation layer over the drain of the thin film transistor; Depositing a second transparent conductive film, and the pixel electrode is formed by a patterning process, the pixel electrode through the via hole is electrically connected to the drain electrode of the thin film transistor. DRAWINGS
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。  In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below. It is obvious that the drawings in the following description relate only to some embodiments of the present invention, and are not intended to limit the present invention. .
图 1为本发明实施例提供的阵列基板的制造过程示意图一；  1 is a schematic diagram 1 of a manufacturing process of an array substrate according to an embodiment of the present invention;
图 2为本发明实施例提供的阵列基板的制造过程示意图二；  2 is a second schematic diagram of a manufacturing process of an array substrate according to an embodiment of the present invention;
图 3为本发明实施例提供的阵列基板的制造过程示意图三；  3 is a schematic diagram 3 of a manufacturing process of an array substrate according to an embodiment of the present invention;
图 4为本发明实施例提供的阵列基板的制造过程示意图四；  4 is a schematic diagram 4 of a manufacturing process of an array substrate according to an embodiment of the present invention;
图 5为本发明实施例提供的阵列基板的制造过程示意图五；  5 is a schematic diagram 5 of a manufacturing process of an array substrate according to an embodiment of the present invention;
图 6为本发明实施例提供的阵列基板的制造过程示意图六；  6 is a schematic diagram 6 of a manufacturing process of an array substrate according to an embodiment of the present invention;
图 7为本发明实施例提供的阵列基板的制造过程示意图七；  7 is a schematic diagram 7 of a manufacturing process of an array substrate according to an embodiment of the present invention;
图 8为本发明实施例提供的阵列基板的制造过程示意图八；  8 is a schematic diagram 8 of a manufacturing process of an array substrate according to an embodiment of the present invention;
图 9为本发明实施例提供的阵列基板的制造过程示意图九；  FIG. 9 is a schematic diagram 9 of a manufacturing process of an array substrate according to an embodiment of the present invention; FIG.
图 10为本发明实施例提供的阵列基板的制造过程示意图十； 图 11为本发明实施例提供的阵列基板的制造过程示意图十一； 图 12为本发明实施例提供的制造完成的阵列基板的结构示意图。 10 is a schematic diagram 10 of a manufacturing process of an array substrate according to an embodiment of the present invention; FIG. 11 is a schematic diagram of a manufacturing process of an array substrate according to an embodiment of the present invention; FIG. 12 is a schematic structural diagram of a manufactured array substrate according to an embodiment of the present invention.
附图标记：  Reference mark:
1-基板， 2-第一透明导电薄膜， 2a-公共电极 ， 3-栅金属薄膜， 3a-栅极， 4-栅绝缘层， 5-有机绝缘层， 6-源极， 7-漏极， 8-光刻胶， 9-有源层， 10-钝化 层， 11-第二透明导电薄膜， 11a-像素电极， 51-侧壁凸起部， 52-中心凸起部。 具体实施方式  1-substrate, 2-first transparent conductive film, 2a-common electrode, 3-gate metal film, 3a-gate, 4-gate insulating layer, 5-organic insulating layer, 6-source, 7-drain, 8-photoresist, 9-active layer, 10-passivation layer, 11-second transparent conductive film, 11a-pixel electrode, 51-side wall bump, 52-center bump. detailed description
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。  The technical solutions of the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings of the embodiments of the present invention. It is apparent that the described embodiments are part of the embodiments of the invention, rather than all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the described embodiments of the present invention without departing from the scope of the invention are within the scope of the invention.
在本发明的实施例中， 提供了一种阵列基板及其制造方法， 用以精确控 制利用喷墨打印工艺所形成的薄膜晶体管的源 /漏极的形状。在本发明的实施 例中， 还提供了包括上述阵列基板的显示装置。  In an embodiment of the present invention, an array substrate and a method of fabricating the same are provided for precisely controlling the shape of a source/drain of a thin film transistor formed by an inkjet printing process. In an embodiment of the present invention, a display device including the above array substrate is also provided.
下面，参考图 1至图 12详细说明本发明的实施例提供的阵列基板及其制 造方法。  Hereinafter, an array substrate and a method of fabricating the same according to embodiments of the present invention will be described in detail with reference to FIGS. 1 through 12.
如图 12所示，本发明的实施例提供的阵列基板可以包括：基板 1 (例如， 透明基板）以及在基板 1上形成的多个像素结构，每个像素结构包括： 栅线、 数据线、 薄膜晶体管和像素电极 l la。 薄膜晶体管包括栅极 3a、 栅绝缘层 4、 有源层 9、 源极 6和漏极 7 , 其中， 栅极 3a与栅线电连接， 源极 6与数据线 电连接， 漏极 7与像素电极 11a电连接。 此外， 像素结构还可以包括： 有机 绝缘层 5, 有机绝缘层 5位于栅绝缘层 4上并且在薄膜晶体管的位置处具有 "山"字形结构或 "W"字形结构（其具有 "山"或 "W"字形的截面形状）， 薄膜晶体管的源极 6和漏极 7分别位于 "W" 字形结构的两个低凹部处， 薄 膜晶体管的有源层 9覆盖薄膜晶体管的源极 6和漏极 7。  As shown in FIG. 12, an array substrate provided by an embodiment of the present invention may include: a substrate 1 (eg, a transparent substrate) and a plurality of pixel structures formed on the substrate 1, each pixel structure including: a gate line, a data line, Thin film transistor and pixel electrode l la. The thin film transistor includes a gate 3a, a gate insulating layer 4, an active layer 9, a source 6 and a drain 7, wherein the gate 3a is electrically connected to the gate line, the source 6 is electrically connected to the data line, and the drain 7 and the pixel The electrode 11a is electrically connected. In addition, the pixel structure may further include: an organic insulating layer 5 on the gate insulating layer 4 and having a "mountain" shape structure or a "W" shape structure at the position of the thin film transistor (which has "mountain" or "" W"" cross-sectional shape), the source 6 and the drain 7 of the thin film transistor are respectively located at two low recesses of the "W"-shaped structure, and the active layer 9 of the thin film transistor covers the source 6 and the drain 7 of the thin film transistor .
在本发明的实施例中， 例如， 有源层 9可以由有机半导体、 氧化物半导 体或硅半导体等形成。 当有源层 9由有机半导体形成时， 阵列基板为有机薄 膜晶体管阵列基板（即 OTFT阵列基板 ) 。 在本发明的实施例中， 有机绝缘层 5的 "W" 字形结构包括侧壁凸起部 51和中心凸起部 52,在侧壁凸起部 51和中心凸起部 52之间形成低凹部。薄 膜晶体管的源极 6和漏极 7分别位于 "W" 字形结构的两个低凹部处， 并且 源极 6和漏极 7的上表面低于中心凸起部 52的上表面。 In the embodiment of the invention, for example, the active layer 9 may be formed of an organic semiconductor, an oxide semiconductor, a silicon semiconductor or the like. When the active layer 9 is formed of an organic semiconductor, the array substrate is an organic thin film transistor array substrate (ie, an OTFT array substrate). In the embodiment of the present invention, the "W"-shaped structure of the organic insulating layer 5 includes the side wall convex portion 51 and the central convex portion 52, and a low concave portion is formed between the side wall convex portion 51 and the central convex portion 52. . The source 6 and the drain 7 of the thin film transistor are respectively located at the two low recesses of the "W"-shaped structure, and the upper surfaces of the source 6 and the drain 7 are lower than the upper surface of the central boss 52.
在本发明的实施例中， 有机绝缘层 5的 "W" 字形结构可以是中间高、 两边低的结构， 也可以是中间低、 两边高的结构（如图 12所示）， 还可以是 中间与两边高度相等的结构， 还可以是左边高于右边， 右边高于中间的结构 等， 但是在本发明的实施例中 "W" 字形结构并不以上述列举为限， 还可以 为其他可能的组合。  In the embodiment of the present invention, the "W"-shaped structure of the organic insulating layer 5 may be a structure with a middle height and a low side on both sides, or a structure with a low middle and two sides high (as shown in FIG. 12), or may be in the middle. The structure equal to the height of the two sides may also be a structure on the left side higher than the right side, the right side is higher than the middle side, etc., but in the embodiment of the present invention, the "W"-shaped structure is not limited to the above list, and may be other possible combination.
在本发明的实施例中， 例如， 当 "W" 字形结构为左边高于右边， 右边 高于中间的结构时， 左边的高出部分可以作为隔垫物使用。 本领域的技术人 员可以理解， 可以通过其他方式合理设置 "W" 字形结构的形状， 实现其作 为隔垫物的附加功能， 即 "W" 字形结构可以同时作为隔垫物。  In the embodiment of the present invention, for example, when the "W"-shaped structure is a structure whose left side is higher than the right side and the right side is higher than the middle, the upper left portion can be used as a spacer. Those skilled in the art will appreciate that the shape of the "W" shaped structure can be reasonably set by other means to achieve its additional function as a spacer, that is, the "W" shaped structure can simultaneously serve as a spacer.
在本发明的实施例中， 有机绝缘层 5的材料可以为有机光敏材料或普通 有机材料， 但是本发明的实施例不限于此。  In the embodiment of the invention, the material of the organic insulating layer 5 may be an organic photosensitive material or a common organic material, but the embodiment of the invention is not limited thereto.
在本发明的实施例提供的上述阵列基板上具有 "W" 字形结构的有机绝 缘层 5, 其低凹部处可以防止在喷墨打印工艺时墨滴的流动， 从而能够精确 控制墨滴的尺寸， 即精确控制利用喷墨打印工艺所形成的源 /漏极的形状。  The organic insulating layer 5 having a "W"-shaped structure on the above array substrate provided by the embodiment of the present invention can prevent the flow of ink droplets during the inkjet printing process, thereby accurately controlling the size of the ink droplets. That is, the shape of the source/drain formed by the inkjet printing process is precisely controlled.
在本实施例中，如图 12所示，有机绝缘层 5的 "W"字形结构为中间低、 两边高的 "W" 字形结构， 即侧壁凸起部 51的高度大于中心凸起部 52的高 度， 并且薄膜晶体管的有源层 9设置在 "W" 字形结构的内侧， 例如， 有源 层 9可以由有机半导体材料形成。 在此情况下， 上述中间低、 两边高的 "W" 字形结构使得不仅可以利用喷墨打印工艺形成源极 6和漏极 7, 而且可以利 用喷墨打印工艺形成有源层 9, 并且 "W" 字形结构的凸起部可以用来防止 有机半导体材料的流动。 由于喷墨打印工艺较传统的光刻构图工艺而言更为 简单， 因此可以简化工艺以及降低制造成本。  In the present embodiment, as shown in FIG. 12, the "W"-shaped structure of the organic insulating layer 5 is a "W"-shaped structure having a low middle and a high height on both sides, that is, the height of the side wall convex portion 51 is larger than the central convex portion 52. The height, and the active layer 9 of the thin film transistor is disposed inside the "W"-shaped structure, for example, the active layer 9 may be formed of an organic semiconductor material. In this case, the above-mentioned low-low, high-side "W"-shaped structure allows the source 6 and the drain 7 to be formed not only by the ink-jet printing process, but also the active layer 9 can be formed by an ink-jet printing process, and "W The raised portion of the glyph structure can be used to prevent the flow of organic semiconductor material. Since the inkjet printing process is simpler than the conventional photolithographic patterning process, the process can be simplified and the manufacturing cost can be reduced.
在本发明的实施例中， 当有机绝缘层 5的 "W" 字形结构为中间低、 两 边高并且左边高于右边、 右边高于中间的结构时， 此时， 左边的高出部分可 以作为隔垫物使用。 在此情况下， 可以进一步简化工艺以及降低制造成本。  In the embodiment of the present invention, when the "W"-shaped structure of the organic insulating layer 5 is a structure in which the middle is low, the two sides are high, and the left side is higher than the right side and the right side is higher than the middle, at this time, the upper portion of the left side can be used as a partition. Use the mat. In this case, the process can be further simplified and the manufacturing cost can be reduced.
在本发明的实施例中， 像素结构还可以包括： 公共电极 2a, 公共电极 2a 位于栅绝缘层 4的下方， 并与栅极 3a同层设置。 在此， 同层设置是指公共电 极 2a与栅极 3a处于阵列基板的同一层， 并不限定二者厚度相同； 并且， 二 者可以由相同的材料形成，也可以由不同的材料形成。在本发明的实施例中， 例如， 公共电极 2a、 栅极 3a和栅线利用一次构图工艺制造完成。 在此， 一 次构图工艺是指使用一个掩膜板完成构图的工艺。 举例而言， 可以在透明基 板 1上先沉积透明导电材料（用于形成公共电极的材料） 以形成第一透明导 电薄膜 2, 再沉积钼、 铜等金属材料中的一种（用于形成栅线和栅极的材料） 以形成栅金属薄膜 3 (参见图 1 )； 然后， 利用一次半色调曝光构图工艺将上 述两薄膜形成公共电极 2a、 栅极 3a和栅线（参见图 2 ) 。 如图 12所示， 由 于第一透明导电薄膜 2在栅金属薄膜 3的下方，并且使用的是一次构图工艺， 故最终形成的栅极 3a和栅线下方仍会保留第一透明导电薄膜 2的与其图案一 致的部分。 在本发明的实施例中， 阵列基板也可以不设置像素电极 2a。 在此 情况下， 阵列基板一般用于 TN型液晶显示器或 OLED显示面板或电子纸显 示面板等。 In an embodiment of the present invention, the pixel structure may further include: a common electrode 2a, the common electrode 2a It is located below the gate insulating layer 4 and is disposed in the same layer as the gate 3a. Here, the same layer arrangement means that the common electrode 2a and the gate electrode 3a are in the same layer of the array substrate, and the thickness of the same is not limited; and both may be formed of the same material or may be formed of different materials. In an embodiment of the present invention, for example, the common electrode 2a, the gate 3a, and the gate line are fabricated using a one-time patterning process. Here, the one-time patterning process refers to a process of patterning using a mask. For example, a transparent conductive material (a material for forming a common electrode) may be deposited on the transparent substrate 1 to form the first transparent conductive film 2, and then one of a metal material such as molybdenum or copper may be deposited (for forming a gate). The material of the line and the gate) is formed to form the gate metal film 3 (see FIG. 1); then, the above two films are formed into the common electrode 2a, the gate electrode 3a, and the gate line by a halftone exposure patterning process (see FIG. 2). As shown in FIG. 12, since the first transparent conductive film 2 is under the gate metal film 3 and a patterning process is used, the finally formed gate 3a and the gate line still retain the first transparent conductive film 2 The part that matches the pattern. In the embodiment of the present invention, the array substrate may not be provided with the pixel electrode 2a. In this case, the array substrate is generally used for a TN type liquid crystal display or an OLED display panel or an electronic paper display panel or the like.
在本发明的实施例中， 像素结构还可以包括： 钝化层 10, 钝化层 10覆 盖有源层 9, 并且像素电极 11a形成在钝化层 10上。 薄膜晶体管的漏极 7与 像素电极 11a电连接， 例如， 漏极 7与像素电极 11a通过钝化层 10、 有源层 9在同一位置处的过孔电连接。 或者， 像素电极可以为条状并且公共电极也为条状。 在本发明的一些实施例 中， 也可以不设置公共电极， 像素电极设置为板状或者条状。 在此， 像素电 极（或公共电极）为条状是指一个像素单元内的像素电极（或公共电极） 由 多个条状电极构成。  In an embodiment of the present invention, the pixel structure may further include: a passivation layer 10 covering the active layer 9, and a pixel electrode 11a formed on the passivation layer 10. The drain electrode 7 of the thin film transistor is electrically connected to the pixel electrode 11a. For example, the drain electrode 7 is electrically connected to the pixel electrode 11a via the passivation layer 10 and the via hole at the same position of the active layer 9. Alternatively, the pixel electrode may be strip-shaped and the common electrode may also be strip-shaped. In some embodiments of the present invention, the common electrode may not be provided, and the pixel electrode is provided in a plate shape or a strip shape. Here, the fact that the pixel electrode (or the common electrode) is strip-shaped means that the pixel electrode (or the common electrode) in one pixel unit is composed of a plurality of strip electrodes.
如上所述， 在本发明的实施例提供的阵列基板中， 在栅绝缘层上形成有 机绝缘层， 并且该有机绝缘层在薄膜晶体管的位置处具有 "W" 字形结构， 薄膜晶体管的源极和漏极分别位于 "w"字形结构的两个低凹部处，因此" W" 字形结构的低凹部可以防止在喷墨打印工艺中的墨滴的流动， 从而精确控制 墨滴的尺寸， 即精确控制利用喷墨打印工艺所形成的 TFT 源 /漏极的形状。 此外， 由于有机绝缘层在薄膜晶体管的位置处具有中间低、 两边高的 "W" 字形结构，并且薄膜晶体管的有源层设置在 "W"字形结构的内侧， 因此 "W" 字形结构的内侧可以防止有机半导体材料的流动， 从而有源层可以通过喷墨 打印工艺形成， 而喷墨打印工艺较传统的光刻构图工艺而言更为简单； 此外， 栅金属层和公共电极在一次构图工艺中完成， 这样可以简化制造工艺， 降低 制造成本、 提高生产率。 As described above, in the array substrate provided by the embodiment of the present invention, an organic insulating layer is formed on the gate insulating layer, and the organic insulating layer has a "W"-shaped structure at the position of the thin film transistor, and the source of the thin film transistor The drains are respectively located at the two low recesses of the "w"-shaped structure, so the low recess of the "W"-shaped structure can prevent the flow of ink droplets in the inkjet printing process, thereby precisely controlling the size of the ink droplets, that is, precise control The shape of the TFT source/drain formed by the inkjet printing process. In addition, since the organic insulating layer has a "W"-shaped structure with a low middle and high sides at the position of the thin film transistor, and the active layer of the thin film transistor is disposed inside the "W"-shaped structure, "W" The inner side of the glyph structure prevents the flow of the organic semiconductor material, so that the active layer can be formed by an inkjet printing process, and the inkjet printing process is simpler than the conventional photolithographic patterning process; in addition, the gate metal layer and the common electrode This is done in a patterning process, which simplifies the manufacturing process, reduces manufacturing costs, and increases productivity.
在本发明的实施例中， 还提供了一种显示装置， 其包括上述实施例中的 任一阵列基板。 本发明实施例提供的显示装置可以为液晶面板、 电子纸、 OLED面板、 液晶电视、 液晶显示器、 数码相框、 手机、 平板电脑等具有任 何显示功能的产品或部件。  In an embodiment of the invention, there is also provided a display device comprising any of the array substrates of the above embodiments. The display device provided by the embodiment of the present invention may be a product or component having any display function such as a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, or the like.
本发明实施例提供的显示装置由于包括上述阵列基板， 因此同样可以精 确控制利用喷墨打印工艺所形成的 TFT 源 /漏极的形状以及利用喷墨打印工 艺所形成的有源层的形状； 并且， 在形成栅极和公共电极时还可以使用一次 构图工艺完成。  Since the display device provided by the embodiment of the present invention includes the above array substrate, it is also possible to precisely control the shape of the TFT source/drain formed by the inkjet printing process and the shape of the active layer formed by the inkjet printing process; It can also be done using a patterning process when forming the gate and the common electrode.
在本发明的实施例中，还提供了上述阵列基板的制造方法， 例如， 包括： Al、 在基板 1上形成栅金属薄膜 3 , 并通过构图工艺形成栅金属层， 栅 金属层包括： 栅线和薄膜晶体管的栅极 3a;  In an embodiment of the present invention, a method for fabricating the above array substrate is further provided, for example, comprising: forming a gate metal film 3 on the substrate 1, and forming a gate metal layer by a patterning process, the gate metal layer comprising: a gate line And a gate 3a of the thin film transistor;
在本发明的实施例中， 为简化制造工艺， 在此步骤中在形成栅金属薄膜 3之前还可以包括： 在基板 1 上沉积第一透明导电薄膜 2, 以形成公共电极 2a, 其中，形成栅金属层和公共电极 2a的构图工艺为同一次半色调曝光构图 工艺。  In an embodiment of the present invention, in order to simplify the manufacturing process, before the forming the gate metal film 3 in this step, the method further includes: depositing a first transparent conductive film 2 on the substrate 1 to form a common electrode 2a, wherein the gate is formed The patterning process of the metal layer and the common electrode 2a is the same halftone exposure patterning process.
下面针对依次沉积第一透明导电薄膜 2、 栅金属薄膜 3并利用一次构图 工艺将两薄膜形成公共电极 2a和栅金属层 (包括栅极 3a和栅线 ) 的过程进 行详述。  The following is a detailed description of the process of sequentially depositing the first transparent conductive film 2, the gate metal film 3, and forming the two films into the common electrode 2a and the gate metal layer (including the gate electrode 3a and the gate line) by one patterning process.
首先， 如图 1所示， 在基板 1上依次沉积第一透明导电薄膜 2和栅金属 薄膜 3 , 并在栅金属薄膜 3上涂布光刻胶 8。  First, as shown in Fig. 1, a first transparent conductive film 2 and a gate metal film 3 are sequentially deposited on a substrate 1, and a photoresist 8 is coated on the gate metal film 3.
接下来， 如图 2所示， 利用半色调掩模板对光刻胶 8进行曝光， 之后进 行显影， 以获得光刻胶掩模， 其中， 区域 A为光刻胶完全去除区， 区域 B为 光刻胶完全保留区， 区域 C为光刻胶部分保留区； 然后， 通过刻蚀等工艺， 去除掉第一透明导电薄膜 2和栅金属薄膜 3处于光刻胶完全去除区 A内的部 分， 得到栅极 3a和栅线的图案。  Next, as shown in FIG. 2, the photoresist 8 is exposed by a halftone mask, and then developed to obtain a photoresist mask, wherein the region A is a photoresist completely removed region, and the region B is light. The photoresist is completely reserved, and the region C is a photoresist partial retention region; then, the portion of the first transparent conductive film 2 and the gate metal film 3 in the photoresist completely removed region A is removed by etching or the like, A pattern of the gate 3a and the gate line.
接下来， 如图 3所示， 对图 2所示的刻蚀后的阵列基板进行灰化处理， 以完全去除掉光刻胶部分保留区 c的光刻胶， 而部分地保留光刻胶完全保留 区 B的光刻胶； 之后， 利用刻蚀工艺， 刻蚀掉栅金属薄膜 3处于光刻胶部分 保留区 C内的部分， 以得到 OTFT阵列基板的公共电极 2a; 然后， 还需要剥 离掉栅极 3a和栅线上的光刻胶， 即光刻胶完全保留区 B的光刻胶。 Next, as shown in FIG. 3, the etched array substrate shown in FIG. 2 is subjected to ashing treatment, To completely remove the photoresist of the photoresist portion retaining region c, and partially retain the photoresist of the photoresist completely remaining region B; thereafter, etching the gate metal film 3 in the photoresist by an etching process A portion of the portion C is reserved to obtain the common electrode 2a of the OTFT array substrate; then, it is also necessary to strip off the photoresist on the gate 3a and the gate line, that is, the photoresist in the photoresist completely remaining region B.
A2、 如图 4所示， 在基板 1上形成栅绝缘层 4以覆盖栅金属层； 在本发明的实施例中， 在此步骤中可以利用等离子体增强化学汽相沉积 法（ Plasma Enhanced Chemical Vapor Deposition, PECVD )在栅线和栅极上 沉积厚度为 1000人至 6000人的氮化硅、氧化硅和氮氧化硅等材料中的至少一 种， 以形成栅绝缘层 4。  A2, as shown in FIG. 4, a gate insulating layer 4 is formed on the substrate 1 to cover the gate metal layer; in the embodiment of the present invention, plasma enhanced chemical vapor deposition (plasma enhanced chemical Vapor) may be utilized in this step. Deposition, PECVD) depositing at least one of silicon nitride, silicon oxide, silicon oxynitride or the like having a thickness of 1,000 to 6,000 on the gate line and the gate to form the gate insulating layer 4.
A3、 如图 5所示， 在形成有栅绝缘层 4的基板 1上沉积有机光敏材料薄 膜 5,并利用一次构图工艺在薄膜晶体管区域将有机光敏材料薄膜 5制成" W" 字形结构， 以形成有机绝缘层 5;  A3. As shown in FIG. 5, an organic photosensitive material film 5 is deposited on the substrate 1 on which the gate insulating layer 4 is formed, and the organic photosensitive material film 5 is formed into a "W"-shaped structure in the thin film transistor region by a patterning process. Forming an organic insulating layer 5;
在本发明的实施例中， 在此步骤中所釆用的构图工艺为半色调曝光构图 工艺。 这里的 "W" 字形结构可以是中间高、 两边低的结构， 也可以是中间 低、 两边高的结构等。 但需要说明的是， 在本发明的实施例中， 参考图 5 , "W" 字形结构例如为中间低、 两边高的结构。  In an embodiment of the invention, the patterning process employed in this step is a halftone exposure patterning process. The "W" glyph structure here may be a structure with a middle height and a low side on both sides, or a structure with a low middle and a high height on both sides. It should be noted, however, that in the embodiment of the present invention, referring to FIG. 5, the "W"-shaped structure is, for example, a structure having a low middle and a high height on both sides.
此外， 在本发明的实施例中， 本步骤也可以釆用如下方式： 在形成有栅 绝缘层 4的基板 1上沉积有机材料薄膜 5 , 涂布光刻胶， 并通过利用半色调 掩模板的一次构图工艺 （包括曝光、 显影、 刻蚀、 灰化、 刻蚀等步骤）在薄 膜晶体管区域将有机材料薄膜 5制成 "W" 字形结构， 形成有机绝缘层 5。  In addition, in the embodiment of the present invention, this step may also be as follows: depositing an organic material film 5 on the substrate 1 on which the gate insulating layer 4 is formed, applying a photoresist, and using a halftone mask A patterning process (including exposure, development, etching, ashing, etching, etc.) forms the organic material film 5 into a "W"-shaped structure in the thin film transistor region to form an organic insulating layer 5.
A4、 参考图 6, 利用喷墨打印工艺分别在有机绝缘层 5的 "W" 字形结 构的两个低凹部处打印墨滴， 以形成薄膜晶体管的源极 6和漏极 7;  A4, referring to FIG. 6, using inkjet printing process, respectively, printing ink droplets at two low recesses of the "W"-shaped structure of the organic insulating layer 5 to form the source 6 and the drain 7 of the thin film transistor;
A5、 参考图 7, 利用一次构图工艺形成薄膜晶体管的有源层 9,有源层 9 覆盖薄膜晶体管的源极 6和漏极 7;  A5, refer to FIG. 7, forming a active layer of the thin film transistor by using one patterning process, and the active layer 9 covers the source 6 and the drain 7 of the thin film transistor;
在本发明的实施例中， 在有机绝缘层 5具有中间低、 两边高的 "W" 字 形结构的情况下， 此步骤例如可以为， 利用喷墨打印工艺在 "W" 字形结构 的内侧打印墨滴 （有机半导体材料） ， 以形成薄膜晶体管的有源层 9。 在此 情况下， 有源层为有机半导体层。  In the embodiment of the present invention, in the case where the organic insulating layer 5 has a "W"-shaped structure with a low middle and high sides, this step may be, for example, printing ink on the inner side of the "W"-shaped structure by an inkjet printing process. Drops (organic semiconductor material) to form the active layer 9 of the thin film transistor. In this case, the active layer is an organic semiconductor layer.
此外， 在本发明的一些实施例中， 如果有机绝缘层具有中间高、 两边低 的 "W" 字形结构， 则可以釆用传统光刻工艺形成有源层 9。 当然， 在本发 明的一些实施例中， 也可以通过沉积、 溅射、 涂覆等其他方式形成有源层薄 膜， 再通过构图工艺形成有源层的图案。 在此情况下， 有源层可以为硅半导 体材料、 氧化物半导体材料或有机半导体材料。 Further, in some embodiments of the present invention, if the organic insulating layer has a "W"-shaped structure with an intermediate high and low sides, the active layer 9 can be formed by a conventional photolithography process. Of course, in this hair In some embodiments of the invention, the active layer film may also be formed by deposition, sputtering, coating, or the like, and the pattern of the active layer is formed by a patterning process. In this case, the active layer may be a silicon semiconductor material, an oxide semiconductor material, or an organic semiconductor material.
A6、 参考图 8和图 9, 在形成有有源层 9的基板 1上形成钝化层 10, 并 在薄膜晶体管的漏极 7上方形成穿过有源层 9和钝化层 10的过孔；  A6, referring to FIG. 8 and FIG. 9, a passivation layer 10 is formed on the substrate 1 on which the active layer 9 is formed, and a via hole penetrating the active layer 9 and the passivation layer 10 is formed over the drain electrode 7 of the thin film transistor. ;
在本发明的实施例中， 例如， 如图 8所示， 在图 7所示的 OTFT阵列基 板上利用有机光敏材料（可以为普通有机材料， 也可以为有机光敏材料， 本 发明的实施例不限于此）形成钝化层 10, 并通过构图工艺在薄膜晶体管的漏 极 7上方形成过孔。 当然， 在本发明的一些实施例中， 还可以直接通过喷墨 打印工艺形成带有过孔的钝化层 10。 之后， 如图 9所示， 刻蚀掉图 8中过孔 下方的有源层 9, 从而使得薄膜晶体管的漏极 7暴露出来以与像素电极 11a 电连接。  In an embodiment of the present invention, for example, as shown in FIG. 8, an organic photosensitive material (which may be a common organic material or an organic photosensitive material) may be used on the OTFT array substrate shown in FIG. 7, and the embodiment of the present invention does not. The passivation layer 10 is formed, and a via hole is formed over the drain electrode 7 of the thin film transistor by a patterning process. Of course, in some embodiments of the invention, the passivation layer 10 with vias can also be formed directly by an ink jet printing process. Thereafter, as shown in Fig. 9, the active layer 9 under the via hole in Fig. 8 is etched away so that the drain electrode 7 of the thin film transistor is exposed to be electrically connected to the pixel electrode 11a.
A7、 参考图 10、 图 11和图 12, 在钝化层 10上沉积第二透明导电薄膜 11 , 并通过构图工艺形成像素电极 11a, 像素电极 11a通过上述过孔与薄膜 晶体管的漏极 7电连接。  A7, referring to FIG. 10, FIG. 11, and FIG. 12, a second transparent conductive film 11 is deposited on the passivation layer 10, and a pixel electrode 11a is formed by a patterning process, and the pixel electrode 11a is electrically connected to the drain 7 of the thin film transistor through the via hole. connection.
如图 10所示， 在形成钝化层 10的阵列基板上， 可以通过溅射形成第二 透明导电薄膜 11; 如图 11所示， 在第二透明导电薄膜 11上涂布一层光刻胶 8, 并釆用光刻工艺对光刻胶 8 进行曝光和显影， 以形成光刻胶掩模； 如图 12所示，通过蚀刻去除光刻胶完全去除区域的第二透明导电薄膜 11 ,形成像 素电极 l la。  As shown in FIG. 10, on the array substrate on which the passivation layer 10 is formed, the second transparent conductive film 11 may be formed by sputtering; as shown in FIG. 11, a photoresist is coated on the second transparent conductive film 11. 8. The photoresist 8 is exposed and developed by a photolithography process to form a photoresist mask; as shown in FIG. 12, the second transparent conductive film 11 in the completely removed region of the photoresist is removed by etching to form The pixel electrode l la.
在本发明的实施例中， 半色调曝光构图工艺可以通过半色调掩模 ( Half Tone Mask, HTM )或灰色调掩模 ( GrayTone Mask, GTM ) 实现。  In an embodiment of the invention, the halftone exposure patterning process can be implemented by a Half Tone Mask (HTM) or a GrayTone Mask (GTM).
在本发明的实施例提供的上述阵列基板的制造方法中， 通过在栅绝缘层 上形成有机光敏材料薄膜， 并利用半色调曝光构图工艺将薄膜晶体管区域内 的有机光敏材料薄膜制成具有 "W" 字形结构的有机绝缘层， 使得可以利用 喷墨打印工艺在 "W"字形结构的两个低凹部处打印墨滴来精确控制源 /漏极 的尺寸； 另外， 本发明的一些实施例中， 有源层（为有机半导体材料）生长 在有机绝缘层的 "W" 字形结构的内侧， 相较于现有技术， 这样更有利于有 源层的制造； 此外， 栅金属层和公共电极在一次构图工艺中完成， 这样可以 简化制造工艺、 降低制造成本和提高生产率。 以上实施例仅用以说明本发明的技术方案， 而非对其限制； 尽管参照前 述实施例对本发明进行了详细的说明， 本领域的普通技术人员应当理解： 其 依然可以对前述各实施例所记载的技术方案进行修改， 或者对其中部分技术 特征进行等同替换； 而这些修改或者替换， 并不使相应技术方案的本质脱离 本发明各实施例技术方案的精神和范围。 In the above method for fabricating the array substrate provided by the embodiment of the present invention, the organic photosensitive material film in the thin film transistor region is formed into a "W" by forming an organic photosensitive material film on the gate insulating layer and using a halftone exposure patterning process. The organic insulating layer of the glyph structure makes it possible to print the ink droplets at the two low recesses of the "W"-shaped structure by the ink jet printing process to precisely control the size of the source/drain; further, in some embodiments of the present invention, The active layer (which is an organic semiconductor material) is grown on the inner side of the "W"-shaped structure of the organic insulating layer, which is more advantageous for the fabrication of the active layer than the prior art; in addition, the gate metal layer and the common electrode are once This is done in the patterning process, which simplifies the manufacturing process, reduces manufacturing costs and increases productivity. The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to be limiting; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that The technical solutions are described as being modified, or equivalents are replaced by some of the technical features; and such modifications or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

权利要求书 Claim
1、 一种阵列基板， 包括： 1. An array substrate comprising:
基板； 以及  Substrate;
在所述基板上形成的像素结构， 所述像素结构包括： 栅线、 数据线、 薄 膜晶体管和像素电极， 所述薄膜晶体管包括栅极、 栅绝缘层、 有源层、 源极 和漏极， 其中， 所述栅极与所述栅线电连接， 所述源极与所述数据线电连接， 所述漏极与所述像素电极电连接，  a pixel structure formed on the substrate, the pixel structure comprising: a gate line, a data line, a thin film transistor, and a pixel electrode, the thin film transistor including a gate, a gate insulating layer, an active layer, a source and a drain, The gate is electrically connected to the gate line, the source is electrically connected to the data line, and the drain is electrically connected to the pixel electrode.
其中， 所述像素结构还包括： 有机绝缘层， 所述有机绝缘层位于所述栅 绝缘层上方， 并且在所述薄膜晶体管的位置处具有 "W" 字形结构， 以及 所述薄膜晶体管的源极和漏极分别位于所述 "W" 字形结构的两个低凹 部处， 并且所述薄膜晶体管的有源层覆盖所述薄膜晶体管的源极和漏极。  The pixel structure further includes: an organic insulating layer, the organic insulating layer is located above the gate insulating layer, and has a “W”-shaped structure at a position of the thin film transistor, and a source of the thin film transistor And a drain are respectively located at two low recesses of the "W"-shaped structure, and an active layer of the thin film transistor covers a source and a drain of the thin film transistor.
2、 根据权利要求 1所述的阵列基板， 其中， 所述有源层由有机半导体、 氧化物半导体或硅半导体材料形成。  2. The array substrate according to claim 1, wherein the active layer is formed of an organic semiconductor, an oxide semiconductor or a silicon semiconductor material.
3、 根据权利要求 1或 2所述的阵列基板， 其中， 所述 "W" 字形结构为 中间低、 两边高的 "W" 字形结构， 并且所述薄膜晶体管的有源层设置在所 述 "W" 字形结构的内侧。  The array substrate according to claim 1 or 2, wherein the "W"-shaped structure is a "W"-shaped structure having a low middle and two sides high, and an active layer of the thin film transistor is disposed at the The inner side of the W" glyph structure.
4、根据权利要求 1至 3中任一项所述的阵列基板， 其中， 所述像素结构 还包括： 钝化层， 所述钝化层覆盖所述有源层， 并且所述像素电极形成在所 述钝化层上；  The array substrate according to any one of claims 1 to 3, wherein the pixel structure further comprises: a passivation layer, the passivation layer covers the active layer, and the pixel electrode is formed at On the passivation layer;
所述漏极与所述像素电极通过所述钝化层和所述有源层在同一位置处的 过孔电连接。  The drain is electrically connected to a via hole of the pixel electrode at the same position through the passivation layer and the active layer.
5、根据权利要求 1至 4中任一项所述的阵列基板， 其中， 所述像素结构 还包括： 公共电极， 所述公共电极位于所述栅绝缘层的下方， 并与所述栅极 同层设置。  The array substrate according to any one of claims 1 to 4, wherein the pixel structure further comprises: a common electrode, the common electrode is located below the gate insulating layer, and is the same as the gate Layer settings.
6、根据权利要求 5所述的阵列基板， 其中， 所述像素电极为条状， 所述 公共电极为板状； 或者， 所述像素电极为条状， 所述公共电极也为条状。  The array substrate according to claim 5, wherein the pixel electrode has a strip shape, and the common electrode has a plate shape; or the pixel electrode has a strip shape, and the common electrode also has a strip shape.
7、根据权利要求 1至 6中任一项所述的阵列基板， 其中， 所述有机绝缘 层的材料为有机光敏材料。  The array substrate according to any one of claims 1 to 6, wherein the material of the organic insulating layer is an organic photosensitive material.
8、 一种显示装置， 包括权利要求 1至 7中任一项所述的阵列基板。 A display device comprising the array substrate according to any one of claims 1 to 7.
9、 一种阵列基板的制造方法， 包括： 9. A method of fabricating an array substrate, comprising:
在基板上形成栅金属薄膜， 并通过构图工艺形成栅金属层； 其中， 所述 栅金属层包括栅线和薄膜晶体管的栅极；  Forming a gate metal film on the substrate, and forming a gate metal layer by a patterning process; wherein the gate metal layer comprises a gate line and a gate of the thin film transistor;
在所述基板上形成栅绝缘层以覆盖所述栅金属层；  Forming a gate insulating layer on the substrate to cover the gate metal layer;
在形成有所述栅绝缘层的所述基板上沉积有机材料薄膜， 并利用一次构 图工艺在薄膜晶体管区域将所述有机材料薄膜制成 "W" 字形结构， 以形成 有机绝缘层；  Depositing an organic material film on the substrate on which the gate insulating layer is formed, and forming the organic material film into a "W"-shaped structure in a thin film transistor region by a patterning process to form an organic insulating layer;
利用喷墨打印工艺分别在所述 "W"字形结构的两个低凹部处打印墨滴， 以形成所述薄膜晶体管的源极和漏极；  Printing ink droplets at two low recesses of the "W"-shaped structure by an inkjet printing process to form a source and a drain of the thin film transistor;
利用一次构图工艺形成所述薄膜晶体管的有源层， 所述有源层覆盖所述 薄膜晶体管的源极和漏极；  Forming an active layer of the thin film transistor by a patterning process, the active layer covering a source and a drain of the thin film transistor;
在形成有所述有源层的所述基板上形成钝化层， 并在所述薄膜晶体管的 漏极上方的所述有源层和所述钝化层的同一位置处形成过孔；  Forming a passivation layer on the substrate on which the active layer is formed, and forming a via at the same position of the active layer and the passivation layer over the drain of the thin film transistor;
在所述钝化层上沉积第二透明导电薄膜，并通过构图工艺形成像素电极， 所述像素电极通过所述过孔而与所述薄膜晶体管的漏极电连接。  Depositing a second transparent conductive film on the passivation layer, and forming a pixel electrode by a patterning process, the pixel electrode being electrically connected to a drain of the thin film transistor through the via hole.
10、 根据权利要求 9所述的阵列基板的制造方法， 其中， 在所述基板上 形成所述栅金属薄膜之前， 所述方法还包括： 在所述基板上沉积第一透明导 电薄膜， 以形成公共电极；  The method of manufacturing an array substrate according to claim 9, wherein before the forming the gate metal film on the substrate, the method further comprises: depositing a first transparent conductive film on the substrate to form Common electrode
其中， 形成所述栅金属层和所述公共电极的构图工艺为同一次半色调曝 光构图工艺。  Wherein, the patterning process for forming the gate metal layer and the common electrode is the same halftone exposure patterning process.
11、根据权利要求 9或 10所述的阵列基板的制造方法， 其中， 所述制成 "W" 字形结构所釆用的构图工艺为半色调曝光构图工艺。  The method of manufacturing an array substrate according to claim 9 or 10, wherein the patterning process for forming the "W"-shaped structure is a halftone exposure patterning process.
12、根据权利要 9至 11中任一项所述的阵列基板的制造方法， 其中， 所 述 "W" 字形结构为中间低、 两边高的 "W" 字形结构，  The method of manufacturing an array substrate according to any one of claims 9 to 11, wherein the "W"-shaped structure is a "W"-shaped structure having a low middle and a high height on both sides.
所述有源层为有机半导体， 所述利用一次构图工艺形成薄膜晶体管的有 源层包括：  The active layer is an organic semiconductor, and the forming an active layer of the thin film transistor by using a patterning process includes:
利用喷墨打印工艺在所述 "W" 字形结构的内侧打印墨滴， 以形成所述 薄膜晶体管的有源层。  An ink droplet is printed on the inside of the "W"-shaped structure by an inkjet printing process to form an active layer of the thin film transistor.
PCT/CN2012/084463 2012-01-04 2012-11-12 Array substrate, method for manufacturing same, and display device WO2013102372A1 (en)

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