US20100078644A1 - Insulating film pattern, method for manufacturing the same, and method for manufacturing thin film transistor substrate using the same - Google Patents
Insulating film pattern, method for manufacturing the same, and method for manufacturing thin film transistor substrate using the same Download PDFInfo
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- US20100078644A1 US20100078644A1 US12/423,542 US42354209A US2010078644A1 US 20100078644 A1 US20100078644 A1 US 20100078644A1 US 42354209 A US42354209 A US 42354209A US 2010078644 A1 US2010078644 A1 US 2010078644A1
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- 239000010408 film Substances 0.000 title claims abstract description 158
- 239000000758 substrate Substances 0.000 title claims abstract description 102
- 239000010409 thin film Substances 0.000 title claims abstract description 21
- 238000000034 method Methods 0.000 title claims description 61
- 238000004519 manufacturing process Methods 0.000 title claims description 43
- 239000004065 semiconductor Substances 0.000 claims abstract description 69
- 238000005192 partition Methods 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 14
- 239000007791 liquid phase Substances 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 4
- 238000003860 storage Methods 0.000 description 20
- 239000004973 liquid crystal related substance Substances 0.000 description 10
- 239000011810 insulating material Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 239000011159 matrix material Substances 0.000 description 4
- 238000004380 ashing Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000003086 colorant Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
- H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1292—Multistep manufacturing methods using liquid deposition, e.g. printing
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
Definitions
- the present invention relates to an insulating film pattern, a method for manufacturing the insulating film pattern, and a method for manufacturing a thin film transistor substrate using the insulating film pattern. More particularly, the present invention relates to an insulating film pattern that may improve the productivity and simplify the manufacturing of a thin film transistor, a method for manufacturing the insulating film pattern, and a method for manufacturing a thin film transistor substrate using the insulating film pattern.
- a display apparatus In general, a display apparatus is used to display images by changing data from an electrical format into images visible to human eyes.
- a liquid crystal display (LCD) is one type of display apparatus and displays images using optical characteristics of liquid crystals.
- the LCD includes an LCD panel that displays images and a backlight assembly that provides light to the LCD panel.
- the LCD panel includes a thin film transistor (TFT) substrate, an opposite substrate facing the TFT substrate, and a liquid crystal layer interposed between the TFT substrate and the opposite substrate.
- TFT thin film transistor
- the TFT substrate includes pixels serving as a basic unit to display the image, and each pixel has a TFT to turn a pixel voltage on and off, and a pixel electrode.
- the pixel electrode is connected to a drain electrode of the TFT, and receives the pixel voltage from the TFT.
- the TFT substrate has a multilayer structure including thin films, so the TFT substrate is generally formed by patterning the thin films through a photolithography process using expensive masks, so that the process time and manufacturing cost are greater than desired.
- This invention provides an insulating film pattern that may improve the productivity and simplify the manufacturing of a TFT.
- This invention also provides a method for manufacturing an insulating film pattern.
- This invention also provides a method for manufacturing a TFT substrate using an insulting film pattern.
- the present invention discloses an insulating film pattern including a first surface having a first pattern part to form a source electrode, a drain electrode and a semiconductor layer of a thin film transistor, and a second surface facing the first surface.
- the first pattern part includes a source pattern that extends in a first direction and is recessed in the insulating film pattern to form the source electrode, a drain pattern that is spaced apart from the source pattern and is recessed in the insulating film pattern to form the drain electrode, and a semiconductor pattern that is arranged between the source pattern and the drain pattern and is recessed in the insulating film pattern to form the semiconductor layer.
- the present invention also discloses a method for manufacturing an insulating film pattern.
- the method includes forming a resist layer on an upper surface of a substrate, aligning an imprint apparatus with the resist layer, the imprint apparatus including an etching pattern, bonding the imprint apparatus to the substrate with the resist layer interposed between the imprint apparatus and the substrate, forming a first pattern part on a surface of the resist layer by the etching pattern, the first pattern part comprising a source pattern, a drain pattern, and a semiconductor pattern, and separating the imprint apparatus from the substrate with the resist layer having the first pattern part as an insulating film pattern bonded to the imprint apparatus.
- the present invention also discloses a method for manufacturing a thin film transistor substrate.
- the method includes depositing on an upper surface of a base substrate an insulating film pattern having a first pattern part on an upper surface of the insulating film pattern, the first pattern part having a source pattern, a drain pattern, and a semiconductor pattern recessed in the insulating film pattern, forming a source electrode and a drain electrode of a thin film transistor through an inkjet print scheme using the source pattern and the drain pattern, forming a gate insulting film by etching a portion of the insulting film pattern, and forming a semiconductor layer of the thin film transistor through an inkjet print scheme using the semiconductor pattern.
- FIG. 1 is a sectional view illustrating an LCD panel according to an exemplary embodiment of the present invention.
- FIG. 2 is a plan view illustrating a TFT substrate shown in FIG. 1 .
- FIG. 3 is a flowchart showing a method for manufacturing a TFT substrate according to an exemplary embodiment of the present invention.
- FIG. 4 is a perspective view illustrating a portion of an insulating film pattern used to manufacture the TFT substrate shown in FIG. 3 .
- FIG. 5A and FIG. 5B are sectional views showing a method for manufacturing the insulating film pattern shown in FIG. 4 .
- FIG. 6A , FIG. 6B , FIG. 6C , FIG. 6D , and FIG. 6E are sectional views showing a method for manufacturing a TFT using the insulating film pattern shown in FIG. 4 .
- FIG. 7 is a flowchart showing a method for manufacturing a TFT substrate according to another exemplary embodiment of the present invention.
- FIG. 8 is a perspective view illustrating a portion of an insulating film pattern used to manufacture the TFT substrate shown in FIG. 7 .
- FIG. 9A and FIG. 9B are sectional views showing a method for manufacturing the insulating film pattern shown in FIG. 8 .
- FIG. 10A and FIG. 10B are sectional views showing a method for manufacturing a TFT using the insulating film pattern shown in FIG. 8 .
- first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
- spatially relative terms such as “beneath”, “below”, “lower”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
- FIG. 1 is a sectional view illustrating an LCD panel according to an exemplary embodiment of the present invention
- FIG. 2 is a plan view illustrating the TFT substrate 100 shown in FIG. 1 .
- an LCD 400 includes a TFT substrate 100 , an opposite substrate 200 facing the TFT substrate 100 , and a liquid crystal layer 300 interposed between the TFT substrate 100 and the opposite substrate 200 .
- the liquid crystal layer 300 includes liquid crystals 310 .
- the TFT substrate 100 includes a first base substrate 110 , a gate line GL, a data line DL, a pixel part PX, and a gate insulating film 140 .
- a pixel area PA is a region on the first base substrate 110 , and includes a region in which images are displayed.
- the gate line GL is arranged on an upper surface of the first base substrate 110 and extends in a first direction D 1 to transmit a gate signal.
- the data line DL is arranged on the first base substrate 110 .
- the data line DL is insulated from the gate line GL and crosses with the gate line GL.
- the data line DL also extends in a second direction D 2 substantially perpendicular to the first direction D 1 .
- the data line DL and the gate line GL define the boundaries of the pixel area PA.
- the pixel part PX is arranged in the pixel area PA.
- the pixel part PX includes a TFT 120 to provide a pixel voltage according to whether the TFT 120 is on or off, and a pixel electrode 130 to receive the pixel voltage from the TFT 120 .
- the TFT 120 includes a gate electrode 121 , a source electrode 122 , a drain electrode 123 , and a semiconductor layer 124 .
- the gate electrode 121 extends from the gate line GL
- the source electrode 122 extends from the data line DL to at least partially overlap with the gate electrode 121 .
- the drain electrode 123 faces the source electrode 122 with the semiconductor layer 124 interposed there between.
- the semiconductor layer 124 is arranged in a region corresponding to the gate electrode 121 and may partially cover an upper surface of the source electrode 122 and an upper surface of the drain electrode 123 .
- the semiconductor layer 124 may partially cover a lower surface of the source electrode 122 and a lower surface of the drain electrode 123 .
- the pixel electrode 130 is connected to the drain electrode 123 to receive the pixel voltage.
- the pixel electrode 130 may include transparent conductive material such as Indium Zinc Oxide (IZO) or Indium Tin Oxide (ITO).
- the gate insulating film 140 is arranged on the upper part of the first base substrate 110 on which the gate line GL and the gate electrode 121 are formed.
- the gate insulating film 140 may includes organic insulating material and covers the gate line GL and the gate electrode 121 .
- the date line DL, the source electrode 122 , the drain electrode 123 and the semiconductor layer 124 are arranged on an upper surface of the gate insulating film 140 .
- the upper surfaces of the source electrode 122 and the drain electrode 123 may be positioned lower than the upper surface of the gate insulating film 140 , and the gate insulating film 140 may cover a side surface of the source electrode 122 and a side surface of the drain electrode 123 .
- the TFT substrate 100 further includes a protection film 150 .
- the protection film 150 is arranged on an upper part of the gate insulating film 140 to cover the data line DL, the source electrode 122 , the drain electrode 123 , and the semiconductor layer 124 .
- a contact hole CH is arranged in the protection film 150 to expose the drain electrode 123 .
- the pixel electrode 130 is arranged on an upper surface of the protection film 150 and is connected to the drain electrode 123 through the contact hole CH.
- the TFT substrate 100 further includes a storage line SL to transmit a storage voltage and a storage electrode SE.
- the storage line SL and the storage electrode SE may be formed of the same material as the gate line GL, and may be formed during a process or step of forming the gate line GL. Although not shown in FIG. 1 , the storage line SL and the storage electrode SE may be arranged on the same layer as the gate line GL.
- the storage line SL extends in the first direction D 1
- the storage electrode SE extends from the storage line SL in the second direction D 2 on the pixel area PA.
- the opposite substrate 200 is provided opposite to the TFT substrate 100 .
- the opposite substrate 200 includes a second base substrate 210 , a color filter 220 , a black matrix 230 , an overcoat layer 240 , and a common electrode 250 .
- the second base substrate 210 faces the first base substrate 110 , and the color filter 220 and the black matrix 230 are arranged on a lower surface of the second base substrate 210 to face the first base substrate 110 .
- the color filter 220 is arranged in the pixel area PA and filters out predetermined colors of light from light passing through the color filter 220 .
- the black matrix 230 blocks light and is arranged adjacent to the color filter 220 on the second base substrate 210 .
- the overcoat layer 240 is arranged on the black matrix 230 and the color filter 220 to planarize the opposite substrate 200 .
- the common electrode 250 is arranged on a lower surface of the overcoat layer 240 to receive a common voltage.
- the liquid crystal layer 300 is interposed between the TFT substrate 100 and the opposite substrate 200 . Transmittance of light passing through the liquid crystal layer 300 is adjusted according to an electric field, which is generated between the pixel electrode 130 and the common electrode 250 and affects the alignment of the liquid crystals 310 in the liquid crystal layer 300 , and the light is provided to the color filter 220 .
- FIG. 3 is a flowchart showing a method for manufacturing a TFT substrate according to an exemplary embodiment of the present invention.
- the gate line GL and the gate electrode 121 are formed on the first base substrate 110 (S 110 ).
- An insulating film pattern 501 is then formed on the first base substrate 110 (S 120 ).
- the structure of the insulating film pattern 501 and the process of forming the insulating film pattern 501 will be described below in more detail with reference to FIG. 4 , FIG. 5A , and FIG. 5B .
- the data line DL, the source electrode 122 , and the drain electrode 123 may be formed through an inkjet print scheme using the insulating film pattern 501 (S 130 ). Then, the semiconductor layer 124 and the gate insulating film 140 are formed using the insulating film pattern 501 (S 140 ). As a result, the TFT 120 is formed on the first base substrate 100 .
- the protection film 150 is formed on the first base substrate 100 (S 150 ), and the pixel electrode 130 is formed on the protection film 150 (S 160 ).
- FIG. 4 is a perspective view illustrating a portion of the insulating film pattern 501 used to manufacture the TFT substrate 100 shown in FIG. 3 .
- the insulating film pattern 501 may include organic insulating material, and a first pattern part 510 is arranged on an upper surface of the insulating film pattern 501 .
- the first pattern part 510 includes a first line pattern 511 used to form the data line DL (see FIG. 1 ), a source pattern 512 used to form the source electrode 122 , a drain pattern 513 used to form the drain electrode 123 , and a semiconductor pattern 514 used to form the semiconductor layer 124 .
- the first line pattern 511 , the source pattern 512 , the drain pattern 513 , and the semiconductor pattern 514 are recessed in the upper surface of the insulating film pattern 501 .
- the first line pattern 511 extends in the second direction D 2 and the source pattern 512 extends from the first line pattern 511 in the first direction D 1 .
- the drain pattern 513 faces the source pattern 512 with the semiconductor pattern 514 interposed there between, and extends in the first direction D 1 .
- the semiconductor pattern 514 When viewed in a plan view, the semiconductor pattern 514 has a generally I-shape elongated in the first direction D 1 .
- a middle part of the semiconductor pattern 514 contacts an end of the source pattern 512 and an end of the drain pattern 513 , and the middle part has a width that is less than a distance between two ends of the semiconductor pattern 514 facing each other in the second direction D 2 .
- the semiconductor pattern 514 is recessed deeper into the insulating film pattern 501 than the source pattern 512 and the drain pattern 513 . That is, the first line pattern 511 , the source pattern 512 , and the drain pattern 513 have substantially the same depth, and the semiconductor pattern 514 has a depth greater than that of the source pattern 512 .
- the semiconductor layer 124 see FIG. 1
- the deposited amount of liquid-phase semiconductor material may be more easily controlled, and the semiconductor layer 124 may be formed more precisely.
- bottom surfaces 512 a and 513 a which define a lower surface of the source pattern 512 and the drain pattern 513 , respectively, are positioned higher than a bottom surface 514 a that defines a lower surface of the semiconductor pattern 514 . For this reason, if the source electrode 122 and the drain electrode 123 are formed through the inkjet print scheme, the liquid-phase metal dropped in the source pattern 512 and the drain pattern 513 might be introduced into the semiconductor pattern 514 .
- the first pattern part 510 also includes a first partition wall 515 and a second partition wall 516 .
- the first partition wall 515 is arranged between the source pattern 512 and the semiconductor pattern 514 , and protrudes from the bottom surface 512 a to surround an end of the source pattern 512 . Accordingly, when the source electrode 122 is formed, the amount of ink dropped to form the source electrode 122 can be more easily controlled and the source electrode 122 can be formed more precisely because of the first partition wall 515 .
- a distance from the bottom surface 512 a to an upper surface 515 a of the first partition wall 515 is less than a distance from the bottom surface 512 a to the upper surface of the insulating film pattern 501 .
- the second partition wall 516 is arranged between the drain pattern 513 and the semiconductor pattern 514 , and protrudes from the bottom surface 513 a to surround an end of the drain pattern 513 . Accordingly, when the drain electrode 123 is formed, the amount of ink dropped to form the drain electrode 123 can be more easily controlled and the drain electrode 123 can be formed more precisely because of the second partition wall 516 .
- a distance from the bottom surface 513 a to an upper surface 516 a of the second partition wall 516 is less than a distance from the bottom surface 513 a to the upper surface of the insulating film pattern 501 .
- FIG. 5A and FIG. 5B are sectional views showing a method for manufacturing the insulating film pattern 501 shown in FIG. 4 .
- a resist layer 620 which may include an organic insulating material, is formed on a substrate 610 .
- An imprint apparatus 700 is disposed above the substrate 610 on which the resist layer 620 is formed.
- the imprint apparatus 700 includes an imprint substrate 710 and a mold layer 720 formed at one side of the imprint substrate 710 .
- the mold layer 720 is provided with an etching pattern 721 to etch the resist layer 620 .
- the etching pattern 721 of the mold layer 720 is then directed downward.
- the imprint apparatus 700 bonds to the substrate 610 with the resist layer 620 interposed there between.
- the imprint apparatus 700 is pressed against the substrate 610 , the resist layer 620 is bonded to the mold layer 720 .
- the insulating film pattern 501 is formed from the resist layer 620 , and the first pattern part 510 is formed on the upper surface of the insulating film pattern 501 in a region corresponding to the etching pattern 721 .
- the imprint apparatus 700 is separated from the substrate 610 with the mold layer 720 bonded to the insulating film pattern 501 .
- FIG. 6A , FIG. 6B , FIG. 6C , FIG. 6D , and FIG. 6E are sectional views showing a method for manufacturing the TFT 120 using the insulating film pattern 501 shown in FIG. 4 .
- the imprint apparatus 700 bonded with the insulating film pattern 501 is disposed above the first base substrate 110 on which the gate electrode 121 is disposed.
- the gate line GL see FIG. 2
- the storage line SL see FIG. 2
- the storage electrode SE see FIG. 2
- the imprint apparatus 700 is bonded to the first base substrate 110 .
- the imprint apparatus 700 is separated from the first base substrate 110 . Accordingly, as shown in FIG. 6B , the insulating film pattern 501 is formed on the first base substrate 110 .
- the upper surface of the insulating film pattern 501 , on which the first pattern part 510 is formed, is exposed, and the semiconductor pattern 514 of the first pattern part 510 is disposed on the gate electrode 121 .
- the insulating film pattern 501 is formed through the imprint scheme, and is deposited on the first base substrate 110 through a contact print scheme. Accordingly, the number of the processes to form the TFT substrate 100 can be reduced, the productivity may be improved and the manufacturing cost may be reduced by simplifying the manufacturing steps.
- liquid-phase metal is dropped on the source pattern 512 and the drain pattern 514 of the insulating film pattern 501 to form the source electrode 122 and the drain electrode 123 on the insulating film pattern 501 .
- the data line DL (see FIG. 2 ) may be formed during a process or step in which the source electrode 122 and the drain electrode 123 are formed, and the data line DL may be formed using the first line pattern 511 (see FIG. 4 ) through the same scheme as the source electrode 122 .
- a portion of the insulting film pattern 501 undergoes an ashing process, thereby removing the first and second partition walls 515 and 516 .
- the insulating film pattern 501 is also subject to an undercut etching at a portion below the source electrode 122 and the drain electrode 123 .
- the gate insulating film 140 is formed on the first base substrate 110 .
- the liquid-phase organic semiconductor material is dropped on the semiconductor pattern 514 formed in the gate insulating film 140 , thereby forming the semiconductor layer 124 .
- the TFT 120 is formed. Since the semiconductor pattern 514 is more deeply recessed than the source pattern 512 and the drain pattern 514 , the amount of organic semiconductor material can be more easily controlled, and the semiconductor layer 124 can be more precisely formed.
- the TFT substrate 100 the TFT 120 , and the gate insulating film 140 are formed using the insulating film pattern 501 . Accordingly, the source electrode 122 , the drain electrode 123 , and the semiconductor layer 124 are formed through the inkjet print scheme, so that the process time may be reduced, the productivity may be improved, and the manufacturing cost may be reduced.
- FIG. 7 is a flowchart showing a method for manufacturing the TFT substrate 100 according to another exemplary embodiment of the present invention.
- an insulating film pattern 502 (see FIG. 8 ) is formed on the first base substrate 110 (S 210 ).
- the structure of the insulating film pattern 502 and the method for manufacturing the insulating film pattern 502 will be described in more detail with reference to FIG. 8 , FIG. 9A , and FIG. 9B .
- the gate line GL and the gate electrode 121 are formed through the inkjet print scheme using the insulating film pattern 502 (S 220 ).
- the data line DL, the source electrode 122 , and the drain electrode 123 are formed through the inkjet print scheme using the insulating film pattern 502 (S 230 ).
- the semiconductor layer 124 and the gate insulating film 140 are formed using the insulating film pattern 502 (S 240 ). As a result, the TFT 120 is formed on the first base substrate 100 .
- the protection film 150 is formed on the first base substrate 100 (S 250 ), and the pixel electrode 130 is formed on the protection film 150 (S 260 ).
- FIG. 8 is a perspective view illustrating a portion of the insulating film pattern 502 used to manufacture the TFT substrate 100 shown in FIG. 1 .
- the insulating film pattern 502 may include organic insulating material, and the first pattern part 510 is formed on an upper surface of the insulating film pattern 502 to form the source electrode 122 , the drain electrode 123 , and the semiconductor layer 124 of the TFT 120 . Since the first pattern part 510 according to the present exemplary embodiment is substantially similar to the first pattern part 510 of the insulating film pattern 501 shown in FIG. 4 , the same reference numerals will be used to designate the same elements, and detailed description thereof will be omitted to avoid redundancy.
- a second pattern part 520 is formed at a lower surface of the insulating film pattern 502 .
- the second pattern part 520 is recessed in the lower surface of the insulating film pattern 502 and is separated from the first pattern part 5 10 .
- the second pattern part 520 includes a second line pattern 521 used to form the gate line GL and a gate pattern 522 used to form the gate electrode 121 .
- the second line pattern 521 extends in the first direction D 1 , and crosses with the first line pattern 511 below the first pattern part 510 .
- the gate pattern 522 extends from the second line pattern 521 and is disposed in a region below and corresponding to the semiconductor pattern 514 of the first pattern part 510 .
- the second pattern part 520 may further include patterns to form the storage line SL and the storage electrode SE.
- FIG. 9A and FIG. 9B are sectional views showing a method for manufacturing the insulating film pattern 502 shown in FIG. 8 .
- a dummy pattern 630 having a shape corresponding to the gate line GL (see FIG. 2 ) and the gate electrode 121 (see FIG. 1 ) is arranged on the substrate 610 .
- the storage line SL (see FIG. 2 ) and the storage electrode SE are formed together with the gate line GL and the gate electrode 121 , and patterns to form the storage line SL and the storage electrode SE are included in the second pattern part 520 , an additional pattern having a shape corresponding to the storage line SL (see FIG. 2 ) and the storage electrode SE may be arranged on the substrate 610 together with the dummy pattern 630 .
- the resist layer 620 which may include organic insulating material, is formed on the substrate 610 on which the dummy pattern 630 is formed.
- the imprint apparatus 700 is disposed above the substrate 610 on which the resist layer 620 is formed. Since the imprint apparatus 700 according to the present exemplary embodiment has a structure substantially similar to that of the imprint apparatus 700 shown in FIG. 5A , the same reference numerals will be used to designate the same elements, and detailed description thereof will be omitted to avoid redundancy.
- the etching pattern 721 of the mold layer 720 is directed downward.
- the imprint apparatus 700 is bonded to the substrate 610 with the resist layer 620 interposed there between.
- the resist layer 620 bonds to the mold layer 720 of the imprint apparatus 700 .
- the insulating film pattern 502 is formed, and the first pattern part 510 is formed on the upper surface of the insulating film pattern 502 in a region corresponding with the etching pattern 721 .
- the imprint apparatus 700 is separated from the substrate 610 with the mold layer 720 bonded to the insulating film pattern 502 .
- the insulating film pattern 502 is separated from the substrate 610 and the dummy pattern 630 , so that the second pattern part 520 is formed at the lower surface of the insulating film pattern 502 by the dummy pattern 630 .
- FIG. 10A and FIG. 10B are sectional views showing a process of forming the TFT 120 using the insulating film pattern 502 shown in FIG. 8 .
- the insulating film pattern 502 is deposited on the first base substrate 110 through the contact print scheme. Since the process of depositing the insulting film pattern 502 according to the present exemplary embodiment is substantially similar to that shown in FIG. 6A , the detailed description thereof will be omitted in order to avoid redundancy.
- the upper surface of the insulating film pattern 502 on which the first pattern part 510 is formed is exposed, and the lower surface of the insulating film pattern 502 on which the second pattern part 520 is formed contacts the upper surface of the first base substrate 110 .
- the insulting film pattern 502 is formed through the imprint scheme, and is deposited on the first base substrate 110 through the contact print scheme. Accordingly, the number of processes can be reduced, the productivity can be improved and the manufacturing cost can be reduced.
- the gate electrode 121 is formed through the inkjet print scheme using the gate pattern 522 of the second pattern part 520 of the insulating film pattern 502 .
- Liquid-phase metal is injected into a side of the insulating film pattern 502 to form the gate electrode 121 .
- the gate line GL (see FIG. 2 ) may be formed in a process or step of forming the gate electrode 121 , and the gate line GL is formed through a similar manufacturing process as the gate electrode 121 using the second line pattern 521 (see FIG. 8 ) of the second pattern part 520 .
- liquid-phase metal is dropped on the source pattern 512 and the drain pattern 514 of the insulating film pattern 502 to form the source electrode 122 and the drain electrode 123 , respectively.
- the semiconductor layer 124 (see FIG. 1 ) and the gate insulating film 140 (see FIG. 1 ) are formed. Since the process of forming the semiconductor layer 124 and the gate insulting film 140 is substantially similar to that shown in FIG. 6D and FIG. 6E , the detailed description thereof will be omitted to avoid redundancy.
- the TFT 120 As described above, in the TFT substrate 100 , the TFT 120 , and the gate insulating film 140 are formed using the insulating film pattern 502 . Accordingly, the TFT 120 of the TFT substrate 100 is formed through the inkjet print scheme, so the process time may be reduced, the productivity may be improved, and the manufacturing cost may be reduced.
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Abstract
Description
- This application claims priority from and the benefit of Korean Patent Application No. 10-2008-0094787, filed on Sep. 26, 2008, which is hereby incorporated by reference for all purposes as if fully set forth herein.
- 1. Field of the Invention
- The present invention relates to an insulating film pattern, a method for manufacturing the insulating film pattern, and a method for manufacturing a thin film transistor substrate using the insulating film pattern. More particularly, the present invention relates to an insulating film pattern that may improve the productivity and simplify the manufacturing of a thin film transistor, a method for manufacturing the insulating film pattern, and a method for manufacturing a thin film transistor substrate using the insulating film pattern.
- 2Discussion of the Background
- In general, a display apparatus is used to display images by changing data from an electrical format into images visible to human eyes. A liquid crystal display (LCD) is one type of display apparatus and displays images using optical characteristics of liquid crystals.
- In detail, the LCD includes an LCD panel that displays images and a backlight assembly that provides light to the LCD panel. The LCD panel includes a thin film transistor (TFT) substrate, an opposite substrate facing the TFT substrate, and a liquid crystal layer interposed between the TFT substrate and the opposite substrate.
- The TFT substrate includes pixels serving as a basic unit to display the image, and each pixel has a TFT to turn a pixel voltage on and off, and a pixel electrode. The pixel electrode is connected to a drain electrode of the TFT, and receives the pixel voltage from the TFT.
- The TFT substrate has a multilayer structure including thin films, so the TFT substrate is generally formed by patterning the thin films through a photolithography process using expensive masks, so that the process time and manufacturing cost are greater than desired.
- This invention provides an insulating film pattern that may improve the productivity and simplify the manufacturing of a TFT.
- This invention also provides a method for manufacturing an insulating film pattern.
- This invention also provides a method for manufacturing a TFT substrate using an insulting film pattern.
- Additional features of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention.
- The present invention discloses an insulating film pattern including a first surface having a first pattern part to form a source electrode, a drain electrode and a semiconductor layer of a thin film transistor, and a second surface facing the first surface. Further, the first pattern part includes a source pattern that extends in a first direction and is recessed in the insulating film pattern to form the source electrode, a drain pattern that is spaced apart from the source pattern and is recessed in the insulating film pattern to form the drain electrode, and a semiconductor pattern that is arranged between the source pattern and the drain pattern and is recessed in the insulating film pattern to form the semiconductor layer.
- The present invention also discloses a method for manufacturing an insulating film pattern. The method includes forming a resist layer on an upper surface of a substrate, aligning an imprint apparatus with the resist layer, the imprint apparatus including an etching pattern, bonding the imprint apparatus to the substrate with the resist layer interposed between the imprint apparatus and the substrate, forming a first pattern part on a surface of the resist layer by the etching pattern, the first pattern part comprising a source pattern, a drain pattern, and a semiconductor pattern, and separating the imprint apparatus from the substrate with the resist layer having the first pattern part as an insulating film pattern bonded to the imprint apparatus.
- The present invention also discloses a method for manufacturing a thin film transistor substrate. The method includes depositing on an upper surface of a base substrate an insulating film pattern having a first pattern part on an upper surface of the insulating film pattern, the first pattern part having a source pattern, a drain pattern, and a semiconductor pattern recessed in the insulating film pattern, forming a source electrode and a drain electrode of a thin film transistor through an inkjet print scheme using the source pattern and the drain pattern, forming a gate insulting film by etching a portion of the insulting film pattern, and forming a semiconductor layer of the thin film transistor through an inkjet print scheme using the semiconductor pattern.
- It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
- The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention, and together with the description serve to explain the principles of the invention.
-
FIG. 1 is a sectional view illustrating an LCD panel according to an exemplary embodiment of the present invention. -
FIG. 2 is a plan view illustrating a TFT substrate shown inFIG. 1 . -
FIG. 3 is a flowchart showing a method for manufacturing a TFT substrate according to an exemplary embodiment of the present invention. -
FIG. 4 is a perspective view illustrating a portion of an insulating film pattern used to manufacture the TFT substrate shown inFIG. 3 . -
FIG. 5A andFIG. 5B are sectional views showing a method for manufacturing the insulating film pattern shown inFIG. 4 . -
FIG. 6A ,FIG. 6B ,FIG. 6C ,FIG. 6D , andFIG. 6E are sectional views showing a method for manufacturing a TFT using the insulating film pattern shown inFIG. 4 . -
FIG. 7 is a flowchart showing a method for manufacturing a TFT substrate according to another exemplary embodiment of the present invention. -
FIG. 8 is a perspective view illustrating a portion of an insulating film pattern used to manufacture the TFT substrate shown inFIG. 7 . -
FIG. 9A andFIG. 9B are sectional views showing a method for manufacturing the insulating film pattern shown inFIG. 8 . -
FIG. 10A andFIG. 10B are sectional views showing a method for manufacturing a TFT using the insulating film pattern shown inFIG. 8 . - The invention is described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure is thorough, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals in the drawings denote like elements.
- It will be understood that when an element or layer is referred to as being “on” or “connected to” another element or layer, it can be directly on or directly connected to the other element or layer, mechanically or electrically, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on” or “directly connected to” another element or layer, there are no intervening elements or layers present.
- It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
- Spatially relative terms, such as “beneath”, “below”, “lower”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
- Hereinafter, embodiments of the present invention will be described in detail with reference to accompanying drawings.
-
FIG. 1 is a sectional view illustrating an LCD panel according to an exemplary embodiment of the present invention, andFIG. 2 is a plan view illustrating theTFT substrate 100 shown inFIG. 1 . - Referring to
FIG. 1 andFIG. 2 , anLCD 400 includes aTFT substrate 100, anopposite substrate 200 facing theTFT substrate 100, and aliquid crystal layer 300 interposed between theTFT substrate 100 and theopposite substrate 200. Theliquid crystal layer 300 includesliquid crystals 310. - The
TFT substrate 100 includes afirst base substrate 110, a gate line GL, a data line DL, a pixel part PX, and agate insulating film 140. - A pixel area PA is a region on the
first base substrate 110, and includes a region in which images are displayed. - The gate line GL is arranged on an upper surface of the
first base substrate 110 and extends in a first direction D1 to transmit a gate signal. The data line DL is arranged on thefirst base substrate 110. The data line DL is insulated from the gate line GL and crosses with the gate line GL. The data line DL also extends in a second direction D2 substantially perpendicular to the first direction D1. The data line DL and the gate line GL define the boundaries of the pixel area PA. - The pixel part PX is arranged in the pixel area PA. The pixel part PX includes a
TFT 120 to provide a pixel voltage according to whether theTFT 120 is on or off, and apixel electrode 130 to receive the pixel voltage from theTFT 120. - In more detail, the
TFT 120 includes agate electrode 121, asource electrode 122, adrain electrode 123, and asemiconductor layer 124. Thegate electrode 121 extends from the gate line GL, and thesource electrode 122 extends from the data line DL to at least partially overlap with thegate electrode 121. Thedrain electrode 123 faces thesource electrode 122 with thesemiconductor layer 124 interposed there between. Thesemiconductor layer 124 is arranged in a region corresponding to thegate electrode 121 and may partially cover an upper surface of thesource electrode 122 and an upper surface of thedrain electrode 123. In addition, thesemiconductor layer 124 may partially cover a lower surface of thesource electrode 122 and a lower surface of thedrain electrode 123. - The
pixel electrode 130 is connected to thedrain electrode 123 to receive the pixel voltage. Thepixel electrode 130 may include transparent conductive material such as Indium Zinc Oxide (IZO) or Indium Tin Oxide (ITO). - The
gate insulating film 140 is arranged on the upper part of thefirst base substrate 110 on which the gate line GL and thegate electrode 121 are formed. Thegate insulating film 140 may includes organic insulating material and covers the gate line GL and thegate electrode 121. The date line DL, thesource electrode 122, thedrain electrode 123 and thesemiconductor layer 124 are arranged on an upper surface of thegate insulating film 140. The upper surfaces of thesource electrode 122 and thedrain electrode 123 may be positioned lower than the upper surface of thegate insulating film 140, and thegate insulating film 140 may cover a side surface of thesource electrode 122 and a side surface of thedrain electrode 123. - The
TFT substrate 100 further includes aprotection film 150. Theprotection film 150 is arranged on an upper part of thegate insulating film 140 to cover the data line DL, thesource electrode 122, thedrain electrode 123, and thesemiconductor layer 124. A contact hole CH is arranged in theprotection film 150 to expose thedrain electrode 123. Thepixel electrode 130 is arranged on an upper surface of theprotection film 150 and is connected to thedrain electrode 123 through the contact hole CH. - In addition, the
TFT substrate 100 further includes a storage line SL to transmit a storage voltage and a storage electrode SE. The storage line SL and the storage electrode SE may be formed of the same material as the gate line GL, and may be formed during a process or step of forming the gate line GL. Although not shown inFIG. 1 , the storage line SL and the storage electrode SE may be arranged on the same layer as the gate line GL. The storage line SL extends in the first direction D1, and the storage electrode SE extends from the storage line SL in the second direction D2 on the pixel area PA. - The
opposite substrate 200 is provided opposite to theTFT substrate 100. Theopposite substrate 200 includes asecond base substrate 210, acolor filter 220, ablack matrix 230, anovercoat layer 240, and acommon electrode 250. - In more detail, the
second base substrate 210 faces thefirst base substrate 110, and thecolor filter 220 and theblack matrix 230 are arranged on a lower surface of thesecond base substrate 210 to face thefirst base substrate 110. Thecolor filter 220 is arranged in the pixel area PA and filters out predetermined colors of light from light passing through thecolor filter 220. Theblack matrix 230 blocks light and is arranged adjacent to thecolor filter 220 on thesecond base substrate 210. Theovercoat layer 240 is arranged on theblack matrix 230 and thecolor filter 220 to planarize theopposite substrate 200. Thecommon electrode 250 is arranged on a lower surface of theovercoat layer 240 to receive a common voltage. - The
liquid crystal layer 300 is interposed between theTFT substrate 100 and theopposite substrate 200. Transmittance of light passing through theliquid crystal layer 300 is adjusted according to an electric field, which is generated between thepixel electrode 130 and thecommon electrode 250 and affects the alignment of theliquid crystals 310 in theliquid crystal layer 300, and the light is provided to thecolor filter 220. -
FIG. 3 is a flowchart showing a method for manufacturing a TFT substrate according to an exemplary embodiment of the present invention. - Referring to
FIG. 1 ,FIG. 2 , andFIG. 3 , the gate line GL and thegate electrode 121 are formed on the first base substrate 110 (S110). - An insulating
film pattern 501 is then formed on the first base substrate 110 (S120). The structure of the insulatingfilm pattern 501 and the process of forming the insulatingfilm pattern 501 will be described below in more detail with reference toFIG. 4 ,FIG. 5A , andFIG. 5B . - The data line DL, the
source electrode 122, and thedrain electrode 123 may be formed through an inkjet print scheme using the insulating film pattern 501 (S130). Then, thesemiconductor layer 124 and thegate insulating film 140 are formed using the insulating film pattern 501 (S140). As a result, theTFT 120 is formed on thefirst base substrate 100. - The process of forming the
TFT 120 and thegate insulating film 140 using the insulatingfilm pattern 501 will be described below in more detail with reference toFIG. 6A ,FIG. 6B ,FIG. 6C ,FIG. 6D , andFIG. 6E . - Then, the
protection film 150 is formed on the first base substrate 100 (S150), and thepixel electrode 130 is formed on the protection film 150 (S160). - Hereinafter, the method for manufacturing the insulating
film pattern 501 and the method for manufacturing theTFT 120 using the insulatingfilm pattern 501 will be described in more detail with reference to the drawings. -
FIG. 4 is a perspective view illustrating a portion of the insulatingfilm pattern 501 used to manufacture theTFT substrate 100 shown inFIG. 3 . - Referring to
FIG. 2 andFIG. 4 , the insulatingfilm pattern 501 may include organic insulating material, and afirst pattern part 510 is arranged on an upper surface of the insulatingfilm pattern 501. - The
first pattern part 510 includes afirst line pattern 511 used to form the data line DL (seeFIG. 1 ), asource pattern 512 used to form thesource electrode 122, adrain pattern 513 used to form thedrain electrode 123, and asemiconductor pattern 514 used to form thesemiconductor layer 124. - The
first line pattern 511, thesource pattern 512, thedrain pattern 513, and thesemiconductor pattern 514 are recessed in the upper surface of the insulatingfilm pattern 501. - In more detail, the
first line pattern 511 extends in the second direction D2 and thesource pattern 512 extends from thefirst line pattern 511 in the first direction D1. Thedrain pattern 513 faces thesource pattern 512 with thesemiconductor pattern 514 interposed there between, and extends in the first direction D1. - When viewed in a plan view, the
semiconductor pattern 514 has a generally I-shape elongated in the first direction D1. A middle part of thesemiconductor pattern 514 contacts an end of thesource pattern 512 and an end of thedrain pattern 513, and the middle part has a width that is less than a distance between two ends of thesemiconductor pattern 514 facing each other in the second direction D2. - In addition, the
semiconductor pattern 514 is recessed deeper into the insulatingfilm pattern 501 than thesource pattern 512 and thedrain pattern 513. That is, thefirst line pattern 511, thesource pattern 512, and thedrain pattern 513 have substantially the same depth, and thesemiconductor pattern 514 has a depth greater than that of thesource pattern 512. As a result, if the semiconductor layer 124 (seeFIG. 1 ) is formed through the inkjet print scheme, the deposited amount of liquid-phase semiconductor material may be more easily controlled, and thesemiconductor layer 124 may be formed more precisely. - As described above, bottom surfaces 512 a and 513 a, which define a lower surface of the
source pattern 512 and thedrain pattern 513, respectively, are positioned higher than abottom surface 514 a that defines a lower surface of thesemiconductor pattern 514. For this reason, if thesource electrode 122 and thedrain electrode 123 are formed through the inkjet print scheme, the liquid-phase metal dropped in thesource pattern 512 and thedrain pattern 513 might be introduced into thesemiconductor pattern 514. - To prevent the liquid-phase metal from being introduced into the
semiconductor pattern 514, thefirst pattern part 510 also includes afirst partition wall 515 and asecond partition wall 516. Thefirst partition wall 515 is arranged between thesource pattern 512 and thesemiconductor pattern 514, and protrudes from thebottom surface 512 a to surround an end of thesource pattern 512. Accordingly, when thesource electrode 122 is formed, the amount of ink dropped to form thesource electrode 122 can be more easily controlled and thesource electrode 122 can be formed more precisely because of thefirst partition wall 515. - In an exemplary embodiment of the present invention, a distance from the
bottom surface 512 a to anupper surface 515 a of thefirst partition wall 515 is less than a distance from thebottom surface 512 a to the upper surface of the insulatingfilm pattern 501. - The
second partition wall 516 is arranged between thedrain pattern 513 and thesemiconductor pattern 514, and protrudes from thebottom surface 513 a to surround an end of thedrain pattern 513. Accordingly, when thedrain electrode 123 is formed, the amount of ink dropped to form thedrain electrode 123 can be more easily controlled and thedrain electrode 123 can be formed more precisely because of thesecond partition wall 516. - In an exemplary embodiment of the present invention, a distance from the
bottom surface 513 a to anupper surface 516 a of thesecond partition wall 516 is less than a distance from thebottom surface 513 a to the upper surface of the insulatingfilm pattern 501. - Hereinafter, the method for manufacturing the insulating
film pattern 501 through an imprint scheme will be described in more detail with reference to the drawings. -
FIG. 5A andFIG. 5B are sectional views showing a method for manufacturing the insulatingfilm pattern 501 shown inFIG. 4 . - Referring to
FIG. 5A , a resistlayer 620, which may include an organic insulating material, is formed on asubstrate 610. - An
imprint apparatus 700 is disposed above thesubstrate 610 on which the resistlayer 620 is formed. Theimprint apparatus 700 includes animprint substrate 710 and amold layer 720 formed at one side of theimprint substrate 710. Themold layer 720 is provided with anetching pattern 721 to etch the resistlayer 620. - With the
imprint apparatus 700 disposed above the resistlayer 620, theetching pattern 721 of themold layer 720 is then directed downward. - Then, the
imprint apparatus 700 bonds to thesubstrate 610 with the resistlayer 620 interposed there between. - Referring to
FIG. 5B , as theimprint apparatus 700 is pressed against thesubstrate 610, the resistlayer 620 is bonded to themold layer 720. As a result, the insulatingfilm pattern 501 is formed from the resistlayer 620, and thefirst pattern part 510 is formed on the upper surface of the insulatingfilm pattern 501 in a region corresponding to theetching pattern 721. - After that, the
imprint apparatus 700 is separated from thesubstrate 610 with themold layer 720 bonded to the insulatingfilm pattern 501. - Hereinafter, the method for manufacturing the
TFT 120 using the insulatingfilm pattern 501 will be described in more detail with reference to the drawings. -
FIG. 6A ,FIG. 6B ,FIG. 6C ,FIG. 6D , andFIG. 6E are sectional views showing a method for manufacturing theTFT 120 using the insulatingfilm pattern 501 shown inFIG. 4 . - Referring to
FIG. 6A andFIG. 6B , theimprint apparatus 700 bonded with the insulatingfilm pattern 501 is disposed above thefirst base substrate 110 on which thegate electrode 121 is disposed. Although not shown inFIG. 6A andFIG. 6B , the gate line GL (seeFIG. 2 ), the storage line SL (seeFIG. 2 ) and the storage electrode SE (seeFIG. 2 ) can be formed on the upper surface of thefirst base substrate 110 during a process in which thegate electrode 121 is formed. - Then, with the insulating
film pattern 501 interposed between theimprint apparatus 700 and thefirst base substrate 110, theimprint apparatus 700 is bonded to thefirst base substrate 110. - After that, with the insulating
film pattern 501 bonded to thefirst base substrate 110, theimprint apparatus 700 is separated from thefirst base substrate 110. Accordingly, as shown inFIG. 6B , the insulatingfilm pattern 501 is formed on thefirst base substrate 110. The upper surface of the insulatingfilm pattern 501, on which thefirst pattern part 510 is formed, is exposed, and thesemiconductor pattern 514 of thefirst pattern part 510 is disposed on thegate electrode 121. - As described above, the insulating
film pattern 501 is formed through the imprint scheme, and is deposited on thefirst base substrate 110 through a contact print scheme. Accordingly, the number of the processes to form theTFT substrate 100 can be reduced, the productivity may be improved and the manufacturing cost may be reduced by simplifying the manufacturing steps. - Referring to
FIG. 6C , liquid-phase metal is dropped on thesource pattern 512 and thedrain pattern 514 of the insulatingfilm pattern 501 to form thesource electrode 122 and thedrain electrode 123 on the insulatingfilm pattern 501. - Although not shown in
FIG. 6C , the data line DL (seeFIG. 2 ) may be formed during a process or step in which thesource electrode 122 and thedrain electrode 123 are formed, and the data line DL may be formed using the first line pattern 511 (seeFIG. 4 ) through the same scheme as thesource electrode 122. - Referring to
FIG. 6D andFIG. 6E , a portion of theinsulting film pattern 501, including a portion near where thesource electrode 122 and thedrain electrode 123 are formed, undergoes an ashing process, thereby removing the first andsecond partition walls film pattern 501 is also subject to an undercut etching at a portion below thesource electrode 122 and thedrain electrode 123. By these steps, thegate insulating film 140 is formed on thefirst base substrate 110. - After that, the liquid-phase organic semiconductor material is dropped on the
semiconductor pattern 514 formed in thegate insulating film 140, thereby forming thesemiconductor layer 124. As a result, theTFT 120 is formed. Since thesemiconductor pattern 514 is more deeply recessed than thesource pattern 512 and thedrain pattern 514, the amount of organic semiconductor material can be more easily controlled, and thesemiconductor layer 124 can be more precisely formed. - As described above, in the
TFT substrate 100, theTFT 120, and thegate insulating film 140 are formed using the insulatingfilm pattern 501. Accordingly, thesource electrode 122, thedrain electrode 123, and thesemiconductor layer 124 are formed through the inkjet print scheme, so that the process time may be reduced, the productivity may be improved, and the manufacturing cost may be reduced. -
FIG. 7 is a flowchart showing a method for manufacturing theTFT substrate 100 according to another exemplary embodiment of the present invention. - Referring to
FIG. 1 ,FIG. 2 , andFIG. 7 , an insulating film pattern 502 (seeFIG. 8 ) is formed on the first base substrate 110 (S210). The structure of the insulatingfilm pattern 502 and the method for manufacturing the insulatingfilm pattern 502 will be described in more detail with reference toFIG. 8 ,FIG. 9A , andFIG. 9B . - The gate line GL and the
gate electrode 121 are formed through the inkjet print scheme using the insulating film pattern 502 (S220). - The data line DL, the
source electrode 122, and thedrain electrode 123 are formed through the inkjet print scheme using the insulating film pattern 502 (S230). - Then, the
semiconductor layer 124 and thegate insulating film 140 are formed using the insulating film pattern 502 (S240). As a result, theTFT 120 is formed on thefirst base substrate 100. - The process of forming the
gate insulating film 140 using the insulatingfilm pattern 502 will be explained below in reference toFIG. 10A andFIG. 10B . - Then, the
protection film 150 is formed on the first base substrate 100 (S250), and thepixel electrode 130 is formed on the protection film 150 (S260). -
FIG. 8 is a perspective view illustrating a portion of the insulatingfilm pattern 502 used to manufacture theTFT substrate 100 shown inFIG. 1 . - Referring to
FIG. 2 andFIG. 8 , the insulatingfilm pattern 502 may include organic insulating material, and thefirst pattern part 510 is formed on an upper surface of the insulatingfilm pattern 502 to form thesource electrode 122, thedrain electrode 123, and thesemiconductor layer 124 of theTFT 120. Since thefirst pattern part 510 according to the present exemplary embodiment is substantially similar to thefirst pattern part 510 of the insulatingfilm pattern 501 shown inFIG. 4 , the same reference numerals will be used to designate the same elements, and detailed description thereof will be omitted to avoid redundancy. - In addition, a
second pattern part 520 is formed at a lower surface of the insulatingfilm pattern 502. Thesecond pattern part 520 is recessed in the lower surface of the insulatingfilm pattern 502 and is separated from the first pattern part 5 10. - In more detail, the
second pattern part 520 includes asecond line pattern 521 used to form the gate line GL and agate pattern 522 used to form thegate electrode 121. Thesecond line pattern 521 extends in the first direction D1, and crosses with thefirst line pattern 511 below thefirst pattern part 510. Thegate pattern 522 extends from thesecond line pattern 521 and is disposed in a region below and corresponding to thesemiconductor pattern 514 of thefirst pattern part 510. - Although not shown in
FIG. 8 , thesecond pattern part 520 may further include patterns to form the storage line SL and the storage electrode SE. - Hereinafter, the method for manufacturing the insulating
film pattern 502 using the imprint scheme will be described in more detail with reference to the drawings. -
FIG. 9A andFIG. 9B are sectional views showing a method for manufacturing the insulatingfilm pattern 502 shown inFIG. 8 . - Referring to
FIG. 9A , adummy pattern 630 having a shape corresponding to the gate line GL (seeFIG. 2 ) and the gate electrode 121 (seeFIG. 1 ) is arranged on thesubstrate 610. Although not shown inFIG. 9A , if the storage line SL (seeFIG. 2 ) and the storage electrode SE are formed together with the gate line GL and thegate electrode 121, and patterns to form the storage line SL and the storage electrode SE are included in thesecond pattern part 520, an additional pattern having a shape corresponding to the storage line SL (seeFIG. 2 ) and the storage electrode SE may be arranged on thesubstrate 610 together with thedummy pattern 630. - Then, the resist
layer 620, which may include organic insulating material, is formed on thesubstrate 610 on which thedummy pattern 630 is formed. - The
imprint apparatus 700 is disposed above thesubstrate 610 on which the resistlayer 620 is formed. Since theimprint apparatus 700 according to the present exemplary embodiment has a structure substantially similar to that of theimprint apparatus 700 shown inFIG. 5A , the same reference numerals will be used to designate the same elements, and detailed description thereof will be omitted to avoid redundancy. - When the
imprint apparatus 700 is disposed above the resistlayer 620, theetching pattern 721 of themold layer 720 is directed downward. - Then, the
imprint apparatus 700 is bonded to thesubstrate 610 with the resistlayer 620 interposed there between. - Referring to
FIG. 9B , as theimprint apparatus 700 is pressed against thesubstrate 610, the resistlayer 620 bonds to themold layer 720 of theimprint apparatus 700. As a result, the insulatingfilm pattern 502 is formed, and thefirst pattern part 510 is formed on the upper surface of the insulatingfilm pattern 502 in a region corresponding with theetching pattern 721. - After that, the
imprint apparatus 700 is separated from thesubstrate 610 with themold layer 720 bonded to the insulatingfilm pattern 502. The insulatingfilm pattern 502 is separated from thesubstrate 610 and thedummy pattern 630, so that thesecond pattern part 520 is formed at the lower surface of the insulatingfilm pattern 502 by thedummy pattern 630. - Hereinafter, the method for manufacturing the
TFT 120 using the insulatingfilm pattern 502 will be described in more detail with reference to the drawings. -
FIG. 10A andFIG. 10B are sectional views showing a process of forming theTFT 120 using the insulatingfilm pattern 502 shown inFIG. 8 . - Referring to
FIG. 10A , the insulatingfilm pattern 502 is deposited on thefirst base substrate 110 through the contact print scheme. Since the process of depositing theinsulting film pattern 502 according to the present exemplary embodiment is substantially similar to that shown inFIG. 6A , the detailed description thereof will be omitted in order to avoid redundancy. The upper surface of the insulatingfilm pattern 502 on which thefirst pattern part 510 is formed is exposed, and the lower surface of the insulatingfilm pattern 502 on which thesecond pattern part 520 is formed contacts the upper surface of thefirst base substrate 110. - As described above, the
insulting film pattern 502 is formed through the imprint scheme, and is deposited on thefirst base substrate 110 through the contact print scheme. Accordingly, the number of processes can be reduced, the productivity can be improved and the manufacturing cost can be reduced. - Referring to
FIG. 10B , thegate electrode 121 is formed through the inkjet print scheme using thegate pattern 522 of thesecond pattern part 520 of the insulatingfilm pattern 502. Liquid-phase metal is injected into a side of the insulatingfilm pattern 502 to form thegate electrode 121. - Although not shown in
FIG. 10B , the gate line GL (seeFIG. 2 ) may be formed in a process or step of forming thegate electrode 121, and the gate line GL is formed through a similar manufacturing process as thegate electrode 121 using the second line pattern 521 (seeFIG. 8 ) of thesecond pattern part 520. - Subsequently, liquid-phase metal is dropped on the
source pattern 512 and thedrain pattern 514 of the insulatingfilm pattern 502 to form thesource electrode 122 and thedrain electrode 123, respectively. - After that, the semiconductor layer 124 (see
FIG. 1 ) and the gate insulating film 140 (seeFIG. 1 ) are formed. Since the process of forming thesemiconductor layer 124 and the gateinsulting film 140 is substantially similar to that shown inFIG. 6D andFIG. 6E , the detailed description thereof will be omitted to avoid redundancy. - As described above, in the
TFT substrate 100, theTFT 120, and thegate insulating film 140 are formed using the insulatingfilm pattern 502. Accordingly, theTFT 120 of theTFT substrate 100 is formed through the inkjet print scheme, so the process time may be reduced, the productivity may be improved, and the manufacturing cost may be reduced. - It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
Claims (19)
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KR1020080094787A KR101532058B1 (en) | 2008-09-26 | 2008-09-26 | Insulating film pattern for fabricating thin film trarnsistor, method of fabricating the same, and method of fabricating thin film trasistor substrate using the same |
KR10-2008-0094787 | 2008-09-26 |
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US20100078644A1 true US20100078644A1 (en) | 2010-04-01 |
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US12/423,542 Expired - Fee Related US8012845B2 (en) | 2008-09-26 | 2009-04-14 | Insulating film pattern, method for manufacturing the same, and method for manufacturing thin film transistor substrate using the same |
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Cited By (5)
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CN102629664A (en) * | 2012-01-04 | 2012-08-08 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof, and display apparatus |
WO2012140094A1 (en) * | 2011-04-14 | 2012-10-18 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Method for manufacturing an opto-microelectronic device |
US20130292678A1 (en) * | 2010-06-11 | 2013-11-07 | Lg Display Co., Ltd. | Thin Film Transistor Substrate, Method of Fabricating the Same and Flat Display Having the Same |
US9190530B2 (en) | 2012-12-28 | 2015-11-17 | Samsung Display Co., Ltd. | Thin film transistor in which the gate electrode has the same thickness as an insulating layer |
US11150502B2 (en) * | 2017-03-10 | 2021-10-19 | Sharp Kabushiki Kaisha | Display substrate and display device |
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GB2432044A (en) | 2005-11-04 | 2007-05-09 | Seiko Epson Corp | Patterning of electronic devices by brush painting onto surface energy modified substrates |
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US20050164494A1 (en) * | 2003-06-20 | 2005-07-28 | Matsushita Electric Industrial Co., Ltd. | Method for forming semiconductor device |
US20090057960A1 (en) * | 2005-03-30 | 2009-03-05 | Zeon Corporation | Resin mold and process for producing a molded article using the mold |
US20060258163A1 (en) * | 2005-04-06 | 2006-11-16 | Kenya Ohashi | Methods of fabricating nano-scale and micro-scale mold for nano-imprint, and mold usage on nano-imprinting equipment |
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Also Published As
Publication number | Publication date |
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KR20100035410A (en) | 2010-04-05 |
US8012845B2 (en) | 2011-09-06 |
KR101532058B1 (en) | 2015-06-29 |
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