WO2015062265A1 - Pixel structure, array substrate, display device, and method for manufacturing a pixel structure - Google Patents

Pixel structure, array substrate, display device, and method for manufacturing a pixel structure Download PDF

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Publication number
WO2015062265A1
WO2015062265A1 PCT/CN2014/078851 CN2014078851W WO2015062265A1 WO 2015062265 A1 WO2015062265 A1 WO 2015062265A1 CN 2014078851 W CN2014078851 W CN 2014078851W WO 2015062265 A1 WO2015062265 A1 WO 2015062265A1
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WO
WIPO (PCT)
Prior art keywords
layer
via hole
transparent electrode
pixel structure
compensation block
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PCT/CN2014/078851
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French (fr)
Chinese (zh)
Inventor
曹占锋
谷敬霞
姚琪
张峰
丁录科
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京东方科技集团股份有限公司
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Publication of WO2015062265A1 publication Critical patent/WO2015062265A1/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • At least one embodiment of the present invention is directed to a pixel structure, an array substrate, a display device, and a method of fabricating a pixel structure.
  • FIG. 1 is a schematic structural view of a pixel structure.
  • the pixel structure includes: a base substrate, a gate layer 1 disposed on the base substrate, a gate insulating layer 2 covering the gate layer 1, and an active layer 3 disposed on the gate insulating layer 2, covering the active layer a source/drain layer 4 of layer 3, a first passivation layer 5 covering the source/drain layer 4, a resin layer 6 disposed on the first passivation layer 5, and a first transparent electrode layer 7 disposed on the resin layer 6.
  • a second passivation layer 8 covering the first transparent electrode layer 7, and a second transparent electrode layer 9 disposed on the upper surface of the second passivation layer 8.
  • the first passivation layer 5 has a plurality of first vias in communication with the source and drain layers 4, and the resin layer 6 has a plurality of second vias in one-to-one correspondence with the plurality of first vias, the second passivation layer 8 Having a plurality of third vias corresponding to the plurality of second vias, the second transparent electrode layer 9 passing through the conductive film deposited in the corresponding third via, in the second via, and in the first via It is electrically connected to the source and drain layers 4.
  • At least one embodiment of the present invention provides a pixel structure, an array substrate, and a method of fabricating a pixel structure for reducing the probability of disconnection of the second transparent electrode layer from the source and drain layers, and improving the quality of the array substrate.
  • At least one embodiment of the present invention provides a pixel structure including: a base substrate on which an active drain layer is disposed; a first passivation layer covering the source and drain layers, the first passivation layer having a first via that communicates with the source and drain layers; a resin layer covering the first passivation layer, the resin layer has a second via communicating with the first via; and is disposed on the resin layer a first transparent electrode layer thereon; a second passivation layer on the resin layer and covering the first transparent electrode layer, the second passivation layer having a third via hole communicating with the second via hole; a conductive compensation block in the via hole; a second transparent electrode layer disposed on the second passivation layer, in the third via hole, in the second via hole, and in the first via hole; The second transparent electrode layer is electrically connected to the source and drain layers through the conductive compensation block.
  • At least one embodiment of the present invention provides an array substrate including the above pixel structure. At least one embodiment of the present invention provides a display device including the above array substrate. At least one embodiment of the present invention provides a method of fabricating a pixel structure, comprising: forming a patterned gate layer on an upper surface of a base substrate; forming a gate insulating layer covering the gate layer; Forming an active layer on an upper surface of the gate insulating layer; forming a source/drain layer covering the active layer; and forming a patterned first passivation layer and a patterned resin by a single patterning process a first passivation layer covering the source and drain layers, and the first passivation layer has a first via connected to the source and drain layers; the resin layer is disposed on the layer a first passivation layer upper surface, and the resin layer has a second via corresponding to the first via; a patterned first transparent electrode layer is formed on the resin layer; and A conductive compensation block is formed in a via.
  • FIG. 1 is a schematic structural view of a pixel structure
  • FIG. 2 is a schematic structural diagram of a pixel structure according to an embodiment of the present invention.
  • FIG. 3 is a cross-sectional view showing a pixel structure of a second passivation layer having a two-layer structure
  • FIG. 4 is a flow chart of manufacturing a pixel structure according to an embodiment of the present invention.
  • FIG. 5a is a cross-sectional view showing a pixel structure after etching a resin layer in a first passivation layer and a resin layer
  • FIG. 5b is a cross-sectional view showing a pixel structure after etching the first passivation layer in the first passivation layer and the resin layer; ;
  • Figure 5c is a cross-sectional view of a pixel structure in which a conductive compensation block is disposed in a first via hole
  • Figure 5d is a cross-sectional view of a pixel structure in which a second passivation layer is formed;
  • FIG. 5e is a cross-sectional view of a pixel structure after etching the second passivation layer;
  • Figure 5f is a cross-sectional view showing a pixel structure in which a second transparent electrode layer is formed;
  • 6a is a cross-sectional view showing a pixel structure when the second passivation layer has a two-layer structure
  • FIG. 6b is a cross-sectional view of a pixel structure after etching the upper layer structure of the second passivation layer
  • FIG. 6c is a cross-sectional view of the pixel structure after plasma processing of the second passivation layer lower layer structure.
  • FIG. 7 is a display according to an embodiment of the present invention. Schematic diagram of the device.
  • a first via hole is formed on the first passivation layer 5 and a second via hole is formed on the resin layer 6 by a patterning process, respectively.
  • the apertures of the first via hole and the second via hole may be inconsistent; thus, the phenomenon that the second transparent electrode layer is disconnected from the source and drain layers may occur.
  • the second transparent electrode layer 9 is disconnected from the source and drain layers 4, thereby affecting the quality of the array substrate.
  • At least one embodiment of the present invention provides a pixel structure by adding a conductive compensation block in the first via hole. And electrically connecting the second transparent electrode layer to the source and drain layers through the conductive compensation block to reduce the probability of the second transparent electrode layer deposited in the first via hole being disconnected, that is, reducing the second transparent electrode The probability of the layer being disconnected from the source and drain layers, thereby improving the quality of the array substrate.
  • FIG. 2 is a schematic structural diagram of a pixel structure according to at least one embodiment of the present invention.
  • the pixel structure provided by the embodiment of the present invention includes: a substrate substrate 20 on which the active drain layer 4 is disposed; a first passivation layer 5 covering the source and drain layers 4, and the first passivation layer 5 has a source and drain layer 4 a first via that is connected; Covering the resin layer 6 of the first passivation layer 5, the resin layer 6 has a second via corresponding to the first via; the first transparent electrode layer 7 disposed on the resin layer 6; on the resin layer 6 and covering the first a second passivation layer 8 of the transparent electrode layer 7, the second passivation layer 8 has a third via hole corresponding to the second via hole; and a conductive compensation block 10 disposed in the first via hole; a second transparent electrode layer 9 on the passivation layer 8 , in the third via hole, in the second via hole, and in the first via hole, and the second transparent electrode layer 9 is electrically connected to the source and drain layer 4
  • the second transparent electrode layer 9 includes: a film layer located on the upper surface of the second passivation layer 8 and located in the third via hole, in the second via hole, in the first via hole, and on the upper surface of the conductive compensation block 10 Membrane layer.
  • the third via, the second via, and the first via are in communication with each other.
  • a conductive compensation block 10 is disposed in the first via hole, and when the conductive film is deposited in the third via hole, in the second via hole, and in the first via hole to form the second transparent electrode layer 9
  • the presence of the conductive compensation block 10 can effectively reduce the influence of lateral etching in the first via hole, and can effectively reduce the probability of disconnection of the second transparent electrode layer 9 deposited in the first via hole, thereby The probability of the second transparent electrode layer 9 being disconnected from the source and drain layers 4 is reduced, thereby improving the quality of the array substrate.
  • the yield of the pixel structure is improved, in one example, the conductive compensation block.
  • the thickness of 10, the thickness of the second transparent electrode layer 9, and the thickness of the first passivation layer 5 satisfy the following relationship:
  • T1 is the thickness of the conductive compensation block 10
  • ⁇ 2 is the thickness of the second transparent electrode layer 9
  • ⁇ 3 is the thickness of the first passivation layer 5.
  • the arrangement is such that the sum of the thicknesses of the conductive compensation block 10 and the second transparent electrode layer 9 is greater than or equal to the thickness of the first passivation layer 5, thereby eliminating the influence of the lateral etching and reducing the deposition in the first via hole.
  • the probability of disconnection of the second transparent electrode layer 9 reduces the probability of the second transparent electrode layer 9 being disconnected from the source and drain layers 4, thereby improving the quality of the array substrate.
  • the thickness of the conductive compensation block 10 in order to increase the reliability of the pixel structure, the thickness of the conductive compensation block 10, the thickness of the second transparent electrode layer 9, and the first passivation layer 5 are prevented from being affected by manufacturing process instability or other factors.
  • the thickness is not very uniform, and the thickness of the conductive compensation block 10, the thickness of the second transparent electrode layer 9, and the thickness of the first passivation layer 5 satisfy the following relationship:
  • T1 is the thickness of the conductive compensation block 10
  • ⁇ 2 is the thickness of the second transparent electrode layer 9
  • ⁇ 3 is the thickness of the first passivation layer 5.
  • the thickness of the conductive compensation block 10 may be 700 angstroms
  • the thickness of the second transparent electrode layer 9 may also be 700 angstroms.
  • the thickness of the first passivation layer 5 is generally 500-1500 angstroms
  • the thickness of the conductive compensation block 10 is generally 400-800 angstroms, which may be equal to the first transparent electrode layer 7
  • the second transparent electrode layer 9 The thickness is generally 400-800 angstroms.
  • the thickness of the conductive compensation block 10 can be set by the above two relations, and can be selected according to actual conditions.
  • the conductive compensation block 10 may be formed simultaneously with the first transparent electrode layer 7, or may be formed after the first passivation layer 5 is formed, after the resin layer 6 is formed, or after the second passivation layer 8 is formed.
  • a desired conductive compensation block 10 can be formed in the first via hole by processes such as deposition, masking, etching, and lift-off.
  • the conductive compensation block 10 is formed simultaneously with the first transparent electrode layer 7, and therefore, the thickness of the conductive compensation block 10 is equal to the thickness of the first transparent electrode layer 7.
  • the first transparent electrode layer 7 may be made of one or more materials of indium tin oxide (ITO), molybdenum, molybdenum aluminum alloy, and any combination thereof, so the conductive compensation block 10 is, for example, an indium tin oxide compensation block, Molybdenum compensation block or molybdenum aluminum alloy compensation block and so on.
  • ITO indium tin oxide
  • Molybdenum compensation block or molybdenum aluminum alloy compensation block and so on.
  • 3 is a cross-sectional view showing a pixel structure of a second passivation layer having a two-layer structure.
  • the second passivation layer 8 is disposed on the resin layer 6, on the first transparent electrode layer 7, and the first via hole.
  • the transparent oxide layer 81 in the inner and second via holes, the insulating material layer 82 disposed on the transparent oxide layer 81; the thickness of the conductive compensation block 10 is equal to the thickness of the transparent oxide layer 81.
  • the transparent oxide layer 81 and the insulating material layer 82 can be formed, for example, by deposition, and the conductive compensation block 10 first forms a communication with the transparent oxide layer 81 in the insulating material layer 82 and the corresponding region of the first via hole by a process such as masking, etching, or the like.
  • the third via hole is then turned into a conductor by a transparent oxide layer 81 and a corresponding region of the first via hole by, for example, a plasma processing process, and the conductor can be used as the conductive compensation block 10, and then subjected to a lift-off process. Only the above layer structure is shown in Fig. 3, and other structures relating to the substrate or the like may be the same as those shown in Fig. 2.
  • the above pixel structure further includes: a gate layer 1, a gate insulating layer 2 and an active layer 3 between the base substrate 20 and the source and drain layers 4; the gate layer 1 is disposed on the substrate On the substrate 20; the gate insulating layer 2 covers the gate layer 1; and the active layer 3 is disposed on the gate insulating layer 2.
  • At least one embodiment of the present invention also provides an array substrate comprising the pixel structure described in any of the above embodiments.
  • the array substrate of the embodiment of the present invention includes a plurality of gate lines and a plurality of data lines, the gate lines and the data lines crossing each other thereby defining sub-pixel units arranged in a matrix, and the sub-pixel units include the above pixel structures.
  • the gate of the thin film transistor of each sub-pixel unit is electrically connected or integrally formed with the corresponding gate line
  • the source is electrically connected or integrally formed with the corresponding data line
  • the drain is electrically connected or integrally formed with the corresponding pixel electrode.
  • At least one embodiment of the present invention also provides a display device comprising the array substrate provided by any of the above embodiments.
  • a display device includes an array substrate 200 and a counter substrate 300.
  • the array substrate 200 and the opposite substrate 300 are opposed to each other and pass through a sealant 350 to form a liquid crystal cell in the liquid crystal cell.
  • the liquid crystal material 400 is filled.
  • the counter substrate 300 is, for example, a color filter substrate.
  • the pixel electrode of each pixel unit of the array substrate 200 is used to apply an electric field to control the degree of rotation of the liquid crystal material to perform a display operation.
  • the liquid crystal display device further includes a backlight 500 that provides backlighting for the array substrate 200.
  • FIG. 4 is a flow chart of manufacturing a pixel structure according to an embodiment of the present invention.
  • the method for fabricating the pixel structure provided by the embodiment of the present invention includes the following steps.
  • Step 101 Form a patterned gate layer 1 on the upper surface of the base substrate by a patterning process.
  • Step 102 forming a gate insulating layer 2 covering the gate layer 1.
  • Step 103 Forming the patterned active layer 3 on the upper surface of the gate insulating layer 2 by a patterning process.
  • Step 104 Form a source/drain layer 4 covering the active layer 3 by a patterning process.
  • the specific manufacturing process of the above steps 101 to 104 will not be described in detail herein.
  • Step 105 Form a patterned first passivation layer 5 and a patterned resin layer 6 by a patterning process; the first passivation layer 5 covers the source and drain layers 4, and the first passivation layer 5 has The first via hole 50 in which the source drain layer 4 is in communication; the resin layer 6 is disposed on the upper surface of the first passivation layer 5, and the resin layer 6 has a second via hole 60 corresponding to the first via hole 50.
  • the first via 50 is in communication with the second via 60.
  • FIG. 5a is a cross-sectional view showing a pixel structure after etching the resin layer 6 in the first passivation layer 5 and the resin layer 6;
  • FIG. 5b is a first passivation layer 5 in the first passivation layer 5 and the resin layer 6.
  • a patterned first passivation layer 5 and a patterned resin layer 6 are formed by a patterning process.
  • a passivation material is coated on the source and drain layer 4 to form a first passivation layer 5; a passivation layer 5 is coated with a resin to form a resin layer 6; a second via hole 60 is formed on the resin layer 6 by a masking, etching, and stripping process, and a first via hole 50 is formed on the first passivation layer 5, And the first via 50 corresponds to the second via 60.
  • a first via hole 50 can be formed in the first passivation layer 5 and a second via hole 60 can be formed in the resin layer 6 by a single patterning process, and the subsequent offset resin layer 6 can be omitted.
  • the process of a passivation layer 5, that is, the process of offsetting the third via from the second via by a certain distance. This makes the first via hole directly opposite to the second via hole so as not to affect the aperture ratio of the pixel structure, and is advantageous for fabricating an array substrate having a high separation ratio.
  • Step 106 Form a patterned first transparent electrode layer 7 on the upper surface of the resin layer 6 and a conductive compensation block 10 in the first via hole 50 by a patterning process.
  • Figure 5c is a cross-sectional view of the pixel structure in which the conductive compensation block 10 is disposed within the first via 50.
  • a patterned first transparent electrode layer 7 is formed on the upper surface of the resin layer 6 and a conductive compensation block 10 is formed in the first via hole 50 by a patterning process.
  • a transparent conductive film is deposited on the upper surface of the resin layer 6 and the first via 50; the first transparent electrode layer 7 is formed on the resin layer 6 by a masking, etching, and stripping process, in the first via
  • a conductive compensation block 10 is formed in 50.
  • Step 107 Form a second passivation layer 8 covering the resin layer 6 and the first transparent electrode layer 7 by a patterning process, and the second passivation layer 8 has a third via hole 80 corresponding to the second via hole 60.
  • Figure 5d is a cross-sectional view of a pixel structure in which a second passivation layer is formed;
  • Figure 5e is a cross-sectional view of a pixel structure after etching the second passivation layer.
  • Step 108 forming a second transparent electrode layer 9 in the upper surface of the second passivation layer 8, the third via 80, the second via 60, and the first via 50 by a patterning process,
  • the two transparent electrode layers 9 are electrically connected to the source and drain layers 4 through the conductive compensation block 10.
  • Fig. 5f a cross-sectional view of a pixel structure in which a second transparent electrode layer is formed is shown.
  • Forming the second transparent electrode layer 9 by a patterning process comprising: depositing a transparent conductive layer on the upper surface of the second passivation layer 8, in the third via hole, in the second via hole, and in the first via hole a transparent conductive film covering the conductive compensation block 10, so that the second transparent electrode layer 9 includes a transparent conductive film on the upper surface of the second passivation layer 8, and is located in the third via hole 80 and in the second via hole 60.
  • the transparent conductive film in the first via hole 50 and the upper surface of the conductive compensation block 10 is such that the second transparent electrode layer 9 is electrically connected to the source and drain layer 4 through the conductive compensation block 10.
  • the conductive compensation block 10 is formed simultaneously with the first transparent electrode layer 7, but the manner of forming the conductive compensation block 10 is not limited thereto, and may be formed by, for example, plasma processing the second passivation layer 8.
  • FIGs 6a, 6b and 6c Another embodiment of the invention is illustrated in Figures 6a, 6b and 6c.
  • 6a is a cross-sectional view of a pixel structure when the second passivation layer has a two-layer structure
  • FIG. 6b is a cross-sectional view of the pixel structure after etching the upper layer structure of the second passivation layer
  • FIG. 6c is a lower layer of the second passivation layer.
  • the second passivation layer 8 includes: a transparent oxide layer 81 formed on the first transparent electrode layer 7, on the resin layer 6 and in the first via hole, in the second via hole, and insulation formed on the transparent oxide layer 81 Material layer 82.
  • the material of the insulating material layer 82 may include any one or a combination of several materials such as silicon nitride, silicon dioxide, silicon oxynitride, and the like.
  • the fabrication process of the second passivation layer 8 is as follows, for example.
  • a transparent oxide layer 81 is formed on the first transparent electrode layer 7, on the resin layer 6, and in the first via, in the second via.
  • the transparent oxide layer 81 may be formed by sputtering deposition of materials such as indium tin oxide (ITZO), indium gallium oxide (IGZO) or oxidized (ZnO).
  • ITZO indium tin oxide
  • IGZO indium gallium oxide
  • ZnO oxidized
  • An insulating transparent oxide film can be obtained by selecting appropriate parameters during deposition. For example, when indium gallium oxide (IGZO) is used, the deposition gas is oxygen (0 2 ), and when the oxygen content is 60 to 200 sccm, it can be obtained. Insulated Indium Gallium Oxide (IGZO) transparent oxide film layer.
  • the transparent oxide layer 81 Forming an insulating material layer 82 on the transparent oxide layer 81; forming a third via hole communicating with the transparent oxide layer 81 in a region corresponding to the first via hole in the insulating material layer 82 by a masking, etching, and stripping process; In the plasma treatment process, the region corresponding to the first via hole of the transparent oxide layer 81 becomes a conductor, and the conductor is the conductive compensation block 10.
  • the thickness of the transparent oxide layer 81 is generally 600-1500 angstroms, and the thickness of the insulating material layer 82 is generally 300 1000 angstroms. For example, the thickness of the transparent oxide layer 81 is 1000 angstroms, and the thickness of the insulating material layer 82 is 500 angstroms.
  • the second transparent electrode layer 9 and the source and drain layers 4 are connected by a conductor of the transparent oxide layer 81 (ie, the conductive compensation block 10).
  • the plasma treatment can be performed in a dry etching (Dry Etch) device or a plasma enhanced chemical vapor deposition (PEVCD) device, and the specific technology is well known to those skilled in the art, so the specific process of the plasma treatment is This will not be described in detail.
  • Dry Etch dry etching
  • PEVCD plasma enhanced chemical vapor deposition
  • the pixel structure is fabricated by using seven times of pattern processing, and the mask is reduced compared with the pixel structure of the eight-time pattern processing process.
  • the number of uses simplifies the production process, thereby improving the yield of the pixel structure;
  • the second via 60 can be formed on the resin layer 6 by using a patterning process. Forming a first via 50 on the first passivation layer 5, such that the third via is not offset from the second via by a certain distance to form a half contact between the second transparent electrode layer 9 and the source and drain layer 4.
  • the first via 50 and the second via 60 can be directly opposed, and the saved offset distance is very beneficial to the mask design, which is advantageous for fabricating the array substrate with high resolution.
  • the second transparent electrode layer passes through the conductive compensation block and the source and drain layers through a conductive compensation block added in the first via hole. Electrically connecting to reduce the probability of disconnection of the second transparent electrode layer deposited in the first via, that is, reducing the probability of disconnection of the second transparent electrode layer from the source and drain layers, thereby improving the quality of the array substrate .
  • the array substrate provided by at least one embodiment of the present invention includes the above pixel structure, and the array substrate may be any type of array substrate, such as a TFT-LCD array substrate.
  • the display device provided by at least one embodiment of the present invention includes the above array substrate, and the display device may be: a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc., any product or component having a display function. .
  • the display device reference may be made to the above embodiments, and the repeated description is omitted. It is apparent that those skilled in the art can make various modifications and variations to the invention without departing from the spirit and scope of the invention. Thus, it is intended that the present invention cover the modifications and the modifications

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Abstract

A pixel structure, array substrate, display device, and method for manufacturing a pixel structure, the pixel structure comprising: arranging a passivation layer (5) covering a source/drain electrode layer (4) and having a first via (50), a resin layer (6) covering the first passivation layer (5) and having a second via (60), a first transparent electrode layer (7) arranged on the resin layer (6), a second passivation layer (8) covering the resin layer (6) and the first transparent electrode layer (7) and having a third via (80), a conductive compensation block (10) arranged in the first via (50); a second transparent electrode layer (9) arranged on said second passivation layer (8), in said third via (80), in said second via (60), and in said first via (50), and said second transparent electrode layer (9) being electrically connected to said source/drain electrode layer (4) by means of said conductive compensation block (10). The pixel structure reduces the chances of the second transparent electrode layer (9) and source/drain electrode layer (4) disconnecting, improving the quality of the array substrate.

Description

像素结构、 阵列基板、 显示装置及像素结构的制造方法 技术领域  Pixel structure, array substrate, display device, and manufacturing method of pixel structure
本发明的至少一个实施例涉及一种像素结构、 阵列基板、 显示装置及像 素结构的制造方法。 背景技术  At least one embodiment of the present invention is directed to a pixel structure, an array substrate, a display device, and a method of fabricating a pixel structure. Background technique
目前，高分辨率是显示面板的一大发展趋势，当显示面板的分辨率从 200 个像素 /每英寸（ pixels per inch, 以下简称 ppi )提升至 300ppi、 400ppi、 500ppi 或 500ppi以上时， 由于像素之间的间距减小使得开口率急剧下降， 为此出现 了一种釆用八次图形化处理工艺制作的阵列基板， 可以有效地补偿开口率。  At present, high resolution is a major trend in display panels. When the resolution of the display panel is increased from 200 pixels per inch (ppi) to 300ppi, 400ppi, 500ppi or more, depending on the pixel. The reduction in the spacing between them causes the aperture ratio to drop sharply. For this reason, an array substrate fabricated by eight patterning processes has been produced, which can effectively compensate the aperture ratio.
图 1为一种像素结构的结构示意图。 该像素结构包括： 衬底基板， 设置 于衬底基板上的栅极层 1，覆盖栅极层 1的栅极绝缘层 2，设置于栅极绝缘层 2上的有源层 3， 覆盖有源层 3的源漏极层 4， 覆盖源漏极层 4的第一钝化层 5， 设置于第一钝化层 5上的树脂层 6， 设置于树脂层 6上的第一透明电极层 7; 覆盖第一透明电极层 7的第二钝化层 8， 设置于第二钝化层 8上表面的第 二透明电极层 9。 第一钝化层 5具有多个与源漏极层 4连通的第一过孔， 树 脂层 6具有与多个第一过孔一一对应的多个第二过孔， 第二钝化层 8具有与 多个第二过孔——对应的多个第三过孔， 第二透明电极层 9通过沉积在对应 的第三过孔内、 第二过孔内和第一过孔内的导电膜与源漏极层 4电连接。 发明内容  FIG. 1 is a schematic structural view of a pixel structure. The pixel structure includes: a base substrate, a gate layer 1 disposed on the base substrate, a gate insulating layer 2 covering the gate layer 1, and an active layer 3 disposed on the gate insulating layer 2, covering the active layer a source/drain layer 4 of layer 3, a first passivation layer 5 covering the source/drain layer 4, a resin layer 6 disposed on the first passivation layer 5, and a first transparent electrode layer 7 disposed on the resin layer 6. A second passivation layer 8 covering the first transparent electrode layer 7, and a second transparent electrode layer 9 disposed on the upper surface of the second passivation layer 8. The first passivation layer 5 has a plurality of first vias in communication with the source and drain layers 4, and the resin layer 6 has a plurality of second vias in one-to-one correspondence with the plurality of first vias, the second passivation layer 8 Having a plurality of third vias corresponding to the plurality of second vias, the second transparent electrode layer 9 passing through the conductive film deposited in the corresponding third via, in the second via, and in the first via It is electrically connected to the source and drain layers 4. Summary of the invention
本发明的至少一个实施例提供了一种像素结构、 阵列基板及像素结构的 制造方法， 用于减小第二透明电极层与源漏极层断开的机率， 提高阵列基板 的质量。  At least one embodiment of the present invention provides a pixel structure, an array substrate, and a method of fabricating a pixel structure for reducing the probability of disconnection of the second transparent electrode layer from the source and drain layers, and improving the quality of the array substrate.
本发明的至少一个实施例提供了一种像素结构， 包括： 设置有源漏极层 的衬底基板； 覆盖所述源漏极层的第一钝化层， 所述第一钝化层具有与所述 源漏极层连通的第一过孔； 覆盖所述第一钝化层的树脂层， 所述树脂层具有 与所述第一过孔连通的第二过孔； 设置于所述树脂层上的第一透明电极层； 位于所述树脂层上并覆盖所述第一透明电极层的第二钝化层， 所述第二钝化 层具有与所述第二过孔连通的第三过孔； 设置于所述第一过孔内的导电补偿 块； 设置于所述第二钝化层上、 所述第三过孔内、 所述第二过孔内和所述第 一过孔内的第二透明电极层； 所述第二透明电极层通过所述导电补偿块与所 述源漏极层电连接。 At least one embodiment of the present invention provides a pixel structure including: a base substrate on which an active drain layer is disposed; a first passivation layer covering the source and drain layers, the first passivation layer having a first via that communicates with the source and drain layers; a resin layer covering the first passivation layer, the resin layer has a second via communicating with the first via; and is disposed on the resin layer a first transparent electrode layer thereon; a second passivation layer on the resin layer and covering the first transparent electrode layer, the second passivation layer having a third via hole communicating with the second via hole; a conductive compensation block in the via hole; a second transparent electrode layer disposed on the second passivation layer, in the third via hole, in the second via hole, and in the first via hole; The second transparent electrode layer is electrically connected to the source and drain layers through the conductive compensation block.
本发明的至少一个实施例提供了一种阵列基板， 包括上述像素结构。 本发明的至少一个实施例提供了一种显示装置， 包括上述阵列基板。 本发明的至少一个实施例提供了一种像素结构的制造方法， 包括： 在衬 底基板的上表面形成图形化的栅极层； 形成覆盖所述栅极层的栅极绝缘层； 在所述栅极绝缘层的上表面形成图形化的有源层； 形成覆盖所述有源层的源 漏极层； 以及通过一次图形化处理工艺， 形成图形化的第一钝化层和图形化 的树脂层； 其中， 所述第一钝化层覆盖所述源漏极层， 且所述第一钝化层具 有与所述源漏极层连通的第一过孔； 所述树脂层设置于所述第一钝化层上表 面， 且所述树脂层具有与所述第一过孔对应的第二过孔； 在所述树脂层的上 形成图形化的第一透明电极层； 以及在所述第一过孔内形成导电补偿块。 附图说明  At least one embodiment of the present invention provides an array substrate including the above pixel structure. At least one embodiment of the present invention provides a display device including the above array substrate. At least one embodiment of the present invention provides a method of fabricating a pixel structure, comprising: forming a patterned gate layer on an upper surface of a base substrate; forming a gate insulating layer covering the gate layer; Forming an active layer on an upper surface of the gate insulating layer; forming a source/drain layer covering the active layer; and forming a patterned first passivation layer and a patterned resin by a single patterning process a first passivation layer covering the source and drain layers, and the first passivation layer has a first via connected to the source and drain layers; the resin layer is disposed on the layer a first passivation layer upper surface, and the resin layer has a second via corresponding to the first via; a patterned first transparent electrode layer is formed on the resin layer; and A conductive compensation block is formed in a via. DRAWINGS
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。  In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below. It is obvious that the drawings in the following description relate only to some embodiments of the present invention, and are not intended to limit the present invention. .
图 1为一种像素结构的结构示意图；  1 is a schematic structural view of a pixel structure;
图 2为本发明实施例提供的一种像素结构的结构示意图；  2 is a schematic structural diagram of a pixel structure according to an embodiment of the present invention;
图 3为第二钝化层具有两层结构的像素结构的剖视图；  3 is a cross-sectional view showing a pixel structure of a second passivation layer having a two-layer structure;
图 4为本发明实施例提供的一种像素结构的制作流程图；  4 is a flow chart of manufacturing a pixel structure according to an embodiment of the present invention;
图 5a为对第一钝化层和树脂层中树脂层刻蚀后的像素结构的剖视图； 图 5b 为对第一钝化层和树脂层中第一钝化层刻蚀后的像素结构的剖视 图；  5a is a cross-sectional view showing a pixel structure after etching a resin layer in a first passivation layer and a resin layer; FIG. 5b is a cross-sectional view showing a pixel structure after etching the first passivation layer in the first passivation layer and the resin layer; ;
图 5c为在第一过孔内设置有导电补偿块的像素结构的剖视图； 图 5d为形成有第二钝化层的像素结构的剖视图；  Figure 5c is a cross-sectional view of a pixel structure in which a conductive compensation block is disposed in a first via hole; Figure 5d is a cross-sectional view of a pixel structure in which a second passivation layer is formed;
图 5e为对第二钝化层刻蚀后的像素结构的剖视图； 图 5f为形成有第二透明电极层的像素结构的剖视图； 5e is a cross-sectional view of a pixel structure after etching the second passivation layer; Figure 5f is a cross-sectional view showing a pixel structure in which a second transparent electrode layer is formed;
图 6a为第二钝化层具有两层结构时的像素结构的剖视图；  6a is a cross-sectional view showing a pixel structure when the second passivation layer has a two-layer structure;
图 6b为对第二钝化层的上层结构刻蚀后的像素结构的剖视图； 图 6c为对第二钝化层下层结构等离子处理后的像素结构的剖视图 图 7为根据本发明实施例的显示装置的示意图。  6b is a cross-sectional view of a pixel structure after etching the upper layer structure of the second passivation layer; FIG. 6c is a cross-sectional view of the pixel structure after plasma processing of the second passivation layer lower layer structure. FIG. 7 is a display according to an embodiment of the present invention. Schematic diagram of the device.
附图标记：  Reference mark:
1-栅极层， 2-栅极绝缘层， 3-有源层，  1-gate layer, 2-gate insulating layer, 3-active layer,
4-源漏极层， 5第一钝化层， 6-树脂层，  4-source drain layer, 5 first passivation layer, 6-resin layer,
7-第一透明电极层， 8-第二钝化层， 9-第二透明电极层: 10-导电补偿块， 81-透明氧化层， 82-绝缘材料层。 具体实施方式  7-first transparent electrode layer, 8-second passivation layer, 9-second transparent electrode layer: 10-conductive compensation block, 81-transparent oxide layer, 82-insulating material layer. detailed description
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图， 对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。  The technical solutions of the embodiments of the present invention will be clearly and completely described in the following with reference to the accompanying drawings. It is apparent that the described embodiments are part of the embodiments of the invention, rather than all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the described embodiments of the present invention without departing from the scope of the invention are within the scope of the invention.
本申请的发明人发现， 在图 1所示的像素结构的制作过程中， 分别通过 图形化处理工艺在第一钝化层 5上形成第一过孔和在树脂层 6上形成第二过 孔时， 会发生第一钝化层 5侧向刻蚀的现象， 这会使第一过孔和第二过孔的 孔径不一致； 因而会出现第二透明电极层与源漏极层断开的现象。 如图 1中 A区所示第二透明电极层 9与源漏极层 4断开， 进而影响阵列基板的质量。  The inventors of the present application have found that, in the fabrication process of the pixel structure shown in FIG. 1, a first via hole is formed on the first passivation layer 5 and a second via hole is formed on the resin layer 6 by a patterning process, respectively. When the first passivation layer 5 is laterally etched, the apertures of the first via hole and the second via hole may be inconsistent; thus, the phenomenon that the second transparent electrode layer is disconnected from the source and drain layers may occur. . As shown in the A region of Fig. 1, the second transparent electrode layer 9 is disconnected from the source and drain layers 4, thereby affecting the quality of the array substrate.
为了减小第二透明电极层与源漏极层断开的机率，提高阵列基板的质量， 本发明的至少一个实施例提供了一种像素结构， 通过在第一过孔内增设一个 导电补偿块， 使第二透明电极层通过所述导电补偿块与源漏极层电连接， 以 减小沉积在第一过孔内的第二透明电极层断开的机率， 即减小了第二透明电 极层与源漏极层断开的机率， 从而提高阵列基板的质量。  In order to reduce the probability of the second transparent electrode layer being disconnected from the source and drain layers and improving the quality of the array substrate, at least one embodiment of the present invention provides a pixel structure by adding a conductive compensation block in the first via hole. And electrically connecting the second transparent electrode layer to the source and drain layers through the conductive compensation block to reduce the probability of the second transparent electrode layer deposited in the first via hole being disconnected, that is, reducing the second transparent electrode The probability of the layer being disconnected from the source and drain layers, thereby improving the quality of the array substrate.
图 2为本发明至少一个实施例提供的一种像素结构的结构示意图。 本发 明实施例提供的像素结构包括： 设置有源漏极层 4的衬底基板 20; 覆盖源漏 极层 4的第一钝化层 5， 第一钝化层 5具有与源漏极层 4连通的第一过孔； 覆盖第一钝化层 5的树脂层 6， 树脂层 6具有与第一过孔对应的第二过孔； 设置于树脂层 6上的第一透明电极层 7; 位于树脂层 6上并覆盖第一透明电 极层 7的第二钝化层 8， 第二钝化层 8具有与第二过孔对应的第三过孔； 以 及设置于第一过孔内的导电补偿块 10;设置于第二钝化层 8上、第三过孔内、 第二过孔内以及第一过孔内的第二透明电极层 9， 第二透明电极层 9通过导 电补偿块 10与源漏极层 4电连接。相应地， 第二透明电极层 9包括： 位于第 二钝化层 8上表面的膜层和位于第三过孔内、 第二过孔内、 第一过孔内、 导 电补偿块 10上表面的膜层。 第三过孔、 第二过孔和第一过孔彼此连通。 FIG. 2 is a schematic structural diagram of a pixel structure according to at least one embodiment of the present invention. The pixel structure provided by the embodiment of the present invention includes: a substrate substrate 20 on which the active drain layer 4 is disposed; a first passivation layer 5 covering the source and drain layers 4, and the first passivation layer 5 has a source and drain layer 4 a first via that is connected; Covering the resin layer 6 of the first passivation layer 5, the resin layer 6 has a second via corresponding to the first via; the first transparent electrode layer 7 disposed on the resin layer 6; on the resin layer 6 and covering the first a second passivation layer 8 of the transparent electrode layer 7, the second passivation layer 8 has a third via hole corresponding to the second via hole; and a conductive compensation block 10 disposed in the first via hole; a second transparent electrode layer 9 on the passivation layer 8 , in the third via hole, in the second via hole, and in the first via hole, and the second transparent electrode layer 9 is electrically connected to the source and drain layer 4 through the conductive compensation block 10 . Correspondingly, the second transparent electrode layer 9 includes: a film layer located on the upper surface of the second passivation layer 8 and located in the third via hole, in the second via hole, in the first via hole, and on the upper surface of the conductive compensation block 10 Membrane layer. The third via, the second via, and the first via are in communication with each other.
在本发明实施例中， 第一过孔内对应设置一个导电补偿块 10， 当在第三 过孔内、 第二过孔内和第一过孔内沉积导电膜形成第二透明电极层 9时， 导 电补偿块 10的存在可以有效地降低第一过孔内的侧向刻蚀产生的影响，可以 有效地减小沉积在第一过孔内的第二透明电极层 9的断开机率， 从而减小了 第二透明电极层 9与源漏极层 4断开的机率， 进而提高阵列基板的质量。  In the embodiment of the present invention, a conductive compensation block 10 is disposed in the first via hole, and when the conductive film is deposited in the third via hole, in the second via hole, and in the first via hole to form the second transparent electrode layer 9 The presence of the conductive compensation block 10 can effectively reduce the influence of lateral etching in the first via hole, and can effectively reduce the probability of disconnection of the second transparent electrode layer 9 deposited in the first via hole, thereby The probability of the second transparent electrode layer 9 being disconnected from the source and drain layers 4 is reduced, thereby improving the quality of the array substrate.
在本发明的至少一个实施例中， 为了有效地消除第一过孔内的侧向刻蚀 对第二透明电极层 9产生的影响， 提高像素结构的合格率， 在一个示例中， 导电补偿块 10的厚度、第二透明电极层 9的厚度和第一钝化层 5的厚度满足 以下关系式：  In at least one embodiment of the present invention, in order to effectively eliminate the influence of the lateral etching in the first via on the second transparent electrode layer 9, the yield of the pixel structure is improved, in one example, the conductive compensation block. The thickness of 10, the thickness of the second transparent electrode layer 9, and the thickness of the first passivation layer 5 satisfy the following relationship:
T1+T2>T3  T1+T2>T3
其中， T1为导电补偿块 10的厚度， Τ2为第二透明电极层 9的厚度， Τ3 为第一钝化层 5的厚度。 如此设置， 使得导电补偿块 10和第二透明电极层 9 的厚度之和大于或等于第一钝化层 5的厚度， 从而消除侧向刻蚀的影响， 减 小沉积在第一过孔内的第二透明电极层 9的断开机率， 从而减小了第二透明 电极层 9与源漏极层 4断开的机率， 进而提高阵列基板的质量。  Wherein T1 is the thickness of the conductive compensation block 10, Τ2 is the thickness of the second transparent electrode layer 9, and Τ3 is the thickness of the first passivation layer 5. The arrangement is such that the sum of the thicknesses of the conductive compensation block 10 and the second transparent electrode layer 9 is greater than or equal to the thickness of the first passivation layer 5, thereby eliminating the influence of the lateral etching and reducing the deposition in the first via hole. The probability of disconnection of the second transparent electrode layer 9 reduces the probability of the second transparent electrode layer 9 being disconnected from the source and drain layers 4, thereby improving the quality of the array substrate.
在本发明的一些实施例中， 为了增加像素结构的可靠性， 防止因制作工 艺不稳定或其他因素影响造成导电补偿块 10的厚度、第二透明电极层 9的厚 度和第一钝化层 5的厚度不是很均勾的现象，导电补偿块 10的厚度、第二透 明电极层 9的厚度和第一钝化层 5的厚度满足以下关系式： In some embodiments of the present invention, in order to increase the reliability of the pixel structure, the thickness of the conductive compensation block 10, the thickness of the second transparent electrode layer 9, and the first passivation layer 5 are prevented from being affected by manufacturing process instability or other factors. The thickness is not very uniform, and the thickness of the conductive compensation block 10, the thickness of the second transparent electrode layer 9, and the thickness of the first passivation layer 5 satisfy the following relationship:
Figure imgf000006_0001
Figure imgf000006_0001
其中， T1为导电补偿块 10的厚度， Τ2为第二透明电极层 9的厚度， Τ3 为第一钝化层 5的厚度。 例如， 当第一钝化层 5的厚度为 1000埃时， 导电补偿块 10的厚度可以 为 700埃， 第二透明电极层 9的厚度也可以为 700埃。 需要说明的是， 第一 钝化层 5的厚度一般为 500-1500埃； 导电补偿块 10的厚度一般为 400-800 埃，可以与第一透明电极层 7相等；第二透明电极层 9的厚度一般为 400-800 埃。 Wherein T1 is the thickness of the conductive compensation block 10, Τ2 is the thickness of the second transparent electrode layer 9, and Τ3 is the thickness of the first passivation layer 5. For example, when the thickness of the first passivation layer 5 is 1000 angstroms, the thickness of the conductive compensation block 10 may be 700 angstroms, and the thickness of the second transparent electrode layer 9 may also be 700 angstroms. It should be noted that the thickness of the first passivation layer 5 is generally 500-1500 angstroms; the thickness of the conductive compensation block 10 is generally 400-800 angstroms, which may be equal to the first transparent electrode layer 7; the second transparent electrode layer 9 The thickness is generally 400-800 angstroms.
因此，导电补偿块 10的厚度可通过上述两个关系式设定，具体可根据实 际情况选择。  Therefore, the thickness of the conductive compensation block 10 can be set by the above two relations, and can be selected according to actual conditions.
在上述像素结构中， 导电补偿块 10可以与第一透明电极层 7同时形成， 也可以在第一钝化层 5形成后、 在树脂层 6形成后或在第二钝化层 8形成后 形成。 例如可通过沉积、 掩膜、 刻蚀、 剥离等工序在第一过孔内形成所需的 导电补偿块 10。 在图 2所示的情形中， 为了简化像素结构的制作工艺， 导电 补偿块 10与第一透明电极层 7同时形成， 因此， 导电补偿块 10的厚度与第 一透明电极层 7的厚度相等。此外，第一透明电极层 7可以由氧化铟锡（ ITO )、 钼、 钼铝合金和其任意组合的一种或多种材料制成的， 所以导电补偿块 10 例如为氧化铟锡补偿块、 钼补偿块或钼铝合金补偿块等等。  In the above pixel structure, the conductive compensation block 10 may be formed simultaneously with the first transparent electrode layer 7, or may be formed after the first passivation layer 5 is formed, after the resin layer 6 is formed, or after the second passivation layer 8 is formed. . For example, a desired conductive compensation block 10 can be formed in the first via hole by processes such as deposition, masking, etching, and lift-off. In the case shown in Fig. 2, in order to simplify the fabrication process of the pixel structure, the conductive compensation block 10 is formed simultaneously with the first transparent electrode layer 7, and therefore, the thickness of the conductive compensation block 10 is equal to the thickness of the first transparent electrode layer 7. In addition, the first transparent electrode layer 7 may be made of one or more materials of indium tin oxide (ITO), molybdenum, molybdenum aluminum alloy, and any combination thereof, so the conductive compensation block 10 is, for example, an indium tin oxide compensation block, Molybdenum compensation block or molybdenum aluminum alloy compensation block and so on.
本发明的实施例不限于上述两种实施方式， 也可以釆用如下方式实现。 图 3为第二钝化层具有两层结构的像素结构的剖视图， 在本实施方式中， 第 二钝化层 8包括设置于树脂层 6上、 第一透明电极层 7上、 第一过孔内以及 第二过孔内的透明氧化层 81， 设置于透明氧化层 81上的绝缘材料层 82; 导 电补偿块 10的厚度与透明氧化物层 81的厚度相等。透明氧化层 81和绝缘材 料层 82例如可通过沉积方式形成， 而导电补偿块 10首先通过掩膜、 刻蚀等 工序在绝缘材料层 82与第一过孔对应区域形成与透明氧化层 81连通的第三 过孔，然后通过例如等离子处理工艺将透明氧化层 81与第一过孔对应区域变 成导电体， 该导电体即可当做导电补偿块 10， 然后进行剥离工序。 图 3中仅 示出了上述层结构， 其他关于衬底基板等的结构可以与图 2所示的相同。  The embodiments of the present invention are not limited to the above two embodiments, and may be implemented in the following manner. 3 is a cross-sectional view showing a pixel structure of a second passivation layer having a two-layer structure. In the embodiment, the second passivation layer 8 is disposed on the resin layer 6, on the first transparent electrode layer 7, and the first via hole. The transparent oxide layer 81 in the inner and second via holes, the insulating material layer 82 disposed on the transparent oxide layer 81; the thickness of the conductive compensation block 10 is equal to the thickness of the transparent oxide layer 81. The transparent oxide layer 81 and the insulating material layer 82 can be formed, for example, by deposition, and the conductive compensation block 10 first forms a communication with the transparent oxide layer 81 in the insulating material layer 82 and the corresponding region of the first via hole by a process such as masking, etching, or the like. The third via hole is then turned into a conductor by a transparent oxide layer 81 and a corresponding region of the first via hole by, for example, a plasma processing process, and the conductor can be used as the conductive compensation block 10, and then subjected to a lift-off process. Only the above layer structure is shown in Fig. 3, and other structures relating to the substrate or the like may be the same as those shown in Fig. 2.
如图 2所示，上述像素结构还包括：位于衬底基板 20和源漏极层 4之间 的栅极层 1、 栅极绝缘层 2和有源层 3; 栅极层 1设置于衬底基板 20上； 栅 极绝缘层 2覆盖栅极层 1 ; 有源层 3设置于栅极绝缘层 2上。  As shown in FIG. 2, the above pixel structure further includes: a gate layer 1, a gate insulating layer 2 and an active layer 3 between the base substrate 20 and the source and drain layers 4; the gate layer 1 is disposed on the substrate On the substrate 20; the gate insulating layer 2 covers the gate layer 1; and the active layer 3 is disposed on the gate insulating layer 2.
本发明的至少一个实施例还提供了一种阵列基板， 包括上述任一实施例 所描述的像素结构。 本发明实施例的阵列基板包括多条栅线和多条数据线， 这些栅线和数据 线彼此交叉由此限定了排列为矩阵的亚像素单元， 亚像素单元包括上述像素 结构。 例如， 每个亚像素单元的薄膜晶体管的栅极与相应的栅线电连接或一 体形成， 源极与相应的数据线电连接或一体形成， 漏极与相应的像素电极电 连接或一体形成。 At least one embodiment of the present invention also provides an array substrate comprising the pixel structure described in any of the above embodiments. The array substrate of the embodiment of the present invention includes a plurality of gate lines and a plurality of data lines, the gate lines and the data lines crossing each other thereby defining sub-pixel units arranged in a matrix, and the sub-pixel units include the above pixel structures. For example, the gate of the thin film transistor of each sub-pixel unit is electrically connected or integrally formed with the corresponding gate line, the source is electrically connected or integrally formed with the corresponding data line, and the drain is electrically connected or integrally formed with the corresponding pixel electrode.
本发明的至少一个实施例还提供了一种显示装置， 包括上述任一实施例 所提供的阵列基板。  At least one embodiment of the present invention also provides a display device comprising the array substrate provided by any of the above embodiments.
如图 7所示， 本发明一个实施例的显示装置包括阵列基板 200与对置基 板 300， 阵列基板 200与对置基板 300彼此对置且通过封框胶 350以形成液 晶盒， 在液晶盒中填充有液晶材料 400。 该对置基板 300例如为彩膜基板。 阵列基板 200的每个像素单元的像素电极用于施加电场对液晶材料的旋转的 程度进行控制从而进行显示操作。 在一些实施例中， 该液晶显示装置还包括 为阵列基板 200提供背光的背光源 500。  As shown in FIG. 7, a display device according to an embodiment of the present invention includes an array substrate 200 and a counter substrate 300. The array substrate 200 and the opposite substrate 300 are opposed to each other and pass through a sealant 350 to form a liquid crystal cell in the liquid crystal cell. The liquid crystal material 400 is filled. The counter substrate 300 is, for example, a color filter substrate. The pixel electrode of each pixel unit of the array substrate 200 is used to apply an electric field to control the degree of rotation of the liquid crystal material to perform a display operation. In some embodiments, the liquid crystal display device further includes a backlight 500 that provides backlighting for the array substrate 200.
图 4为本发明实施例提供的一种像素结构的制作流程图。 本发明实施例 提供的像素结构的制造方法包括以下步骤。  FIG. 4 is a flow chart of manufacturing a pixel structure according to an embodiment of the present invention. The method for fabricating the pixel structure provided by the embodiment of the present invention includes the following steps.
步骤 101、 通过一次图形化处理工艺， 在衬底基板的上表面形成图形化 的栅极层 1。  Step 101: Form a patterned gate layer 1 on the upper surface of the base substrate by a patterning process.
步骤 102、 形成覆盖栅极层 1的栅极绝缘层 2。  Step 102, forming a gate insulating layer 2 covering the gate layer 1.
步骤 103、 通过一次图形化处理工艺， 在栅极绝缘层 2的上表面形成图 形化的有源层 3。  Step 103: Forming the patterned active layer 3 on the upper surface of the gate insulating layer 2 by a patterning process.
步骤 104、 通过一次图形化处理工艺， 形成覆盖有源层 3的源漏极层 4。 上述步骤 101〜步骤 104的具体制作过程在这里不再详细描述了。  Step 104: Form a source/drain layer 4 covering the active layer 3 by a patterning process. The specific manufacturing process of the above steps 101 to 104 will not be described in detail herein.
步骤 105、 通过一次图形化处理工艺， 形成图形化的第一钝化层 5和图 形化的树脂层 6; 第一钝化层 5覆盖源漏极层 4，且第一钝化层 5具有与源漏 极层 4连通的第一过孔 50; 树脂层 6设置于第一钝化层 5上表面， 且树脂层 6具有与第一过孔 50对应的第二过孔 60。 第一过孔 50与第二过孔 60连通。  Step 105: Form a patterned first passivation layer 5 and a patterned resin layer 6 by a patterning process; the first passivation layer 5 covers the source and drain layers 4, and the first passivation layer 5 has The first via hole 50 in which the source drain layer 4 is in communication; the resin layer 6 is disposed on the upper surface of the first passivation layer 5, and the resin layer 6 has a second via hole 60 corresponding to the first via hole 50. The first via 50 is in communication with the second via 60.
图 5a为对第一钝化层 5和树脂层 6中的树脂层 6刻蚀后的像素结构的剖 视图；图 5b为对第一钝化层 5和树脂层 6中的第一钝化层 5刻蚀后的像素结 构的剖视图。 通过一次图形化处理工艺， 形成图形化的第一钝化层 5和图形 化的树脂层 6。例如， 在源漏极层 4上涂覆钝化材料形成第一钝化层 5; 在第 一钝化层 5上涂覆树脂形成树脂层 6; 通过掩膜、刻蚀、 剥离工序在树脂层 6 上形成第二过孔 60， 在第一钝化层 5上形成第一过孔 50， 且第一过孔 50与 第二过孔 60对应。如此设计， 通过一次图形化处理工艺， 即可在第一钝化层 5中形成第一过孔 50， 在树脂层 6中形成第二过孔 60， 可以省去后续偏移树 脂层 6或第一钝化层 5的过程， 也就是说， 可以省去使第三过孔与第二过孔 偏移一定距离的过程。 这使得第一过孔与第二过孔直接相对从而不会影响像 素结构的开口率， 有利于制作具有高分别率的阵列基板。 5a is a cross-sectional view showing a pixel structure after etching the resin layer 6 in the first passivation layer 5 and the resin layer 6; FIG. 5b is a first passivation layer 5 in the first passivation layer 5 and the resin layer 6. A cross-sectional view of the etched pixel structure. A patterned first passivation layer 5 and a patterned resin layer 6 are formed by a patterning process. For example, a passivation material is coated on the source and drain layer 4 to form a first passivation layer 5; a passivation layer 5 is coated with a resin to form a resin layer 6; a second via hole 60 is formed on the resin layer 6 by a masking, etching, and stripping process, and a first via hole 50 is formed on the first passivation layer 5, And the first via 50 corresponds to the second via 60. So designed, a first via hole 50 can be formed in the first passivation layer 5 and a second via hole 60 can be formed in the resin layer 6 by a single patterning process, and the subsequent offset resin layer 6 can be omitted. The process of a passivation layer 5, that is, the process of offsetting the third via from the second via by a certain distance. This makes the first via hole directly opposite to the second via hole so as not to affect the aperture ratio of the pixel structure, and is advantageous for fabricating an array substrate having a high separation ratio.
步骤 106、 通过一次图形化处理工艺， 在树脂层 6的上表面形成图形化 的第一透明电极层 7， 以及在第一过孔 50内形成一个导电补偿块 10。 图 5c 为在第一过孔 50内设置有导电补偿块 10的像素结构的剖视图。 这里通过一 次图形化处理工艺， 在树脂层 6的上表面形成图形化的第一透明电极层 7， 以及在第一过孔 50内形成一个导电补偿块 10。 例如， 在树脂层 6的上表面 和第一过孔 50内沉积一层透明导电膜； 通过掩膜、刻蚀、 剥离工序在树脂层 6上形成第一透明电极层 7， 在第一过孔 50内形成一个导电补偿块 10。  Step 106: Form a patterned first transparent electrode layer 7 on the upper surface of the resin layer 6 and a conductive compensation block 10 in the first via hole 50 by a patterning process. Figure 5c is a cross-sectional view of the pixel structure in which the conductive compensation block 10 is disposed within the first via 50. Here, a patterned first transparent electrode layer 7 is formed on the upper surface of the resin layer 6 and a conductive compensation block 10 is formed in the first via hole 50 by a patterning process. For example, a transparent conductive film is deposited on the upper surface of the resin layer 6 and the first via 50; the first transparent electrode layer 7 is formed on the resin layer 6 by a masking, etching, and stripping process, in the first via A conductive compensation block 10 is formed in 50.
步骤 107、 通过一次图形化处理工艺， 形成覆盖树脂层 6和第一透明电 极层 7的第二钝化层 8， 第二钝化层 8具有第二过孔 60对应的第三过孔 80。 图 5d为形成有第二钝化层的像素结构的剖视图； 图 5e为对第二钝化层刻蚀 后的像素结构的剖视图。  Step 107: Form a second passivation layer 8 covering the resin layer 6 and the first transparent electrode layer 7 by a patterning process, and the second passivation layer 8 has a third via hole 80 corresponding to the second via hole 60. Figure 5d is a cross-sectional view of a pixel structure in which a second passivation layer is formed; Figure 5e is a cross-sectional view of a pixel structure after etching the second passivation layer.
步骤 108、 通过一次图形化处理工艺， 在第二钝化层 8的上表面、 第三 过孔内 80、 第二过孔内 60以及第一过孔 50内形成第二透明电极层 9， 第二 透明电极层 9通过导电补偿块 10与源漏极层 4电连接。 参见图 5f为形成有 第二透明电极层的像素结构的剖视图。 通过一次图形化处理工艺形成第二透 明电极层 9， 其包括： 在第二钝化层 8的上表面， 第三过孔内、 第二过孔内 和第一过孔内沉积一层透明导电膜， 所述透明导电膜覆盖导电补偿块 10， 从 而第二透明电极层 9包括位于第二钝化层 8上表面的透明导电膜， 位于第三 过孔 80内、 第二过孔 60内、 第一过孔 50内和导电补偿块 10上表面的透明 导电膜， 使得第二透明电极层 9通过导电补偿块 10与源漏极层 4电连接。  Step 108, forming a second transparent electrode layer 9 in the upper surface of the second passivation layer 8, the third via 80, the second via 60, and the first via 50 by a patterning process, The two transparent electrode layers 9 are electrically connected to the source and drain layers 4 through the conductive compensation block 10. Referring to Fig. 5f, a cross-sectional view of a pixel structure in which a second transparent electrode layer is formed is shown. Forming the second transparent electrode layer 9 by a patterning process, comprising: depositing a transparent conductive layer on the upper surface of the second passivation layer 8, in the third via hole, in the second via hole, and in the first via hole a transparent conductive film covering the conductive compensation block 10, so that the second transparent electrode layer 9 includes a transparent conductive film on the upper surface of the second passivation layer 8, and is located in the third via hole 80 and in the second via hole 60. The transparent conductive film in the first via hole 50 and the upper surface of the conductive compensation block 10 is such that the second transparent electrode layer 9 is electrically connected to the source and drain layer 4 through the conductive compensation block 10.
在上述实施例中，导电补偿块 10与第一透明电极层 7同时形成，但导电 补偿块 10的形成方式不限于此，还可以通过对第二钝化层 8进行例如等离子 处理形成。 本发明的另一实施例请参见图 6a、 图 6b和图 6c。 图 6a为第二钝化层具 有两层结构时的像素结构的剖视图；图 6b为对第二钝化层的上层结构刻蚀后 的像素结构的剖视图；图 6c为对第二钝化层下层结构等离子处理后的像素结 构的剖视图。 在通过一次图形化处理工艺， 在树脂层 6上形成第一透明电极 层 7之后， 在第一透明电极层 7上、 树脂层 6上以及第一过孔中、 第二过孔 中形成第二钝化层 8。 第二钝化层 8包括： 形成在第一透明电极层 7上、 树 脂层 6上以及第一过孔中、 第二过孔中的透明氧化层 81， 以及形成在透明氧 化层 81上的绝缘材料层 82。 绝缘材料层 82的材料可以包括氮化硅， 二氧化 硅， 氧氮化硅等材料中的任意一种或几种的组合。 In the above embodiment, the conductive compensation block 10 is formed simultaneously with the first transparent electrode layer 7, but the manner of forming the conductive compensation block 10 is not limited thereto, and may be formed by, for example, plasma processing the second passivation layer 8. Another embodiment of the invention is illustrated in Figures 6a, 6b and 6c. 6a is a cross-sectional view of a pixel structure when the second passivation layer has a two-layer structure; FIG. 6b is a cross-sectional view of the pixel structure after etching the upper layer structure of the second passivation layer; and FIG. 6c is a lower layer of the second passivation layer. A cross-sectional view of a pixel structure after structured plasma processing. After the first transparent electrode layer 7 is formed on the resin layer 6 by a patterning process, a second is formed on the first transparent electrode layer 7, on the resin layer 6, and in the first via, and in the second via. Passivation layer 8. The second passivation layer 8 includes: a transparent oxide layer 81 formed on the first transparent electrode layer 7, on the resin layer 6 and in the first via hole, in the second via hole, and insulation formed on the transparent oxide layer 81 Material layer 82. The material of the insulating material layer 82 may include any one or a combination of several materials such as silicon nitride, silicon dioxide, silicon oxynitride, and the like.
该第二钝化层 8的制作过程例如如下所述。  The fabrication process of the second passivation layer 8 is as follows, for example.
在第一透明电极层 7上、 树脂层 6上以及第一过孔中、 第二过孔中形成 一透明氧化层 81。 透明氧化层 81可以为氧化铟锡辞 ( ITZO ) 、 氧化铟镓辞 ( IGZO )或氧化辞（ZnO )等材料通过溅射沉积的方式制成的。 沉积时选择 合适的参数可以得到绝缘的透明氧化物薄膜， 例如， 当釆用氧化铟镓辞 ( IGZO ) 时， 沉积气体釆用氧气（02 ) ， 当氧气含量在 60~200sccm时， 可 以得到绝缘的氧化铟镓辞 ( IGZO )透明氧化物膜层。 A transparent oxide layer 81 is formed on the first transparent electrode layer 7, on the resin layer 6, and in the first via, in the second via. The transparent oxide layer 81 may be formed by sputtering deposition of materials such as indium tin oxide (ITZO), indium gallium oxide (IGZO) or oxidized (ZnO). An insulating transparent oxide film can be obtained by selecting appropriate parameters during deposition. For example, when indium gallium oxide (IGZO) is used, the deposition gas is oxygen (0 2 ), and when the oxygen content is 60 to 200 sccm, it can be obtained. Insulated Indium Gallium Oxide (IGZO) transparent oxide film layer.
在透明氧化层 81上形成绝缘材料层 82; 通过掩膜、 刻蚀、 剥离工序， 在绝缘材料层 82与第一过孔对应的区域形成与透明氧化层 81连通的第三过 孔；通过例如等离子处理工艺，使透明氧化层 81与第一过孔对应的区域变成 导电体， 导电体即为导电补偿块 10。 上述透明氧化层 81 的厚度一般为 600-1500埃， 绝缘材料层 82的厚度一般为 300 1000埃， 例如， 透明氧化层 81的厚度为 1000埃， 绝缘材料层 82的厚度为 500埃， 如此保证第二透明电 极层 9和源漏极层 4通过透明氧化层 81的导电体（即导电补偿块 10 )连接。  Forming an insulating material layer 82 on the transparent oxide layer 81; forming a third via hole communicating with the transparent oxide layer 81 in a region corresponding to the first via hole in the insulating material layer 82 by a masking, etching, and stripping process; In the plasma treatment process, the region corresponding to the first via hole of the transparent oxide layer 81 becomes a conductor, and the conductor is the conductive compensation block 10. The thickness of the transparent oxide layer 81 is generally 600-1500 angstroms, and the thickness of the insulating material layer 82 is generally 300 1000 angstroms. For example, the thickness of the transparent oxide layer 81 is 1000 angstroms, and the thickness of the insulating material layer 82 is 500 angstroms. The second transparent electrode layer 9 and the source and drain layers 4 are connected by a conductor of the transparent oxide layer 81 (ie, the conductive compensation block 10).
需要说明的是， 等离子处理可以在干刻蚀（Dry Etch )设备或等离子体 增强化学气相沉积（ PEVCD )设备中进行， 其具体技术为本领域技术人员所 述熟知， 因此等离子处理的具体过程在此不再详细描述。  It should be noted that the plasma treatment can be performed in a dry etching (Dry Etch) device or a plasma enhanced chemical vapor deposition (PEVCD) device, and the specific technology is well known to those skilled in the art, so the specific process of the plasma treatment is This will not be described in detail.
从上述可知， 在本发明实施例提供的像素结构的制造方法中， 制作像素 结构釆用了七次图形化处理工艺， 与釆用八次图形化处理工艺的像素结构相 比， 减少了掩模板的使用数量， 简化了生产工艺， 从而提高了像素结构的良 品率； 此外， 釆用一次图形化处理工艺即可在树脂层 6上形成第二过孔 60， 在第一钝化层 5上形成第一过孔 50，这样不需要使第三过孔与第二过孔偏移 一定的距离以形成第二透明电极层 9和源漏极层 4的半接触， 可以使第一过 孔 50与第二过孔 60直接相对， 而节省的偏移距离对掩模设计非常有益， 有 利于制作具有高分辨率的阵列基板。 As can be seen from the above, in the manufacturing method of the pixel structure provided by the embodiment of the present invention, the pixel structure is fabricated by using seven times of pattern processing, and the mask is reduced compared with the pixel structure of the eight-time pattern processing process. The number of uses simplifies the production process, thereby improving the yield of the pixel structure; further, the second via 60 can be formed on the resin layer 6 by using a patterning process. Forming a first via 50 on the first passivation layer 5, such that the third via is not offset from the second via by a certain distance to form a half contact between the second transparent electrode layer 9 and the source and drain layer 4. The first via 50 and the second via 60 can be directly opposed, and the saved offset distance is very beneficial to the mask design, which is advantageous for fabricating the array substrate with high resolution.
综上所述， 在本发明的至少一个实施例提供的像素结构中， 通过在第一 过孔内增设的一个导电补偿块， 使第二透明电极层通过所述导电补偿块与源 漏极层电连接， 以减小沉积在第一过孔内的第二透明电极层断开的机率， 即 减小了第二透明电极层与源漏极层断开的机率，从而提高了阵列基板的质量。  In a pixel structure provided by at least one embodiment of the present invention, the second transparent electrode layer passes through the conductive compensation block and the source and drain layers through a conductive compensation block added in the first via hole. Electrically connecting to reduce the probability of disconnection of the second transparent electrode layer deposited in the first via, that is, reducing the probability of disconnection of the second transparent electrode layer from the source and drain layers, thereby improving the quality of the array substrate .
本发明的至少一个实施例提供的阵列基板， 包括上述像素结构， 所述阵 列基板可以为任何类型的阵列基板， 例如 TFT-LCD阵列基板。  The array substrate provided by at least one embodiment of the present invention includes the above pixel structure, and the array substrate may be any type of array substrate, such as a TFT-LCD array substrate.
本发明的至少一个实施例提供的显示装置， 包括上述阵列基板， 该显示 装置可以为： 手机、 平板电脑、 电视机、 显示器、 笔记本电脑、 数码相框、 导航仪等任何具有显示功能的产品或部件。 该显示装置的实施可以参见上述 实施例， 重复之处不再赘述。 显然， 本领域的技术人员可以对本发明进行各 种改动和变型而不脱离本发明的精神和范围。 这样， 倘若本发明的这些修改 和变型属于本发明权利要求及其等同技术的范围之内， 则本发明也意图包含 这些改动和变型在内。  The display device provided by at least one embodiment of the present invention includes the above array substrate, and the display device may be: a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc., any product or component having a display function. . For the implementation of the display device, reference may be made to the above embodiments, and the repeated description is omitted. It is apparent that those skilled in the art can make various modifications and variations to the invention without departing from the spirit and scope of the invention. Thus, it is intended that the present invention cover the modifications and the modifications
本申请要求于 2013年 10月 29日递交的中国专利申请第 201310522155.7 号的优先权， 在此全文引用上述中国专利申请公开的内容以作为本申请的一 部分。  The present application claims the priority of the Chinese Patent Application No. 201310522155.7 filed on Oct. 29, 2013, the entire disclosure of which is hereby incorporated by reference in its entirety.

Claims

权利要求书 claims
1、 一种像素结构， 包括： 1. A pixel structure, including:
设置有源漏极层的衬底基板； a base substrate with an active drain layer;
覆盖所述源漏极层的第一钝化层， 所述第一钝化层具有与所述源漏极层 连通的第一过孔； A first passivation layer covering the source and drain layers, the first passivation layer having a first via hole connected to the source and drain layers;
覆盖所述第一钝化层的树脂层， 所述树脂层具有与所述第一过孔连通的 第二过孔； A resin layer covering the first passivation layer, the resin layer having a second via hole connected to the first via hole;
设置于所述树脂层上的第一透明电极层； a first transparent electrode layer provided on the resin layer;
位于所述树脂层上并覆盖所述第一透明电极层的第二钝化层， 所述第二 钝化层具有与所述第二过孔连通的第三过孔； a second passivation layer located on the resin layer and covering the first transparent electrode layer, the second passivation layer having a third via hole connected to the second via hole;
设置于所述第一过孔内的导电补偿块； a conductive compensation block disposed in the first via hole;
设置于所述第二钝化层上、 所述第三过孔内、 所述第二过孔内和所述第 一过孔内的第二透明电极层， 所述第二透明电极层通过所述导电补偿块与所 述源漏极层电连接。 A second transparent electrode layer disposed on the second passivation layer, in the third via hole, in the second via hole and in the first via hole, the second transparent electrode layer passes through The conductive compensation block is electrically connected to the source and drain layers.
2、 如权利要求 1所述的像素结构， 其中， 所述导电补偿块的厚度、 所述 第二透明电极层的厚度、 所述第一钝化层的厚度满足以下关系式： 2. The pixel structure according to claim 1, wherein the thickness of the conductive compensation block, the thickness of the second transparent electrode layer, and the thickness of the first passivation layer satisfy the following relationship:
T1+T2>T3 T1+T2>T3
其中， T1为导电补偿块的厚度， Τ2为第二透明电极层的厚度， Τ3为第 一钝化层的厚度。 Wherein, T1 is the thickness of the conductive compensation block, T2 is the thickness of the second transparent electrode layer, and T3 is the thickness of the first passivation layer.
3、 如权利要求 1所述的像素结构， 其中， 所述导电补偿块的厚度、 第二 透明电极层的厚度、 第一钝化层的厚度满足以下关系式： 3. The pixel structure according to claim 1, wherein the thickness of the conductive compensation block, the thickness of the second transparent electrode layer, and the thickness of the first passivation layer satisfy the following relationship:
Figure imgf000012_0001
Figure imgf000012_0001
其中， T1为导电补偿块的厚度， Τ2为第二透明电极层的厚度， Τ3为第 一钝化层的厚度。 Wherein, T1 is the thickness of the conductive compensation block, T2 is the thickness of the second transparent electrode layer, and T3 is the thickness of the first passivation layer.
4、 如权利要求 1-3任一所述的像素结构， 其中， 所述导电补偿块包括氧 化铟锡补偿块、 钼补偿块或钼铝合金补偿块。 4. The pixel structure according to any one of claims 1 to 3, wherein the conductive compensation block includes an indium tin oxide compensation block, a molybdenum compensation block or a molybdenum-aluminum alloy compensation block.
5、 如权利要求 1-4任一所述的像素结构， 其中， 所述第二钝化层包括： 设置于所述树脂层、 所述第一透明电极层、 所述第一过孔内和所述第二过孔 内的透明氧化物层， 以及设置于所述透明氧化物层上的绝缘材料层。 5. The pixel structure according to any one of claims 1 to 4, wherein the second passivation layer includes: disposed in the resin layer, the first transparent electrode layer, the first via hole and a transparent oxide layer in the second via hole, and an insulating material layer disposed on the transparent oxide layer.
6、如权利要求 5所述的像素结构， 其中， 所述导电补偿块的厚度与所述 透明氧化物层的厚度相等。 6. The pixel structure of claim 5, wherein the thickness of the conductive compensation block is equal to the thickness of the transparent oxide layer.
7、 如权利要求 1-6任一所述的像素结构， 还包括： 位于所述衬底基板和 所述源漏极层之间的栅极层、 栅极绝缘层和有源层； 其中， 7. The pixel structure according to any one of claims 1 to 6, further comprising: a gate layer, a gate insulation layer and an active layer located between the base substrate and the source and drain layers; wherein,
所述栅极层设置于所述衬底基板上； The gate layer is provided on the base substrate;
所述栅极绝缘层覆盖所述栅极层； The gate insulating layer covers the gate layer;
所述有源层设置于所述栅极绝缘层上。 The active layer is disposed on the gate insulation layer.
8、 一种阵列基板， 包括如权利要求 1-7任一所述的像素结构。 8. An array substrate, including the pixel structure according to any one of claims 1-7.
9、 一种显示装置， 包括如权利要求 8所述的阵列基板。 9. A display device, comprising the array substrate as claimed in claim 8.
10、 一种像素结构的制造方法， 包括： 10. A method of manufacturing a pixel structure, including:
在衬底基板的上表面形成图形化的栅极层； Form a patterned gate layer on the upper surface of the base substrate;
形成覆盖所述栅极层的栅极绝缘层； forming a gate insulating layer covering the gate layer;
在所述栅极绝缘层的上表面形成图形化的有源层； Form a patterned active layer on the upper surface of the gate insulating layer;
形成覆盖所述有源层的源漏极层； 以及 forming a source and drain layer covering the active layer; and
通过一次图形化处理工艺，形成图形化的第一钝化层和图形化的树脂层， 其中， 所述第一钝化层覆盖所述源漏极层， 且所述第一钝化层具有与所述源 漏极层连通的第一过孔； 所述树脂层设置于所述第一钝化层的上表面， 且所 述树脂层具有与所述第一过孔连通的第二过孔； 在所述树脂层的上形成图形 化的第一透明电极层； 以及 Through a patterning process, a patterned first passivation layer and a patterned resin layer are formed, wherein the first passivation layer covers the source and drain layers, and the first passivation layer has a a first via hole connecting the source and drain layers; the resin layer is provided on the upper surface of the first passivation layer, and the resin layer has a second via hole communicating with the first via hole; forming a patterned first transparent electrode layer on the resin layer; and
在所述第一过孔内形成导电补偿块。 A conductive compensation block is formed in the first via hole.
11、如权利要求 10所述的像素结构的制造方法， 其中， 在所述树脂层的 上表面形成的图形化的所述第一透明电极层与在所述第一过孔内形成的所述 导电补偿块通过一次图形化处理工艺形成。 11. The method of manufacturing a pixel structure according to claim 10, wherein the patterned first transparent electrode layer formed on the upper surface of the resin layer and the patterned first transparent electrode layer formed in the first via hole The conductive compensation block is formed through a patterning process.
12、如权利要求 11所述的像素结构的制造方法，还包括： 形成覆盖所述 树脂层和所述第一透明电极层的第二钝化层， 所述第二钝化层具有与所述第 二过孔连通的第三过孔。 12. The method of manufacturing a pixel structure according to claim 11, further comprising: forming a second passivation layer covering the resin layer and the first transparent electrode layer, the second passivation layer having a structure similar to that of the first transparent electrode layer. The second via connects to the third via.
13、如权利要求 12所述的像素结构的制造方法，还包括： 在所述第二钝 化层的上表面、 所述第三过孔内、 所述第二过孔内和所述第一过孔内形成第 二透明电极层， 所述第二透明电极层通过所述导电补偿块与所述源漏极层电 连接。 13. The method of manufacturing a pixel structure as claimed in claim 12, further comprising: placing a pixel on the upper surface of the second passivation layer, in the third via hole, in the second via hole and in the first A second transparent electrode layer is formed in the via hole, and the second transparent electrode layer is electrically connected to the source and drain layer through the conductive compensation block.
14、 如权利要求 10所述的像素结构的制造方法， 还包括： 在所述第一透明电极层上、 所述树脂层上、 所述第一过孔中和所述第二 过孔中形成第二钝化层， 所述第二钝化层包括： 形成在所述第一透明电极层 上、 所述树脂层上以及所述第一过孔中、 所述第二过孔中的透明氧化层， 和 形成在所述透明氧化层上的绝缘材料层。 14. The method of manufacturing a pixel structure according to claim 10, further comprising: forming on the first transparent electrode layer, on the resin layer, in the first via hole and in the second via hole. a second passivation layer, the second passivation layer including: a transparent oxide layer formed on the first transparent electrode layer, the resin layer, and in the first via hole and the second via hole; layer, and an insulating material layer formed on the transparent oxide layer.
15、如权利要求 14所述的像素结构的制造方法，还包括： 在所述绝缘材 料层与所述第一过孔对应的区域形成与所述透明氧化层连通的第三过孔。 15. The method of manufacturing a pixel structure according to claim 14, further comprising: forming a third via hole connected to the transparent oxide layer in a region of the insulating material layer corresponding to the first via hole.
16、 如权利要求 14-15任一所述的像素结构的制造方法， 其中， 在所述 第一过孔内形成导电补偿块包括： 16. The method of manufacturing a pixel structure according to any one of claims 14 to 15, wherein forming a conductive compensation block in the first via hole includes:
通过等离子处理工艺， 使所述透明氧化层与所述第一过孔对应的区域变 成导电体， 所述导电体即为所述导电补偿块。 Through a plasma treatment process, the area of the transparent oxide layer corresponding to the first via hole becomes a conductor, and the conductor is the conductive compensation block.
17、 如权利要求 15或 16所述的像素结构的制造方法， 还包括： 在所述 第二钝化层的上表面、 所述第三过孔内、 所述第二过孔内、 所述第一过孔内 和所述导电补偿块上表面形成第二透明电极层， 所述第二透明电极层通过所 述导电补偿块与所述源漏极层电连接。 17. The method of manufacturing a pixel structure according to claim 15 or 16, further comprising: on the upper surface of the second passivation layer, in the third via hole, in the second via hole, in the A second transparent electrode layer is formed in the first via hole and on the upper surface of the conductive compensation block, and the second transparent electrode layer is electrically connected to the source and drain layer through the conductive compensation block.
18、 如权利要求 10-17任一所述的像素结构的制造方法， 其中， 形成图 形化的第一钝化层和图形化的树脂层包括： 18. The method for manufacturing a pixel structure according to any one of claims 10 to 17, wherein forming the patterned first passivation layer and the patterned resin layer includes:
在所述源漏极层上涂覆钝化材料形成所述第一钝化层； Coating a passivation material on the source and drain layers to form the first passivation layer;
在所述第一钝化层上涂覆树脂形成所述树脂层； Coating resin on the first passivation layer to form the resin layer;
通过掩膜、 刻蚀、 剥离工序在所述树脂层上形成所述第二过孔， 在所述 第一钝化层上形成所述第一过孔， 且所述第一过孔与所述第二过孔对应。 The second via hole is formed on the resin layer through masking, etching, and stripping processes, the first via hole is formed on the first passivation layer, and the first via hole is connected to the The second via hole corresponds.
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