CN111341822B - Display substrate, preparation method thereof, display panel and display device - Google Patents
Display substrate, preparation method thereof, display panel and display device Download PDFInfo
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- CN111341822B CN111341822B CN202010181724.6A CN202010181724A CN111341822B CN 111341822 B CN111341822 B CN 111341822B CN 202010181724 A CN202010181724 A CN 202010181724A CN 111341822 B CN111341822 B CN 111341822B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
Abstract
The invention relates to the technical field of display, and provides a display substrate, a preparation method of the display substrate, a display panel and a display device. The display substrate comprises a substrate, and a thin film transistor arranged on the substrate; the passivation layer is arranged on the thin film transistor and is provided with a through hole; the protective layer is arranged on the passivation layer, a through hole is formed in the protective layer, and the distance between the hole wall of the through hole and the passivation layer is increased along the radial direction of the through hole; the planarization layer is arranged on the protection layer group, a third through hole is formed in the planarization layer, the distance between the hole wall of the third through hole and the passivation layer is increased along the radial direction of the third through hole, and the orthographic projection of the third through hole on the substrate base plate is within the orthographic projection of the through hole on the substrate base plate or is superposed with the orthographic projection of the through hole on the substrate base plate; the first electrode layer is arranged on the planarization layer and is connected with the source and drain electrodes of the thin film transistor through the third through hole, the through hole and the through hole. The third via hole of the display substrate has a slope, so that the first electrode is prevented from being broken or badly lapped.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display substrate, a preparation method of the display substrate, a display panel provided with the display substrate and a display device provided with the display panel.
Background
At present, with the development of technology, the requirement for the display device is higher and higher, the requirement for the flatness of the backplane in the OLED (organic light-Emitting Diode) technology is very high, and SOG (spin on glass coating) is a main local planarization technology in the semiconductor process, and the planarization effect is very good, so that the technology is applied to the OLED. Form the planarization layer through SOG, but because SOG's material is at the dry etching in-process, the etching rate is fast for the pore wall inclination angle is steeper, almost reaches perpendicularly, makes subsequent electrode overlap joint have broken string or overlap joint bad risk.
Therefore, it is necessary to research a new display substrate, a method of manufacturing the display substrate, a display panel on which the display substrate is mounted, and a display device on which the display panel is mounted.
The above information disclosed in this background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not constitute prior art that is already known to a person of ordinary skill in the art.
Disclosure of Invention
The present invention is directed to overcome the disadvantage of a steep hole wall slope angle in the prior art, and provides a display substrate with a gentle hole wall slope angle, a method for manufacturing the display substrate, a display panel mounted with the display substrate, and a display device mounted with the display panel.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
According to an aspect of the present disclosure, there is provided a display substrate including:
a substrate base plate;
the thin film transistor is arranged on the substrate base plate;
the passivation layer is arranged on one surface of the thin film transistor, which is far away from the substrate base plate, and a through hole is formed in the passivation layer;
the protective layer group is arranged on one surface of the passivation layer, which is far away from the substrate base plate, a through hole is formed in the protective layer group, and the distance between the hole wall of the through hole and the passivation layer is increased along the radial direction of the through hole;
the planarization layer is arranged on one surface of the protection layer group, which is far away from the substrate base plate, a third through hole is formed in the planarization layer, the distance between the hole wall of the third through hole and the passivation layer is increased along the radial direction of the third through hole, the orthographic projection of the third through hole on the substrate base plate is within the orthographic projection of the through hole on the substrate base plate, or the orthographic projection of the third through hole on the substrate base plate is superposed with the orthographic projection of the through hole on the substrate base plate;
and the first electrode layer is arranged on one surface of the planarization layer, which is deviated from the substrate base plate, and is connected with the source and drain electrodes of the thin film transistor through the third through hole, the through hole and the through hole.
In one exemplary embodiment of the present disclosure, the protection layer group includes:
the first protective layer is arranged on one surface of the passivation layer, which is far away from the substrate base plate, and is provided with a first through hole, and the distance between the hole wall of the first through hole and the passivation layer is increased along the radial direction of the first through hole;
the second protective layer is arranged on one surface, deviating from the substrate base plate, of the first protective layer, the orthographic projection of the first protective layer on the substrate base plate is located within the orthographic projection of the second protective layer on the substrate base plate, a second through hole is formed in the second protective layer, the orthographic projection of the second through hole on the substrate base plate is located within the orthographic projection of the first through hole on the substrate base plate, and the distance between the hole wall of the second through hole and the passivation layer is increased along the radial direction of the second through hole.
In one exemplary embodiment of the present disclosure, the first protective layer includes:
the first annular surface is attached to the passivation layer;
the second annular surface is opposite to the first annular surface and is connected with the first annular surface, and the second annular surface is arranged to be an arc surface protruding from one surface of the substrate base plate.
In an exemplary embodiment of the present disclosure, the first protection layer is made of an organic material, the second protection layer is made of one or more materials selected from indium gallium zinc oxide, indium tin oxide, and indium zinc oxide, and the planarization layer is made of a dielectric material.
In an exemplary embodiment of the present disclosure, a thickness of the planarization layer is greater than or equal to a thickness of a thickest point of the protection layer group.
In an exemplary embodiment of the present disclosure, the display substrate further includes:
the light-emitting layer is arranged on one surface of the first electrode layer, which is far away from the substrate base plate;
and the second electrode layer is arranged on one surface of the light-emitting layer, which is deviated from the substrate base plate.
According to an aspect of the present disclosure, there is provided a method of manufacturing a display substrate, including:
providing a substrate base plate;
forming a thin film transistor over the base substrate;
forming a passivation layer on one surface of the thin film transistor, which is far away from the substrate base plate, and patterning the passivation layer to form a through hole;
forming a protection layer group on one surface of the passivation layer, which is far away from the substrate base plate, and patterning the protection layer group to form a through hole, wherein the distance between the hole wall of the through hole and the passivation layer is increased along the radial direction of the through hole;
forming a planarization layer on one surface of the protection layer group, which is far away from the substrate base plate, and patterning the planarization layer to form a third via hole, wherein the distance between the hole wall of the third via hole and the passivation layer increases along the radial direction of the third via hole, and the orthographic projection of the third via hole on the substrate base plate is within the orthographic projection of the via hole on the substrate base plate, or the orthographic projection of the third via hole on the substrate base plate is coincident with the orthographic projection of the via hole on the substrate base plate;
and forming a first electrode layer on one surface of the planarization layer, which is far away from the substrate base plate, wherein the first electrode layer is connected with the source and drain electrodes of the thin film transistor through the third via hole, the via hole and the through hole.
In an exemplary embodiment of the present disclosure, forming a protection layer group on a side of the passivation layer away from the substrate base plate, and performing a patterning process on the protection layer group to form a via hole includes:
forming a first protective layer on one surface of the passivation layer, which is far away from the substrate base plate, and performing patterning treatment on the first protective layer to form a first through hole, wherein the distance between the hole wall of the first through hole and the passivation layer is increased along the radial direction of the first through hole;
forming a second protective layer on one surface of the first protective layer, which is far away from the substrate base plate, and performing patterning treatment on the second protective layer to form a second through hole, wherein the orthographic projection of the first protective layer on the substrate base plate is located within the orthographic projection of the second protective layer on the substrate base plate, the orthographic projection of the second through hole on the substrate base plate is located within the orthographic projection of the first through hole on the substrate base plate, and the distance between the hole wall of the second through hole and the passivation layer is increased along the radial direction of the second through hole.
In an exemplary embodiment of the present disclosure, the patterning process of the first protective layer and the second protective layer is photolithography, and the patterning process of the planarization layer is dry etching; the first protective layer is made of an organic material, the second protective layer is made of indium gallium zinc oxide, indium tin oxide or indium zinc oxide, and the planarization layer is made of a dielectric material.
According to an aspect of the present disclosure, there is provided a display panel including the display substrate of any one of the above.
According to an aspect of the present disclosure, there is provided a display device including the display panel of any one of the above.
According to the technical scheme, the invention has at least one of the following advantages and positive effects:
according to the display substrate, the surface of the passivation layer, which is far away from the substrate, is provided with the protection layer group, the protection layer group is provided with the through hole, and the distance between the hole wall of the through hole and the passivation layer is increased along the radial direction of the through hole, so that the hole wall of the through hole has a certain inclination; the surface of the protection layer group, which is far away from the substrate base plate, is provided with a planarization layer, a third through hole is formed in the planarization layer, the distance between the hole wall of the third through hole and the passivation layer is increased along the radial direction of the third through hole, the orthographic projection of the third through hole on the substrate base plate is within the orthographic projection of the through hole on the substrate base plate, or the orthographic projection of the third through hole on the substrate base plate is superposed with the orthographic projection of the through hole on the substrate base plate, so that the hole wall of the third through hole has a certain inclination. In the process of forming the third via hole, due to the protection of the protection layer group, the hole wall of the third via hole on the planarization layer has a certain inclination, so that the risk of disconnection or poor overlapping in the subsequent overlapping of the first electrode is avoided.
Drawings
The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.
FIG. 1 is a schematic structural diagram of an exemplary embodiment of a display substrate according to the present invention;
FIG. 2 is a schematic block flow diagram of one exemplary embodiment of a method of fabricating a display substrate according to the present invention;
FIG. 3 is a schematic diagram illustrating the display substrate of FIG. 1 after forming an inter-layer dielectric layer thereon;
FIG. 4 is a schematic view of the structure after the through holes are formed on the basis of FIG. 3;
FIG. 5 is a schematic structural diagram of forming a source and a drain on the basis of FIG. 4;
FIG. 6 is a schematic structural diagram of a passivation layer formed on the basis of FIG. 5;
FIG. 7 is a schematic diagram of a structure of forming a first passivation layer on the basis of FIG. 6;
FIG. 8 is a schematic diagram of a structure of forming a second passivation layer on the basis of FIG. 7;
FIG. 9 is a schematic structural diagram of a planarization material layer formed on the substrate of FIG. 8;
FIG. 10 is a schematic structural diagram of a planarization layer formed on the basis of FIG. 9;
fig. 11 is a schematic structural diagram of a first electrode layer formed on the basis of fig. 10.
The reference numerals of the main elements in the figures are as follows:
1. a substrate base plate; 2. a light-shielding layer; 3. a buffer layer;
41. an active layer; 42. a gate insulating layer; 43. a gate electrode; 44. an interlayer dielectric layer; 45. a source and a drain; 46. through the hole;
5. a passivation layer;
61. a first protective layer; 62. a second protective layer; 63. a first via hole; 64. a second via hole;
71. a planarization material layer; 72. a planarization layer; 73. a third via hole;
8. a first electrode layer; 9. and a light emitting layer.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.
The invention firstly provides a display substrate, which is shown in figure 1 and is a structural schematic diagram of an exemplary embodiment of the display substrate; the display substrate may include a substrate 1, a thin film transistor, a passivation layer 5, a protection layer group, and a planarization layer 72; the thin film transistor is arranged on the substrate base plate 1; the passivation layer 5 is arranged on one surface of the thin film transistor, which is far away from the substrate base plate 1, and is provided with a through hole; the protective layer group is arranged on one surface of the passivation layer 5, which is far away from the substrate base plate 1, a through hole is formed in the protective layer group, and the distance between the hole wall of the through hole and the passivation layer 5 is increased along the radial direction of the through hole; the planarization layer 72 is arranged on one surface of the protection layer group, which is far away from the substrate base plate 1, a third via hole 73 is arranged on the planarization layer 72, and the orthographic projection of the third via hole 73 on the substrate base plate 1 is consistent with the orthographic projection of the via hole on the substrate base plate 1.
The planarization layer is disposed on a side of the protection layer group facing away from the substrate base plate, and the position of the third via 73 coincides with the position of the via. The hole wall of the via hole on the protection layer group has a certain inclination, so that when the third via hole 73 is formed on the planarization layer, the protection layer group can be prevented from being etched to form the support of the planarization layer, the hole wall of the third via hole 73 on the planarization layer also has a certain inclination, and the risk of line breakage or poor overlapping in subsequent electrode overlapping is avoided.
In the present exemplary embodiment, the base substrate 1 may be a glass substrate or a flexible substrate.
In the present exemplary embodiment, a light-shielding layer 2 is provided on a base substrate 1, and a buffer layer 3 is provided on a surface of the light-shielding layer 2 facing away from the base substrate 1. A thin film transistor is arranged on one surface of the buffer layer 3 deviating from the substrate base plate 1, and the specific structure of the thin film transistor comprises: the active layer 41 provided on the surface of the buffer layer 3 facing away from the substrate 1 is provided with a gate insulating layer 42 on the surface of the active layer 41 facing away from the substrate 1, a gate electrode 43 on the surface of the gate insulating layer 42 facing away from the substrate 1, an interlayer dielectric layer 44 on the surface of the gate electrode 43 facing away from the substrate 1, and a through hole 46 in the interlayer dielectric layer 44. A source/drain electrode 45 is provided on a surface of the interlayer dielectric layer 44 facing away from the substrate 1, and the source/drain electrode 45 is connected to the active layer 41 through a via hole 46 in the interlayer dielectric layer 44. A passivation layer 5 is arranged on one surface of the source/drain electrode 45, which is far away from the substrate base plate 1.
The thin film transistor is a top gate thin film transistor. In other example embodiments of the present invention, the thin film transistor may also be a bottom gate thin film transistor, and the structure of the bottom gate thin film transistor is the prior art and will not be described herein again.
With reference to fig. 1, a first protective layer 61 is disposed on a surface of the passivation layer 5 away from the substrate 1, a first via hole 63 is disposed on the first protective layer 61, and a distance between a hole wall of the first via hole and the passivation layer increases along a radial direction of the first via hole, that is, the hole wall of the first via hole has a certain slope, and the first via hole is a bell mouth. The first protective layer 61 is made of an organic material, and specifically, may be a pixel defining layer or a phenolic resin material. The first protective layer 61 may include a first annular surface and a second annular surface; the first ring surface is attached to the passivation layer 5; the first annulus is planar. The second ring surface is opposite to the first ring surface, the outer ring edge of the second ring surface is connected with the outer ring edge of the first ring surface, and the inner ring edge of the second ring surface is connected with the inner ring edge of the first ring surface; the second annular surface is provided as an arc surface protruding to a surface away from the substrate base board 1. That is, the cross-sectional shape of the first protective layer 61 perpendicular to the base substrate 1 is two less semicircles, and the space between the two less semicircles is the first via 63 formed.
In addition, the structure of the first protective layer 61 is not limited to the above description, and for example, the cross-sectional shape of the first protective layer 61 perpendicular to the base substrate 1 may also be trapezoidal, triangular, or the like, as long as the side where the hole wall of the first via 63 is formed is made a hypotenuse rather than a square.
A second protective layer 62 is disposed on a surface of the first protective layer 61 facing away from the substrate base plate 1, and the second protective layer 62 completely covers the first protective layer 61, so that an orthographic projection of the first protective layer 61 on the substrate base plate 1 is larger than an orthographic projection of the second protective layer 62 on the substrate base plate 1, and thus the orthographic projection of the first protective layer 61 on the substrate base plate 1 is located within an orthographic projection of the second protective layer 62 on the substrate base plate 1. The second protective layer 62 is provided with a second via hole 64, and a distance between a hole wall of the second via hole and the passivation layer increases along a radial direction of the second via hole, that is, the hole wall of the second via hole has a certain slope, and the second via hole is a bell mouth. The second via hole has a shape substantially corresponding to the shape of the first via hole due to the substantially uniform thickness of the second protective layer 62. Since the second passivation layer 62 completely covers the first passivation layer 61 and the second passivation layer 62 has a thickness, the radial dimension (diameter in the case of a circular hole) of the second via 64 is smaller than the radial dimension (diameter in the case of a circular hole) of the first via 63, so that the orthographic projection of the second via 64 on the substrate base 1 is located within the orthographic projection of the first via 63 on the substrate base 1. The material of the second passivation layer 62 may be IGZO (indium gallium zinc oxide), ITO (indium tin oxide), IZO (indium zinc oxide), or a mixture of two or more thereof.
In addition, in other example embodiments of the present invention, the protection layer group may also include only one protection layer, and three or more protection layers may also be provided as long as the hole wall of the via hole formed by the protection layer has a relatively gentle slope.
In the present exemplary embodiment, a planarization layer 72 is provided on a surface of the second protective layer 62 facing away from the base substrate 1. The planarization layer 72 is made of a dielectric material. The thickness of the planarization layer 72 is equal to the thickness of the thickest set of protection layers. In the present exemplary embodiment, the thickness of the planarization layer 72 is equal to the sum of the thickness of the thickest portion of the first protective layer 61 and the thickest portion of the second protective layer 62, so that the display substrate is one plane after the planarization layer 72 is coated. The planarization layer 72 is provided with a third via 73, and an orthographic projection of the third via 73 on the substrate base plate 1 is coincident with an orthographic projection of the second via 64 on the substrate base plate 1. Of course, the thickness of the planarization layer 72 may also be greater than the thickness of the protective layer group, i.e., the thickness of the planarization layer 72 is greater than the sum of the thickness of the first protective layer 61 and the thickness of the second protective layer 62. Furthermore, the orthographic projection of the third via 73 on the substrate base plate 1 may also be within the orthographic projection of the second via 64 on the substrate base plate 1, i.e. the radial dimension of the third via 73 is smaller than the radial dimension of the second via 64.
In the present exemplary embodiment, the first electrode layer 8 is provided on the surface of the planarization layer 72 facing away from the base substrate 1, and the first electrode layer 8 may be an anode. The first electrode layer 8 is connected to the source and drain electrodes 45 through the third via 73, the second via 64, the first via 63, and the through hole. A light-emitting layer 9 is provided on the side of the first electrode layer 8 facing away from the substrate base plate 1, and a second electrode layer, which may be a cathode, is provided on the side of the light-emitting layer 9 facing away from the substrate base plate 1.
Note that the structure of the display substrate is a top emission type, but it is needless to say that the display substrate may be a bottom emission type in another exemplary embodiment of the present invention.
Further, the present invention also provides a method for manufacturing a display substrate, referring to the schematic flow diagram of an exemplary embodiment of the method for manufacturing a display substrate of the present invention shown in fig. 2, the method may include the following steps:
in step S10, a substrate 1 is provided.
Step S20, forming a thin film transistor on the substrate base plate 1.
And step S30, forming a passivation layer 5 on one surface of the thin film transistor, which is far away from the substrate base plate 1, and patterning the passivation layer 5 to form a through hole.
Step S40, forming a protection layer group on a surface of the passivation layer 5 away from the substrate base plate 1, and performing patterning processing on the first protection layer 61 to form a via hole, wherein a distance between a hole wall of the via hole and the passivation layer 5 increases along a radial direction of the via hole.
Step S50, forming a planarization layer 72 on a surface of the second protection layer 62 away from the substrate base plate 1, and performing patterning processing on the planarization layer 72 to form a third via hole 73, where a distance between a hole wall of the third via hole 73 and the passivation layer 5 increases along a radial direction of the third via hole 73, an orthographic projection of the third via hole 73 on the substrate base plate 1 is within an orthographic projection of the via hole on the substrate base plate 1, or the orthographic projection of the third via hole 73 on the substrate base plate 1 coincides with an orthographic projection of the second via hole 64 on the substrate base plate 1.
Step S60, forming a first electrode layer on a surface of the planarization layer away from the substrate base plate, where the first electrode layer is connected to the source and drain of the thin film transistor through the third via hole 73, the via hole, and the through hole.
The respective steps of the method for manufacturing the display substrate will be described in detail below.
A substrate 1 is provided, and the substrate 1 may be a glass substrate or a flexible substrate.
Referring to fig. 3, a light-shielding layer 2 is formed on an underlying substrate 1, and a buffer layer 3 is formed on a surface of the light-shielding layer 2 facing away from the underlying substrate 1. An active layer 41 is formed on a surface of the buffer layer 3 facing away from the base substrate 1, a gate insulating layer 42 is formed on a surface of the active layer 41 facing away from the base substrate 1, a gate electrode 43 is formed on a surface of the gate insulating layer 42 facing away from the base substrate 1, and an interlayer dielectric layer 44 is formed on a surface of the gate electrode 43 facing away from the base substrate 1.
Referring to fig. 4, the interlayer dielectric layer 44 is patterned to form via holes 46.
Referring to fig. 5, a source/drain electrode 45 is formed on a surface of the interlayer dielectric layer 44 facing away from the substrate 1, and the source/drain electrode 45 is connected to the active layer 41 through a via hole 46 in the interlayer dielectric layer 44.
Referring to fig. 6, a passivation layer 5 is formed on a surface of the source/drain electrode 45 facing away from the substrate base plate 1.
Referring to fig. 7, a first protective material layer is deposited on a side of the passivation layer 5 away from the substrate base plate 1, and the first protective material layer is subjected to photolithography to form a first protective layer 61 and a first via 63. The first protective layer 61 may comprise a first annulus and a second annulus; the first ring surface is attached to the passivation layer 5; the first annulus is planar. The second ring surface is opposite to the first ring surface, is connected with the first ring surface and is arranged into an arc surface protruding towards one surface back to the substrate base plate 1. That is, the cross-sectional shape of the first protective layer 61 perpendicular to the base substrate 1 is two less semicircles, and the space between the two less semicircles is the first via hole 63 to be formed.
Referring to fig. 8, a second protective material layer is deposited on a side of the first protective layer 61 facing away from the substrate base plate 1, and the second protective material layer is subjected to photolithography to form a second protective layer 62 and a second via 64. The second protective layer 62 completely covers the first protective layer 61 such that an orthographic projection of the first protective layer 61 on the base substrate 1 is larger than an orthographic projection of the second protective layer 62 on the base substrate 1, and thus the orthographic projection of the first protective layer 61 on the base substrate 1 is located within the orthographic projection of the second protective layer 62 on the base substrate 1. Since the second passivation layer 62 completely covers the first passivation layer 61 and the second passivation layer 62 has a thickness, the diameter of the second via 64 is smaller than the diameter of the first via 63, so that the orthographic projection of the second via 64 on the substrate 1 is located within the orthographic projection of the first via 63 on the substrate 1. The material of the second passivation layer 62 may be IGZO (indium gallium zinc oxide), ITO (indium tin oxide), IZO (indium zinc oxide), or the like. The second protective layer 62 can protect the first protective layer 61 when the planarization layer 72 is dry-etched in a subsequent process.
Referring to fig. 9, a liquid solvent containing a dielectric material is spin-coated on the surfaces of the second protective layer 62 and the passivation layer 5 facing away from the base substrate 1, and then the solvent is removed by a heat treatment to form a planarization material layer 71. The material of the planarization material layer 71 is a dielectric material (approximately silicon dioxide SiO 2).
Referring to fig. 10, the layer 71 of applied planarization material is dry etched to form a planarization layer 72 and a third via 73, the orthographic projection of the third via 73 on the substrate base 1 coinciding with the orthographic projection of the via on said substrate base 1. The thickness of the planarization layer 72 is equal to the thickness of the thickest set of protection layers. In the present exemplary embodiment, the thickness of the planarization layer 72 is equal to the sum of the thickness of the thickest part of the first protective layer 61 and the thickness of the thickest part of the second protective layer 62, so that the display substrate is one plane after the planarization material layer 71 is coated. Of course, the thickness of the planarization layer 72 may also be greater than the thickness of the protective layer group, i.e., the thickness of the planarization layer 72 is greater than the sum of the thickness of the first protective layer 61 and the thickness of the second protective layer 62. Furthermore, the orthographic projection of the third via 73 on the substrate base plate 1 may also be within the orthographic projection of the second via 64 on the substrate base plate 1, i.e. the radial dimension of the third via 73 is smaller than the radial dimension of the second via 64.
Referring to fig. 11, a first electrode layer 8 is formed on a surface of the planarization layer 72 facing away from the base substrate 1, and the first electrode layer 8 may be an anode. The first electrode layer 8 is connected to the source and drain electrodes 45 through the third via 73, the second via 64, the first via 63, and the through hole. Referring to fig. 1, a light-emitting layer 9 is formed on a surface of the first electrode layer 8 facing away from the base substrate 1, and a second electrode layer, which may be a cathode, is formed on a surface of the light-emitting layer 9 facing away from the base substrate 1.
Furthermore, the invention also provides a display panel, which comprises the display substrate. The detailed structure of the display substrate has already been described above, and therefore, the detailed description thereof is omitted here.
Compared with the prior art, the beneficial effects of the display panel provided by the embodiment of the invention are the same as the beneficial effects of the display substrate provided by the embodiment, and the details are not repeated herein.
Furthermore, the invention also provides a display device which comprises the display panel. The specific type of the display device is not particularly limited, and any display device commonly used in the art may be used, specifically, for example, a liquid crystal display, an OLED display, a mobile device such as a mobile phone, a wearable device such as a watch, a VR device, and the like.
It should be noted that the display device includes other necessary components and components besides the display panel, taking the display as an example, specifically, such as a housing, a circuit board, a power line, and the like, and those skilled in the art can supplement the display device accordingly according to the specific use requirements of the display device, and details are not described herein.
Compared with the prior art, the display device provided by the embodiment of the invention has the same beneficial effects as the display substrate provided by the embodiment, and the detailed description is omitted here.
The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments, and the features discussed in connection with the embodiments are interchangeable, if possible. In the above description, numerous specific details are provided to give a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention may be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.
Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". Other relative terms, such as "high", "low", "top", "bottom", and the like, are also intended to have similar meanings. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.
In this specification, the terms "a", "an", "the" and "the" are used to indicate the presence of one or more elements/components/parts/etc.; the terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.; the terms "first," "second," and "third," etc. are used merely as labels, and are not limiting as to the number of their objects.
It is to be understood that the invention is not limited in its application to the details of construction and the arrangement of components set forth in the description. The invention is capable of other embodiments and of being practiced and carried out in various ways. The foregoing variations and modifications fall within the scope of the present invention. It will be understood that the invention disclosed and defined in this specification extends to all alternative combinations of two or more of the individual features mentioned or evident from the text and/or drawings. All of these different combinations constitute alternative aspects of the present invention. The embodiments described in this specification illustrate the best mode known for carrying out the invention and will enable those skilled in the art to utilize the invention.
Claims (10)
1. A display substrate, comprising:
a substrate base plate;
the thin film transistor is arranged on the substrate base plate;
the passivation layer is arranged on one surface of the thin film transistor, which is far away from the substrate base plate, and a through hole is formed in the passivation layer;
the protection layer group locates deviating from of passivation layer the one side of substrate base plate, be provided with the via hole on the protection layer group, the pore wall of via hole with distance between the passivation layer is followed the radial increase of via hole, the protection layer group includes: the first protective layer is arranged on one surface of the passivation layer, which is far away from the substrate base plate, and is provided with a first through hole, and the distance between the hole wall of the first through hole and the passivation layer is increased along the radial direction of the first through hole; the first protective layer comprises a first annular surface and a second annular surface, and the first annular surface is attached to the passivation layer; the second ring surface is arranged opposite to the first ring surface and is connected with the first ring surface, and the second ring surface is an arc surface protruding towards one surface departing from the substrate base plate;
the planarization layer is arranged on one surface of the protection layer group, which is far away from the substrate base plate, a third through hole is formed in the planarization layer, the distance between the hole wall of the third through hole and the passivation layer is increased along the radial direction of the third through hole, the orthographic projection of the third through hole on the substrate base plate is within the orthographic projection of the through hole on the substrate base plate, or the orthographic projection of the third through hole on the substrate base plate is superposed with the orthographic projection of the through hole on the substrate base plate;
and the first electrode layer is arranged on one surface of the planarization layer, which is far away from the substrate base plate, and the first electrode layer is connected with the source drain electrode of the thin film transistor through the third through hole, the through hole and the through hole.
2. The display substrate of claim 1, wherein the set of protection layers further comprises:
the second protective layer is arranged on one surface, deviating from the substrate base plate, of the first protective layer, the orthographic projection of the first protective layer on the substrate base plate is located within the orthographic projection of the second protective layer on the substrate base plate, a second through hole is formed in the second protective layer, the orthographic projection of the second through hole on the substrate base plate is located within the orthographic projection of the first through hole on the substrate base plate, and the distance between the hole wall of the second through hole and the passivation layer is increased along the radial direction of the second through hole.
3. The display substrate according to claim 2, wherein the first protective layer is made of an organic material, the second protective layer is made of one or more of indium gallium zinc oxide, indium tin oxide and indium zinc oxide, and the planarization layer is made of a dielectric material.
4. The display substrate of claim 1, wherein the thickness of the planarization layer is greater than or equal to the thickness of the thickest of the set of protection layers.
5. The display substrate of claim 1, further comprising:
the light-emitting layer is arranged on one surface of the first electrode layer, which is far away from the substrate base plate;
and the second electrode layer is arranged on one surface of the light-emitting layer, which is deviated from the substrate base plate.
6. A method for preparing a display substrate is characterized by comprising the following steps:
providing a substrate base plate;
forming a thin film transistor over the base substrate;
forming a passivation layer on one surface of the thin film transistor, which is far away from the substrate base plate, and patterning the passivation layer to form a through hole;
forming a protection layer group on one surface of the passivation layer, which is far away from the substrate base plate, and patterning the protection layer group to form a through hole, wherein the distance between the hole wall of the through hole and the passivation layer is increased along the radial direction of the through hole;
forming a planarization layer on one surface of the protection layer group, which is far away from the substrate base plate, and patterning the planarization layer to form a third via hole, wherein the distance between the hole wall of the third via hole and the passivation layer is increased along the radial direction of the third via hole, and the orthographic projection of the third via hole on the substrate base plate is within the orthographic projection of the via hole on the substrate base plate, or the orthographic projection of the third via hole on the substrate base plate is coincident with the orthographic projection of the via hole on the substrate base plate;
forming a first electrode layer on one surface of the planarization layer, which is far away from the substrate base plate, wherein the first electrode layer is connected with the source and drain electrodes of the thin film transistor through the third via hole, the via hole and the through hole;
wherein, form the protection layer group in the one side of the passivation layer that deviates from the substrate base plate to carry out patterning to the protection layer group in order to form the via hole, include:
forming a first protective layer on one surface of the passivation layer, which is far away from the substrate base plate, and performing patterning treatment on the first protective layer to form a first through hole, wherein the distance between the hole wall of the first through hole and the passivation layer is increased along the radial direction of the first through hole; the first protective layer comprises a first ring surface and a second ring surface, and the first ring surface is attached to the passivation layer; the second ring surface is opposite to the first ring surface and is connected with the first ring surface, and the second ring surface is arranged to be an arc surface protruding from one surface of the substrate base plate.
7. The method for manufacturing a display substrate according to claim 6, wherein a protection layer group is formed on a surface of the passivation layer away from the substrate base plate, and the protection layer group is subjected to patterning processing to form a via hole, further comprising:
forming a second protective layer on one surface of the first protective layer, which is far away from the substrate base plate, and performing patterning treatment on the second protective layer to form a second through hole, wherein the orthographic projection of the first protective layer on the substrate base plate is located within the orthographic projection of the second protective layer on the substrate base plate, the orthographic projection of the second through hole on the substrate base plate is located within the orthographic projection of the first through hole on the substrate base plate, and the distance between the hole wall of the second through hole and the passivation layer is increased along the radial direction of the second through hole.
8. The method for manufacturing a display substrate according to claim 7, wherein the patterning process of the first protective layer and the second protective layer is photolithography, and the patterning process of the planarization layer is dry etching; the first protective layer is made of an organic material, the second protective layer is made of indium gallium zinc oxide, indium tin oxide or indium zinc oxide, and the planarization layer is made of a dielectric material.
9. A display panel comprising the display substrate according to any one of claims 1 to 5.
10. A display device characterized by comprising the display panel according to claim 9.
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| CN202010181724.6A CN111341822B (en) | 2020-03-16 | 2020-03-16 | Display substrate, preparation method thereof, display panel and display device |
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| JP2000208626A (en) * | 1999-01-18 | 2000-07-28 | Toshiba Corp | Production of semiconductor device |
| TWI228782B (en) * | 2004-01-19 | 2005-03-01 | Toppoly Optoelectronics Corp | Method of fabricating display panel |
| CN103531593B (en) * | 2013-10-29 | 2015-03-04 | 京东方科技集团股份有限公司 | Pixel structure, array substrate, display device and manufacturing method of pixel structure |
| KR102505879B1 (en) * | 2016-03-24 | 2023-03-06 | 삼성디스플레이 주식회사 | Display apparatus |
| CN107424520B (en) * | 2017-07-26 | 2019-04-16 | 京东方科技集团股份有限公司 | Substrate and preparation method thereof, display panel, display device |
| CN109300947B (en) * | 2018-09-28 | 2021-09-07 | 京东方科技集团股份有限公司 | Flexible display substrate, manufacturing method thereof and display device |
| CN110797303B (en) * | 2019-11-08 | 2022-05-06 | 京东方科技集团股份有限公司 | Substrate, preparation method thereof and display device |
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