JP2008065012A - Liquid crystal display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display panel of low costs wherein performance of a thin film transistor is not lowered by using a simple process by which a gate electrode is formed without using a bank. <P>SOLUTION: A gate line GL is formed by ink jet direct drawing on an inner surface of a substrate SUB. A gate electrode GT is formed by the ink jet direct drawing at a gate electrode part of the thin film transistor. The gate electrode GT is partially overlapped on the gate line GL and film-deposited directly on the inner surface of the substrate SUB at a part (the gate electrode) to be an underlayer of a semiconductor film of the thin film transistor. The cross section of the gate line GL applied by the ink jet direct drawing and then baked has a nearly partial circular shape and the gate electrode GT is formed by layering a part of a thin conductive thin film formed by the ink jet direct drawing on the gate line. As the film thickness of the gate electrode GT, such a film thickness that is considered to have no level difference to a gate insulating film to be formed on the gate electrode GT is obtained. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a liquid crystal display panel constituting a liquid crystal display device, and more particularly to an active matrix type liquid crystal display panel.

  The liquid crystal display device is configured by combining a liquid crystal display panel PNL with peripheral devices such as a drive circuit and a backlight. Usually, a liquid crystal display panel constituting an active matrix type liquid crystal display device has a liquid crystal between one insulating substrate (active matrix substrate or thin film transistor substrate) and the other insulating substrate (counter substrate or color filter substrate). It is configured by enclosing.

  A thin film transistor (TFT) and a pixel electrode driven by the thin film transistor are provided on the inner surface of the active matrix substrate, and an alignment film is formed on the uppermost layer to provide a liquid crystal alignment control ability. A polarizing plate is attached to the outer surface (rear surface). On the other hand, the inner surface of the color filter substrate has a color filter, a light shielding layer (black matrix) partitioning between the color filters of adjacent pixels, and a counter electrode. Control ability is given. A polarizing plate is also attached to the outer surface (surface).

  FIG. 6 is a cross-sectional view illustrating a conventional configuration of a thin film transistor. In this thin film transistor, the gate electrode is formed by sputtering a gate metal (conductive material) and a photo process (photolithography process). A gate electrode GT, a gate insulating film GI, a semiconductor film SI composed of a silicon semiconductor film S and an n + silicon semiconductor film nS (contact layer), a source electrode SD1 and a drain are formed on the inner surface of an insulating substrate (thin film transistor substrate) SUB preferably made of glass. The electrode SD2 is stacked. In this thin film transistor, the thickness H of the gate electrode GT is 0.6 to 1 μm or more, and has a step having a taper indicated by an arrow B. A protective film, a pixel electrode, and an alignment film are formed on this, but illustration is omitted.

  FIG. 7 is a cross-sectional view illustrating another conventional configuration of a thin film transistor. This thin film transistor is formed by applying a conductive material by ink jet to a bank in which the gate electrode is formed following the gate electrode, and baking it. A gate electrode GT, a gate insulating film GI, a silicon semiconductor film S and an n + silicon semiconductor film nS (formed by a gate bank G-BNK formed by a photolithography process on the inner surface of an insulating substrate (thin film transistor substrate) SUB, preferably made of glass. The semiconductor film SI composed of the contact layer), the source electrode SD1, and the drain electrode SD2 are stacked. A protective film, a pixel electrode, and an alignment film are formed on this, but illustration is omitted.

  8A and 8B are explanatory diagrams of a process of manufacturing the thin film transistor of FIGS. 6 and 7, FIG. 8A shows a process of manufacturing the thin film transistor of FIG. 6, and FIG. 8B shows a process of manufacturing the thin film transistor of FIG. .

  First, manufacture of the thin film transistor of FIG. 6 will be described with reference to FIG. A gate metal is sputtered on the surface of the thin film transistor substrate (hereinafter simply referred to as substrate) SUB (P-a1). A photoresist is applied thereon, and gate wiring photo processing is performed to leave a resist having a gate wiring pattern by mask exposure (P-a2). This is dry-etched to dissolve gate metal other than the gate wiring pattern (P-a3), and then the resist is removed. Remove (P-a4).

  ITO (indium tin oxide) or Ni (nickel) is sputtered on the gate wiring (P-a5), a photoresist is applied, and a gate electrode pattern (or an upper layer of the gate wiring is included by mask exposure) Gate wiring photo processing is performed to leave a resist having a gate electrode pattern (P-a6). This is etched to dissolve gate metal other than the pattern of the gate electrode GL (or the gate electrode including the upper layer of the gate wiring) (P-a7), and then the resist is removed. It is removed (P-a8). Thereafter, a thin film transistor is manufactured by performing a process subsequent to a process of sequentially forming three layers of a gate insulating film GI, a silicon semiconductor film, and an n + silicon semiconductor film by CVD.

  Next, manufacture of the thin film transistor of FIG. 7 will be described with reference to FIG. An ink-jet bank material (photoresist) is applied to the surface of the substrate SUB (P-b1), and a groove of the gate bank G-BNK having a pattern of the gate wiring and the gate electrode GT is patterned by mask exposure (P- b2) and firing (baking) (Pb3) to form the gate bank G-BNK. The groove of the gate bank G-BNK obtained by baking is given lyophilicity, and lyophobic treatment is performed to give repellency to other parts. First, silver (Ag) or copper ( A solution (ink) in which conductive fine particles such as Cu) are dispersed is applied by inkjet (P-b4). Next, a solution (ink) in which conductive fine particles such as nickel, ITO, silver, and copper are dispersed is applied to the gate electrode GT by inkjet (P-b5). Thereafter, a thin film transistor is manufactured by performing a process subsequent to a process of sequentially forming three layers of a gate insulating film GI, a silicon semiconductor film, and an n + silicon semiconductor film by CVD.

Patent Document 1 discloses that the wiring of the thin film transistor substrate described above is formed by an ink jet method. In Patent Document 1, a gate electrode of a thin film transistor TFT is formed by an ink jet method using a liquid material containing a conductive material, and a source electrode and a drain electrode of the thin film transistor TFT are made of a liquid material containing a semiconductor material. And forming by an ink jet method. Patent Document 2 discloses that the photocatalyst layer is exposed to obtain a lyophilic pattern.
JP 2003-318193 A JP 2000-249821 A

  In the prior art shown in FIG. 6, since the gate electrode is patterned by dry etching of the gate metal, a step having a taper is formed at the etching edge. The tapered surface is severely uneven, which is one of the factors that hinder the performance improvement of the thin film transistor, such as the gate insulating film and the silicon semiconductor film formed on the tapered surface being deteriorated and the off-leakage being increased. Furthermore, the taper portion forming the step has a gate insulating film that crosses over, and the CVD film thickness becomes thin at this crossing portion to cause pinholes, step breaks, etc., so it is necessary to make the film thickness larger than necessary. As a result, the performance of the thin film transistor is lowered, which is one of the factors that hinder the performance improvement.

  In the prior art shown in FIG. 7, since conductive ink is poured into the groove of the bank, a step that becomes an obstacle to CVD film formation does not occur. However, although not shown in FIG. 8B, a pre-process for patterning the bank and its lyophobic treatment is required, which complicates the process and increases costs.

  An object of the present invention is to provide a low-cost liquid crystal display panel that does not deteriorate the performance of a thin film transistor by using a simple process for forming a gate electrode without using a bank.

  In order to achieve the above object, in the liquid crystal display panel of the present invention, the gate electrode is formed by ink-jet direct drawing.

  According to the present invention, it is possible to provide a liquid crystal display panel including a high-performance thin film transistor that can greatly reduce the number of processes, is low in cost, and has very small steps.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings of the examples.

  FIG. 1 is an explanatory view of a manufacturing process of a gate wiring and a gate electrode portion of a thin film transistor constituting a liquid crystal display panel according to a first embodiment of the present invention, and an essential structure thereof. FIG. (B) is sectional drawing along the AA 'line of Fig.1 (a). FIG. 2 is a cross-sectional view showing the entire structure of the thin film transistor constituting the first embodiment of the liquid crystal display panel according to the present invention. FIG. 3 is a manufacturing process diagram of the gate wiring and the gate electrode portion of the thin film transistor constituting the first embodiment of the liquid crystal display panel according to the present invention.

  1A and 3, the gate wiring GL is formed on the inner surface of the substrate SUB by ink-jet direct drawing ((a-1) in FIG. 1 (a), P-1 in FIG. 3). As a material of the gate wiring GL, an ink in which fine particles of silver (Ag) or copper (Cu) are dispersed in a solvent is used. Next, the gate electrode GT is formed on the gate electrode portion of the thin film transistor by ink-jet direct drawing ((a-2) in FIG. 1A, P-2 in FIG. 3). The gate electrode GT partially overlaps the gate wiring GL, and is directly formed on the inner surface of the substrate SUB at the lower layer (gate electrode) of the semiconductor film of the thin film transistor. As the material of the gate electrode GT, ink in which fine particles of nickel (Ni), ITO, silver (Ag), or copper (Cu) are dispersed in a solvent is used.

  A cross-sectional structure of the gate line GL and the gate line GL is shown in FIG. The cross section of the gate wiring GL applied and fired by ink jet direct drawing is substantially partially circular, and a part of a thin conductive thin film formed by ink jet direct drawing is laminated thereon to form the gate electrode GT. ing. The thickness of the gate electrode GT can be regarded as a step-less thickness with respect to the gate insulating film formed in the upper layer. This film thickness can be 2000 mm or less, and can also be 1000 mm or less.

  Thereafter, as shown in FIG. 2, three layers of a gate insulating film GI, a silicon semiconductor film S, and an n + silicon semiconductor film nS are sequentially formed by CVD, and a source electrode SD1 and a drain electrode SD2 are formed by a conventional process. Note that the n + silicon semiconductor film nS is a contact layer of the source electrode and the drain electrode, and forms an active layer SI of the thin film transistor together with the silicon semiconductor film S.

  According to the first embodiment, there is no step in the gate electrode that becomes an obstacle to CVD film formation, and there is no need for a pre-process for bank patterning or lyophobic treatment, thereby reducing performance with a simple process. It is possible to provide a low-cost liquid crystal display panel using a thin film transistor that is not used.

  FIG. 4 is a plan view of a main part of a gate wiring, a gate electrode part, a source electrode and a drain electrode part of a thin film transistor constituting Embodiment 2 of the liquid crystal display panel according to the present invention. In the second embodiment, similarly to the first embodiment, the gate wiring GL is directly drawn by inkjet, and the gate electrode GT is formed thereon by inkjet direct drawing. A gate insulating film and a semiconductor film SI (not shown) are formed on the gate electrode GT by CVD, and the semiconductor film SI is patterned.

  Thereafter, the metal film of the source wiring SL is sputtered so as to cover the semiconductor film SI, and the source electrode SD1 and the drain electrode SD2 are formed on the semiconductor film SI by a photo process. The source electrode SD1 and the drain electrode SD2 are patterned in a comb shape that meshes with each other. For example, the gate electrode GT has a width (W) in a direction parallel to the gate line GL of 30 μm and a length (L) in a direction parallel to the source line SL of 30 μm or more. According to the second embodiment, as in the first embodiment, since the gate electrode GT has almost no step, the fine source electrode SD1 and the drain electrode SD2 can be formed, so that the channel length can be increased.

  FIG. 5 is a process diagram for explaining Example 3 of the liquid crystal display panel according to the present invention. In the third embodiment, a narrow gate electrode GT is formed. As in the first embodiment described with reference to FIG. 1, the gate wiring GL is directly drawn by ink jet (P-1). A metal thin film for the gate electrode GT is directly drawn on an ink jet by partially overlapping the gate wiring GL (P-2). It is difficult to form a fine pattern with the metal thin film for the gate electrode GT by ink-jet direct drawing. In Example 3, a photoresist is applied on the metal thin film for the gate electrode GT directly drawn by inkjet, mask exposure and development (P-3), wet etching (P-4), and the photoresist is peeled and washed. (P-5).

  Thereafter, the three layers of the gate insulating film GI, the silicon semiconductor film S, and the n + silicon semiconductor film nS are sequentially formed by CVD, and the source electrode SD1 and the drain electrode SD2 are formed by a conventional process. According to the third embodiment, in addition to the effects of the first embodiment, a narrow gate electrode GT that cannot be obtained by inkjet direct drawing can be obtained, and a thin film transistor compatible with high-definition display can be manufactured.

The manufacturing process of the gate wiring and gate electrode part of the thin film transistor which comprises Example 1 of the liquid crystal display panel by this invention, and its explanatory drawing can be demonstrated. It is sectional drawing which shows the whole structure of the thin-film transistor which comprises Example 1 of the liquid crystal display panel by this invention. It is a manufacturing process figure of the gate wiring and gate-electrode part of the thin-film transistor which comprises Example 1 of the liquid crystal display panel by this invention. It is the principal part top view of the gate wiring of the thin-film transistor which comprises Example 2 of the liquid crystal display panel by this invention, a gate electrode part, a source electrode, and a drain electrode part. It is a process figure for demonstrating Example 3 of the liquid crystal display panel by this invention. It is sectional drawing explaining the conventional structure of a thin-film transistor. It is sectional drawing explaining the other conventional structure of a thin-film transistor. It is explanatory drawing of the process of manufacturing the thin-film transistor of FIG. 6 and FIG.

Explanation of symbols

SUB ... Substrate (thin film transistor substrate), GL ... Gate wiring, GT ... Gate electrode, GI ... Gate insulating film, nSI ... n ⁺ contact layer, S ... Silicon semiconductor layer.

Claims (18)

A liquid crystal display panel having an insulating substrate on which a thin film transistor is formed,
The thin film transistor on the insulating substrate includes a gate wiring made of the first conductive wiring material formed on the insulating substrate by ink jet direct drawing, and a part of the gate wiring superimposed on the gate wiring by ink jet direct drawing. A liquid crystal display panel comprising a gate electrode made of a thin film of the second conductive wiring material formed. In claim 1,
The second conductive wiring material is a solution in which any one of Ni, ITO, Ag, Cu fine particles or a mixture of two or more fine particles is dispersed in an inkjet solvent. . In claim 1,
The liquid crystal display panel, wherein the second conductive wiring material is a solution in which Ag or Cu fine particles or a mixture of these fine particles is dispersed in an inkjet solvent. In claim 2 or 3,
A liquid crystal display panel, wherein the thickness of the gate electrode is 2000 mm or less. In claim 2 or 3,
A liquid crystal display panel, wherein the gate electrode has a thickness of 1000 mm or less. A liquid crystal display panel having an insulating substrate on which a thin film transistor is formed,
The thin film transistor on the insulating substrate includes a gate wiring made of a first conductive wiring material formed on the insulating substrate by direct drawing of an ink jet;
A gate electrode made of a thin film of a second conductive wiring material formed by direct drawing of an ink jet with a portion superimposed on the gate wiring;
A semiconductor film formed to cover the gate electrode;
A liquid crystal display panel comprising a source electrode and a drain electrode facing each other over a channel formed in the semiconductor film and on the semiconductor film. In claim 6,
The liquid crystal display panel, wherein the source electrode and the drain electrode have a comb shape that meshes with each other on the semiconductor film. In claim 6 or 7,
The second conductive wiring material is a solution in which any one of Ni, ITO, Ag, Cu fine particles or a mixture of two or more fine particles is dispersed in an inkjet solvent. . In claim 6 or 7,
The liquid crystal display panel, wherein the second conductive wiring material is a solution in which Ag or Cu fine particles or a mixture of these fine particles is dispersed in an inkjet solvent. In claim 6,
A liquid crystal display panel, wherein the thickness of the gate electrode is 2000 mm or less. In claim 6,
A liquid crystal display panel, wherein the gate electrode has a thickness of 1000 mm or less. A liquid crystal display panel having an insulating substrate on which a thin film transistor is formed,
The thin film transistor on the insulating substrate includes a gate wiring made of a first conductive wiring material formed on the insulating substrate by direct drawing of an ink jet;
A gate electrode obtained by processing a thin film of a second conductive wiring material formed by direct drawing of an ink jet with a part superimposed on the gate wiring;
A semiconductor film formed to cover the gate electrode;
A liquid crystal display panel comprising a source electrode and a drain electrode facing each other over a channel formed in the semiconductor film and on the semiconductor film. In claim 12,
The liquid crystal display panel, wherein the gate electrode has a width of 10 μm or less. In claim 12,
The liquid crystal display panel, wherein the source electrode and the drain electrode have a comb shape that meshes with each other on the semiconductor film. In claim 12, 13 or 14,
The second conductive wiring material is a solution in which any one of Ni, ITO, Ag, Cu fine particles or a mixture of two or more fine particles is dispersed in an inkjet solvent. . In claim 12, 13 or 14,
The liquid crystal display panel, wherein the second conductive wiring material is a solution in which Ag or Cu fine particles or a mixture of these fine particles is dispersed in an inkjet solvent. In claim 12,
A liquid crystal display panel, wherein the thickness of the gate electrode is 2000 mm or less. In claim 12,
A liquid crystal display panel, wherein the gate electrode has a thickness of 1000 mm or less.

Images