KR20160130073A - Organic light emitting diode display and method for repairing organic light emitting diode display - Google Patents

Abstract

An embodiment of the present invention provides an organic light emitting diode (OLED) display and a method for repairing the same, capable of easily repairing at least one defective pixel. The OLED display includes a substrate; a plurality of OLEDs which are disposed on the substrate and are separated from each other; a plurality of pixel circuits which each include a plurality of thin film transistors respectively connected to the OLEDs; a plurality of data lines which individually extend in a first direction on the substrate, are separated from each other in a second direction crossing the first direction, and are respectively connected to the pixel circuits; a plurality of connection lines which are respectively adjacent to the data lines, extend in a direction parallel to the first direction, and are respectively connected to pixel circuits; and a wire which directly connects one portion of one of the data lines to one portion of one of the connection lines adjacent to the one data line.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting diode (OLED) display device and an OLED display device,

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an organic light emitting display and a repair method for the organic light emitting display. More particularly, the present invention relates to an organic light emitting display in which one or more defective pixels are repaired.

Typical examples of flat panel display devices include organic light emitting displays, liquid crystal displays, and plasma display panels.

The organic light emitting display includes a substrate and a plurality of pixel circuits including a plurality of thin film transistors formed on the substrate over the substrate, and a plurality of organic light emitting elements connected to each of the plurality of pixel circuits.

An embodiment of the present invention is to provide an OLED display device in which one or more defective pixels are easily repaired, and a repair method of an OLED display device that easily repairs one or more defective pixels.

According to an aspect of the present invention, there is provided an organic light emitting display comprising: a substrate; a plurality of organic light emitting elements positioned on the substrate, the organic light emitting elements being spaced apart from each other; A plurality of pixel circuits each including a plurality of pixel circuits connected to the plurality of pixel circuits, the plurality of pixel circuits being arranged to be spaced apart from each other in a second direction extending in a first direction on the substrate and intersecting the first direction, A plurality of connection lines extending in a direction parallel to the first direction adjacent to the data lines, each of the connection lines being connected to the plurality of pixel circuits, and a portion of one data line among the plurality of data lines And a wire directly connecting between a portion of one of the plurality of connection lines and one of the neighboring data lines A portion of each of the plurality of data lines corresponding to one portion of the one data line and a portion of each of the plurality of connection lines corresponding to a portion of the one connection line may be curved.

Wherein the wire comprises a first subwire directly connecting a first portion of the one data line and a fourth portion of the one connection line and a second subwire spaced apart from the first subwire, And a second sub-wire directly connecting the fifth portion of the one connection line.

One pixel circuit connected to the one data line among the plurality of pixel circuits is defective, and the one pixel circuit can be disconnected from the organic light emitting element.

A third portion between the first portion and the second portion of the one data line is isolated from the first portion and the second portion in a state of being connected to the one pixel circuit, The fourth portion of the line, the fifth portion, the sixth portion between the fourth portion and the fifth portion is cut and isolated from the other portion, and a first portion of the one data line is connected to the first sub- And the second portion of the one data line through the fourth portion, the sixth portion, the fifth portion, and the second sub-wire of the one connection line.

The plurality of connection lines may be located in the same layer as the plurality of data lines.

The wire may be located on one data line and one connection line.

The surface of the other portion of each of the plurality of data lines may include a corner.

The surface of the other portion of each of the plurality of connection lines may include an edge.

Wherein the plurality of thin film transistors comprise a first thin film transistor located on the substrate and including a first active pattern connected to the organic light emitting element and a first gate electrode located on the first active pattern, And a second gate electrode connected to one end of the first active pattern and connected to the data line and a second gate electrode positioned on the second active pattern, and a second thin film transistor connected to the other end of the first active pattern, And a third thin film transistor including a third active pattern connected to the first gate electrode through a bridge and a third gate electrode positioned on the third active pattern.

And may be located on the second active pattern and traverse the second active pattern and the third active pattern, respectively, and may be connected to the second gate electrode and the third gate electrode.

And a driving power line adjacent to the data line on the first scan line and crossing the first scan line and connected to the first active pattern.

The pixel circuit may include a capacitor electrode connected to the driving power supply line and located on the first gate electrode and overlapped with the first gate electrode to form a capacitor together with the first gate electrode.

Wherein the plurality of thin film transistors comprise a fourth active pattern connected to the third active pattern and connected to the first gate electrode through the node line and a fourth gate electrode positioned on the fourth active pattern, Further comprising a thin film transistor, a second scan line located on the fourth active pattern and crossing the fourth active pattern, the second scan line being connected to the fourth gate electrode, and an initialization power line connected to the fourth active pattern .

The initialization power supply line may extend in a direction parallel to the second direction and may be connected to the plurality of connection lines.

Wherein the plurality of thin film transistors include a fifth thin film transistor including a fifth active pattern connecting between the first active pattern and the driving power supply line and a fifth gate electrode positioned on the fifth active pattern, A sixth active pattern including a first active pattern, a sixth active pattern connecting between the organic light emitting elements, and a sixth gate electrode located on the sixth active pattern, wherein the fifth active pattern and the second active pattern, 6 active patterns and each of the fifth active pattern and the sixth active pattern, and the emission control lines connected to the fifth gate electrode and the sixth gate electrode, respectively.

Wherein the plurality of thin film transistors further comprise a seventh thin film transistor including a seventh active pattern connected to the fourth active pattern and a seventh gate electrode located on the seventh active pattern, And a third scan line connected to the seventh gate electrode across the seventh active pattern.

Further, another aspect of the present invention is a display device including a plurality of data lines having a curved surface and a surface of a part connected to a plurality of pixel circuits including a plurality of thin film transistors on a substrate, Forming a plurality of connection lines whose surface has a curved surface shape, connecting a portion of one data line connected to one pixel circuit among the plurality of pixel circuits among the plurality of data lines, And connecting a part of the line with a wire.

The forming of the plurality of data lines and the plurality of connection lines may be performed using a halftone mask.

The one-pixel circuit may be defective.

Wherein the step of forming the plurality of data lines and the plurality of connection lines comprises the step of forming the plurality of data lines so that the surface of each of the first portion of each of the plurality of data lines and the second portion spaced apart from the first portion has a curved surface shape, Forming a plurality of connection lines such that a surface of each of the fourth portion of the plurality of connection lines and the fourth portion of the fifth portion spaced apart from the fourth portion has a curved shape, Wherein the step of connecting using the wire comprises connecting directly between the first portion of the one data line and the fourth portion of the one connecting line using a first subwire, And directly connecting the second portion of the one connection line and the fifth portion of the one connection line using a second sub-wire.

Wherein the step of connecting using the wire comprises cutting a third portion between the first portion and the second portion of the one data line from the first portion and the second portion in connection with the one pixel circuit, and isolating the fourth portion, the fifth portion, the sixth portion between the fourth portion and the fifth portion of the one connection line from another portion, .

According to one embodiment of the present invention, there is provided an organic light emitting display device in which defective one or more pixels are easily repaired, and an organic light emitting display device Repair method is provided.

1 is a plan view schematically showing an organic light emitting display according to an embodiment of the present invention.
FIG. 2 is a circuit diagram illustrating one pixel of an organic light emitting diode display according to an exemplary embodiment of the present invention. Referring to FIG.
FIG. 3 is a layout diagram showing a first pixel, a second pixel, and a third pixel among a plurality of pixels of the organic light emitting diode display according to an embodiment of the present invention shown in FIG.
4 is a cross-sectional view taken along the line IV-IV in Fig.
5 is a cross-sectional view taken along line V-V in Fig.
6 is a flowchart illustrating a repair method of an OLED display according to another embodiment of the present invention.
7 and 8 are views showing a first pixel, a second pixel and a third pixel among a plurality of pixels of the organic light emitting display according to another embodiment of the present invention .

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention may be embodied in many different forms and is not limited to the embodiments described herein.

In order to clearly illustrate the present invention, parts not related to the description are omitted, and the same or similar components are denoted by the same reference numerals throughout the specification.

In addition, since the sizes and thicknesses of the respective components shown in the drawings are arbitrarily shown for convenience of explanation, the present invention is not necessarily limited to those shown in the drawings.

In the drawings, the thickness is enlarged to clearly represent the layers and regions. In the drawings, for the convenience of explanation, the thicknesses of some layers and regions are exaggerated. It will be understood that when a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the other portion "directly on" but also the other portion in between.

Also, throughout the specification, when an element is referred to as "including" an element, it is understood that the element may include other elements as well, without departing from the other elements unless specifically stated otherwise. Also, throughout the specification, the term "on " means to be located above or below a target portion, and does not necessarily mean that the target portion is located on the image side with respect to the gravitational direction.

Hereinafter, an OLED display according to an embodiment of the present invention will be described with reference to FIGS. 1 to 5. FIG.

1 is a plan view schematically showing an organic light emitting display according to an embodiment of the present invention. Hereinafter, a pixel may mean a minimum unit for displaying an image.

1, an OLED display according to an embodiment of the present invention includes a substrate SUB, a plurality of pixels PXn, a plurality of data lines DA, a plurality of connection lines CL And a data driver DD.

The substrate SUB includes a display area DIA for displaying an image and a non-display area NDA adjacent to the display area DIA. The non-display area NDA may be positioned to surround the rim of the display area DIA, but it is not limited thereto and may be located in various areas on the substrate SUB. The substrate SUB is an insulating substrate including glass, polymer, stainless steel, or the like. The substrate SUB can be flexible, stretchable, foldable, bendable, or rollable. The entire organic light emitting diode display can be flexible by making the substrate SUB flexible, stretchable, foldable, bendable, or rollable. Foldable, bendable, or rollable with respect to the first and second embodiments of the present invention.

The plurality of pixels PXn are located on the substrate SUB corresponding to the display area DIA of the substrate SUB. Each of the plurality of pixels PXn is connected to each of the plurality of data lines DA and each of the plurality of connection lines CL and supplies a driving current corresponding to the data signal supplied from each of the data lines DA And a pixel circuit including a plurality of thin film transistors and at least one capacitor for controlling a driving current flowing through the organic light emitting element. Each of the plurality of pixels PXn includes the organic light emitting element and the pixel circuit connected to the organic light emitting element.

1, each of the plurality of pixels PXn may be connected to each of a plurality of scan lines connected to a gate driver for supplying different scan signals, and may further include a driving power supply line And an initialization power line connected to the connection line CL. In addition, the second electrode, which is a cathode electrode of the organic light emitting element included in each of the plurality of pixels PXn, may be connected to a common power source. The detailed structure of each of the plurality of pixels PXn will be described later. The gate driving unit, the plurality of scan lines, the driving power supply line, and the initialization power supply line may be connected to each of the plurality of pixels PXn in a variety of known ways.

The data driver DD is located on the non-display area NDA of the substrate SUB and is connected to a plurality of data lines DA and a plurality of connection lines CL. Meanwhile, in another embodiment of the present invention, each of the plurality of data lines DA and the plurality of connection lines CL may be connected to another driving unit, not connected to the data driving unit DD.

Each of the plurality of data lines DA extends in one direction on the substrate SUB and is spaced apart from each other in the other direction intersecting with one direction and connected to the pixel circuits of each of the plurality of pixels PXn.

Each of the plurality of connection lines CL is adjacent to the data line DA and extends in a direction parallel to the one direction, and is connected to each pixel circuit of the plurality of pixels PXn.

Hereinafter, a circuit of one pixel PXn of the organic light emitting diode display according to one embodiment of the present invention will be described with reference to FIG.

FIG. 2 is a circuit diagram illustrating one pixel of an organic light emitting diode display according to an exemplary embodiment of the present invention. Referring to FIG.

2, one pixel PXn of the organic light emitting display according to an exemplary embodiment of the present invention includes a plurality of thin film transistors T1, T2, T3, T4, T5, T6, and T7 and a capacitor Cst (Sn, Sn-1, Sn-2, EM, and Sn) selectively connected to the plurality of thin film transistors (T1, T2, T3, T4, T5, T6, T7) Vin, CL, DA, ELVDD) and an organic light emitting diode (OLED).

The plurality of thin film transistors T1, T2, T3, T4, T5, T6 and T7 are connected to the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, A fifth thin film transistor T5, a sixth thin film transistor T6 and a seventh thin film transistor T7.

The first gate electrode G1 of the first thin film transistor T1 is connected to the third drain electrode D3 of the third thin film transistor T3 and the fourth drain electrode D4 of the fourth thin film transistor T4 The first source electrode S1 is connected to the second drain electrode D2 of the second thin film transistor T2 and the fifth drain electrode D5 of the fifth thin film transistor T5, The electrode D1 is connected to the third source electrode S3 of the third thin film transistor T3 and the sixth source electrode S6 of the sixth thin film transistor T6.

The second gate electrode G2 of the second thin film transistor T2 is connected to the first scan line Sn and the second source electrode S2 is connected to the data line DA, (D2) is connected to the first source electrode (S1) of the first thin film transistor (T1).

The third gate electrode G3 of the third thin film transistor T3 is connected to the first scan line Sn and the third source electrode S3 is connected to the first drain electrode D1 of the first thin film transistor T1 And the third drain electrode D3 is connected to the first gate electrode G1 of the first thin film transistor T1.

The fourth gate electrode G4 of the fourth thin film transistor T4 is connected to the second scan line Sn-1 and the fourth source electrode S4 is connected to the initialization power line Vin And the fourth drain electrode D4 is connected to the first gate electrode G1 of the first thin film transistor T1.

The fifth gate electrode G5 of the fifth thin film transistor T5 is connected to the emission control line EM and the fifth source electrode S5 is connected to the driving power supply line ELVDD, (D5) is connected to the first source electrode (S1) of the first thin film transistor (T1).

The sixth gate electrode G6 of the sixth thin film transistor T6 is connected to the emission control line EM and the sixth source electrode S6 is connected to the first drain electrode D1 of the first thin film transistor T1. Lt; / RTI >

The seventh gate electrode G7 of the seventh thin film transistor T7 is connected to the third scan line Sn-2, the seventh source electrode S7 is connected to the organic light emitting diode OLED, The seventh drain electrode D7 is connected to the fourth source electrode S4 of the fourth thin film transistor T4.

The plurality of scan lines are connected to the first gate electrode G2 and the third gate electrode G3 of the second thin film transistor T2 and the third thin film transistor T3, A second scan line Sn-1 for transferring the second scan signal to the fourth gate electrode G4 of the fourth thin film transistor T4, a seventh gate of the seventh thin film transistor T7, The fifth gate electrode G5 and the sixth gate electrode G6 of the third scan line Sn-2, the fifth TFT T5 and the sixth TFT T6 for transmitting the third scan signal to the electrode G7, And an emission control line EM for transmitting a light emission control signal to each of the electrodes G6.

The capacitor Cst includes one electrode connected to the driving power supply line ELVDD and the other electrode connected to the first gate electrode G1 and the third drain electrode D3 of the third thin film transistor T3.

The organic light emitting diode OLED includes a first electrode, a second electrode positioned on the first electrode, and an organic light emitting layer disposed between the first electrode and the second electrode. The first electrode of the organic light emitting diode OLED is connected to the seventh source electrode S7 of the seventh thin film transistor T7 and the sixth drain electrode D6 of the sixth thin film transistor T6, The electrodes are connected to a common power supply (ELVSS) through which a common signal is transmitted.

An example of the driving of one pixel PXn including the pixel circuit PC, the plurality of wirings (Sn, Sn-1, Sn-2, EM, Vin, CL, DA, ELVDD) and the organic light emitting element OLED When the third scan signal is transmitted to the third scan line Sn-2 and the seventh thin film transistor T7 is turned on, the remaining current flowing to the first electrode of the organic light emitting device OLED The current flows out to the fourth thin film transistor T4 through the seventh thin film transistor T7 so that the unintended emission of the organic light emitting element OLED due to the residual current flowing to the first electrode of the organic light emitting element OLED .

Next, when the second scan signal is transmitted to the second scan line Sn-1 and the initialization signal is transmitted to the initialization power supply line Vin through the connection line CL, the fourth thin film transistor T4 is turned on The initialization voltage by the initialization signal is supplied to the first gate electrode G1 of the first thin film transistor T1 and the other electrode of the capacitor Cst through the fourth thin film transistor T4, The capacitor G1 and the capacitor Cst are initialized. At this time, the first gate electrode G1 is initialized and the first thin film transistor T1 is turned on.

Next, when the first scan signal is transmitted to the first scan line Sn and the data signal is transmitted to the data line DA, the second thin film transistor T2 and the third thin film transistor T3 are turned on The data voltage Vd by the data signal is supplied to the first gate electrode G1 through the second thin film transistor T2, the first thin film transistor T1 and the third thin film transistor T3. At this time, the voltage supplied to the first gate electrode G1 is lower than the compensated voltage {Vth} which is reduced by the threshold voltage (Vth) of the first thin film transistor T1 from the data voltage Vd supplied from the first data line DA Vd + Vth, and Vth is a value of (-)}. The compensation voltage Vd + Vth supplied to the first gate electrode G1 is also supplied to the other electrode of the capacitor Cst connected to the first gate electrode G1.

The drive voltage Vd is supplied from the drive power supply line ELVDD to the one electrode of the capacitor Cst and the compensation voltage Vd + Vth is supplied to the other electrode of the capacitor Cst. The charge corresponding to the voltage difference applied to each electrode is stored and the first thin film transistor T1 is turned on for a predetermined time.

Next, when the emission control signal is applied to the emission control line EM, the fifth thin film transistor T5 and the sixth thin film transistor T6 are turned on and the driving voltage Vel are supplied to the first thin film transistor Tl through the fifth thin film transistor T5.

Then, the driving voltage (Vel) passes through the first thin film transistor (T1) turned on by the capacitor (Cst), and the voltage supplied to the first gate electrode (G1) by the capacitor (Cst) The driving current Id corresponding to the voltage difference between the first thin film transistor Tl and the second thin film transistor Tl flows through the first drain electrode D1 of the first thin film transistor T1, Is supplied to the light emitting device OLED and is emitted for a predetermined period of time in the organic light emitting device OLED.

The OLED display according to an embodiment of the present invention includes a pixel circuit PC including a first thin film transistor T1 through a seventh thin film transistor T7 and a capacitor Cst, The scan line Sn, the scan line Sn, the data line DA, the driving power supply line ELVDD, the initialization power supply line Vin, and the connection line CL. However, The organic light emitting diode display according to another embodiment may include a pixel circuit including a plurality of thin film transistors and one or more capacitors, and wirings including at least one scan line and at least one driving power supply line connected thereto.

Hereinafter, a plurality of pixels PXn adjacent to each other located in the display region DIA of the substrate SUB among the plurality of pixels PXn of the organic light emitting diode display according to the exemplary embodiment of the present invention described above with reference to FIG. PX1, the second pixel PX2, and the third pixel PX3 will be described.

FIG. 3 is a layout diagram showing a first pixel, a second pixel, and a third pixel among a plurality of pixels of the organic light emitting diode display according to an embodiment of the present invention shown in FIG.

3, the first pixel PX1, the second pixel PX2, and the third pixel PX3, which are located on the substrate SUB and are adjacent to each other, are connected to the first thin film transistor T1, The first thin film transistor T3, the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6, the seventh thin film transistor T7, The scan line Sn, the second scan line Sn-1, the third scan line Sn-2, the emission control line EM, the capacitor Cst, the data line DA, the driving power line ELVDD, A gate bridge GB, a connection line CL, an initial power supply line Vin, and an organic light emitting diode (OLED). Here, the first pixel PX1 further includes a wire WI differently from the second pixel PX2 and the third pixel PX3.

The first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3 which are the plurality of thin film transistors of the first pixel PX1, the second pixel PX2 and the third pixel PX3, The fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6, the seventh thin film transistor T7, the gate bridge GB and the capacitor Cst form a pixel circuit PC .

The first thin film transistor T1 is located on the substrate SUB and includes a first active layer A1 and a first gate electrode G1.

The first active layer A1 includes a first source electrode S1, a first channel C1, and a first drain electrode D1. The first source electrode S1 is connected to the second drain electrode D2 of the second thin film transistor T2 and the fifth drain electrode D5 of the fifth thin film transistor T5, D1 are connected to the third source electrode S3 of the third thin film transistor T3 and the sixth source electrode S6 of the sixth thin film transistor T6, respectively. The first channel (C1), which is a channel region of the first active layer (A1) overlapping the first gate electrode (G1), is bent and extended at least once. The first channel (C1) Since the length of the first channel C1 can be made longer by bending the gate electrode G1 more than once in the space overlapping the gate electrode G1, The driving range can be widely formed. Thus, by changing the magnitude of the gate voltage applied to the first gate electrode G1 within a wide driving range to finely control the gradation of light emitted from the organic light emitting diode OLED, The quality of the resulting image can be improved. The shape of the first active layer A1 may be variously modified. For example, the first active layer A1 may be modified into various shapes such as 'reverse S', 'S', 'M', and 'W'.

The first active layer A1 may be made of polysilicon or an oxide semiconductor. The oxide semiconductor may be at least one selected from the group consisting of Ti, Hf, Zr, Al, Ta, Ge, Zn, Ga, (Zn-In-O), zinc-tin oxide (Zn-Sn-Zn), indium- Zr-O) indium-gallium oxide (In-Ga-O), indium-tin oxide (In-Sn-O), indium-zirconium oxide Zr-Ga-O), indium-aluminum oxide (In-Al-O), indium-zirconium-tin oxide (In- In-Zn-Al-O, indium-tin-aluminum oxide, indium-aluminum-gallium oxide, indium-tantalum oxide (In-Ta-O), indium-tantalum-gallium oxide (In-Ta-Zn-O), indium-tantalum- -Ga-O), indium Germanium-gallium oxide (In-Ge-Zn-O), indium-germanium-tin oxide (In-Ge-Sn-O) In-Ge-Ga-O), titanium-indium-zinc oxide (Ti-In-Zn-O), and hafnium-indium-zinc oxide (Hf-In-Zn-O). In the case where the first active layer A1 is made of an oxide semiconductor, a separate protective layer may be added to protect the oxide semiconductor, which is vulnerable to the external environment such as high temperature.

The first channel C1 of the first active layer A1 may be channel doped with an N-type impurity or a P-type impurity and each of the first source electrode S1 and the first drain electrode D1 may be doped with a first channel C1 and the doping impurity of the opposite type doped to the first channel C1 may be doped.

The first gate electrode G1 is located on the first channel C1 of the first active layer A1 and has an island shape. The first gate electrode G1 is connected to the fourth drain electrode D4 of the fourth thin film transistor T4 and the third drain electrode D4 of the third thin film transistor T3 by a gate bridge GB passing through a contact hole CNT. And is connected to the third drain electrode D3. The first gate electrode G1 overlaps with the capacitor electrode CE and can function as a gate electrode of the first thin film transistor T1 and also function as another electrode of the capacitor Cst. That is, the first gate electrode G1 forms a capacitor Cst together with the capacitor electrode CE.

The second thin film transistor T2 is located on the substrate SUB and includes a second active layer A2 and a second gate electrode G2. The second active layer A2 includes a second source electrode S2, a second channel C2, and a second drain electrode D2. The second source electrode S2 is connected to the data line DA through the contact hole and the second drain electrode D2 is connected to the first source electrode S1 of the first thin film transistor T1. The second channel C2 which is the channel region of the second active layer A2 overlapping the second gate electrode G2 is located between the second source electrode S2 and the second drain electrode D2. That is, the second active layer A2 is connected to the first active layer A1.

The second channel C2 of the second active layer A2 may be channel doped with an N-type impurity or a P-type impurity and each of the second source electrode S2 and the second drain electrode D2 may be doped with a first channel C1 and the doping impurity of the opposite type doped to the first channel C1 may be doped. The second active layer A2 is located on the same layer as the first active layer A1 and is formed of the same material as the first active layer A1 and is formed integrally with the first active layer A1.

The second gate electrode G2 is located on the second channel C2 of the second active layer A2 and is formed integrally with the first scan line Sn.

The third thin film transistor T3 is located on the substrate SUB and includes a third active layer A3 and a third gate electrode G3.

The third active layer A3 includes a third source electrode S3, a third channel C3, and a third drain electrode D3. The third source electrode S3 is connected to the first drain electrode D1 and the third drain electrode D3 is connected to the first gate electrode G1 of the first thin film transistor T1 by the gate bridge GB passing through the contact hole. And is connected to the electrode G1. The third channel C3 which is the channel region of the third active layer A3 overlapping the third gate electrode G3 is located between the third source electrode S3 and the third drain electrode D3. That is, the third active layer A3 connects between the first active layer A1 and the first gate electrode G1.

The third channel C3 of the third active layer A3 may be channel-doped with an N-type impurity or a P-type impurity, and each of the third source electrode S3 and the third drain electrode D3 may be channel- C3, and doped with a doping impurity of the opposite type as the doping impurity doped to the third channel C3. The third active layer A3 is located in the same layer as the first active layer A1 and the second active layer A2 and is formed of the same material as the first active layer A1 and the second active layer A2 And is formed integrally with the first active layer A1 and the second active layer A2.

The third gate electrode G3 is located on the third channel C3 of the third active layer A3 and is formed integrally with the first scan line Sn. The third gate electrode G3 is formed as a dual gate electrode.

The fourth thin film transistor T4 is located on the substrate SUB and includes a fourth active layer A4 and a fourth gate electrode G4.

The fourth active layer A4 includes a fourth source electrode S4, a fourth channel C4, and a fourth drain electrode D4. The fourth source electrode S4 is connected to the initial power supply line Vin connected to the connection line CL through the contact hole and the fourth drain electrode D4 is connected to the gate electrode And is connected to the first gate electrode G1 of the first thin film transistor T1. The fourth channel C4 which is the channel region of the fourth active layer A4 overlapping the fourth gate electrode G4 is located between the fourth source electrode S4 and the fourth drain electrode D4. That is, the fourth active layer A4 connects the initial power supply line Vin and the first gate electrode G1, and is connected to the third active layer A3 and the first gate electrode G1, respectively .

The fourth channel C4 of the fourth active layer A4 may be channel-doped with an N-type impurity or a P-type impurity and each of the fourth source electrode S4 and the fourth drain electrode D4 may be channel- C4 may be interposed between the fourth channel C4 and the doping impurity of the opposite type doped to the fourth channel C4. The fourth active layer A4 is located in the same layer as the first active layer A1, the second active layer A2 and the third active layer A3 and the first active layer A1, The second active layer A2 and the third active layer A3 and is formed integrally with the first active layer A1, the second active layer A2 and the third active layer A3.

The fourth gate electrode G4 is located on the fourth channel C4 of the fourth active layer A4 and is formed integrally with the second scan line Sn-1. The fourth gate electrode G4 is formed as a dual gate electrode.

The fifth thin film transistor T5 is located on the substrate SUB and includes a fifth active layer A5 and a fifth gate electrode G5.

The fifth active layer A5 includes a fifth source electrode S5, a fifth channel C5, and a fifth drain electrode D5. The fifth source electrode S5 is connected to the driving power source line ELVDD through the contact hole and the fifth drain electrode D5 is connected to the first source electrode S1 of the first thin film transistor T1 . The fifth channel C5 which is the channel region of the fifth active layer A5 overlapping the fifth gate electrode G5 is located between the fifth source electrode S5 and the fifth drain electrode D5. That is, the fifth active layer A5 connects between the driving power supply line ELVDD and the first active layer A1.

The fifth channel C5 of the fifth active layer A5 may be channel-doped with an N-type impurity or a P-type impurity, and each of the fifth source electrode S5 and the fifth drain electrode D5 may be channel- The doping impurity of the opposite type to the doping impurity doped to the fifth channel C5 may be doped. The fifth active layer A5 is located in the same layer as the first active layer A1, the second active layer A2, the third active layer A3 and the fourth active layer A4, The first active layer A1, the second active layer A2, the third active layer A3, and the fourth active layer A4 are formed of the same material as the first active layer A1, the second active layer A2, The third active layer A3, and the fourth active layer A4.

The fifth gate electrode G5 is located on the fifth channel C5 of the fifth active layer A5 and is formed integrally with the emission control line EM.

The sixth thin film transistor T6 is located on the substrate SUB and includes a sixth active layer A6 and a sixth gate electrode G6.

The sixth active layer A6 includes a sixth source electrode S6, a sixth channel C6, and a sixth drain electrode D6. The sixth source electrode S6 is connected to the first drain electrode D1 of the first thin film transistor T1 and the sixth drain electrode D6 is connected to the first electrode of the organic light emitting diode OLED through the contact hole. (E1). The sixth channel C6 which is the channel region of the sixth active layer A6 overlapping the sixth gate electrode G6 is located between the sixth source electrode S6 and the sixth drain electrode D6. That is, the sixth active layer A6 connects between the first active layer A1 and the first electrode E1 of the organic light emitting device OLED.

The sixth channel C6 of the sixth active layer A6 may be channel doped with an N-type impurity or a P-type impurity and each of the sixth source electrode S6 and the sixth drain electrode D6 may be channel- C6 and the doping impurities of the opposite type doped to the sixth channel C6 may be doped. The sixth active layer A6 is formed on the same layer as the first active layer A1, the second active layer A2, the third active layer A3, the fourth active layer A4 and the fifth active layer A5, And is formed of the same material as the first active layer A1, the second active layer A2, the third active layer A3, the fourth active layer A4 and the fifth active layer A5, Is integrally formed with the first active layer A1, the second active layer A2, the third active layer A3, the fourth active layer A4, and the fifth active layer A5.

The sixth gate electrode G6 is located on the sixth channel C6 of the sixth active layer A6 and is formed integrally with the emission control line EM.

The seventh thin film transistor T7 is located on the substrate SUB and includes a seventh active layer A7 and a seventh gate electrode G7.

The seventh active layer A7 includes a seventh source electrode S7, a seventh channel C7, and a seventh drain electrode D7. The seventh source electrode S7 is connected to the first electrode of the organic light emitting element of another pixel (which may be a pixel located on the upper side of the pixel shown in Fig. 3) not shown in Fig. 3, And the electrode D7 is connected to the fourth source electrode S4 of the fourth thin film transistor T4. The seventh channel C7, which is the channel region of the seventh active layer A7 overlapping the seventh gate electrode G7, is located between the seventh source electrode S7 and the seventh drain electrode D7. That is, the seventh active layer A7 connects between the first electrode of the organic light emitting device and the fourth active layer A4.

The seventh channel C7 of the seventh active layer A7 may be channel-doped with an N-type impurity or a P-type impurity, and each of the seventh source electrode S7 and the seventh drain electrode D7 may be channel- C7) to be doped with a doping impurity of the opposite type to the doping impurity doped to the seventh channel (C7). The seventh active layer A7 includes a first active layer A1, a second active layer A2, a third active layer A3, a fourth active layer A4, a fifth active layer A5, The first active layer A1, the second active layer A2, the third active layer A3, the fourth active layer A4 and the fifth active layer A5, which are located in the same layer as the active layer A6, ), The sixth active layer A6, and the first active layer A1, the second active layer A2, the third active layer A3, the fourth active layer A4, the fifth active layer A4, The active layer A5, and the sixth active layer A6.

The seventh gate electrode G7 is located on the seventh channel C7 of the seventh active layer A7 and is formed integrally with the third scan line Sn-2.

The first scan line Sn is located on the second active layer A2 and the third active layer A3 and extends in the direction transverse to the second active layer A2 and the third active layer A3 The second gate electrode G2 and the third gate electrode G3 and is connected to the second gate electrode G2 and the third gate electrode G3.

The second scan line Sn-1 is spaced apart from the first scan line Sn and is located on the fourth active layer A4 and extends in the direction transverse to the fourth active layer A4, And is formed integrally with the gate electrode G4 and connected to the fourth gate electrode G4.

The third scan line Sn-2 is located on the seventh active layer A7 away from the second scan line Sn-1 and extends in the direction crossing the seventh active layer A7, And is formed integrally with the seventh gate electrode G7 and connected to the seventh gate electrode G7.

The emission control line EM is located on the fifth active layer A5 and the sixth active layer A6 away from the first scan line Sn and the fifth active layer A5 and the sixth active layer A6 and is formed integrally with the fifth gate electrode G5 and the sixth gate electrode G6 and is connected to the fifth gate electrode G5 and the sixth gate electrode G6 .

The first scan line Sn, the first scan line Sn, the second scan line Sn-1, the first scan line Sn, the second scan line Sn, The third gate electrode G3, the fourth gate electrode G4, the fifth gate electrode G5, the sixth gate electrode G6 and the seventh gate electrode G7 are located on the same layer, And is formed of the same material. In another embodiment of the present invention, the emission control line EM, the third scan line Sn-2, the second scan line Sn-1, the first scan line Sn, the first gate electrode A fifth gate electrode G5, a sixth gate electrode G6, a seventh gate electrode G7, a fifth gate electrode G6, a third gate electrode G1, a second gate electrode G2, a third gate electrode G3, a fourth gate electrode G4, Each of which may be selectively formed on different layers and formed of different materials.

The capacitor Cst includes one electrode and another electrode facing each other with an insulating layer therebetween. The one electrode may be the capacitor electrode CE and the other electrode may be the first gate electrode G1. The capacitor electrode CE is located on the first gate electrode G1 and is connected to the driving power supply line ELVDD through the contact hole.

The capacitor electrode CE forms a capacitor Cst together with the first gate electrode G1 and the first gate electrode G1 and the capacitor electrode CE are formed of the same or different metals in different layers .

The capacitor electrode CE includes an opening OA through which a part of the first gate electrode G1 is exposed and the gate bridge GB is connected to the first gate electrode G1 through the opening OA have.

The data line DA is located on the first scan line Sn and extends in one direction across the first scan line Sn and each of the plurality of data lines DA is connected to the first scan line Sn, Direction. The data line DA is connected to the second source electrode S2 of the second active layer A2 through the contact hole. The data line DA is connected to the first scan line Sn, the second scan line Sn-1, the third scan line Sn-2, the emission control line EM, Extended.

The driving power supply line ELVDD is spaced apart from the data line DA and is located on the first scan line Sn and extends in one direction across the first scan line Sn, CE and the fifth source electrode S5 of the fifth active layer A5 connected to the first active layer A1. The driving power supply line ELVDD is connected to the first scan line Sn, the second scan line Sn-1, the third scan line Sn-2, the emission control line EM, It is prolonged.

The gate bridge GB is spaced apart from the driving power supply line ELVDD and electrically connected to the third drain electrode D3 of the third active layer A3 and the fourth drain electrode D3 of the fourth active layer A4 through the contact hole D4 are connected to the first gate electrode G1 exposed by the opening OA of the capacitor electrode CE through the contact hole. That is, the gate bridge GB includes a first thin film transistor T 1, which is one of the first thin film transistor T 1 to the seventh thin film transistor T 7, which is a plurality of thin film transistors, and a third thin film transistor T 3, And the fourth thin film transistor T4, which is one of the other thin film transistors.

The connection line CL is disposed between neighboring data lines DA and extends in a direction parallel to one direction which is the extending direction of the data line DA. The connection line CL is connected to the initialization power supply line Vin and is connected to each of the first pixel PX1, the second pixel PX2 and the third pixel PX3 via the initialization power supply line Vin . The connection line CL extends in a direction parallel to the one direction and the initialization power supply line Vin extends in a direction crossing the connection line CL so that the connection line CL and the initialization power supply line And has a matrix form in a plan view over the entire SUB.

The connection line CL is located on the same layer as the gate bridge GB, the data line DA and the driving power supply line ELVDD described above, and is formed of the same material. Meanwhile, in another embodiment of the present invention, each of the connection line CL, the data line DA, the driving power supply line ELVDD and the gate bridge GB is selectively formed on different layers and formed of different materials .

The initialization power supply line Vin extends in the direction intersecting the extension direction of the connection line CL and extends in the direction parallel to the aforementioned other direction which is the arrangement direction of each of the plurality of data lines DA. The initialization power line Vin is connected to the connection line CL through the contact hole and is connected to the fourth source electrode S4 of the fourth active layer A4 through the contact hole. The initialization power supply line Vin is formed on the same layer as the capacitor electrode CE and made of the same material. On the other hand, in another embodiment of the present invention, the initialization power supply line (Vin) may be formed of a different material by being located on a different layer from the capacitor electrode CE.

The organic light emitting diode OLED includes a first electrode E1, an organic light emitting layer, and a second electrode. The first electrode E1 is connected to the sixth drain electrode D6 of the sixth thin film transistor T6 through a contact hole. The first electrode E1, the organic light emitting layer, and the second electrode may be sequentially stacked. At least one of the first electrode E1 and the second electrode may be a light-transmissive electrode, a light reflective electrode, And light emitted from the organic light emitting layer may be emitted in at least one direction of the first electrode E1 and the second electrode.

A capping layer covering the organic light emitting diode OLED may be disposed on the organic light emitting diode OLED and a thin film encapsulation layer may be formed on the organic light emitting diode OLED through the capping layer. Or the encapsulation substrate may be located.

3 to 5, the first pixel PX1, the second pixel PX2, the second pixel PX2 of the third pixel PX3, and the wire WI relative to the third pixel PX3, The first pixel PX1, which further includes the pixel PX1, will be described in detail.

4 is a cross-sectional view taken along the line IV-IV in Fig. 5 is a cross-sectional view taken along line V-V in Fig. Each of Figs. 4 and 5 shows a cross section of a data line, a connection line and a wire for convenience of explanation.

As shown in FIGS. 3 to 5, the first pixel PX1 is a pixel repaired by a repair method of an organic light emitting display device to be described later, and includes a data line DA included in the first pixel PX1, The line CL has a structure different from that of the second pixel PX2 and the third pixel PX3 and is cut off in the middle, but the first pixel PX1, the second pixel PX2, The surface shapes of the data line DA and the connection line CL included in each of the data lines PX3 and PX3 have the same shape.

The pixel circuit PC of the first pixel PX1 may be defective differently from the pixel circuits PC of the second pixel PX2 and the third pixel PX3 and the pixel circuit PC of the first pixel PX1 PC) is cut (CUT) from the organic light emitting device OLED.

The first pixel PX1 further includes a wire WI directly connecting between a part of the data line DA and a part of the connection line CL and a data line DA connected to the wire WI The surface of at least one of the part of the part and the connecting line CL has a curved shape.

A portion of each of the plurality of data lines DA connected to the second pixel PX2 and the third pixel PX3 corresponding to a portion of one data line DA connected to the first pixel PX1, The surface of the substrate has a curved surface.

The surface of one portion of each of the plurality of connection lines CL corresponding to one portion of one connection line CL connected to the first pixel PX1 also has a curved surface shape.

Specifically, the data line DA of the first pixel PX1 includes a first portion PA1, a second portion PA2, and a third portion PA3, and the connection line CL includes a fourth portion PA4, a fifth portion PA5, and a sixth portion PA6. The wire WI includes a first sub-wire W1 and a second sub-wire W2.

The first part PA1 of the data line DA is connected to the fourth part PA4 of the connection line CL through the first subwire W1, And directly connects the first part PA1 of the data line DA located in the first connection part CL and the fourth part PA4 of the connection line CL. The first sub wire W1 is located on the data line DA and the connection line CL and is in direct contact with each of the data line DA and the connection line CL.

The second portion PA2 of the data line DA is connected to the fifth portion PA5 of the connection line CL through the second subwire W2 and the second subwirings W2 are connected to the same layer And directly connects the second portion PA2 of the data line DA located at the first portion PA4 and the fifth portion PA5 of the connection line CL. The second sub-wire W2 is located on the data line DA and the connection line CL and is in direct contact with each of the data line DA and the connection line CL.

A connection line CL connected by the first sub-wire PA1 and the second sub-wire PA2 of the data line DA connected by the first sub-wire W1 and the second sub- Each of the fourth portion PA4 and the fifth portion PA5 has a curved surface and similarly the first portion PA1 and the second portion PA2 of each of the plurality of data lines DA And the surface of each of the fourth portion PA4 and the fifth portion PA5 of each of the plurality of connection lines CL also has a curved surface shape.

As described above, the surface of each of the first portion PA1 of the data line DA and the fourth portion PA4 of the connection line CL directly connected to the first sub wire W1 has a curved surface shape, The surface of each of the second part PA2 of the data line DA and the fifth part PA5 of the connection line CL directly contacting the wire W1 and directly connected to the second sub wire W2 By having a curved surface shape, each of the first sub-wire W1 and the second sub-wire W2 easily connects between the data line DA and the connection line CL. Concretely, when the surface of each of the connection line CL and the data line DA to which the wire WI is directly connected has a corner, the wire WI is inadvertently cut (CUT) by this edge, The connection between the data line DA and the connection line CL may not be performed by the wire WI. In an embodiment of the present invention, however, Since the surfaces of each of the first portion PA1 and the second portion PA2 and the fourth portion PA4 and the fifth portion PA5 of the connection line CL have a curved surface shape, The data line DA and the connection line CL are easily connected.

The surface of the other part of the data line DA other than the first part PA1 and the second part PA2 of the data line DA is different from the first part PA1 and the second part PA2, And the surface of the other part of the connection line CL other than the fourth part PA4 and the fifth part PA5 of the connection line CL is different from the fourth part PA4 and the fifth part PA5, .

The third part PA3 located between the first part PA1 and the second part PA2 of the data line DA is connected to the first part PA1 and the second part PA2, PA2 and PA4 of the connecting line CL and the fourth part PA4 of the connecting line CL and the fifth part PA5 of the connecting line CL and the sixth part PA4 between the fourth part PA4 and the fifth part PA5, (PA6) is cut off (CUT) from other parts and isolated.

The first portion PA1 of the data line DA of the first pixel PX1 is connected to the first sub-wire W1, the fourth portion PA4 of the connection line CL, the sixth portion PA6, The fifth portion PA5, and the second sub-wire W2 to the second portion PA2 of the data line DA. The data signal through the data line DA connected to the first pixel PX1 is connected to the first part PA1 of the data line DA, the first sub wire W1, the fourth part of the connection line CL, The pixel circuit of the first pixel PX1 through the second portion PA2 of the first pixel PX1 via the first portion PA4, the sixth portion PA6, the fifth portion PA5, the second subwire W2 and the second portion PA2 of the data line DA PC and is supplied to other pixels below the first pixel PX1.

That is, the pixel circuit PC of the defective first pixel PX1 is not connected to the data line DA, and the data signal through the data line DA is connected to the wire WI and the connection line CL. To the pixels other than the first pixel PX1. As a result, when the plurality of pixels emit light, the first pixel PX1 does not emit light, so that the first pixel PX1 is inhibited from being viewed.

That is, the first pixel PX1 in which a defect is generated is repaired, whereby the display of the defective first pixel PX1 is suppressed.

In the conventional organic light emitting diode display, the surface of the data line directly contacting with the wire includes the edge, so that the wire is inadvertently cut by the edge, so that the connection between the data line and the connection line by the wire is not performed.

Alternatively, in an embodiment of the present invention, the surface of the data line to which the wire is directly connected has a curved shape, so that the data line and the connection line are easily connected by the wire.

As described above, the organic light emitting diode display according to an embodiment of the present invention has a curved surface shape in which at least one surface of a part of a data line DA and a part of a connection line CL in contact with a wire WI , And the data line DA and the connection line CL are easily connected by the wire WI. That is, an organic light emitting display in which repair is easily performed is provided.

In addition, in the organic light emitting diode display according to the embodiment of the present invention, only the surface of one part of one data line DA connected by the wire WI and the surface of one part of one connection line CL are curved Not only a part of one data line DA but also a part of each of a plurality of data lines DA corresponding to a part of one connection line CL, The data line DA and the connection line CL are connected to each other before the connection between the data line DA and the connection line CL is made by using the wire WI, ) It is not necessary to process each surface with a curved surface. That is, an organic light emitting display in which repair is easily performed is provided.

Hereinafter, a repair method of an OLED display according to another embodiment of the present invention will be described with reference to FIGS. 6 to 8. FIG. An organic light emitting display according to an embodiment of the present invention may be provided using the repair method of the OLED display according to another embodiment of the present invention.

6 is a flowchart illustrating a repair method of an OLED display according to another embodiment of the present invention. 7 and 8 are views showing a first pixel, a second pixel and a third pixel among a plurality of pixels of the organic light emitting display according to another embodiment of the present invention .

First, as shown in FIGS. 6 and 7, a surface of a portion forms a plurality of data lines having a curved surface shape and a plurality of connection lines having a surface shape of a surface portion (S100).

Specifically, when forming the plurality of data lines DA and the plurality of connection lines CL while manufacturing the organic light emitting display device, the first portion PA1 and the second portion PA2 of each of the plurality of data lines DA, The surface of each of the fourth portion PA4 and the fifth portion PA5 of each of the surfaces of the second portion PA2 and the plurality of connection lines CL is formed to have a curved shape.

For example, when a plurality of data lines DA and a plurality of connection lines CL are formed by using a photolithography process, a first portion PA1 of each of the plurality of data lines DA by using a halftone mask ) And the second portion PA2 are formed so as to have a curved surface shape and the fourth portion PA4 and the fifth portion PA5 of each of the plurality of connection lines CL are formed by using a halftone mask The surface is formed to have a curved shape.

Next, as shown in FIG. 8, one part of one data line and one part of one connection line are connected using a wire (S200).

Specifically, the plurality of thin film transistors T1, T2, T3, T4, and T6 of the first pixel PX1, the second pixel PX2, and the third pixel PX3, which are a plurality of pixels included in the organic light emitting display, The first pixel PX1, the second pixel PX2 and the third pixel PX3 of the first pixel PX1, T5, T6, T7, If it is confirmed that the pixel PX1 is a defective pixel in which a defect has occurred, a part of one data line DA connected to the pixel circuit PC of the first pixel PX1 as one pixel circuit and a part of one connection line CL Connect the wires between the parts (WI).

Concretely, the first part PA1 of the data line DA and the fourth part PA4 of the connection line CL are directly connected by using the first sub-wire W1 using the deposition process, and the data line DA between the second portion PA2 of the connection line CL and the fifth portion PA5 of the connection line CL using the second sub-wire W2.

The third part PA3 between the first part PA1 and the second part PA2 of the data line DA of the first pixel PX1 is connected to the first part PX1 in the state of being connected to the one pixel circuit PC, (CUT) from the first part PA1 and the second part PA2 and isolates the fourth part PA4, the fifth part PA5, the fourth part PA4 and the fifth part PA4 of the connection line CL PA5 is cut off (CUT) from the other part to isolate the sixth part PA6 between the first part PA1 and the second part PA5.

According to another aspect of the present invention, there is provided an OLED display according to an embodiment of the present invention using the repair method of the OLED display.

Meanwhile, in another embodiment of the present invention, the data line DA is connected to the connection line CL by the wire WI, but in another embodiment of the present invention, the data line DA is connected by the wire WI The driving power supply line ELVDD or another line located on the same layer as the data line DA. In this case, the surface of one portion of the driving power supply line ELVDD corresponding to the first portion PA1 and the second portion PA2 of the data line DA may have a curved surface shape, The surface of one portion of the other line corresponding to the first portion PA1 and the second portion PA2 of the first portion PA2 may have a curved shape.

As described above, according to another embodiment of the present invention, a repair method of an organic light emitting display device is such that at least one surface of a part of the data line DA and a part of the connection line CL is already formed in a curved shape, The data line DA and the connection line CL are connected by a wire WI by connecting one part of the connection line CL with a part of the data line DA having a curved surface using the wire WI, Are easily connected. That is, a repair method of an organic light emitting display device in which repair by a wire WI is easily performed is provided.

While the present invention has been described in terms of several embodiments, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the following claims. Those who are engaged in the technology field will understand easily.

The organic light emitting device OLED, the pixel circuit PC, the data line DA, the connection line CL, the wire WI,

Claims (20)

Board;
A plurality of organic light emitting elements positioned on the substrate and spaced apart from each other;
A plurality of pixel circuits each including a plurality of thin film transistors connected to each of the plurality of organic light emitting elements;
A plurality of data lines connected to the plurality of pixel circuits, the plurality of data lines being spaced apart from each other in a second direction extending in a first direction on the substrate and intersecting the first direction;
A plurality of connection lines each extending in a direction parallel to the first direction adjacent to the data lines, the plurality of connection lines being connected to the plurality of pixel circuits; And
A wire connecting a part of a data line of the plurality of data lines and a part of a neighboring one of the plurality of connection lines to a neighboring one of the plurality of connection lines,
/ RTI >
Wherein a part of each of the plurality of data lines corresponding to a part of one data line and a part of each part of each of the plurality of connection lines corresponding to a part of the one connection line are curved, . The method of claim 1,
The wire
A first sub wire directly connecting between a first portion of one data line and a fourth portion of the one connection line; And
And a second sub-wire spaced apart from the first sub-wire and directly connecting a second portion of the one data line and a fifth portion of the one connection line,
And an organic light emitting diode (OLED). 3. The method of claim 2,
One pixel circuit connected to the one data line among the plurality of pixel circuits is defective,
Wherein the one pixel circuit is cut from the organic light emitting element. 4. The method of claim 3,
A third portion between the first portion and the second portion of the one data line is isolated from the first portion and the second portion in connection with the one pixel circuit,
The fourth portion, the fifth portion, the sixth portion between the fourth portion and the fifth portion of the one connection line are cut and isolated from other portions,
Wherein the first portion of one data line is connected to the second portion of the one data line through the first subwire, the fourth portion of the one connection line, the sixth portion, the fifth portion, And an organic light emitting diode (OLED). The method of claim 1,
Wherein the plurality of connection lines are located on the same layer as the plurality of data lines. The method of claim 1,
Wherein the wire is positioned on one data line and one connection line. The method of claim 1,
Wherein a surface of another portion of each of the plurality of data lines includes a corner. The method of claim 1,
Wherein a surface of the other portion of each of the plurality of connection lines includes an edge. The method of claim 1,
Wherein the plurality of thin film transistors comprise:
A first thin film transistor located on the substrate and including a first active pattern connected to the organic light emitting device and a first gate electrode positioned on the first active pattern;
A second thin film transistor including a second active pattern connected to one end of the first active pattern and connected to the data line and a second gate electrode positioned on the second active pattern; And
A third active pattern connected to the other end of the first active pattern and connected to the first gate electrode through a gate bridge, and a third gate electrode positioned on the third active pattern,
And an organic light emitting diode (OLED). The method of claim 9,
A first scan line located on the second active pattern and traversing each of the second active pattern and the third active pattern, the first scan line being connected to the second gate electrode and the third gate electrode; And
And a driving power supply line connected to the first active pattern, which is adjacent to the data line on the first scan line and crosses the first scan line,
Further comprising an organic light emitting diode (OLED). 11. The method of claim 10,
The pixel circuit includes:
And a capacitor electrode connected to the driving power line and positioned on the first gate electrode, the capacitor electrode overlapping the first gate electrode to form a capacitor together with the first gate electrode. 12. The method of claim 11,
Wherein the plurality of thin film transistors comprise a fourth active pattern connected to the third active pattern and connected to the first gate electrode through the node line and a fourth gate electrode located on the fourth active pattern, Further comprising a thin film transistor,
A second scan line located on the fourth active pattern and traversing the fourth active pattern, the second scan line being connected to the fourth gate electrode; And
An initialization power line connected to the fourth active pattern,
Further comprising an organic light emitting diode (OLED). The method of claim 12,
Wherein the initialization power supply line extends in a direction parallel to the second direction and is connected to the plurality of connection lines. The method of claim 13,
Wherein the plurality of thin film transistors comprise:
A fifth active layer including a fifth active pattern connecting between the first active pattern and the driving power supply line, and a fifth gate electrode located on the fifth active pattern; And
A sixth active pattern connecting the first active pattern and the organic light emitting element, and a sixth gate electrode located on the sixth active pattern,
Further comprising:
A fifth active pattern, and a sixth active pattern, and each of the fifth active pattern and the sixth active pattern is disposed on each of the fifth gate electrode and the sixth gate electrode,
Further comprising an organic light emitting diode (OLED). The method of claim 14,
Wherein the plurality of thin film transistors further comprise a seventh thin film transistor including a seventh active pattern connected to the fourth active pattern and a seventh gate electrode positioned on the seventh active pattern,
And a third scan line located on the seventh active pattern and crossing the seventh active pattern, the third scan line being connected to the seventh gate electrode. A plurality of data lines having a surface shape of a part connected to a plurality of pixel circuits including a plurality of thin film transistors on a substrate and a plurality of data lines having a surface shape of a part connected to the plurality of pixel circuits, Forming connection lines;
Connecting one portion of one data line connected to one pixel circuit among the plurality of pixel circuits among the plurality of data lines and one portion of one connection line among the plurality of connection lines by wire
And an organic light emitting diode (OLED). 17. The method of claim 16,
Wherein the forming of the plurality of data lines and the plurality of connection lines is performed using a halftone mask. 17. The method of claim 16,
Wherein the one-pixel circuit is defective. 17. The method of claim 16,
Wherein forming the plurality of data lines and the plurality of connection lines comprises:
Forming the plurality of data lines such that a first portion of each of the plurality of data lines and a surface of each of the second portions spaced apart from the first portion have a curved shape; And
Forming the plurality of connection lines such that a surface of each of the fourth portion of each of the plurality of connection lines and the fifth portion of the fourth portion and the spaced apart portion has a curved surface shape
/ RTI >
The connecting using the wire may include:
Connecting directly between the first portion of the one data line and the fourth portion of the one connection line using a first sub-wire; And
Directly connecting the second portion of one data line and the fifth portion of the one connection line using a second sub-wire
And an organic light emitting diode (OLED). 20. The method of claim 19,
The connecting using the wire may include:
Isolating a third portion between the first portion and the second portion of the one data line from the first portion and the second portion in connection with the one pixel circuit; And
Cutting and isolating the fourth portion, the fifth portion, the sixth portion between the fourth portion and the fifth portion of the one connection line from the other portion
And an organic light emitting diode (OLED).

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