KR102372773B1 - Organic light emitting diode display and method for repairing organic light emitting diode display - Google Patents

Abstract

An organic light emitting display device includes a plurality of pixel circuits including a substrate, a plurality of organic light emitting devices positioned on the substrate and spaced apart from each other, and a plurality of thin film transistors each connected to the plurality of organic light emitting devices , , each extending in one direction on the substrate and disposed to be spaced apart from each other in the other direction intersecting the one direction, a plurality of data lines connected to the plurality of pixel circuits, each of which is adjacent to the data line a plurality of connection lines extending in a direction parallel to the direction and connected to the plurality of pixel circuits, and a portion of one data line among the plurality of data lines and a neighboring portion of the one data line among the plurality of connection lines It includes a wire for directly connecting a portion of the connecting line.

Description

An organic light emitting display device and a repair method of an organic light emitting display device {ORGANIC LIGHT EMITTING DIODE DISPLAY AND METHOD FOR REPAIRING ORGANIC LIGHT EMITTING DIODE DISPLAY}

The present invention relates to an organic light emitting diode display and a method for repairing an organic light emitting display, and more particularly, to an organic light emitting diode display in which one or more defective pixels are repaired, and to a repairing method of the organic light emitting display apparatus.

In general, representative examples of the flat panel display include an organic light emitting display, a liquid crystal display, and a plasma display panel.

Among them, the organic light emitting diode display includes a substrate, a plurality of pixel circuits including a plurality of thin film transistors formed on the substrate over the entire substrate, and a plurality of organic light emitting devices connected to each of the plurality of pixel circuits.

An embodiment of the present invention is to provide an organic light emitting display device in which one or more defective pixels are easily repaired, and a repair method of an organic light emitting display device in which one or more defective pixels are easily repaired.

One aspect of the present invention for achieving the above-described technical problem is a substrate, a plurality of thin film positioned on the substrate, each of a plurality of organic light emitting devices spaced apart from each other, each connected to each of the plurality of organic light emitting devices a plurality of pixel circuits including transistors, each of which extends in one direction on the substrate and is disposed to be spaced apart from each other in another direction crossing the one direction, a plurality of data lines connected to the plurality of pixel circuits, each a plurality of connection lines adjacent to the data line and extending in a direction parallel to the one direction, a plurality of connection lines connected to the plurality of pixel circuits, and a portion of one data line among the plurality of data lines and the plurality of connections and a wire directly connecting a portion of the one data line and a neighboring connection line among the lines, wherein the surface of at least one of the portion of the one data line and the portion of the one connection line in contact with the wire is An organic light emitting diode display having a curved surface is provided.

The wire may include a first sub-wire directly connecting a first portion of the one data line and a fourth portion of the one connection line, and a second portion of the one data line and the second portion of the one data line spaced apart from the first sub-wire. It may include a second sub-wire directly connecting the fifth portion of the one connection line.

One pixel circuit connected to the one data line among the plurality of pixel circuits may be defective, and the one pixel circuit may be cut off from the organic light emitting diode.

A third portion between the first portion and the second portion of the one data line is cut and isolated from the first portion and the second portion while being connected to the one pixel circuit, and the one connection the fourth part, the fifth part of the line, and the sixth part between the fourth part and the fifth part are cut and isolated from another part, and the first part of the one data line is the first sub wire , the fourth part, the sixth part, the fifth part, and the second sub wire of the one connection line may be connected to the second part of the one data line.

The plurality of connection lines may be positioned on the same layer as the plurality of data lines.

The wire may be positioned on the one data line and the one connection line.

The surface of the other portion of the one data line may include a corner.

The surface of the other portion of the one connection line may include an edge.

The plurality of thin film transistors may include a first thin film transistor positioned on the substrate and including a first active pattern connected to the organic light emitting diode and a first gate electrode positioned on the first active pattern, the first active pattern a second thin film transistor including a second active pattern connected to one end of the circuit board and a second gate electrode disposed on the second active pattern and a second active pattern connected to the data line, and a gate connected to the other end of the first active pattern and a third thin film transistor including a third active pattern connected to the first gate electrode through a bridge and a third gate electrode disposed on the third active pattern.

a first scan line positioned on the second active pattern to cross each of the second active pattern and the third active pattern and connected to the second gate electrode and the third gate electrode, and on the first scan line A driving power line adjacent to the data line and crossing the first scan line may further include a driving power line connected to the first active pattern.

The pixel circuit may include a capacitor electrode connected to the driving power line and positioned on the first gate electrode and overlapping the first gate electrode to form a capacitor together with the first gate electrode.

The plurality of thin film transistors may include a fourth active pattern connected to the third active pattern and connected to the first gate electrode through the gate bridge, and a fourth gate electrode disposed on the fourth active pattern. Further comprising a thin film transistor, the second scan line being positioned on the fourth active pattern to cross the fourth active pattern, and connected to the fourth gate electrode, and an initialization power line connected to the fourth active pattern. may include

The initialization power line may extend in a direction parallel to the other direction to be connected to the plurality of connection lines.

The plurality of thin film transistors may include a fifth thin film transistor including a fifth active pattern connecting between the first active pattern and the driving power line, and a fifth gate electrode disposed on the fifth active pattern, and A sixth thin film transistor comprising a sixth active pattern connecting between the first active pattern and the organic light emitting device and a sixth gate electrode disposed on the sixth active pattern, wherein the fifth active pattern and the second The light emitting control line may further include a light emission control line positioned on each of the six active patterns to cross each of the fifth and sixth active patterns and connected to each of the fifth and sixth gate electrodes.

The plurality of thin film transistors may further include a seventh thin film transistor including a seventh active pattern connected to the fourth active pattern and a seventh gate electrode disposed on the seventh active pattern, and on the seventh active pattern The display device may further include a third scan line positioned at , crossing the seventh active pattern, and connected to the seventh gate electrode.

In addition, another aspect of the present invention provides a portion of one data line connected to one pixel circuit among a plurality of data lines connected to a plurality of pixel circuits including a plurality of thin film transistors on a substrate and a data line adjacent to the one data line. A method of repairing an organic light emitting diode display, comprising: treating one or more surfaces of a portion of a connection line to be curved; and connecting a portion of the one data line and a portion of the one connection line with a wire using a wire; do.

The step of processing the curved surface may be performed using a laser beam.

The one pixel circuit may be defective.

The processing of the curved surface may include processing the surfaces of the first portion of the one data line and the second portion spaced apart from the first portion to be curved, and a fourth portion and the fourth portion of the one connection line; and processing the surface of each of the spaced apart fifth portions to be curved, wherein the connecting using the wire includes: connecting a first sub wire between the first portion of the one data line and the fourth portion of the one connection line The method may include directly connecting using a second sub wire, and directly connecting a second portion of the one data line and a fifth portion of the one connection line using a second sub wire.

In the connecting using the wire, a third part between the first part and the second part of the one data line is cut from the first part and the second part to isolate it while being connected to the one pixel circuit (isolating), and cutting the fourth part, the fifth part, and the sixth part between the fourth part and the fifth part of the one connection line from another part and isolating it .

According to one of some embodiments of the above-described means for solving the problems of the present invention, an organic light emitting display device in which one or more defective pixels are easily repaired and an organic light emitting display device in which one or more defective pixels are easily repaired A repair method is provided.

1 is a plan view schematically illustrating an organic light emitting diode display according to an exemplary embodiment.
FIG. 2 is a circuit diagram illustrating one pixel of the organic light emitting diode display according to an exemplary embodiment of the present invention shown in FIG. 1 .
3 is a layout view illustrating a first pixel, a second pixel, and a third pixel among a plurality of pixels of the organic light emitting diode display according to an exemplary embodiment of the present invention shown in FIG. 1 .
4 is a cross-sectional view taken along IV-IV of FIG. 3 .
5 is a cross-sectional view taken along V-V of FIG. 3 .
6A is a photograph illustrating a cross-section of a repaired portion of a conventional organic light emitting diode display, and FIG. 6B is a cross-sectional view of a repaired portion of an organic light emitting diode display according to an exemplary embodiment of the present invention. is the picture shown.
7 is a flowchart illustrating a repair method of an organic light emitting diode display according to another exemplary embodiment.
8 and 9 are layout views illustrating a first pixel, a second pixel, and a third pixel among a plurality of pixels of an organic light emitting diode display to describe a repair method of an organic light emitting diode display according to another exemplary embodiment; .

Hereinafter, with reference to the accompanying drawings, various embodiments of the present invention will be described in detail so that those of ordinary skill in the art to which the present invention pertains can easily implement them. The present invention may be embodied in several different forms and is not limited to the embodiments described herein.

In order to clearly explain the present invention, parts irrelevant to the description are omitted, and the same reference numerals are assigned to the same or similar components throughout the specification.

In addition, since the size and thickness of each component shown in the drawings are arbitrarily indicated for convenience of description, the present invention is not necessarily limited to the illustrated bar.

In order to clearly express various layers and regions in the drawings, the thicknesses are enlarged. And in the drawings, for convenience of description, the thickness of some layers and regions are exaggerated. When a part, such as a layer, film, region, plate, etc., is "on" another part, it includes not only the case where the other part is "directly on" but also the case where there is another part in between.

In addition, throughout the specification, when a part "includes" a certain component, this means that other components may be further included, rather than excluding other components, unless otherwise stated. In addition, throughout the specification, "on" means to be located above or below the target part, and does not necessarily mean to be located above the direction of gravity.

Hereinafter, an organic light emitting diode display according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1 to 5 .

1 is a plan view schematically illustrating an organic light emitting diode display according to an exemplary embodiment. Hereinafter, a pixel may mean a minimum unit for displaying an image.

As shown in FIG. 1 , the organic light emitting diode display according to an exemplary embodiment includes a substrate SUB, a plurality of pixels PXn, a plurality of data lines DA, and a plurality of connection lines CL. ), and a data driver DD.

The substrate SUB includes a display area DIA displaying an image and a non-display area NDA adjacent to the display area DIA. The non-display area NDA may be positioned to surround the edge of the display area DIA, but is not limited thereto and may be positioned in various areas on the substrate SUB. The substrate SUB is an insulating substrate including glass, polymer, stainless steel, or the like. The substrate SUB may be flexible, stretchable, foldable, bendable, or rollable. When the substrate SUB is flexible, stretchable, foldable, bendable, or rollable, the entire organic light emitting diode display is flexible. or may be stretchable, foldable, bendable, or rollable.

The plurality of pixels PXn are positioned on the substrate SUB to correspond to the display area DIA of the substrate SUB. Each of the plurality of pixels PXn is connected to each of the plurality of data lines DA and each of the plurality of connection lines CL, and a driving current corresponding to a data signal supplied from each of the data lines DA. and a pixel circuit including an organic light-emitting device that emits light with a luminance corresponding to that, a plurality of thin film transistors for controlling a driving current flowing through the organic light-emitting device, and one or more capacitors. Each of the plurality of pixels PXn includes an organic light emitting device and the pixel circuit connected to the organic light emitting device.

Although not shown in FIG. 1 for convenience of explanation, each of the plurality of pixels PXn may be connected to each of a plurality of scan lines connected to a gate driver supplying different scan signals, and further, a driving power line supplying a voltage and an initialization power line connected to the connection line CL. In addition, a second electrode that is a cathode of the organic light emitting diode included in each of the plurality of pixels PXn may be connected to a common power source. A detailed structure of each of the plurality of pixels PXn will be described later. The above-described gate driver, the plurality of scan lines, the driving power line, and the initialization power line will be described later, but are not limited thereto, and various wirings may be connected to each of the plurality of pixels PXn in various known forms.

The data driver DD is positioned on the non-display area NDA of the substrate SUB and is connected to the plurality of data lines DA and the plurality of connection lines CL. Meanwhile, in another embodiment of the present invention, each of the plurality of data lines DA and the plurality of connection lines CL may not be connected to the data driver DD but may be connected to another driver.

Each of the plurality of data lines DA extends in one direction on the substrate SUB and is disposed to be spaced apart from each other in the other direction intersecting one direction, and is connected to a pixel circuit of each of the plurality of pixels PXn.

Each of the plurality of connection lines CL is adjacent to the data line DA and extends in a direction parallel to the one direction, and is connected to a pixel circuit of each of the plurality of pixels PXn.

Hereinafter, a circuit of one pixel PXn of an organic light emitting diode display according to an exemplary embodiment will be described with reference to FIG. 2 .

FIG. 2 is a circuit diagram illustrating one pixel of the organic light emitting diode display according to an exemplary embodiment of the present invention shown in FIG. 1 .

As shown in FIG. 2 , one pixel PXn of the organic light emitting diode display according to an exemplary embodiment includes a plurality of thin film transistors T1, T2, T3, T4, T5, T6, and T7 and a capacitor Cst. ) including a pixel circuit (PC), a plurality of wirings (Sn, Sn-1, Sn-2, EM) selectively connected to a plurality of thin film transistors (T1, T2, T3, T4, T5, T6, T7); Vin, CL, DA, ELVDD), and an organic light emitting diode (OLED).

The plurality of thin film transistors T1 , T2 , T3 , T4 , T5 , T6 , and T7 include a first thin film transistor T1 , a second thin film transistor T2 , a third thin film transistor T3 , and a fourth thin film transistor T4 . ), a fifth thin film transistor T5 , a sixth thin film transistor T6 , and a seventh thin film transistor T7 .

The first gate electrode G1 of the first thin film transistor T1 is connected to the third drain electrode D3 of the third thin film transistor T3 and the fourth drain electrode D4 of the fourth thin film transistor T4, respectively. The first source electrode S1 is connected to the second drain electrode D2 of the second thin film transistor T2 and the fifth drain electrode D5 of the fifth thin film transistor T5, and the first drain The electrode D1 is connected to each of the third source electrode S3 of the third thin film transistor T3 and the sixth source electrode S6 of the sixth thin film transistor T6 .

The second gate electrode G2 of the second thin film transistor T2 is connected to the first scan line Sn, the second source electrode S2 is connected to the data line DA, and the second drain electrode (D2) is connected to the first source electrode (S1) of the first thin film transistor (T1).

The third gate electrode G3 of the third thin film transistor T3 is connected to the first scan line Sn, and the third source electrode S3 is the first drain electrode D1 of the first thin film transistor T1 . ), and the third drain electrode D3 is connected to the first gate electrode G1 of the first thin film transistor T1.

The fourth gate electrode G4 of the fourth thin film transistor T4 is connected to the second scan line Sn-1, and the fourth source electrode S4 is the initialization power line Vin connected to the connection line CL. ), and the fourth drain electrode D4 is connected to the first gate electrode G1 of the first thin film transistor T1.

The fifth gate electrode G5 of the fifth thin film transistor T5 is connected to the emission control line EM, the fifth source electrode S5 is connected to the driving power line ELVDD, and the fifth drain electrode (D5) is connected to the first source electrode (S1) of the first thin film transistor (T1).

The sixth gate electrode G6 of the sixth thin film transistor T6 is connected to the emission control line EM, and the sixth source electrode S6 is the first drain electrode D1 of the first thin film transistor T1 . is connected with

The seventh gate electrode G7 of the seventh thin film transistor T7 is connected to the third scan line Sn-2, and the seventh source electrode S7 is connected to the organic light emitting diode OLED, 7 The drain electrode D7 is connected to the fourth source electrode S4 of the fourth thin film transistor T4 .

The plurality of scan lines described above is a first scan signal for transferring a first scan signal to each of the second gate electrode G2 and the third gate electrode G3 of the second thin film transistor T2 and the third thin film transistor T3, respectively. The scan line Sn, the second scan line Sn-1 that transmits the second scan signal to the fourth gate electrode G4 of the fourth thin film transistor T4, and the seventh gate of the seventh thin film transistor T7 The fifth gate electrode G5 and the sixth gate of each of the third scan line Sn - 2 , the fifth thin film transistor T5 , and the sixth thin film transistor T6 that transmit the third scan signal to the electrode G7 . A light emission control line EM for transmitting a light emission control signal to each of the electrodes G6 is included.

The capacitor Cst includes one electrode connected to the driving power line ELVDD and the other electrode connected to the first gate electrode G1 and the third drain electrode D3 of the third thin film transistor T3.

The organic light emitting diode OLED includes a first electrode, a second electrode positioned on the first electrode, and an organic light emitting layer positioned between the first electrode and the second electrode. The first electrode of the organic light emitting diode OLED is connected to each of the seventh source electrode S7 of the seventh thin film transistor T7 and the sixth drain electrode D6 of the sixth thin film transistor T6, and the second The electrode is connected to a common power supply (ELVSS) to which a common signal is transmitted.

An example of driving one pixel PXn including the pixel circuit PC, the plurality of wires Sn, Sn-1, Sn-2, EM, Vin, CL, DA, ELVDD, and the organic light emitting diode OLED , first, when the third scan signal is transmitted to the third scan line Sn-2 to turn on the seventh thin film transistor T7, the residual flowing through the first electrode of the organic light emitting diode OLED Unintentional light emission of the organic light emitting diode (OLED) due to residual current flowing in the first electrode of the organic light emitting diode (OLED) as the current flows through the seventh thin film transistor (T7) to the fourth thin film transistor (T4) this is suppressed

Next, when the second scan signal is transmitted to the second scan line Sn-1 and the initialization signal is transmitted to the initialization power line Vin through the connection line CL, the fourth thin film transistor T4 is turned on Thus, the initialization voltage according to the initialization signal is supplied to the first gate electrode G1 of the first thin film transistor T1 and the other electrode of the capacitor Cst through the fourth thin film transistor T4, whereby the first gate electrode (G1) and capacitor (Cst) are initialized. At this time, while the first gate electrode G1 is initialized, the first thin film transistor T1 is turned on.

Next, when the first scan signal is transmitted to the first scan line Sn and the data signal is transmitted to the data line DA, each of the second thin film transistor T2 and the third thin film transistor T3 is turned on The data voltage Vd according to the data signal is supplied to the first gate electrode G1 through the second thin film transistor T2 , the first thin film transistor T1 , and the third thin film transistor T3 . At this time, the voltage supplied to the first gate electrode G1 is a compensation voltage reduced by the threshold voltage Vth of the first thin film transistor T1 from the data voltage Vd supplied from the first data line DA { Vd+Vth, Vth is a (-) value} is supplied. The compensation voltage Vd+Vth supplied to the first gate electrode G1 is also supplied to the other electrode of the capacitor Cst connected to the first gate electrode G1.

Next, the driving voltage Vel according to the driving signal is supplied from the driving power line ELVDD to one electrode of the capacitor Cst, and the above-described compensation voltage Vd+Vth is supplied to the other electrode, thereby forming the capacitor Cst. The first thin film transistor T1 is turned on for a predetermined time by storing electric charges corresponding to the voltage difference applied to both electrodes.

Next, when the emission control signal is applied to the emission control line EM, each of the fifth thin film transistor T5 and the sixth thin film transistor T6 is turned on, and the driving voltage ( Vel) is supplied to the first thin film transistor T1 through the fifth thin film transistor T5 .

Then, while the driving voltage Vel passes through the first thin film transistor T1 turned on by the capacitor Cst, the voltage supplied to the first gate electrode G1 by the capacitor Cst and the driving voltage ( Vel), a driving current Id corresponding to the voltage difference flows through the first drain electrode D1 of the first thin film transistor T1, and the driving current Id is induced through the sixth thin film transistor T6. It is supplied to the light emitting device OLED, and the organic light emitting device OLED emits light for a predetermined period of time.

Meanwhile, in an organic light emitting diode display according to an exemplary embodiment of the present invention, a pixel circuit PC including first to seventh thin film transistors T1 to T7 and a capacitor Cst and a first scan line connected thereto (Sn) to the third scan line (Sn-2), the data line (DA), the driving power line (ELVDD), the initialization power line (Vin), but is composed of the connection line (CL), but is not limited thereto. An organic light emitting diode display according to another exemplary embodiment may include a pixel circuit including a plurality of thin film transistors and one or more capacitors, and wirings including one or more scan lines and one or more driving power lines connected thereto.

Hereinafter, among the plurality of pixels PXn of the organic light emitting diode display according to an embodiment of the present invention described above with reference to FIG. 3 , a first pixel ( ) adjacent to each other located in the display area DIA of the substrate SUB The arrangement of the PX1 , the second pixel PX2 , and the third pixel PX3 will be described.

3 is a layout view illustrating a first pixel, a second pixel, and a third pixel among a plurality of pixels of the organic light emitting diode display according to an exemplary embodiment of the present invention shown in FIG. 1 .

As shown in FIG. 3 , the first pixel PX1 , the second pixel PX2 , and the third pixel PX3 adjacent to each other positioned on the substrate SUB each include a first thin film transistor T1 and a second pixel PX3 . 2 thin film transistor T2, third thin film transistor T3, fourth thin film transistor T4, fifth thin film transistor T5, sixth thin film transistor T6, seventh thin film transistor T7, first scan line Sn, second scan line Sn-1, third scan line Sn-2, light emission control line EM, capacitor Cst, data line DA, driving power line ELVDD, It includes a gate bridge GB, a connection line CL, an initialization power line Vin, and an organic light emitting diode (OLED). Here, the first pixel PX1 further includes a wire WI unlike the second pixel PX2 and the third pixel PX3 .

A first thin film transistor T1 , a second thin film transistor T2 , and a third thin film transistor T3 which are a plurality of thin film transistors of the first pixel PX1 , the second pixel PX2 , and the third pixel PX3 respectively , the fourth thin film transistor T4 , the fifth thin film transistor T5 , the sixth thin film transistor T6 , the seventh thin film transistor T7 , the gate bridge GB, and the capacitor Cst form the pixel circuit PC can be formed

The first thin film transistor T1 is disposed on the substrate SUB and includes a first active layer A1 and a first gate electrode G1 .

The first active layer A1 includes a first source electrode S1 , a first channel C1 , and a first drain electrode D1 . The first source electrode S1 is connected to each of the second drain electrode D2 of the second thin film transistor T2 and the fifth drain electrode D5 of the fifth thin film transistor T5, and the first drain electrode ( D1) is connected to each of the third source electrode S3 of the third thin film transistor T3 and the sixth source electrode S6 of the sixth thin film transistor T6. The first channel C1, which is the channel region of the first active layer A1 overlapping the first gate electrode G1, has a shape that is bent and extended at least once, and the first channel C1 is a limited space. Since the length of the first channel C1 can be formed by being bent and extended one or more times in a space overlapping with the first gate electrode G1, the gate voltage applied to the first gate electrode G1 A wide driving range can be formed. Accordingly, by changing the magnitude of the gate voltage applied to the first gate electrode G1 within a wide driving range to more precisely control the gradation of light emitted from the organic light emitting diode OLED, display from the organic light emitting display device The image quality can be improved. The first active layer A1 may be deformed in various forms, for example, in various forms such as 'inverted S', 'S', 'M', and 'W'.

The first active layer A1 may be made of polysilicon or an oxide semiconductor. Oxide semiconductors are titanium (Ti), hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), germanium (Ge), zinc (Zn), gallium (Ga), tin (Sn), or indium ( oxides based on In), their complex oxides such as zinc oxide (ZnO), indium-gallium-zinc oxide (InGaZnO4), indium-zinc oxide (Zn-In-O), zinc-tin oxide (Zn-Sn- O) indium-gallium oxide (In-Ga-O), indium-tin oxide (In-Sn-O), indium-zirconium oxide (In-Zr-O), indium-zirconium-zinc oxide (In-Zr-Zn) -O), indium-zirconium-tin oxide (In-Zr-Sn-O), indium-zirconium-gallium oxide (In-Zr-Ga-O), indium-aluminum oxide (In-Al-O), indium- Zinc-aluminum oxide (In-Zn-Al-O), indium-tin-aluminum oxide (In-Sn-Al-O), indium-aluminum-gallium oxide (In-Al-Ga-O), indium-tantalum oxide (In-Ta-O), indium-tantalum-zinc oxide (In-Ta-Zn-O), indium-tantalum-tin oxide (In-Ta-Sn-O), indium-tantalum-gallium oxide (In-Ta -Ga-O), indium-germanium oxide (In-Ge-O), indium-germanium-zinc oxide (In-Ge-Zn-O), indium-germanium-tin oxide (In-Ge-Sn-O), Any one of indium-germanium-gallium oxide (In-Ge-Ga-O), titanium-indium-zinc oxide (Ti-In-Zn-O), and hafnium-indium-zinc oxide (Hf-In-Zn-O) may include When the first active layer A1 is made of an oxide semiconductor, a separate protective layer may be added to protect the oxide semiconductor, which is vulnerable to an external environment such as high temperature.

The first channel C1 of the first active layer A1 may be channel-doped with an N-type impurity or a P-type impurity, and each of the first source electrode S1 and the first drain electrode D1 has a first channel ( A doping impurity of a type opposite to that of the doping impurity doped in the first channel C1 may be doped with the first channel C1 spaced therebetween.

The first gate electrode G1 is positioned on the first channel C1 of the first active layer A1 and has an island shape. The first gate electrode G1 is connected to the fourth drain electrode D4 of the fourth thin film transistor T4 and the third thin film transistor T3 by the gate bridge GB through the contact hole CNT. It is connected to the third drain electrode D3. The first gate electrode G1 overlaps the capacitor electrode CE, and may function as a gate electrode of the first thin film transistor T1 and also function as another electrode of the capacitor Cst. That is, the first gate electrode G1 forms a capacitor Cst together with the capacitor electrode CE.

The second thin film transistor T2 is positioned on the substrate SUB and includes a second active layer A2 and a second gate electrode G2 . The second active layer A2 includes a second source electrode S2 , a second channel C2 , and a second drain electrode D2 . The second source electrode S2 is connected to the data line DA through a contact hole, and the second drain electrode D2 is connected to the first source electrode S1 of the first thin film transistor T1 . The second channel C2 , which is a channel region of the second active layer A2 overlapping the second gate electrode G2 , is positioned between the second source electrode S2 and the second drain electrode D2 . That is, the second active layer A2 is connected to the first active layer A1 .

The second channel C2 of the second active layer A2 may be channel-doped with an N-type impurity or a P-type impurity, and each of the second source electrode S2 and the second drain electrode D2 has a first channel ( A doping impurity of a type opposite to that of the doping impurity doped in the first channel C1 may be doped with the first channel C1 spaced therebetween. The second active layer A2 is positioned on the same layer as the first active layer A1 , is formed of the same material as the first active layer A1 , and is integrally formed with the first active layer A1 .

The second gate electrode G2 is positioned on the second channel C2 of the second active layer A2 and is integrally formed with the first scan line Sn.

The third thin film transistor T3 is disposed on the substrate SUB and includes a third active layer A3 and a third gate electrode G3 .

The third active layer A3 includes a third source electrode S3 , a third channel C3 , and a third drain electrode D3 . The third source electrode S3 is connected to the first drain electrode D1, and the third drain electrode D3 is the first gate of the first thin film transistor T1 by the gate bridge GB through the contact hole. It is connected to the electrode G1. The third channel C3 , which is a channel region of the third active layer A3 overlapping the third gate electrode G3 , is positioned between the third source electrode S3 and the third drain electrode D3 . That is, the third active layer A3 connects between the first active layer A1 and the first gate electrode G1 .

The third channel C3 of the third active layer A3 may be channel-doped with an N-type impurity or a P-type impurity, and each of the third source electrode S3 and the third drain electrode D3 has a third channel ( A doping impurity of a type opposite to that of the doping impurity doped in the third channel C3 may be doped with the third channel C3 interposed therebetween. The third active layer A3 is positioned on the same layer as the first active layer A1 and the second active layer A2 and is formed of the same material as the first active layer A1 and the second active layer A2. and is integrally formed with the first active layer A1 and the second active layer A2.

The third gate electrode G3 is positioned on the third channel C3 of the third active layer A3 and is integrally formed with the first scan line Sn. The third gate electrode G3 is formed as a dual gate electrode.

The fourth thin film transistor T4 is disposed on the substrate SUB and includes a fourth active layer A4 and a fourth gate electrode G4 .

The fourth active layer A4 includes a fourth source electrode S4 , a fourth channel C4 , and a fourth drain electrode D4 . The fourth source electrode S4 is connected to the initialization power line Vin connected to the connection line CL through a contact hole, and the fourth drain electrode D4 is formed by a gate bridge GB through the contact hole. 1 is connected to the first gate electrode G1 of the thin film transistor T1. The fourth channel C4 , which is a channel region of the fourth active layer A4 overlapping the fourth gate electrode G4 , is positioned between the fourth source electrode S4 and the fourth drain electrode D4 . That is, the fourth active layer A4 is connected between the initialization power line Vin and the first gate electrode G1 and is connected to the third active layer A3 and the first gate electrode G1, respectively. .

The fourth channel C4 of the fourth active layer A4 may be channel-doped with an N-type impurity or a P-type impurity, and each of the fourth source electrode S4 and the fourth drain electrode D4 has a fourth channel ( A doping impurity of a type opposite to that of the doping impurity doped in the fourth channel C4 may be doped with the fourth channel C4 spaced therebetween. The fourth active layer A4 is located on the same layer as the first active layer A1, the second active layer A2, and the third active layer A3, and the first active layer A1 and the second active layer (A2) and the third active layer (A3) are formed of the same material, and are integrally formed with the first active layer (A1), the second active layer (A2), and the third active layer (A3).

The fourth gate electrode G4 is positioned on the fourth channel C4 of the fourth active layer A4 and is integrally formed with the second scan line Sn-1. The fourth gate electrode G4 is formed as a dual gate electrode.

The fifth thin film transistor T5 is positioned on the substrate SUB and includes a fifth active layer A5 and a fifth gate electrode G5 .

The fifth active layer A5 includes a fifth source electrode S5 , a fifth channel C5 , and a fifth drain electrode D5 . The fifth source electrode S5 is connected to the driving power line ELVDD through a contact hole, and the fifth drain electrode D5 is connected to the first source electrode S1 of the first thin film transistor T1. . The fifth channel C5 , which is a channel region of the fifth active layer A5 overlapping the fifth gate electrode G5 , is positioned between the fifth source electrode S5 and the fifth drain electrode D5 . That is, the fifth active layer A5 connects between the driving power line ELVDD and the first active layer A1 .

The fifth channel C5 of the fifth active layer A5 may be channel-doped with an N-type impurity or a P-type impurity, and each of the fifth source electrode S5 and the fifth drain electrode D5 has a fifth channel ( A doping impurity of a type opposite to that of the doping impurity doped in the fifth channel C5 may be doped with the fifth channel C5 spaced therebetween. The fifth active layer A5 is located on the same layer as the first active layer A1, the second active layer A2, the third active layer A3, and the fourth active layer A4, and the first active layer (A1), the second active layer (A2), the third active layer (A3), is formed of the same material as the fourth active layer (A4), the first active layer (A1), the second active layer (A2), The third active layer A3 and the fourth active layer A4 are integrally formed.

The fifth gate electrode G5 is positioned on the fifth channel C5 of the fifth active layer A5 and is integrally formed with the emission control line EM.

The sixth thin film transistor T6 is disposed on the substrate SUB and includes a sixth active layer A6 and a sixth gate electrode G6.

The sixth active layer A6 includes a sixth source electrode S6 , a sixth channel C6 , and a sixth drain electrode D6 . The sixth source electrode S6 is connected to the first drain electrode D1 of the first thin film transistor T1, and the sixth drain electrode D6 is a first electrode of the organic light emitting diode OLED through a contact hole. (E1) is connected. The sixth channel C6 , which is a channel region of the sixth active layer A6 overlapping the sixth gate electrode G6 , is positioned between the sixth source electrode S6 and the sixth drain electrode D6 . That is, the sixth active layer A6 connects between the first active layer A1 and the first electrode E1 of the organic light emitting diode OLED.

The sixth channel C6 of the sixth active layer A6 may be channel-doped with an N-type impurity or a P-type impurity, and each of the sixth source electrode S6 and the sixth drain electrode D6 has a sixth channel ( A doping impurity of a type opposite to that of the doping impurity doped in the sixth channel C6 may be doped with the sixth channel C6 interposed therebetween. The sixth active layer A6 is the same layer as the first active layer A1 , the second active layer A2 , the third active layer A3 , the fourth active layer A4 , and the fifth active layer A5 . and is formed of the same material as the first active layer (A1), the second active layer (A2), the third active layer (A3), the fourth active layer (A4), and the fifth active layer (A5), The first active layer A1, the second active layer A2, the third active layer A3, the fourth active layer A4, and the fifth active layer A5 are integrally formed.

The sixth gate electrode G6 is positioned on the sixth channel C6 of the sixth active layer A6 and is integrally formed with the emission control line EM.

The seventh thin film transistor T7 is disposed on the substrate SUB and includes a seventh active layer A7 and a seventh gate electrode G7 .

The seventh active layer A7 includes a seventh source electrode S7 , a seventh channel C7 , and a seventh drain electrode D7 . The seventh source electrode S7 is connected to the first electrode of the organic light emitting device of another pixel not shown in FIG. 3 (which may be a pixel positioned above the pixel shown in FIG. 3 ), and the seventh drain The electrode D7 is connected to the fourth source electrode S4 of the fourth thin film transistor T4 . The seventh channel C7, which is a channel region of the seventh active layer A7 overlapping the seventh gate electrode G7, is positioned between the seventh source electrode S7 and the seventh drain electrode D7. That is, the seventh active layer A7 connects between the first electrode of the organic light emitting diode and the fourth active layer A4 .

The seventh channel C7 of the seventh active layer A7 may be channel-doped with an N-type impurity or a P-type impurity, and each of the seventh source electrode S7 and the seventh drain electrode D7 has a seventh channel ( A doping impurity of a type opposite to that of the doping impurity doped in the seventh channel C7 may be doped with the seventh channel C7 spaced therebetween. The seventh active layer A7 includes the first active layer A1, the second active layer A2, the third active layer A3, the fourth active layer A4, the fifth active layer A5, and the sixth active layer A7. Located on the same layer as the active layer A6, the first active layer A1, the second active layer A2, the third active layer A3, the fourth active layer A4, and the fifth active layer A5 ) and the sixth active layer A6, the first active layer A1, the second active layer A2, the third active layer A3, the fourth active layer A4, and the fifth The active layer A5 and the sixth active layer A6 are integrally formed.

The seventh gate electrode G7 is positioned on the seventh channel C7 of the seventh active layer A7 and is integrally formed with the third scan line Sn-2.

The first scan line Sn is positioned on the second active layer A2 and the third active layer A3 and extends in a direction crossing the second active layer A2 and the third active layer A3, , is formed integrally with the second gate electrode G2 and the third gate electrode G3 and is connected to the second gate electrode G2 and the third gate electrode G3.

The second scan line Sn-1 is spaced apart from the first scan line Sn, is positioned on the fourth active layer A4, extends in a direction crossing the fourth active layer A4, and the fourth It is integrally formed with the gate electrode G4 and is connected to the fourth gate electrode G4.

The third scan line Sn-2 is spaced apart from the second scan line Sn-1, is positioned on the seventh active layer A7, and extends in a direction crossing the seventh active layer A7, It is integrally formed with the seventh gate electrode G7 and is connected to the seventh gate electrode G7.

The emission control line EM is spaced apart from the first scan line Sn and positioned on the fifth active layer A5 and the sixth active layer A6, and the fifth active layer A5 and the sixth active layer A5 and the sixth active layer ( It extends in a direction transverse to A6 , and is integrally formed with the fifth gate electrode G5 and the sixth gate electrode G6 and is connected to the fifth gate electrode G5 and the sixth gate electrode G6 . .

As described above, the emission control line EM, the third scan line Sn-2, the second scan line Sn-1, the first scan line Sn, the first gate electrode G1, and the second gate electrode (G2), the third gate electrode (G3), the fourth gate electrode (G4), the fifth gate electrode (G5), the sixth gate electrode (G6), and the seventh gate electrode (G7) are located on the same layer, made of the same material. Meanwhile, in another embodiment of the present invention, the emission control line EM, the third scan line Sn-2, the second scan line Sn-1, the first scan line Sn, the first gate electrode ( G1), second gate electrode G2, third gate electrode G3, fourth gate electrode G4, fifth gate electrode G5, sixth gate electrode G6, seventh gate electrode G7 Each may optionally be positioned in a different layer and formed of a different material.

The capacitor Cst includes one electrode and another electrode facing each other with an insulating layer interposed therebetween. One electrode described above may be the capacitor electrode CE, and the other electrode may be the first gate electrode G1. The capacitor electrode CE is positioned on the first gate electrode G1 and is connected to the driving power line ELVDD through a contact hole.

The capacitor electrode CE forms a capacitor Cst together with the first gate electrode G1, and each of the first gate electrode G1 and the capacitor electrode CE is formed of different or the same metal in different layers. has been

The capacitor electrode CE includes an opening OA exposing a portion of the first gate electrode G1, and the gate bridge GB is connected to the first gate electrode G1 through the opening OA. there is.

The data line DA is positioned on the first scan line Sn and extends in one direction crossing the first scan line Sn, and each of the plurality of data lines DA has a second direction crossing the first scan line Sn. directions are spaced apart from each other. The data line DA is connected to the second source electrode S2 of the second active layer A2 through a contact hole. The data line DA crosses the first scan line Sn, the second scan line Sn-1, the third scan line Sn-2, the emission control line EM, and the initialization power line Vin. has been extended

The driving power line ELVDD is spaced apart from the data line DA, is positioned on the first scan line Sn, and extends in one direction crossing the first scan line Sn, and the capacitor electrode ( CE) and the fifth source electrode S5 of the fifth active layer A5 connected to the first active layer A1. The driving power line ELVDD crosses the first scan line Sn, the second scan line Sn-1, the third scan line Sn-2, the emission control line EM, and the initialization power line Vin. is extended across

The gate bridge GB is spaced apart from the driving power line ELVDD, and through a contact hole, the third drain electrode D3 of the third active layer A3 and the fourth drain electrode D3 of the fourth active layer A4 D4) and connected to the first gate electrode G1 exposed through the opening OA of the capacitor electrode CE through a contact hole. That is, the gate bridge GB includes a first thin film transistor T1 that is any one of the first thin film transistors T1 to T7 which is a plurality of thin film transistors, and a third thin film transistor T3 that is the other one. and between the first thin film transistor T1 which is one and the fourth thin film transistor T4 which is the other, respectively.

The connection line CL is disposed between the adjacent data lines DA and extends in a direction parallel to one direction that is the extension direction of the data line DA. The connection line CL is connected to the initialization power line Vin, and is connected to each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 through the initialization power line Vin. . The connection line CL extends in a direction parallel to one direction and the initialization power line Vin extends in a direction crossing the connection line CL, so that the connection line CL and the initialization power line Vin are connected to the substrate (SUB) has a planar matrix shape throughout.

The connection line CL is positioned on the same layer as the aforementioned gate bridge GB, the data line DA, and the driving power line ELVDD, and is formed of the same material. Meanwhile, in another embodiment of the present invention, each of the connection line CL, the data line DA, the driving power line ELVDD, and the gate bridge GB may be selectively positioned on different layers to be formed of different materials. can

The initialization power line Vin extends in a direction crossing the extending direction of the connection line CL, and extends in a direction parallel to the above-described other direction, which is an arrangement direction of each of the plurality of data lines DA. The initialization power line Vin is connected to the connection line CL through the contact hole, and is connected to the fourth source electrode S4 of the fourth active layer A4 through the contact hole. The initialization power line Vin is positioned on the same layer as the capacitor electrode CE and is formed of the same material. Meanwhile, in another embodiment of the present invention, the initialization power line Vin may be positioned on a different layer from the capacitor electrode CE and may be formed of a different material.

The organic light emitting diode OLED includes a first electrode E1 , an organic light emitting layer, and a second electrode. The first electrode E1 is connected to the sixth drain electrode D6 of the sixth thin film transistor T6 through a contact hole. The first electrode E1, the organic emission layer, and the second electrode may be sequentially stacked, and at least one of the first electrode E1 and the second electrode may be any one of a light transmissive electrode, a light reflective electrode, and a light semitransmissive electrode or more, and the light emitted from the organic emission layer may be emitted in one or more directions of the first electrode E1 and the second electrode.

A capping layer covering the organic light emitting diode (OLED) may be positioned on the organic light emitting device (OLED), and a thin film encapsulation layer is formed on the organic light emitting device (OLED) with the capping layer interposed therebetween. Or, an encapsulation substrate may be located.

Hereinafter, with reference to FIGS. 3 to 5 , the second pixel PX2 and the third pixel PX3 among the first pixel PX1 , the second pixel PX2 and the third pixel PX3 are connected to the wire WI The further included first pixel PX1 will be described in detail.

4 is a cross-sectional view taken along IV-IV of FIG. 3 . 5 is a cross-sectional view taken along V-V of FIG. 3 . 4 and 5 respectively illustrate cross-sections of a data line, a connection line, and a wire for convenience of description.

3 to 5 , the first pixel PX1 is a pixel repaired by a repair method of an organic light emitting diode display to be described later, and is connected to the data line DA included in the first pixel PX1 . The line CL has a structure different from that of the second pixel PX2 and the third pixel PX3 .

The pixel circuit PC of the first pixel PX1 may be different from the pixel circuit PC of each of the second pixel PX2 and the third pixel PX3 , and the pixel circuit PC of the first pixel PX1 may be defective. PC) is cut (CUT) with the organic light emitting device (OLED).

The first pixel PX1 further includes a wire WI directly connecting a portion of the data line DA and a portion of the connection line CL, and includes a wire WI that is in contact with the data line DA. At least one surface of the one portion and the one portion of the connection line CL has a curved shape.

Specifically, the data line DA of the first pixel PX1 includes a first portion PA1 , a second portion PA2 , and a third portion PA3 , and the connection line CL includes a fourth portion PA1 , PA2 , and a third portion PA3 . PA4 ), a fifth portion PA5 , and a sixth portion PA6 . The wire WI includes a first sub-wire W1 and a second sub-wire W2.

The first portion PA1 of the data line DA is connected to the fourth portion PA4 of the connection line CL through a first sub-wire W1, and the first sub-wire W1 has the same layer as each other. The first portion PA1 of the data line DA positioned at , and the fourth portion PA4 of the connection line CL are directly connected. The first sub-wire W1 is positioned on the data line DA and the connection line CL, and is in direct contact with each of the data line DA and the connection line CL.

The second part PA2 of the data line DA is connected to the fifth part PA5 of the connection line CL through the second sub-wire W2, and the second sub-wire W2 has the same layer as each other. The second portion PA2 of the data line DA positioned at , and the fifth portion PA5 of the connection line CL are directly connected. The second sub-wire W2 is positioned on the data line DA and the connection line CL, and is in direct contact with each of the data line DA and the connection line CL.

Each of the first and second portions PA1 and PA2 of the data line DA connected by the first sub-wire W1 and the second part of the connection line CL connected by the second sub-wire W2 Each of the fourth and fifth portions PA4 and PA5 has a curved surface.

As described above, each of the surfaces of the first portion PA1 of the data line DA directly connected to the first sub wire W1 and the fourth portion PA4 of the connection line CL has a curved shape, and the first sub wire W1 has a curved surface. The surface of each of the second portion PA2 of the data line DA that is in direct contact with the wire W1 and directly connected to the second sub-wire W2 and the fifth portion PA5 of the connection line CL is Since it has a curved shape, each of the first sub-wire W1 and the second sub-wire W2 easily connects the data line DA and the connection line CL. Specifically, when the surface of each of the connection line CL and the data line DA to which the wire WI is directly connected has a corner, the wire WI is unintentionally cut by the corner and the wire ( Although the connection between the data line DA and the connection line CL by WI) may not be performed, in an embodiment of the present invention, the first portion ( Since each of the surfaces PA1) and the second part PA2 and the fourth part PA4 and the fifth part PA5 of the connection line CL have a curved shape, the data line (WI) DA) and the connection line CL are easily connected.

Surfaces of other portions of the data line DA other than the first portion PA1 and the second portion PA2 of the data line DA have a corner, unlike the first portion PA1 and the second portion PA2 . , and the surfaces of the other parts of the connection line CL other than the fourth part PA4 and the fifth part PA5 of the connection line CL are different from the fourth part PA4 and the fifth part PA5 and have corners. have

The third part PA3 positioned between the first part PA1 and the second part PA2 of the data line DA is connected to the pixel circuit PC and the first part PA1 and the second part PA2 are connected to the first part PA1 and the second part PA2. A fourth portion PA4, a fifth portion PA5, and a sixth portion between the fourth portion PA4 and the fifth portion PA5 of the connection line CL are isolated and cut from PA2) (PA6) is isolated by CUT from other parts.

Accordingly, the first portion PA1 of the data line DA of the first pixel PX1 is connected to the first sub wire W1 and the fourth portion PA4 and the sixth portion PA6 of the connection line CL. , the fifth portion PA5 and the second sub-wire W2 are connected to the second portion PA2 of the data line DA. In addition, the data signal through the data line DA connected to the first pixel PX1 is transmitted to the first portion PA1 of the data line DA, the first sub wire W1, and the fourth portion of the connection line CL. The pixel circuit of the first pixel PX1 through PA4 , the sixth part PA6 , the fifth part PA5 , the second sub wire W2 , and the second part PA2 of the data line DA PC) and supplied to other pixels under the first pixel PX1.

That is, the pixel circuit PC of the defective first pixel PX1 is not connected to the data line DA, and the data signal passing through the data line DA is transmitted to the wire WI and the connection line CL. is supplied to a pixel other than the first pixel PX1 through . Accordingly, when the plurality of pixels emit light, the first pixel PX1 does not emit light, so that the first pixel PX1 is suppressed from being viewed.

That is, the organic light emitting diode display device in which the defective first pixel PX1 is suppressed from being viewed is provided by repairing the defective first pixel PX1 .

Hereinafter, an effect of the organic light emitting diode display according to an exemplary embodiment will be described with reference to FIG. 6 .

6A is a photograph illustrating a cross-section of a repaired portion of a conventional organic light emitting diode display, and FIG. 6B is a cross-sectional view of a repaired portion of an organic light emitting diode display according to an exemplary embodiment of the present invention. is the picture shown.

As shown in FIG. 6A , in the conventional organic light emitting display device, the surface of the data line SD in direct contact with the wire W includes an edge, so that the wire W is intended by the edge. Since it is not cut (CUT), the connection between the data line SD and the connection line by the wire W is not performed.

On the other hand, as shown in FIG. 6B , in an embodiment of the present invention, the surface of the data line to which the wire is directly connected has a curved surface, so that it is easy to connect the data line and the connection line with the wire. closely connected

As described above, in the organic light emitting diode display according to an embodiment of the present invention, at least one surface of a portion of the data line DA and a portion of the connection line CL in contact with the wire WI has a curved shape. , is easily connected between the data line DA and the connection line CL by the wire WI. That is, an organic light emitting diode display in which repair is easily performed is provided.

Hereinafter, a method for repairing an organic light emitting diode display according to another exemplary embodiment will be described with reference to FIGS. 7 to 9 . The organic light emitting diode display according to the exemplary embodiment described above may be provided by using the repair method of the organic light emitting diode display according to another exemplary embodiment of the present invention.

7 is a flowchart illustrating a repair method of an organic light emitting diode display according to another exemplary embodiment. 8 and 9 are layout views illustrating a first pixel, a second pixel, and a third pixel among a plurality of pixels of the organic light emitting diode display to explain a repair method of the organic light emitting display device according to another exemplary embodiment; .

First, as shown in FIGS. 7 and 8 , at least one surface of a portion of one data line and a portion of one connection line is curved ( S100 ).

Specifically, each of the plurality of thin film transistors T1 , T2 , T3 , T4 , the plurality of thin film transistors T1 , T2 , T3 , T4 , A lighting test is performed to check whether the pixel circuit PC including T5 , T6 , and T7 is defective, and a first of the first pixel PX1 , the second pixel PX2 , and the third pixel PX3 is performed. If it is confirmed that the pixel PX1 is a defective pixel, the first part PA1 and the second part PA1 that is a part of one data line DA connected to the pixel circuit PC of the first pixel PX1 that is one pixel circuit Surfaces of each of the two portions PA2 and the fourth and fifth portions PA4 and PA5 of the one data line DA and one connection line CL adjacent to each other are subjected to a curved surface treatment.

For example, a surface of each of the first and second portions PA1 and PA2 that are a portion of the data line DA and a fourth portion PA4 and a fifth portion of the one connection line CL using a laser beam Surfaces of each of PA5 may be curved, and the surface of each of the first and second portions PA1 and PA2 of the data line DA and the connection line CL are not limited thereto, but are not limited thereto using various known methods. ) of the fourth part PA4 and the fifth part PA5 may be curved.

Next, as shown in FIG. 9 , a wire is connected between a portion of one data line and a portion of one connection line ( S200 ).

In detail, a portion of one data line DA and a portion of one connection line CL are connected using a wire WI.

Specifically, using a deposition process, the first sub wire W1 is directly connected between the first portion PA1 of the data line DA and the fourth portion PA4 of the connection line CL, and the data line ( A second sub wire W2 is directly connected between the second portion PA2 of the DA and the fifth portion PA5 of the connection line CL.

Also, the third part PA3 between the first part PA1 and the second part PA2 of the data line DA of the first pixel PX1 is connected to the one pixel circuit PC, and the first part The fourth part PA4, the fifth part PA5, the fourth part PA4 and the fifth part of the connection line CL are isolated by cutting (CUT) from the PA1 and the second part PA2. The sixth part PA6 between PA5) is cut (CUT) from the other part to isolate it.

The organic light emitting diode display according to an embodiment of the present invention described above can be provided by using the repair method of the organic light emitting display according to another embodiment of the present invention as described above.

Meanwhile, in another embodiment of the present invention, the data line DA is connected to the connection line CL by a wire WI, but in another embodiment of the present invention, the data line DA is connected by a wire WI. It may be connected to the driving power line ELVDD or another line positioned on the same layer as the data line DA.

As described above, in the repair method of an organic light emitting diode display according to another exemplary embodiment of the present invention, at least one surface of a portion of the data line DA and a portion of the connection line CL is treated in a curved shape, and the wire ( WI) is used to connect a portion of the data line DA having a curved surface and a portion of the connection line CL, so that the data line DA and the connection line CL are separated by the wire WI easily connected That is, there is provided a repair method of an organic light emitting diode display in which repair by a wire WI is easily performed.

Although the present invention has been described through several embodiments as described above, the present invention is not limited thereto, and various modifications and variations are possible without departing from the concept and scope of the following claims. Those in the technical field to which it belongs will readily understand.

Substrate (SUB), organic light emitting device (OLED), pixel circuit (PC), data line (DA), connection line (CL), wire (WI)

Claims (20)

Board;
a plurality of organic light emitting devices positioned on the substrate and spaced apart from each other;
a plurality of pixel circuits each including a plurality of thin film transistors connected to each of the plurality of organic light emitting devices;
a plurality of data lines each extending in one direction on the substrate and disposed to be spaced apart from each other in another direction crossing the one direction and connected to the plurality of pixel circuits;
a plurality of connection lines, each of which is adjacent to the data line and extends in a direction parallel to the one direction, and is connected to the plurality of pixel circuits; and
A wire directly connecting a portion of one data line among the plurality of data lines and a portion of one connection line adjacent to the one data line among the plurality of connection lines
includes,
At least one surface of a portion of the one data line and a portion of the one connection line in contact with the wire is a curved surface. In claim 1,
The wire is
a first sub-wire directly connecting a first portion of the one data line and a fourth portion of the one connection line; and
a second sub-wire spaced apart from the first sub-wire and directly connecting a second portion of the one data line and a fifth portion of the one connection line
An organic light emitting diode display comprising: In claim 2,
One pixel circuit connected to the one data line among the plurality of pixel circuits is defective;
The one pixel circuit is cut off from the organic light emitting diode. In claim 3,
a third portion between the first portion and the second portion of the one data line is cut and isolated from the first portion and the second portion while being connected to the one pixel circuit;
the fourth part, the fifth part, and the sixth part between the fourth part and the fifth part of the one connecting line are cut and isolated from another part;
A first portion of the one data line may be connected to a second portion of the one data line through the first sub wire, the fourth portion of the one connection line, the sixth portion, the fifth portion, and the second sub wire. an organic light emitting diode display connected to In claim 1,
The plurality of connection lines are positioned on the same layer as the plurality of data lines. In claim 1,
The wire is positioned on the one data line and the one connection line. In claim 1,
and a surface of the other portion of the one data line includes a corner. In claim 1,
and a surface of the other portion of the one connection line includes a corner. In claim 1,
The plurality of thin film transistors,
a first thin film transistor positioned on the substrate and including a first active pattern connected to the organic light emitting diode and a first gate electrode positioned on the first active pattern;
a second thin film transistor connected to one end of the first active pattern and including a second active pattern connected to the data line and a second gate electrode disposed on the second active pattern; and
A third thin film transistor including a third active pattern connected to the other end of the first active pattern and connected to the first gate electrode through a gate bridge, and a third gate electrode positioned on the third active pattern
An organic light emitting diode display comprising: In claim 9,
a first scan line positioned on the second active pattern to cross each of the second active pattern and the third active pattern and connected to the second gate electrode and the third gate electrode; and
A driving power line adjacent to the data line and crossing the first scan line on the first scan line and connected to the first active pattern
An organic light emitting diode display further comprising a. In claim 10,
The pixel circuit is
and a capacitor electrode connected to the driving power line and positioned on the first gate electrode, the capacitor electrode overlapping the first gate electrode to form a capacitor together with the first gate electrode. In claim 11,
The plurality of thin film transistors may include a fourth active pattern connected to the third active pattern and connected to the first gate electrode through the gate bridge, and a fourth gate electrode disposed on the fourth active pattern. It further comprises a thin film transistor,
a second scan line positioned on the fourth active pattern to cross the fourth active pattern and connected to the fourth gate electrode; and
an initialization power line connected to the fourth active pattern
An organic light emitting diode display further comprising a. In claim 12,
The initialization power line extends in a direction parallel to the other direction and is connected to the plurality of connection lines. In claim 13,
The plurality of thin film transistors,
a fifth thin film transistor including a fifth active pattern connecting between the first active pattern and the driving power line and a fifth gate electrode disposed on the fifth active pattern; and
A sixth thin film transistor including a sixth active pattern connecting the first active pattern and the organic light emitting device and a sixth gate electrode disposed on the sixth active pattern
further comprising,
A light emission control line positioned on each of the fifth and sixth active patterns to cross each of the fifth and sixth active patterns and connected to each of the fifth and sixth gate electrodes
An organic light emitting diode display further comprising a. 15. In claim 14,
The plurality of thin film transistors further include a seventh thin film transistor including a seventh active pattern connected to the fourth active pattern and a seventh gate electrode positioned on the seventh active pattern,
and a third scan line positioned on the seventh active pattern to cross the seventh active pattern and connected to the seventh gate electrode. At least one of a portion of a data line connected to a pixel circuit among a plurality of data lines connected to a plurality of pixel circuits including a plurality of thin film transistors on a substrate and a portion of a connection line adjacent to the one data line curved surface treatment;
connecting a portion of the one data line and a portion of the one connection line using a wire
A method of repairing an organic light emitting diode display comprising: 17. In claim 16,
The step of processing the curved surface is a repair method of an organic light emitting display device performed using a laser beam. 17. In claim 16,
The method of repairing an organic light emitting diode display in which the one pixel circuit is defective. 17. In claim 16,
The step of processing the curved surface,
processing the surfaces of the first portion of the one data line and the second portion spaced apart from the first portion to be curved; and
Surface treatment of the fourth portion of the one connection line and the surface of each of the fifth portion spaced apart from the fourth portion
includes,
The step of connecting using the wire is,
directly connecting a first portion of the one data line and a fourth portion of the one connection line using a first sub wire; and
directly connecting a second portion of the one data line and a fifth portion of the one connection line using a second sub wire;
A method of repairing an organic light emitting diode display comprising: In paragraph 19,
The step of connecting using the wire is,
cutting and isolating a third portion between the first portion and the second portion of the one data line from the first portion and the second portion while being connected to the one pixel circuit; and
cutting and isolating the fourth part, the fifth part, and the sixth part between the fourth part and the fifth part of the one connecting line from other parts
A method of repairing an organic light emitting diode display comprising:

Images