JP4654149B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a technique effective when applied to a heat radiation design technique for a high-frequency transmitting / receiving semiconductor device or a power supply semiconductor device mounted on a portable information terminal such as a cellular phone.

  For example, Patent Document 1 and Patent Document 2 disclose a mounting structure for reducing the thermal resistance as a technology related to heat radiation design of a power semiconductor device for high-frequency transmission and reception mounted on a portable information terminal such as a cellular phone. Yes. Among these, the mounting structure disclosed in Patent Document 1 has a face-up structure in which the circuit formation region (active region) of the semiconductor element 7 is on the element upper surface as shown in the cross-sectional view of FIG. A heat conduction member which is a connecting member is used between the lower part of the element and the multilayer wiring board 1, and a system in which this heat conduction member functions as a so-called heat diffusion plate 5 is adopted. In FIG. 1, 2 is a mold resin, 3 is a bonding wire, 4 is a bonding member, 6 is a bonding member, and 8 is a thermal via.

  On the other hand, in the mounting structure disclosed in Patent Document 2, as shown in the cross-sectional view of FIG. 2, the semiconductor element 7 is a multi-layer wiring board in a face-down manner in which the active region faces the lower surface of the element, that is, in a flip chip connection method. 1 is a layered structure. In this case, a method of efficiently radiating heat to the wiring board is employed by a large-area bump structure dedicated to heat radiation. In FIG. 2, 9 is an electrical connection electrode, 10 is an electrical connection bump, 11 is an insulating layer, 12 is a heat dissipation electrode, and 13 is a heat dissipation bump.

An example of a structure for improving the heat dissipation of a flip-chip connected semiconductor element is also disclosed in Patent Document 3.
JP 2001-102483 A Japanese Patent Laid-Open No. 2003-282631 JP-A-6-260532

  By the way, in the prior art disclosed in the above-mentioned Patent Document 1, the heat conducting member functioning as a heat diffusion plate has only a grounding function for connecting the back surface of the semiconductor element and the wiring board in terms of circuit, such as wire bonding. When the signal wiring is provided by means, there is a problem that the mounting area increases. Moreover, since the number of parts, connecting members, and mounting processes thereof are increased by adding the heat diffusion plate, there is a problem that the cost of the product increases.

  On the other hand, in the prior art disclosed in Patent Document 2, an effect of reducing the thermal resistance in the flip chip mounting structure can be expected, but a thick interlayer insulating film is provided between the main heat generation region of the semiconductor element and the heat dissipation bump. Since it exists, the thermal resistance reduction effect will be limited. Also, if the bumps for heat dissipation and the bumps for electrical connection are different, using solder bumps requires a complicated and expensive mounting process to mount each bump with sufficient adhesion, There is also a problem that the manufacturing cost increases.

  In addition, the mounting structure disclosed in Patent Document 3 discloses a structure in which holes are formed in a wiring board and filled with metal to release heat from the semiconductor element. With this structure, heat dissipation higher than that of the prior art disclosed in Patent Document 2 can be expected, but it is still difficult to adjust the height of the protruding portion from the substrate by making a hole in the substrate and filling it with metal. Since the linear expansion coefficients of the bump for electrical connection and the filling metal are also different, it is considered difficult to apply to a product mounted on a mobile phone or the like whose environmental temperature range is relatively wide from low temperature to high temperature.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of reducing the thermal resistance of a flip chip mounting structure while achieving both heat dissipation and ease of manufacture without causing an increase in manufacturing cost.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  In order to achieve the above object, the present invention provides a flip-chip connection of a semiconductor device mounted with a power circuit device for transmission or a power amplifier such as a power amplifier among semiconductor devices used for portable information terminals such as cellular phones. It is characterized by mounting by. When mounting by this flip chip connection, it is possible to achieve both heat dissipation and ease of manufacture by forming bumps for electrical connection and bumps for heat dissipation with the same material and the same height.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the present invention, in a semiconductor device such as a power amplifier (power amplifier) and a power supply module mounted on a portable information terminal such as a mobile phone, improvement in heat dissipation when a semiconductor element is flip-chip connected, A mounting structure capable of achieving both mass productivity in the manufacturing process can be provided.

  In addition, according to the present invention, when the solder bump is adopted by making the width of the band-shaped heat radiation combined bump formed on the outer peripheral portion of the semiconductor element and the width of the normal signal connection bump substantially constant, It is possible to avoid the occurrence of height variation in the bump due to the surface tension of the solder, and to realize a flip chip mounting structure with high connectivity.

  Furthermore, according to the present invention, by disposing a thermal via group below the second layer of the wiring layer of the multilayer wiring board, the heat brought from the band-shaped heat radiation and bump to the multilayer wiring board can be effectively transferred to the back surface of the multilayer wiring board. It is possible to dissipate heat.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted. Further, in the sectional views of the drawings, a part of the sectional notation is omitted for easy understanding.

  The embodiments of the present invention are applied to a semiconductor device in which a semiconductor circuit for power amplification or signal amplification and a control circuit for controlling the semiconductor circuit are stacked on a multilayer wiring board. The control circuit is formed in parallel on the same semiconductor element, and the semiconductor element has a mounting structure mounted on the multilayer wiring board by flip chip connection. In the case of a semiconductor circuit for signal amplification, a plurality of amplifier circuits for amplifying signals in a plurality of bands are arranged in parallel, and the control circuit is sandwiched between the plurality of amplifier circuits so that the same semiconductor It is characterized by being arranged in parallel on the element. Each embodiment will be specifically described below including these features.

(Embodiment 1)
The semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. 3 is a cross-sectional view showing the mounting structure of the semiconductor device, FIG. 4 is a view showing the arrangement of the element bump electrodes in the semiconductor device, and FIG. 5 is a cross-sectional view showing the connection structure from the active region to the wiring board in the semiconductor device. 6 is a cross-sectional view in the case where a thermal via is formed below the second layer of the wiring board in the mounting structure of the semiconductor device, and FIG. 7 is a cross-sectional view showing another connection structure from the active region to the wiring board in the semiconductor device. 8 is a cross-sectional view showing still another connection structure from the active region to the wiring board in the semiconductor device, and FIG. 9 is a cross-sectional view showing a connection structure from the active region to the thermal via in the source or emitter side wiring layer in the semiconductor device. is there.

  As shown in FIG. 3, the semiconductor device of this embodiment includes a multilayer wiring board 1, a mold resin 2, a semiconductor element 7, a thermal via 8, a drain or gate electrode or collector or base electrode 9a, a source electrode or emitter electrode 9b. , Control circuit electrode 9c, drain or gate bump or collector or base bump 10a, source bump or emitter bump 10b, control circuit bump 10c, underfill resin 14, interlayer connection via 15, substrate insulating layer 16, ground electrode 22, It is composed of a substrate wiring layer 23 and the like.

  In this semiconductor device, a semiconductor element 7 is mounted on a multilayer wiring board 1 by flip chip connection. Among these, the drain, gate electrode, collector, or base electrode 9a of the semiconductor element 7 is connected to the drain, gate electrode, collector, or base electrode 9a of the multilayer wiring board 1 through the drain, gate bump, collector, or base bump 10a. Is done. Further, the source electrode or emitter electrode 9b of the semiconductor element 7 is connected to the source electrode or emitter electrode 9b of the wiring board 1 through the source bump or emitter bump 10b.

  In the case of a power supply circuit or power amplifier targeted in this embodiment, a signal or power output circuit and a circuit for controlling them are formed on the same semiconductor element to increase the mounting density. The area of the semiconductor element 7 is reduced to meet the demand for part size reduction. For this reason, particularly in the case of a circuit for amplifying signals of a plurality of standards / bands, a control circuit is formed in the central portion of the semiconductor element 7 and a signal amplification / power supply circuit is formed in the peripheral portion. . Among these circuits, what generates a large amount of heat and needs to improve heat dissipation is the final output transistor of the signal amplification / power supply circuit formed in the peripheral portion. In the case of FIG. 4, the output stage 17c corresponds to the first stage 17a, the second stage 17b, and the output stage 17c of the active region for signal amplification. In the present embodiment, as shown in FIG. 4, the active region that mainly generates heat is concentrated at the end of the semiconductor element 7.

  FIG. 5 is a cross-sectional view showing an electrode connection structure from the semiconductor element 7 to the multilayer wiring board 1 in the present embodiment shown in FIGS. 3 and 4. As shown in FIG. 5, the semiconductor element 7 mounted on the semiconductor device in the present embodiment is electrically connected from the active region 18 to the electrode 9 (9a, 9b) via the element wiring layer 19, Further, it is connected to the multilayer wiring board 1 via the bumps 10 (10a, 10b). Among these, a barrier metal 21 is formed between the bump 10 and the electrode 9 to prevent material deterioration due to diffusion of atoms between the bump 10 and the electrode 9. In the case of FIG. 5, since the bumps 10a and 10b are not at the same potential, each has a structure insulated by element insulating layers 20a, 20b, and 20c such as interlayer insulating films and passivation films.

  The source or emitter electrode 9 b is connected to the back ground electrode of the multilayer wiring board 1 through the interlayer connection via 15 and the thermal via 8 formed in the multilayer wiring board 1. Heat generated in the active region is transmitted to the multilayer wiring board 1 mainly via the bumps 10 for electrical connection, and is radiated to the outside of the semiconductor device through the thermal via 8 as a main heat dissipation path. The

  As shown in FIG. 4, when various electrodes are intricately arranged, the first layer and the second layer from at least the top as viewed from the side of the multilayer wiring board 1 close to the semiconductor element 7 mounting surface. The wiring layer of the eye requires wiring. For this reason, in the present embodiment, the source electrode or emitter electrode 9b of two different signal amplification circuits are short-circuited at the third or lower layer of the wiring layer to form a large number of common thermal vias 8, The method of routing the control circuit electrode 9c and the drain, gate electrode, collector or base electrode 9a in the first layer and the second layer is shown. However, when the wiring from the electrodes 9a and 9c can be carried out only in the first wiring layer, the thermal via connecting the electrode 9b and the ground electrode can be formed from the second wiring layer. An example is shown in FIG. Of course, the thermal via 8 may be formed immediately below the first layer of the wiring layer, but in that case, it is necessary to arrange it so as not to be short-circuited with 9a and 9c.

  According to the present embodiment, since the material and thickness of the heat dissipation bump and the bump for electrical connection are equal, the complexity of the configuration due to the difference in linear expansion coefficient and the bump height is eliminated, and the cost is low. All the bumps can be formed and the semiconductor element 7 can be mounted. Further, by forming a thermal via that short-circuits the source electrode or the emitter electrode and the ground electrode below the third or second layer of the wiring layer of the multilayer wiring board 1, the flip chip is improved while improving the heat dissipation of the multilayer wiring board. Wiring routing on the wiring board surface layer (first layer) and second layer required in the mounting structure can be realized. In the multilayer wiring board 1, the first layer and the second layer are preferably thinner than the third layer or less.

  For the structure included in the cross-sectional view shown in FIG. 5, as shown in FIG. 7 or FIG. 8, the number of interlayer connection vias 15 connected to the thermal via 8 is the drain or gate electrode (or collector or base electrode). ) It may be increased from the 9a side or the cross-sectional area may be increased. In this case, the heat transmitted to the multilayer wiring board 1 via the source electrode (or emitter electrode) 9b is effectively transmitted to the thermal via 8, so that the heat dissipation can be further improved.

  In the case of the present embodiment, the parallel arrangement of the source electrode (or emitter electrode) 9b and the source bump (or emitter bump) 10b is a distributed arrangement as shown in FIG.

  Hereinafter, in the description of other embodiments of the present embodiment, the drain or gate electrode or collector or base electrode 9a, the source electrode or emitter electrode 9b, the drain or gate bump or collector or base bump 10a, the source bump or emitter The bump 10b may be abbreviated as a drain or gate electrode 9a, a source electrode 9b, a drain or gate bump 10a, and a source bump 10b, respectively.

(Embodiment 2)
A semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. FIG. 10 is a diagram showing an example in which source electrodes are densely arranged in the arrangement of element bump electrodes in a semiconductor device, and FIG. 11 is a connection from an active region to a thermal via for a source or emitter side wiring layer in the semiconductor device. FIG. 12 is a cross-sectional view showing the structure, FIG. 12 is a cross-sectional view showing another connection structure from the active region to the thermal via for the source or emitter side wiring layer in the semiconductor device, and FIG. 13 is for the source or emitter side wiring layer in the semiconductor device. It is sectional drawing which shows other connection structure from an active region to a thermal via. Note that the cross section of the semiconductor device which does not overlap with FIGS. 10 to 13 in this embodiment is similar to FIGS. 3 and 5 to 9.

  In the present embodiment, in the electrode layout shown in FIG. 4, the arrangement interval of the source electrodes 9b arranged in parallel in the vicinity of the output stage 17c of the signal amplification active region is set as the interval between the opposing drain or gate electrodes 9a. It is characterized by a narrower pitch.

  In the present embodiment, the total cross-sectional area of the source electrode 9b in the vicinity of the output stage 17c that generates the largest amount of heat in the active region for signal amplification is larger than that in the embodiment shown in FIG. Therefore, the sum of the cross-sectional areas of the source bumps 10b is also increased, the heat flux passing through the source bumps 10b is relatively reduced, and the thermal resistance can be reduced.

  The arrangement of the source bumps 10b in the present embodiment is expected to be as shown in the cross-sectional view of FIG. 9, but when the distance between the source electrodes 9b is close, a low melting point metal such as solder is applied to the source bumps 10b. If used, they are melted and interconnected in the reflow process, and the source electrode 9b on the semiconductor element 7 side is insulated by element insulating layers 20b and 20c such as a passivation film as shown in the sectional view of FIG. However, the source bump 10b may be a large band-shaped bump. In this case, when the melting / bonding of the bumps is predicted in advance, as shown in FIG. 11, the source electrode 9b of the multi-layer wiring board 1 on the receiving side may be formed by combining a plurality of the same potentials. I do not care.

  In the cross-sectional view shown in FIG. 11, the interlayer connection via 15 for connecting the source electrode 9b and the thermal via 8 is arranged in a one-to-one correspondence with the source bump 10b. As shown in the cross-sectional view shown in FIG. 5, the number of interlayer connection vias 15 may be increased or the area may be increased in order to improve heat dissipation. Thereby, further improvement in heat dissipation can be expected.

(Embodiment 3)
A semiconductor device according to a third embodiment of the present invention will be described with reference to FIGS. FIG. 14 is a diagram showing an example of the arrangement of element bump electrodes in a semiconductor device, in which the source electrode is coupled to a strip-like electrode, and FIG. 15 is a diagram showing the source or emitter side wiring layer in the semiconductor device from the active region to the thermal via. FIG. 16 is a cross-sectional view showing another connection structure from the active region to the thermal via for the source or emitter side wiring layer in the semiconductor device, and FIG. 17 is a source or emitter side wiring layer in the semiconductor device. FIG. 18 is a sectional view showing still another connection structure from the active region to the thermal via. FIG. 18 shows an example of the arrangement of the element bump electrodes in the semiconductor device in which the source electrode is coupled to the belt-like electrode when the wiring board is mounted. It is a permeation | transmission figure which shows the positional relationship of a bump electrode and an active area. Note that the cross-sectional structure that does not overlap with FIGS. 14 to 17 in the present embodiment is the same as FIGS. 3 and 5 to 9.

  In the present embodiment, as shown in FIG. 14, the source electrode 9b in the vicinity of the output stage 17c in the active region for signal amplification is integrated in a band shape, and the corresponding source bump 10b is also linearly formed as a band-shaped bump. It is characterized by arranging in a shape. The cross-sectional structure parallel to the strip-like source bump 10b can adopt a structure as shown in FIG. 15, FIG. 16, or FIG. Further, in the cross-sectional structures of FIGS. 16 and 17 from FIG. 15, the sum of the cross-sectional areas of the interlayer connection vias 15 penetrating the first layer of the substrate insulating layer 16 of the multilayer wiring board 1 becomes larger. The heat dissipation on the wiring board 1 side is improved.

  In the present embodiment, since the source bump 10b has a large band shape, the heat dissipation of the bump in the vicinity of the output stage 17c, which is the main heat generation region, is improved, and the thermal resistance of the semiconductor device can be further reduced. It is.

  FIG. 18 shows the positional relationship between the electrical connection electrodes (9a, 9b, 9c) and the active regions (17a, 17b, 17c) when the semiconductor element 7 of this embodiment and the multilayer wiring board 1 are mounted. As shown in the figure, as seen from above, the active region of the output stage 17c and the range of the strip-like source electrode 9b are arranged in the lower side of the figure (the area of the output stage 17c is the same). Almost overlap on the wide side. In such an arrangement, most of the heat generated in the output stage 17c passes partly through the element insulating layer 20a, but almost directly flows into the source bump 10b, so that the effect of reducing thermal resistance is great. For this reason, in another embodiment of the present invention shown in FIGS. 19 to 22 described later, the cross-sectional area of the source bump 10b, the drain bump, or the gate bump 10a is further enlarged, and therefore this embodiment is arranged. Although lower thermal resistance can be achieved, the effect is limited.

(Embodiment 4)
A semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIG. FIG. 19 is a diagram showing an example of the arrangement of the element bump electrodes in the semiconductor device in which the drain or gate electrode is coupled to the belt-like electrode. In the present embodiment, although the cross-sectional structure is not shown, all cross-sectional structures that can be configured by combinations of cross-sectional views among the structures shown in FIGS. 3 to 18 are included.

  In the present embodiment, as shown in FIG. 19, in the active region for signal amplification, the drain electrode or gate electrode 9a in the vicinity of the output stage 17c is integrated in a band shape, and the corresponding drain bump or gate bump 10a. Is also characterized by a belt-like bump. Since the drain bump or the gate bump 10a has a large band shape, the heat dissipation of the bump in the vicinity of the output stage 17c, which is the main heat generation region, is improved, and the thermal resistance of the semiconductor device can be further reduced.

(Embodiment 5)
A semiconductor device according to a fifth embodiment of the present invention will be described with reference to FIGS. FIG. 20 is a diagram illustrating an example in which the drain or gate electrode and the source electrode are combined with the band-shaped electrode in the arrangement of the element bump electrodes in the semiconductor device, and FIG. FIG. 22 is a diagram illustrating an example in which a drain or gate electrode and a source electrode are coupled to a plurality of strip-shaped electrodes, respectively. FIG. 22 illustrates an arrangement of element bump electrodes in a semiconductor device, in which the drain or gate electrode and the source electrode are the same. It is a figure which shows the example which couple | bonded the electric potential and the thing of the same row shape in strip | belt shape.

  In this embodiment, the source electrode 9b and the drain electrode or the gate electrode 9a form a band-like electrode in the vicinity of the output stage 17c, respectively, and the cross-sectional areas of the drain bump or the gate bump 10a and the source bump 10b are enlarged. As compared with the embodiment shown in FIG. 19, it is possible to reduce the thermal resistance slightly.

(Embodiment 6)
A semiconductor device according to a sixth embodiment of the present invention will be described with reference to FIG. FIG. 23 is a diagram illustrating an example of the arrangement of the element bump electrodes in the semiconductor device in which the emitter electrode is coupled in a band shape with respect to the HBT.

  In the present embodiment, unlike the other embodiments, an electrode is formed when an HBT (Heterojunction Bipolar Transistor) is formed on a GaAs (gallium arsenide) substrate, which is a compound semiconductor, and the HBT element is flip-chip mounted. An example of a layout is shown.

  In FIG. 23, a strip-shaped emitter electrode 9b is formed on the emitter wiring, and the emitter electrode 9b and the multilayer wiring substrate 1 are connected by a strip-shaped emitter bump 10b, so that heat from the heat generating region can be effectively multilayered. It can be transmitted to the wiring board 1 to reduce the thermal resistance.

  In each of the embodiments of the present invention, for example, a square electrode and a lateral electrode in the horizontal direction of FIGS. 4, 10, 14, 18, 19, 20, 21, and 22, respectively. The band-like electrodes are characterized in that the widths in the vertical direction are substantially equal and are arranged in parallel in the horizontal direction in the figure. 4, 10, 14, 18, 19, 20, and 21, there are source electrodes 9 b having the same potential across the columns. Do not combine potential electrodes. When filling the underfill resin, if there is unfilled underfill resin, it may cause defects such as solder flash and water vapor explosion. Therefore, when considering the wraparound of the underfill resin, there are S-shaped or L-shaped bump shapes. In the present invention, by not forming a bump portion having an S-shaped or L-shaped bent portion, the occurrence rate of defects is reduced, and the robustness of the mounting process is reduced. Can be improved.

  Further, in each embodiment of the present invention, as shown in FIG. 24, all the mounted elements on the wiring board and the mounted submodule including the laminated component other than the semiconductor element 7 or the submodule 24 are formed with the same bump. It is also important to mount by the mounting process. Thereby, the cost of the process can be greatly reduced. Needless to say, the mounting element includes a case where a second semiconductor element other than the semiconductor element 7 is mounted.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  INDUSTRIAL APPLICABILITY The present invention can be used for a heat radiation design technique for a high frequency transmission / reception semiconductor device or a power supply semiconductor device mounted on a portable information terminal such as a cellular phone.

It is sectional drawing which shows the mounting structure of the conventional (patent document 1) semiconductor device. It is sectional drawing which shows the mounting structure of the conventional (patent document 2) semiconductor device. It is sectional drawing which shows the mounting structure of the semiconductor device of Embodiment 1 of this invention. It is a figure which shows arrangement | positioning of the element bump electrode in the semiconductor device of Embodiment 1 of this invention. It is sectional drawing which shows the connection structure from the active region in the semiconductor device of Embodiment 1 of this invention to a wiring board. In the mounting structure of the semiconductor device of Embodiment 1 of this invention, it is sectional drawing in the case of forming a thermal via below a wiring board 2nd layer. It is sectional drawing which shows the other connection structure from the active region in the semiconductor device of Embodiment 1 of this invention to a wiring board. It is sectional drawing which shows the further another connection structure from the active region to a wiring board in the semiconductor device of Embodiment 1 of this invention. FIG. 3 is a cross-sectional view showing a connection structure from an active region to a thermal via in the source or emitter side wiring layer in the semiconductor device according to the first embodiment of the present invention. It is a figure which shows the example which arranged the source electrode densely among the arrangement | positioning of the element bump electrode in the semiconductor device of Embodiment 2 of this invention. It is sectional drawing which shows the connection structure from an active region to a thermal via about the source or emitter side wiring layer in the semiconductor device of Embodiment 2 of this invention. It is sectional drawing which shows the other connection structure from an active region to a thermal via about the source or emitter side wiring layer in the semiconductor device of Embodiment 2 of this invention. It is sectional drawing which shows the further another connection structure from an active region to a thermal via about the source or emitter side wiring layer in the semiconductor device of Embodiment 2 of this invention. It is a figure which shows the example which couple | bonded the source electrode with the strip | belt-shaped electrode among arrangement | positioning of the element bump electrode in the semiconductor device of Embodiment 3 of this invention. It is sectional drawing which shows the connection structure from an active region to a thermal via about the source or emitter side wiring layer in the semiconductor device of Embodiment 3 of this invention. It is sectional drawing which shows the other connection structure from an active region to a thermal via about the source or emitter side wiring layer in the semiconductor device of Embodiment 3 of this invention. It is sectional drawing which shows the further another connection structure from an active region to a thermal via about the source or emitter side wiring layer in the semiconductor device of Embodiment 3 of this invention. It is a transmissive | permeability figure which shows the positional relationship of the bump electrode and active area at the time of circuit board mounting about the example which couple | bonded the source electrode with the strip | belt-shaped electrode among the arrangement | positioning of the element bump electrode in the semiconductor device of Embodiment 3 of this invention. . It is a figure which shows the example which couple | bonded the drain or gate electrode with the strip | belt-shaped electrode among arrangement | positioning of the element bump electrode in the semiconductor device of Embodiment 4 of this invention. It is a figure which shows the example which couple | bonded the drain or gate electrode and the source electrode with the strip | belt-shaped electrode among the arrangement | positioning of the element bump electrode in the semiconductor device of Embodiment 5 of this invention. It is a figure which shows the example which combined the drain or gate electrode and the source electrode with the some strip | belt-shaped electrode among the arrangement | positioning of the element bump electrode in the semiconductor device of Embodiment 5 of this invention. It is a figure which shows the example which couple | bonded the drain or gate electrode, and source electrode with the same electric potential and the same column shape in strip | belt shape among the arrangement | positioning of the element bump electrode in the semiconductor device of Embodiment 5 of this invention. It is a figure which shows the example which combined the emitter electrode in strip | belt shape about HBT among arrangement | positioning of the element bump electrode in the semiconductor device of Embodiment 6 of this invention. It is sectional drawing which shows the mounting structure of the semiconductor device of this invention (lamination components other than a semiconductor element or submodule are also mounted).

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Multilayer wiring board, 2 ... Mold resin, 3 ... Bonding wire, 4 ... Joining member, ... 5 Thermal diffusion plate, 6 ... Joining member, 7 ... Semiconductor element, 8 ... Thermal via, 9 ... Electrode for electrical connection, 9a ... Drain or gate electrode or collector or base electrode, 9b ... Source electrode or emitter electrode, 9c ... Control circuit electrode, 10 ... Electric connection bump, 10a ... Drain or gate bump or collector or base bump, 10b ... Source bump or Emitter bump, 10c: Control circuit bump, 11: Insulating layer, 12 ... Heat radiation electrode, 13 ... Heat radiation bump, 14 ... Underfill resin, 15 ... Interlayer connection via, 16 ... Substrate insulation layer, 17 ... Signal amplification Active region, 17a ... first stage, 17b ... second stage, 17c ... output stage, 18 ... active area, 19 ... Child wiring layer, 20, 20a, 20b, 20c ... device insulation layer, 21 ... barrier metal, 22 ... ground electrode, 23 ... substrate wiring layer, 24 ... multilayer part or sub-modules.

Claims (6)

A semiconductor device in which a signal amplification semiconductor circuit and a control circuit for controlling the signal amplification semiconductor circuit are stacked on a wiring board,
The signal amplifying semiconductor circuit has a plurality of amplifying circuits for amplifying signals in a plurality of bands in parallel, and the signal amplifying semiconductor circuit and the control circuit include the control circuit as a plurality of the amplifying circuits. It is formed in parallel on the same semiconductor element by the arrangement in which the amplifier circuit is sandwiched,
The semiconductor element includes a source electrode or an emitter electrode arranged in parallel on the mounting surface side of the wiring board, and a drain electrode or a gate electrode arranged in parallel on the end side with respect to the source electrode or emitter electrode, or a collector electrode or It has a base electrode and is mounted on the wiring board by flip chip connection,
Regarding the arrangement of the bump electrodes for electrically connecting the semiconductor element and the wiring board, the arrangement intervals of the source bump electrodes or the emitter bump electrodes arranged in parallel are the drain bump electrodes or the gate bump electrodes arranged in parallel. Or a mounting structure smaller than the arrangement interval of the collector bump electrode or the base bump electrode,
The source or emitter electrode of the semiconductor element and the ground electrode of the wiring board are electrically connected by the source bump electrode or the emitter bump electrode , and among the wiring layers of the wiring board, the stack of the semiconductor elements The third and lower layers as viewed from the side are connected to the ground electrode on the back surface of the wiring board by a common heat dissipation penetrating electrode ,
The drain electrode or the gate electrode of the semiconductor element, or the collector electrode or the base electrode, and the interlayer connection via of the wiring board disposed outside the through electrode, the drain bump electrode or the gate bump electrode, Alternatively , the semiconductor device is electrically connected by the collector bump electrode or the base bump electrode . The semiconductor device according to claim 1,
The wiring board is a multilayer wiring board formed from a plurality of wiring layers and insulating layers, and through electrodes that electrically connect them, and the first and second layers as viewed from the mounting surface of the semiconductor element A semiconductor device characterized in that the eye is thinner than the third layer and below. A semiconductor device in which a signal amplification semiconductor circuit and a control circuit for controlling the signal amplification semiconductor circuit are stacked on a wiring board,
The signal amplifying semiconductor circuit has a plurality of amplifying circuits for amplifying signals in a plurality of bands in parallel, and the signal amplifying semiconductor circuit and the control circuit include the control circuit as a plurality of the amplifying circuits. It is formed in parallel on the same semiconductor element by the arrangement in which the amplifier circuit is sandwiched,
The semiconductor element includes a source electrode or an emitter electrode arranged in parallel on the mounting surface side of the wiring board, and a drain electrode or a gate electrode arranged in parallel on the end side with respect to the source electrode or emitter electrode, or a collector electrode or It has a base electrode and is mounted on the wiring board by flip chip connection,
Regarding the arrangement of the bump structure for electrically connecting the semiconductor element and the wiring board, at least some of the bumps of the same potential arranged in parallel are connected to each other to form a band-shaped electrode,
The source or emitter electrode of the semiconductor element and the ground electrode of the wiring board are electrically connected by the source bump electrode or the emitter bump electrode , and among the wiring layers of the wiring board, the stack of the semiconductor elements The third and lower layers as viewed from the side are connected to the ground electrode on the back surface of the wiring board by a common heat dissipation penetrating electrode ,
The drain electrode or the gate electrode of the semiconductor element, or the collector electrode or the base electrode, and the interlayer connection via of the wiring board disposed outside the through electrode, the drain bump electrode or the gate bump electrode, Alternatively , the semiconductor device is electrically connected by the collector bump electrode or the base bump electrode . The semiconductor device according to claim 3.
The wiring board is a multilayer wiring board formed from a plurality of wiring layers and insulating layers, and through electrodes that electrically connect them, and the first and second layers as viewed from the mounting surface of the semiconductor element A semiconductor device characterized in that the eye is thinner than the third layer and below. A semiconductor device in which a signal amplification semiconductor circuit and a control circuit for controlling the signal amplification semiconductor circuit are stacked on a wiring board,
The signal amplifying semiconductor circuit has a plurality of amplifying circuits for amplifying signals in a plurality of bands in parallel, and the signal amplifying semiconductor circuit and the control circuit include the control circuit as a plurality of the amplifying circuits. It is formed in parallel on the same semiconductor element by the arrangement in which the amplifier circuit is sandwiched,
The semiconductor element includes a source electrode or an emitter electrode arranged in parallel on the mounting surface side of the wiring board, and a drain electrode or a gate electrode arranged in parallel on the end side with respect to the source electrode or emitter electrode, or a collector electrode or It has a base electrode and is mounted on the wiring board by flip chip connection,
Regarding the arrangement of the bump structure for electrically connecting the semiconductor element and the wiring board, at least some of the bumps of the same potential arranged in parallel are connected to each other to form a band-shaped electrode, and are parallel to the band-shaped electrode. The arrangement of the bumps in the direction is arranged almost linearly,
The source or emitter electrode of the semiconductor element and the ground electrode of the wiring board are electrically connected by the source bump electrode or the emitter bump electrode , and the stack of the semiconductor elements among the wiring layers of the wiring board. The third and lower layers as viewed from the side are connected to the ground electrode on the back surface of the wiring board by a common heat dissipation penetrating electrode ,
The drain electrode or the gate electrode of the semiconductor element, or the collector electrode or the base electrode, and the interlayer connection via of the wiring board disposed outside the through electrode, the drain bump electrode or the gate bump electrode, Alternatively , the semiconductor device is electrically connected by the collector bump electrode or the base bump electrode . The semiconductor device according to claim 5.
The wiring board is a multilayer wiring board formed from a plurality of wiring layers and insulating layers, and through electrodes that electrically connect them, and the first and second layers as viewed from the mounting surface of the semiconductor element A semiconductor device characterized in that the eye is thinner than the third layer and below.

Images