JP2001068587A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a semiconductor device thin, improve the radiation property of the semiconductor device, drop the on-resistance and operate the device at a high speed by installing an insulating sheet, covering the first main face of a semiconductor chip in an area except for a region where a plurality of projecting electrodes are arranged. SOLUTION: An insulating sheet 9 is laid between the element-forming face of a semiconductor chip 10 and the first parts 2A and 3A of a lead 2 and a lead 3. Projecting electrodes are installed between the electrode of the semiconductor chip 10 and the first parts 2A and 3A of the lead 2 and the lead 3, and they are thermally compression-bonded. Thus, a resin path by resin forming becomes unnecessary, and the overall thickness of a package becomes small, by the amount corresponding to the thickness of the resin path. Since the upper faces of the first patterns 2A and 3A and the second parts 2B and 3B as a whole of the leads 2 and 3 are exposed from the insulating sheet 9, radiation property for discharging heat generated from the semiconductor chip 10 outside becomes high. Thus, the semiconductor device can be made thin, radiation property can be improved, and on-resistance can be dropped.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device package technology.

[0002]

2. Description of the Related Art As a semiconductor device, for example, TSSOP is used.
(T hin S hrink S mall O ut-line P ackage) type power transistor surface mount plastic package structure which is referred is known. This TSSOP type power transistor is widely used in a charger for a mobile phone, a video camera, and the like, and a power supply circuit for a personal computer and the like.

A TSSOP power transistor is mainly composed of a semiconductor chip having electrodes formed on an element formation surface and a back surface facing each other, a support for supporting the back surface of the semiconductor chip, and a resin for sealing the semiconductor chip. A sealing body;
It has a configuration having a plurality of leads. Each of the plurality of leads extends inside and outside the resin sealing body, and an internal lead portion (also referred to as an inner lead) located inside the resin sealing body and an external lead located outside the resin sealing body. (Also referred to as an outer lead). Each of the external leads of the plurality of leads is bent and formed into a gull wing type, which is one of the surface mount type lead shapes. Of the plurality of leads, the internal leads of some of the leads are electrically connected to electrodes on the element forming surface of the semiconductor chip via conductive wires, and the internal leads of the other leads are connected to the semiconductor via a support. It is electrically connected to the electrode on the back surface of the chip.

[0004] For the TSSOP type power transistor, for example, Toshiba Review Vol.53 No.11
(1998), pp. 45-47, “2.5V Drive Type III Generation Trench Gate MOSFET”.

[0005]

The present inventors have studied the package (semiconductor package) of a semiconductor device and found the following problems.

(1) As electronic devices become smaller and lighter, semiconductor devices incorporated in these electronic devices have become thinner. Since it is expected that the reduction in size and weight of electronic devices will be promoted in the future, further reduction in the thickness of semiconductor devices is required.

However, in a package structure in which a semiconductor chip is sealed by resin molding (resin molding) like a TSSOP type, when a resin is molded using a molding die, the semiconductor chip is formed on the element forming surface side and the back surface side. A resin passage for flowing resin is required, and the thickness of the entire package is increased by an amount corresponding to the thickness of the resin passage.
Further thinning is difficult.

In a package structure, such as a TSSOP type, in which electrodes and leads on a device forming surface of a semiconductor chip are electrically connected by conductive wires, a loop height of the conductive wire (the device forming surface of the semiconductor chip) is used. The height of the resin on the element molding surface side of the semiconductor chip is increased by an amount corresponding to the height from the top to the top in the vertical direction, so that further thinning is difficult.

(2) Since a large amount of current is handled in a power transistor, a package structure excellent in heat dissipation that radiates heat generated from a semiconductor chip to the outside is desired. However, in a package structure in which the internal leads of the semiconductor chip and the leads are sealed with a resin sealing body, such as the TSSOP type, the internal leads of the semiconductor chip and the leads are covered with a resin having low thermal conductivity. ,
Low heat dissipation for releasing heat generated in the semiconductor chip to the outside.

(3) In a package structure such as a TSSOP type in which electrodes and leads on the element forming surface of a semiconductor chip are electrically connected by conductive wires, a conductive path between the electrodes and the leads of the semiconductor chip is formed. Since the length becomes longer, it becomes a factor that hinders a reduction in on-resistance in a power transistor, and a factor that hinders an increase in speed in a semiconductor device having a semiconductor chip on which a circuit is mounted.

An object of the present invention is to provide a technique capable of reducing the thickness of a semiconductor device.

Another object of the present invention is to provide a technique capable of improving the heat dissipation of a semiconductor device.

Another object of the present invention is to provide a technique capable of reducing the on-resistance of a semiconductor device.

Another object of the present invention is to provide a technique capable of increasing the speed of a semiconductor device.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0016]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1): The first main surface and the second main surface facing each other
A semiconductor chip having a main surface, a first electrode and a second electrode formed on the first main surface, and a third electrode formed on the second main surface; and a semiconductor chip located on the first electrode. One part,
A first lead formed integrally with the first portion and having a second portion located outside the semiconductor chip; a first portion located on the second electrode; and an integral part of the first portion. A second lead formed and having a second portion located outside the semiconductor chip; a first lead between the first portion of the first lead and the first electrode; and a first lead of the second lead.
A plurality of protruding electrodes disposed between the first electrode and the second electrode, and electrically connected to each other, between the first portion of the first lead and the first main surface of the semiconductor chip, and An insulating sheet disposed between a first portion of a second lead and a first main surface of the semiconductor chip, the first sheet being a part of the semiconductor chip other than a region where the plurality of protruding electrodes are disposed.
A semiconductor device having an insulating sheet covering a main surface.

(2) In the semiconductor device according to the means (1), the first electrode is a source electrode, the second electrode is a gate electrode, and the third electrode is a drain electrode. A semiconductor device characterized by the following.

(3) In the semiconductor device according to the means (1), the first electrode is a drain electrode, the second electrode is a gate electrode, and the third electrode is a source electrode. A semiconductor device characterized by the following.

(4) In the semiconductor device according to the means (1), each of the second portions of the first lead and the second lead has its tip end on the second main surface side of the semiconductor chip. A semiconductor device which is bent so as to be positioned.

(5); a first main surface and a second main surface facing each other.
A semiconductor chip having a main surface, a first electrode and a second electrode formed on the first main surface, and a third electrode formed on the second main surface, and having a square planar shape; And the first
A first portion located on the electrode and a second portion formed integrally with the first portion and located outside the first side of the first side and the second side of the semiconductor chip facing each other; Wherein the second portion has a protruding portion protruding outside the semiconductor chip from the first portion, and an intermediate portion bent from the protruding portion toward the second main surface side of the semiconductor chip. A first lead having a mounting portion extending in the same direction as the protruding portion from the intermediate portion; a first portion located on the second electrode; and the semiconductor formed integrally with the first portion and A second lead having a second portion located outside a first side of a chip, wherein the second portion has a protruding portion that protrudes outside the semiconductor chip from the first portion, and a second portion that protrudes from the protruding portion. The second of the semiconductor chips A second lead having an intermediate portion bent to the surface side, a mounting portion extending from the intermediate portion in the same direction as the protruding portion, between a first portion of the first lead and the first electrode, and between the second electrode and the second electrode; A plurality of protruding electrodes arranged between a first part of the lead and the second electrode and electrically connecting each of the first part; a first part of the first lead and a first main surface of the semiconductor chip; And an insulating sheet disposed between the first portion of the second lead and the first main surface of the semiconductor chip, wherein the semiconductor chip is other than a region where the plurality of protruding electrodes are disposed. An insulating sheet covering the first main surface of the first lead, wherein the first lead is formed to have a width wider than the width of the second lead, and a second portion of the first lead is formed from a tip end thereof. One or more slits extending toward the semiconductor chip It is provided a semiconductor device according to claim.

(6); a first main surface and a second main surface facing each other.
A semiconductor chip having a main surface, a first electrode and a second electrode formed on the first main surface, and a third electrode formed on the second main surface; and a semiconductor chip located on the first electrode. One part,
A first lead formed integrally with the first portion and having a second portion located outside the semiconductor chip; a first portion located on the second electrode; and an integral part of the first portion. A second lead formed and having a second portion located outside the semiconductor chip; a first lead between the first portion of the first lead and the first electrode; and a first lead of the second lead.
A plurality of protruding electrodes disposed between the first electrode and the second electrode, and electrically connected to each other, between the first portion of the first lead and the first main surface of the semiconductor chip, and An insulating sheet disposed between a first portion of a second lead and a first main surface of the semiconductor chip, the first sheet being a part of the semiconductor chip other than a region where the plurality of protruding electrodes are disposed.
A method of manufacturing a semiconductor device, comprising: an insulating sheet covering a main surface, wherein a first electrode of the semiconductor chip and a first portion of the first lead and a second electrode of the semiconductor chip are connected to the second electrode. Before the step of electrically connecting each of the leads by thermocompression bonding with the insulating sheet and the protruding electrodes interposed therebetween, the first leads and the second leads are respectively provided. Of the second part by bending and forming the second part
A method of manufacturing a semiconductor device, comprising a step of positioning a tip of a portion on a second main surface side of the semiconductor chip.

(7); a first main surface and a second main surface facing each other.
A main surface, a semiconductor chip having a plurality of electrodes and a circuit formed on the first main surface, a first portion located on the electrode of the semiconductor chip, and integrally formed with the first portion, and A plurality of leads having a second portion located outside the semiconductor chip; and a plurality of protrusions disposed between the first portion of each of the leads and each electrode of the semiconductor chip, and electrically connecting each of the leads. Electrode and the first of each of the leads
An insulating sheet disposed between a portion and a first main surface of the semiconductor chip, the insulating sheet covering a first main surface of the semiconductor chip other than a region where the plurality of protruding electrodes are disposed. And a semiconductor device having:

(8) In the semiconductor device according to the means (7), the second portion of each of the leads is bent such that the tip end is located on the second main surface side of the semiconductor chip. A semiconductor device.

As a result of an investigation of known examples based on the results of the present invention, known examples 1 (Japanese Patent Application Laid-Open No. 10-41694) and a known example 2 (JP-A-10-41694) which describe a technique of connecting a semiconductor chip to a substrate with an insulating film are described. JP-A-11-3909) was found. However, the idea of the publicly known examples 1 and 2 is a technique for directly mounting a chip on a substrate, and does not refer to a technique for connecting the chip to a lead frame. Also,
No mention is made of thinning and heat dissipation of the semiconductor device.

[0026]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

Embodiment 1 In this embodiment, an example in which the present invention is applied to a power transistor which is a semiconductor device will be described. FIG. 1 is a schematic perspective view showing a schematic configuration of a power transistor according to Embodiment 1 of the present invention, FIG. 2 is a schematic cross-sectional view taken along line aa of FIG. 1, and FIG. FIG. 4 is a schematic sectional view taken along line bb, and FIG.
5 and FIG. 6 are a schematic plan view and a schematic bottom view showing a schematic configuration of the semiconductor chip of FIG. 1, and FIG. 7 is a schematic view of FIG. FIG. 8 is a schematic sectional view taken along line d-e of FIG. 5, and FIG. 9 is a schematic plan view showing a plane pattern of the gate conductor layer of FIG. 7. .

As shown in FIGS. 1 to 3, the power transistor 1A of the present embodiment has a configuration mainly including a lead 2, a lead 3, a plurality of protruding electrodes 8, an insulating sheet 9, and a semiconductor chip 10. Has become.

As shown in FIGS. 2 and 3, the semiconductor chip 10 has a source electrode 2 on an element forming surface (first main surface) 10X.
0 and a gate electrode 21, and has a configuration in which a drain electrode 24 is provided on a back surface (second main surface) 10 </ b> Y facing the element forming surface 10 </ b> X. The planar shape of the semiconductor chip 10 is formed in a square shape as shown in FIGS. 5 and 6, and in the present embodiment, is formed in a rectangular shape of, for example, 3.9 [mm] × 2.4 [mm].

As shown in FIG. 7, the semiconductor chip 10
For example, an n + type semiconductor substrate 11A made of single crystal silicon
N- type semiconductor layer 11B made of single crystal silicon on the main surface of
Is mainly composed of the semiconductor substrate 11 on which is formed.
The element forming region of the major surface of the semiconductor substrate 11 (active region), as transistor devices, for example, n-channel conductivity type MOSFET vertical structure (M etal O xide S emicoducto
r F eild E ffect T ransistor) is formed.

The MOSFET mainly has a channel forming region, a gate insulating film 13A, a gate conductor layer 14A, a source region and a drain region. The channel formation region is constituted by a p-type well region 16 formed in the n − type semiconductor layer 11B. The source region includes an n + -type semiconductor region 17 formed in the p-type well region 16. The drain region includes the n− type semiconductor layer 11B and
It is composed of an n + type semiconductor substrate 11A. Gate insulating film 13A is formed along the inner surface of groove 12 extending in the depth direction from the main surface of n − type semiconductor layer 11B, and is formed of, for example, a silicon oxide film. Gate conductor layer 1
4A is embedded in the trench 12 via the gate insulating film 13A, and is formed of, for example, a polycrystalline silicon film into which an impurity for reducing a resistance value is introduced. That is, MOSFE
T is configured as a trench gate type. Trench
A gate type MOSFET is a MOSFET in which a gate conductor layer is formed on a main surface of a semiconductor substrate via a gate insulating film.
Since the occupied area can be reduced as compared with T, it is suitable for miniaturization and low on-resistance of the power transistor.

The element forming region on the main surface of the n − type semiconductor layer 11 B, which is the main surface of the semiconductor substrate 11, is divided into a plurality of island regions by the grooves 12. Each of the plurality of island regions is regularly arranged in a matrix, and the planar shape thereof is formed as a flat octagon. That is, as shown in FIG. 9, the gate conductor layer 14A is formed in a mesh pattern surrounding each of the plurality of island regions divided by the grooves 12. The n + -type semiconductor region 17 as a source region is formed on the main surface of the island region divided by the trench 12.

The n + type semiconductor region 17 and the p type well region 16
Are electrically connected to a source electrode 20 formed thereover through an opening 19 formed in the interlayer insulating film 18, as shown in FIG. The interlayer insulating film 18
It is provided between the gate conductor layer 14A and the source electrode 20, and insulates the gate conductor layer 14A from the source electrode 20. The source electrode 20 is made of, for example, aluminum (A
l) It is formed of a metal film such as a film or an aluminum alloy film. Note that an insulating film 15 is formed between the gate conductor layer 14A and the interlayer insulating film 18.

As shown in FIGS. 8 and 9, the gate conductor layer 14A is formed on the peripheral region (inactive region) of the main surface of the n − -type semiconductor layer 11B through the insulating film 13B. It is integrated with the wiring 14B. Although not shown in detail, the gate lead-out wiring 14B is electrically connected to a gate electrode 21 formed thereon through an opening formed in the interlayer insulating film 18. The gate electrode 21 is formed in the same layer as the source electrode 20, and the source electrode 20,
Each of the gate electrodes 21 is insulated from each other.

As shown in FIGS. 5, 7 and 8, each of the source electrode 20 and the gate electrode 21 is covered with a surface protective film 22 formed thereon. A plurality of bonding openings 23 are formed in the surface protection film 22, and a plurality of protruding electrodes 8 are electrically and mechanically connected to the source electrode 20 and the gate electrode 21 through each of the plurality of bonding openings 23. . The surface protection film 22 is formed of, for example, a silicon oxide film. As the protruding electrode 8, for example, a gold (Au) bump is used, although not limited thereto. The Au bump can be formed by a ball bonding method using an Au wire and using ultrasonic vibration in combination with thermocompression bonding. Au bumps formed by the ball bonding method are firmly connected to the electrodes of the semiconductor chip.

The planar shape of each of the source electrode 20 and the gate electrode 21 is formed in a square shape as shown in FIG. In the present embodiment, the source electrode 20 is, for example, 3.
The gate electrode 21 is formed in a rectangle of 1 [mm] × 2.0 [mm], for example, and is formed in a rectangle of 0.4 [mm] × 0.6 [mm]. On the other hand, the drain electrode 24
As shown in FIG. 6, the semiconductor chip 10 is formed over the entire back surface 10Y. As shown in FIG. 7, the drain electrode 24 is formed on the back surface opposite to the main surface of the n + type semiconductor substrate 11A, and is electrically connected to the n + type semiconductor substrate 11A. The drain electrode 24 is formed of, for example, an Au film.

As shown in FIGS. 1 and 2, the lead 2
A first portion 2A located on the source electrode 20 of the semiconductor chip 10 and an outer side of one of the two long sides 10a formed integrally with the first portion 2A and facing each other of the semiconductor chip 10; And the second portion 2B located at the second position.

The first portion 2A of the lead 2 is
0 is formed in an area larger than the area of the source electrode 20.
It is arranged so as to cover. In the present embodiment, the first portion 2A of the lead 2 is, for example, 3.2 [mm].
It is formed in a size of about × 2.6 [mm].

The first portion 2 A of the lead 2 is electrically and mechanically connected to the source electrode 20 of the semiconductor chip 10 via a plurality of projecting electrodes 8, and furthermore, the insulating sheet 9
Is bonded and fixed to the element forming surface 10X of the semiconductor chip 10 with the interposition of That is, the lead 2 is firmly held on the element forming surface 10 </ b> X of the semiconductor chip 10 by the insulating sheet 9 and the protruding electrode 8.

As shown in FIGS. 1 and 3, the lead 3
It has a first portion 3A located on the gate electrode 21 of the semiconductor chip 10, and a second portion 3B formed integrally with the first portion 3A and located outside one long side 10a of the semiconductor chip 10. It has a configuration.

The first portion 3 A of the lead 3 is
1 and is formed with an area larger than the area of the gate electrode 21.
It is arranged so as to cover. In the present embodiment, the first portion 3A of the lead 3 is, for example, 0.5 [mm].
It is formed in a size of about × 2.6 [mm].

The first portion 3 A of the lead 3 is electrically and mechanically connected to the gate electrode 21 of the semiconductor chip 10 via a plurality of projecting electrodes 8, and furthermore, the insulating sheet 9
Is bonded and fixed to the element forming surface 10X of the semiconductor chip 10 with the interposition of That is, the leads 3 are firmly held on the element forming surface 10 </ b> X of the semiconductor chip 10 by the insulating sheet 9 and the protruding electrodes 8.

The connection between the first portions (2A, 3B) of the leads 2 and 3 and the protruding electrodes 8 formed on the respective electrodes (source electrode 20, gate electrode 21) of the semiconductor chip 10 is heat. It is performed by crimping. The protruding electrode 8 that has been thermocompression-bonded has, for example, a width φ of about 100 [μm] and a height 8h of about 50 [μm]. The thicknesses (2t, 3t) of the leads 2 and 3 are, for example, 0.5 mm.
It is about 15 [mm]. The thickness 10t of the semiconductor chip 10 is, for example, about 0.3 [mm].

As shown in FIGS. 1 to 3, each of the second portions (2B, 3B) of the leads 2 and 3 has a tip (2B4, 3B4) at the back surface 10 of the semiconductor chip 10.
It is bent so as to be located on the Y side. In the present embodiment, each of the second portions (2
B, 3B) are bent and formed into a gull wing type which is one of the surface mount type lead shapes.

The tip portions (2B4, 3B4) of the second portions (2B, 3B) of the leads 2 and 3 are connected to the semiconductor chip 1 in the height direction 10S of the semiconductor chip 10.
0 is arranged at substantially the same height as the back surface 10Y.

The second portion 2B of the lead 2 bent and formed into a gull wing shape has a protruding portion (shoulder portion) 2B1 protruding from the first portion 2A of the lead 2 to the outside of one long side 10a of the semiconductor chip 10. An intermediate portion 2 bent from the projecting portion 2B1 toward the back surface 10Y of the semiconductor chip 10.
B2 and a mounting portion (connection portion) 2B3 extending from the intermediate portion 2B2 in the same direction as the protruding portion 2B1.

The second portion 3B of the lead 3 bent and formed into a gull wing shape includes a protruding portion 3B1 protruding from the first portion 3A of the lead 3 to the outside of one long side 10a of the semiconductor chip 10, and a protruding portion 3B1. And a mounting portion 3B3 extending in the same direction as the protruding portion 3B1 from the intermediate portion 3B2.

The insulating sheet 9 is composed of the leads 2 and 3
Are arranged between the respective first portions (2A, 2B) and the semiconductor chip 10 and cover the element forming surface 10X of the semiconductor chip 10 except for a region where the plurality of protruding electrodes 8 are arranged. As the insulating sheet 9, for example, a resin sheet made of an epoxy-based thermosetting resin containing no conductive particles is used. The upper surface (2A) of the first portion (2A, 3A) of each of the leads 2 and 3
X, 3AX) are exposed from the insulating sheet 9.

As shown in FIG. 1, the lead 2 is provided with a slit 4A extending from the tip 2B4 of the second portion 2B toward the semiconductor chip 10. In the present embodiment, two slits 4A are provided, and the second portion 2B
From the tip 2B4 to the protruding portion 2B1.

As shown in FIGS. 1 and 4, the width 2W of the lead 2 is wider than the width 3W of the lead 3 in order to reduce on-resistance. In this embodiment, the width 2W of the lead 2 is formed, for example, at about 3.2 [mm], and the width 3W of the lead 3 is formed, for example, at about 0.5 [mm].

The first portion 2A of the lead 2 slightly protrudes outside one short side 10c and outside the other long side 10b of the two opposing short sides of the semiconductor chip 10 (FIG. 1). 2 and FIG. 4). The first portion 3A of the lead 3 slightly protrudes outside the other short side 10d and outside the other long side 10b of the semiconductor chip 10 (see FIGS. 3 and 4). The insulating sheet 9 slightly protrudes outside each side (10a, 10b, 10c, 10d) of the semiconductor chip 10.

Incidentally, in the surface mount type package, it is necessary to protect the semiconductor chip from the environment and to firmly hold the leads. In a conventional package structure in which a semiconductor chip is protected and leads are held by resin molding (resin molding), like a TSSOP type, when resin molding is performed using a molding die, an element forming surface side and a rear surface side of the semiconductor chip are formed. Since a resin passage for flowing resin is required, the thickness of the entire package is increased by an amount corresponding to the thickness of the resin passage.

On the other hand, in the power transistor 1A of the present embodiment, the semiconductor chip 10 is
X is protected by an insulating sheet 9 covering the X, and the leads 2 and 3 are
Is held on the element forming surface 10X. Insulating sheet 9
The protection of the semiconductor chip 10 and the holding of the leads (2, 3) will be described later in detail, but the element forming surface 10X of the semiconductor chip 10 and the first portions (2A, 3A) of the leads 2 and 3 respectively. An insulating sheet 9 is interposed between the first and second portions (2, 3) of the electrodes (source electrode 20, gate electrode 21) of the semiconductor chip 10 and the leads 2 and 3 respectively.
A, 3A) is performed by thermocompression bonding with a protruding electrode 8 interposed therebetween, so that a resin path necessary in a conventional package for protecting a semiconductor chip and holding leads by resin molding is unnecessary. . Therefore, the thickness of the entire package is reduced by an amount corresponding to the thickness of the resin passage. Further, since the electrical connection between the electrodes (source electrode 20, gate electrode 21) of the semiconductor chip 10 and the first portions (2A, 3A) of the leads 2 and 3 is made by the protruding electrodes 8, The thickness of the entire package is reduced as compared with the case where conductive wires are used.

In a conventional package structure such as a TSSOP type in which the internal leads of a semiconductor chip and leads are sealed with a resin sealing body, the internal leads of the semiconductor chip and leads are covered with a resin having low thermal conductivity. Because
Low heat dissipation for releasing heat generated in the semiconductor chip to the outside.

On the other hand, in the power transistor 1A of the present embodiment, the side surface and the back surface 10
Y, the upper surface (2X, 3AX) and the entire second portion (2B, 3B) of the first portion (2A, 3A) of the lead (2, 3) are exposed from the insulating sheet 9 and are generated from the semiconductor chip 10. High heat dissipation to release heat to the outside.

In a conventional package structure, such as a TSSOP type, in which electrodes on the element forming surface of a semiconductor chip and leads are electrically connected by conductive wires, a conductive path between the electrodes and leads of the semiconductor chip is long. Therefore, in a power transistor, it becomes a factor that hinders a reduction in on-resistance.

On the other hand, in the power transistor 1A of the present embodiment, the electrode (source electrode 2) of the semiconductor chip 10 is used.
0, the gate electrode 21) and the first portions (2A, 3A) of the leads 2 and 3 are electrically connected by the protruding electrodes 8, so that the electrodes (source electrodes 20, (Gate electrode 21) and lead (2, 2)
3) the conductive path becomes shorter. Therefore, the ON resistance of the power transistor 1A decreases.

Next, a lead frame used for manufacturing the power transistor 1A will be described with reference to FIG. FIG. 10 is a schematic plan view showing a schematic configuration of the lead frame.

As shown in FIG. 10, the lead frame LF
Has a configuration in which a plurality of lead arrangement areas 6 defined by a frame body 5 are arranged in a matrix. Leads 2 and 3 are arranged in each lead arrangement area 6.
Each of the leads 2 and 3 is formed integrally with the frame main body 5, and the respective second portions (2 </ b> B, 3 </ b> B) are connected to the frame main body 5. The lead 2 is provided with two slits (4A).

The lead frame LF is made of, for example, copper (Cu).
Is formed by etching or pressing a metal plate made of Cu or a metal plate made of a Cu-based alloy material to form a predetermined lead pattern. Cu or Cu
The alloy material of the type has better conductivity and thermal conductivity than the alloy material of the iron (Fe) -nickel (Ni) type used as the material of the lead frame.

Next, a method of manufacturing the power transistor 1A will be described with reference to FIGS. FIG.
14 to 14 are schematic cross-sectional views for describing a method for manufacturing a power transistor. 11 to 14, the leads 3 are not shown.

First, the semiconductor chip 1 shown in FIGS.
0 and a lead frame LF shown in FIG. 10 are prepared. On the source electrode 20 and the gate electrode 21 of the semiconductor chip 10
A plurality of protruding electrodes 8 are formed thereon. It is desirable to form the protruding electrodes 8 before dividing the semiconductor wafer into individual semiconductor chips, that is, at the stage of the semiconductor wafer. The reason for this is that after the semiconductor wafer is divided into individual semiconductor chips, the processing unit expands several hundred times compared to the wafer state, so that the processing becomes complicated, and quality and cost are affected. The area of the planar shape of the semiconductor chip is 1
0 [mm ² ] or less, the processing becomes complicated, and the quality and
Affects cost. Protruding electrode 8 before thermocompression bonding
Is about 60 [μm].

Next, as shown in FIG. 11, an insulating sheet 9 is attached to the first portion 2A of the lead 2 and the first portion 3A of the lead 3. As the insulating sheet 9, for example, a resin sheet made of an epoxy-based thermosetting resin containing no conductive particles is used. It is desirable that the insulating sheet 9 has a plane size equal to or slightly larger than the plane size of the semiconductor chip. The reason is that even if the displacement of the insulating sheet 9 and the displacement of the semiconductor chip 10 occur, a short circuit with the leads (2, 3) on the periphery of the semiconductor chip 10 can be suppressed. In this embodiment, the insulating sheet 9 of 4.0 [mm] × 2.5 [mm] is used. The insulating sheet 9 is provided with the protruding electrodes 8.
It is desirable to use a material having a height equal to or slightly thicker than the height. The reason is that the electrode (2
0,21) and the first portion (2A, 3) of the lead (2,3).
Since the tip of the protruding electrode 8 is crushed during the bonding step of electrically connecting the semiconductor chip A), if it is too thick, the amount protruding from the semiconductor chip 10 increases, which causes a poor appearance. Conversely, if the thickness is too thin, the fixing strength of the lead (2, 3) by the insulating sheet 9 decreases, and the lead (2, 3)
This may cause a problem such as peeling. In the present embodiment, since the height of the protruding electrode 8 is about 60 [μm], the insulating sheet 9 having a thickness of about 60 [μm] is used.

Next, the lead frame LF is mounted on the heat stage 30, and thereafter, the semiconductor chip 10 is positioned and arranged on the first portions (2A, 3A) of the leads 2 and 3, respectively. At this time, the semiconductor chip 10 is arranged in a state where the element formation surface 10X faces the first portions (2A, 3A) of the leads 2 and 3 respectively.

Next, as shown in FIG. 12, while the heat stage 30 is heated to about 200 ° C., pressure is applied from the back surface 10 Y side of the semiconductor chip 10 by the bonding tool 31. Pressing by the bonding tool 31 is performed with a force of 50 to 500 [g] per one protruding electrode. At this time, the insulating sheet 9 is once melted by heat from the heat stage 30 and then hardened. On the other hand, the protruding electrode 8
Is in contact with the first portion (2A, 3A) of each of the leads 2 and 3 without sandwiching the melted insulating sheet 9, and the leading end is crushed to obtain a favorable condition. A joint is made.

In this step, the element forming surface 10X of the semiconductor chip 10 is covered with the insulating sheet 8 except for the region where the plurality of protruding electrodes 8 are arranged. The first portions (2A, 3A) of the leads 2 and 3 are bonded and fixed to the element forming surface 10X of the semiconductor chip 10 with an insulating sheet 9. That is, the element forming surface 10X of the semiconductor chip 10
Are protected by the insulating sheet 9, and the leads 2 and 3 are firmly held on the semiconductor chip 10 by the insulating sheet 9.

Next, the insulating sheet 8 is baked.
To cure. The baking treatment is performed in an atmosphere at a temperature of about 180 ° C. for about 30 minutes.

Next, the leads 2 and 3 are cut from the frame main body 5 of the lead frame LF, and then the second portions (2B, 3B) of the leads 2 and 3 are bent and formed into a gull-wing type. In the bending, first, as shown in FIG. 13, the protruding portions (2B1, 3B) of the second portions (2B, 3B) of the leads 2 and 3 respectively.
1) is clamped by the lead holding member 32A and the projection of the bending table 32B, and then the bending punch 3 is attached to the mounting portions (2B3, 3B3) of the second portions of the leads 2 and 3 respectively.
3 and then, as shown in FIG.
This is performed by obliquely moving the bending punch 33 toward the protrusion 2B.

In this step, the width 2W of the lead 2 is
The width of the lead 3 is wider than 3 W in order to reduce the on-resistance. For this reason, the lead 2 is more difficult to bend and form than the lead 3. However, the second portion 2B of the lead 2 has two slits extending from the tip 2B4 to the protruding portion 2B1 toward the semiconductor chip 10. 4A
Is provided, it is possible to reduce the difficulty of bending and forming.

Thereafter, by performing a cutting process for aligning the tip positions of the second portions (2B, 3B) of the leads 2 and 3, the power transistor 1A of the present embodiment is almost completed.

The power transistor 1A thus configured is mounted on a mounting board 35 as shown in FIG. 15 (a schematic cross-sectional view showing a state of being mounted on the mounting board). The mounting portions (2B3, 3B3) of the leads (2, 3) are electrically connected to the lead connection terminals (part of the wiring) 36 of the mounting board 35 by a conductive adhesive (for example, a conductive material having a Pb-Sn composition) 38. And mechanically connected. The drain electrode 24 on the back surface 10Y of the semiconductor chip 10 is
Is electrically and mechanically connected to the chip connection terminal (part of wiring) 37 by an adhesive 38.

The mounting of the power transistor 1A is not limited to this. For example, a paste-like adhesive is formed on the lead connection terminals 36 and the chip connection terminals 37 of the mounting board 35, and then the lead connection is formed. The mounting portions (2B3, 3B3) of the leads (2, 3) with an adhesive material interposed on the terminals 36
3B3), and the drain electrode 24 on the back surface 10Y of the semiconductor chip 10 is disposed on the chip connecting terminal 37 with an adhesive interposed therebetween. Thereafter, the mounting substrate 35 is transported to an infrared reflow furnace, and then the bonding is performed. The material is melted and cured. As a result, the power transistor 1A is mounted on the mounting board 35.

In the mounting process of the power transistor 1A, the second portion (2B, 3B) of the lead (2, 3)
Is bent and formed into a gull wing type which is one of the surface mount type lead shapes. Therefore, the stress generated due to thermal expansion when mounting the power transistor 1A on the mounting board 35 is transferred to the second portion (2B, 3) of the lead (2, 3).
It can be alleviated by the elastic deformation of B). Also,
Stress generated due to the warpage of the mounting board 35 after mounting can also be reduced.

The power transistor 1 of the present embodiment
A is configured such that the drain electrode 24 on the back surface 10Y of the semiconductor chip is joined to the chip connection terminal 37 of the mounting substrate 35 with an adhesive 38 interposed therebetween. Therefore, as shown in FIG. 16 and FIG. 17 (schematic sectional views for explaining the tip positions of the leads), the second
The tip (2B4, 3B4) of the portion (2B, 3B) is located at the tip (2B, 3B4) in the thickness direction 10S of the semiconductor chip 10.
B4, 3B4) are higher than the semiconductor chip back surface 10Y, and the top ends (2B4, 3B) are higher than the semiconductor chip back surface 10Y.
4) It is desirable that the lower edges (2B4Y, 3B4Y) are arranged at a height lower than the semiconductor chip back surface 10Y.

As described above, according to the present embodiment, the following effects can be obtained.

[1] The power transistor 1A includes a semiconductor chip 10 having a source electrode 20 and a gate electrode 21 formed on the element formation surface 10X, and a drain electrode 24 formed on the back surface 10Y. A lead 2 having a first portion 2A located therein, a second portion 2B formed integrally with the first portion 2A and located outside one long side 10a of the semiconductor chip 10, and a gate electrode 21.
A lead 3 having an upper first portion 3A, a second portion formed integrally with the first portion 3A and located outside one long side 10a of the semiconductor chip 10;
A plurality of protruding electrodes 8 disposed between the first portion 2A of the lead 2 and the source electrode 20 and between the first portion 3A of the lead 3 and the gate electrode 21, and electrically connected to each other; First portion 2A and element forming surface 10 of semiconductor chip 10
X and the first portion 3A of the lead 3 and the semiconductor chip 1
And an insulating sheet 9 disposed between the device forming surface 10X and the element forming surface 10X of the semiconductor chip 10 other than the region where the plurality of protruding electrodes 8 are disposed. It has become.

With such a configuration, a resin passage for flowing resin on the element forming surface 10X side and the back surface 10Y side of the semiconductor chip 10 is not required, so that the entire package corresponds to the thickness of the resin passage. Becomes thinner.
Also, since the electrodes (source electrode 20, gate electrode 21) of the semiconductor chip 10 and the first portions (2A, 3A) of the leads 2 and 3 are electrically connected by the protruding electrodes 8, The thickness of the entire package is reduced as compared with the case where conductive wires are used. As a result, the thickness of the power transistor 1A can be reduced.

The side and back surfaces 1 of the semiconductor chip 10
0Y, the upper surface (2X, 3AX) and the entire second portion (2B, 3B) of the first portion (2A, 3A) of the lead (2, 3) are exposed from the insulating sheet 9 and are generated from the semiconductor chip 10. It is possible to improve the heat radiation property of releasing heat to the outside.

Further, the electrical connection between the electrodes (source electrode 20, gate electrode 21) of the semiconductor chip 10 and the first portions (2A, 3A) of the leads 2 and 3 is made by the protruding electrodes 8. Therefore, the electrodes (source electrode 20, gate electrode 21) of the semiconductor chip 10 and the leads (2,
3) the conductive path becomes shorter. As a result, the on-resistance of the power transistor 1A can be reduced.

[2] The width 2W of the lead 2 is equal to the width 3 of the lead 3.
The lead 2 is formed with a width wider than W, and the lead 2 is provided with two slits 4A extending from the tip 2B4 of the second portion 2B to the protruding portion 2B1 toward the semiconductor chip 10.

With such a configuration, the width of the lead 2 is set to 2 W to reduce on-resistance and improve heat dissipation.
Even if the width is widened, the difficulty in bending and forming the second portion 2B of the lead 2 can be reduced, so that the productivity in the lead bending step can be increased.

[3] Second of Lead 2 and Lead 3
The portions (2B, 3B) are bent and formed into a gull wing type. With such a configuration, the stress generated due to thermal expansion when mounting the power transistor 1A on the mounting board 35 is reduced by the second portion (2) of the lead (2, 3).
B, 3B) can be alleviated by the elastic deformation, and the stress generated due to the warpage of the mounting board 35 after mounting can also be alleviated. The damage of the electrode 8 can be suppressed. As a result, the reliability of mounting the power transistor 1A can be improved.

In particular, since a mounting board incorporated in a small electronic device such as a mobile phone, a portable information processing terminal device, or a portable personal computer has a small thickness and is easily warped, the stress caused by the warping of the mounting substrate is reduced by the elasticity of the lead. It is important to relax by deformation.

In this embodiment, the lead (2, 3)
After the semiconductor chip 10 is attached to the lead (2,
Although the example in which the second portion (2B, 3B) of 3) is formed by bending is described, as shown in FIG. 18 (schematic sectional view), before attaching the semiconductor chip 10 to the leads (2, 3). , The second portion (2B, 3) of the lead (2, 3)
B) may be carried out. In this case, breakage or the like of the semiconductor chip 10 generated in the bending step can be substantially eliminated, so that the yield of the power transistor 1A can be improved.

In this embodiment, the leads (2, 3)
Although the example which attached the insulating sheet 9 to the above was explained,
The insulating sheet 9 may be attached to the semiconductor chip 10.

In this embodiment, two slits 4
Although an example in which A is provided has been described, one or more than three may be provided. However, the number of slits 4A is
It must be determined in consideration of the on-resistance, the thermal resistance, the difficulty of bending and the like.

In this embodiment, an example in which an Au bump is used as the protruding electrode 8 has been described. However, another material (for example, a solder material) may be used, or another method (for example, an evaporation method, Ball forming method).

In the present embodiment, an example is described in which a resin sheet made of an epoxy-based thermosetting resin containing no conductive particles is used as the insulating sheet 9. A material made of a material (for example, a polyimide-based thermoplastic resin) may be used.

(Embodiment 2) FIG. 19 is a schematic perspective view showing a schematic configuration of a power transistor according to Embodiment 2 of the present invention. As shown in FIG. 19, the power transistor 1B of the present embodiment has basically the same configuration as that of the above-described first embodiment, but differs in the following configuration.

That is, the two slits 4A provided in the lead 2 are connected to the first end 2B4 of the lead 2 by the first slit 2A.
It extends to the portion 2A. With such a configuration, the lead 2 is formed on the element forming surface 10X of the semiconductor chip 10.
When the first portion 2A is attached by thermocompression bonding, the trapped air and gas generated from the insulating sheet 9 can easily escape, so that the generation of voids can be suppressed. However, heat radiation is lower than in the case of the first embodiment.

(Embodiment 3) FIG. 20 is a schematic perspective view showing a schematic configuration of a power transistor according to Embodiment 3 of the present invention. As shown in FIG. 20, the power transistor 1C of the present embodiment has basically the same configuration as that of the above-described first embodiment, but differs in the following configuration.

That is, the lead 2 is not provided with the slit 4A. With this configuration, the contact area between the lead 2 and the outside air increases, and the electrical resistance from the first portion 2A of the lead 2 to the mounting portion 2B3 of the second portion 2B decreases. Compared with the first and second embodiments, it is possible to further improve heat dissipation and lower on-resistance. However, since the rigidity of the second portion 2B of the lead 2 is increased, the difficulty of bending and forming the lead 2 is increased. Further, stress absorption due to the elastic deformation of the lead 2 is reduced.

(Embodiment 4) FIG. 21 is a schematic perspective view showing a schematic configuration of a power transistor according to Embodiment 4 of the present invention. As shown in FIG. 21, the power transistor 1D of the present embodiment has basically the same configuration as that of the above-described first embodiment, but differs in the following configuration.

That is, the two slits 4A provided in the lead 2 extend from the tip 2B4 of the second portion 2A of the lead 2 to the intermediate portion 2B2. With such a configuration, heat dissipation and on-resistance similar to those in the above-described third embodiment can be obtained, and bending of the lead 2 can be performed with the same level of difficulty as in the first and second embodiments. Stress can be absorbed by molding and elastic deformation of the lead 2.

(Embodiment 5) FIG. 22 is a schematic perspective view showing a schematic configuration of a power transistor according to Embodiment 5 of the present invention. As shown in FIG. 22, the power transistor 1E according to the present embodiment has basically the same configuration as that of the above-described first embodiment, but differs in the following configuration.

That is, the lead 2 is composed of the first portion 2A and the second portion 2A.
It has a portion 2B, and further has a third portion 2C formed integrally with the first portion 2A and located outside the other long side 10b of the semiconductor chip 10. Similarly to the second portion 2B, the third portion 2C of the lead 2 includes a protruding portion 2C1 protruding from the first portion 2A to the outside of the other long side 10b of the semiconductor chip 10, and a protruding portion 2C1 of the semiconductor chip 10 from the protruding portion 2C1. The intermediate portion 2C2 is bent toward the rear surface 10Y, and the mounting portion 2C3 extends from the intermediate portion 2C2 in the same direction as the protruding portion 2C1.

The lead 3 has a first portion 3A and a second portion 3A.
It has a portion 3B, and further has a third portion 3C formed integrally with the first portion 3A and located outside the other long side 10b of the semiconductor chip 10. Similarly to the second portion 3B, the third portion 3C of the lead 3 includes a protruding portion 3C1 protruding from the first portion 3A to the outside of the other long side 10b of the semiconductor chip 10, and a protruding portion 3C1 of the semiconductor chip 10 from the protruding portion 3C1. The intermediate portion 3C2 is bent toward the back surface 10Y, and the mounting portion 3C3 extends from the intermediate portion 3C2 in the same direction as the protruding portion 3C1.

The third portion 2C of the lead 2 has the second portion 2
Similarly to B, two slits 4B are provided extending from the tip 2C4 of the third portion 2C to the protruding portion 2C1 toward the semiconductor chip 10.

With this configuration, the contact area between the leads 2 and 3 and the outside air increases, and
Since the bonding area between the lead 2 and the lead 3 and the mounting substrate increases, the heat radiation is improved as compared with the case of the first embodiment. Further, since the conductive path from the lead 2 to the mounting board is doubled as compared with the case of the first embodiment, a lower on-resistance can be achieved as compared with the case of the first embodiment. However, the occupied area of the power transistor increases. The reference numeral 3C4 shown in the figure is the tip of the third portion 3C of the lead 3.

(Embodiment 6) FIG. 23 is a diagram showing a schematic configuration of a power transistor according to Embodiment 6 of the present invention ((A) is a schematic plan view, and (B) is a line ff in (A)). FIG. As shown in FIG. 23, the power transistor 1F of the present embodiment has basically the same configuration as that of the above-described fifth embodiment, but differs in the following configuration.

That is, the lead 2 has a first portion 2A, a second portion 2B, and a third portion 2C. Further, the lead 2 is formed integrally with the first portion 2A and has two short sides facing each other of the semiconductor chip 10. One short side 1 of the sides (10c, 10d)
It is configured to have a fourth portion 2D located outside of 0c.

The lead 3 has a first portion 3A, a second portion 3B, and a third portion 3C. The lead 3 is formed integrally with the first portion 3A.
It is configured to have a fourth portion 3D located outside 0d.

With such a configuration, the contact area between the lead 2 and the lead 3 and the outside air increases by an amount corresponding to the area of the fourth portion (2D, 3D) of each of the lead 2 and the lead 3. The heat radiation is improved as compared with the case of the fifth embodiment. However, the occupied area of the power transistor is larger than that of the fifth embodiment.

The fourth and fourth leads 2 and 3
The portions (2D, 3D) may be bent and formed into a gull wing type. In this case, the bonding area between the lead 2 and the lead 3 and the mounting substrate increases, so that the heat radiation property and the on-resistance can be further reduced as compared with the sixth embodiment.

(Embodiment 7) FIG. 24 is a diagram showing a schematic configuration of a power transistor according to Embodiment 7 of the present invention ((A) is a schematic plan view, and (B) is a gg line of (A)). FIG. As shown in FIG. 24, the power transistor 1G of the present embodiment has basically the same configuration as that of the above-described first embodiment, but differs in the following configuration.

That is, the heat diffusion plate 36 is adhered and fixed to the back surface 10Y of the semiconductor chip 10 via the adhesive 35.
With such a configuration, the back surface 10Y of the semiconductor chip 10 can be protected, so that damage to the semiconductor chip 10 can be suppressed. Further, since the heat generated in the semiconductor chip 10 is diffused by the heat diffusion plate 36, the heat dissipation of the power transistor is improved.

Note that the power transistor 1 of the present embodiment
G has a configuration in which the heat diffusion plate 36 is joined to the chip connection terminals of the mounting board with an adhesive interposed therebetween. Therefore,
As shown in FIG. 25 (a schematic cross-sectional view for explaining the position of the tip of the lead), the second
The tip (2B4, 3B4) of the portion (2B, 3B) is located at the tip (2B, 3B4) in the thickness direction 10S of the semiconductor chip 10.
B4, 3B4) are higher than the back surface 36Y of the heat diffusion plate 36 at the top edge (2B4X, 3B4X),
B4) the lower edge portion (2B4Y, 3B4Y)
Is desirably arranged at a height that is lower than the back surface 36Y.

The heat diffusion plate 36 may be attached in the mounting process. In such a case, in consideration of the thickness of the attached heat diffusion plate 36 and the thickness of the adhesive, FIG.
6 (Schematic sectional view for explaining the position of the tip of the lead)
As shown in FIG. 5, the tip portions (2B4, 3B4) of the second portions (2B, 3B) of the leads 2 and 3 are located on the semiconductor chip 1 in the thickness direction 10S of the semiconductor chip 10.
It is necessary to bend the leads 2 and 3 so as to be located at a height lower than the back surface 10Y of the “0”.

(Eighth Embodiment) FIGS. 27A and 27B are diagrams showing a schematic configuration of a power transistor according to an eighth embodiment of the present invention. FIG. 27A is a schematic plan view, and FIG. 28 is a schematic plan view showing a schematic configuration of the semiconductor chip of FIG. 27, FIG. 29 is a schematic plan view showing a wiring pattern of the semiconductor chip of FIG. 27, FIG. 30 is a schematic sectional view taken along line ii of FIG.

As shown in FIG. 27, the power transistor 1I of this embodiment has basically the same configuration as that of the above-described first embodiment, but differs in the following configuration.

That is, the semiconductor chip 40 has the drain electrode 52 and the gate electrode 53 on the element formation surface (first main surface) 40X, and has the source electrode on the back surface (second main surface) 40Y facing the element formation surface 40X. 56.

The first portion 2 A of the lead 2 is located on the drain electrode 52 of the semiconductor chip 40 and is electrically connected to the drain electrode 52 via a plurality of protruding electrodes 8. The first portion 3A of the lead 3 is located on the gate electrode 53 of the semiconductor chip 40, and is electrically connected to the gate electrode 53 via a plurality of projecting electrodes 8.

As shown in FIG. 30, the semiconductor chip 40 is made of, for example, a p + type semiconductor substrate 4 made of single crystal silicon.
P-type semiconductor layer 4 of single crystal silicon on main surface of 1A
It is mainly composed of a semiconductor substrate 41 on which 1B is formed. Element formation region (active region) on the main surface of semiconductor substrate 41
Is formed with, for example, an n-channel conductivity type MOSFET having a lateral structure as a transistor element.

The MOSFET mainly has a channel formation region, a gate insulating film 45, a gate conductor layer 46, a source region and a drain region. The channel formation region includes a p-type well region 43 formed in the p − -type semiconductor layer 41B. The drain region is formed in the p-type semiconductor layer 41B and the n-type semiconductor region 47A formed in the p-type well region 43 and the p-type semiconductor layer 41B,
And an n + type semiconductor region 48A electrically connected to the n− type semiconductor region 47A. The source region is p
N− type semiconductor region 47B formed in type well region 43
And an n + -type semiconductor region 48B formed in the p-type well region 43 and electrically connected to the n − -type semiconductor region 47B. The gate conductor layer 46 is formed of, for example, a polycrystalline silicon film into which an impurity for reducing a resistance value is introduced. The gate insulating film 45 is formed of, for example, a silicon oxide film.

A plurality of gate conductor layers 46 extend in the X direction and are arranged at predetermined intervals in the Y direction.
n- type semiconductor region 47A and n + type semiconductor region 48A;
The type semiconductor region 47B and the n + type semiconductor region 48B are arranged so as to sandwich the channel forming region below the gate conductor layer 46, and extend in the X direction similarly to the gate conductor layer 46.

Each of the n + type semiconductor regions 48A and 48B has
Through an opening formed in the interlayer insulating film 49, it is electrically connected to each of the wirings 50A and 50C formed in the first metal layer. The wiring 50C is electrically connected to the p + type semiconductor region 44 formed in the p − type semiconductor layer 41B through an opening formed in the interlayer insulating film 49. The p + type semiconductor region 44 is electrically connected to the p + type semiconductor substrate 41A, and the p + type semiconductor substrate 41A is electrically connected to the source electrode 56 formed on the back surface. Although not shown in detail, the gate conductor layer 46 is electrically connected to a wiring 50B formed in the first metal layer through an opening formed in the interlayer insulating film 49.

Each of wirings 50A and 50B is electrically connected to a drain electrode 52 and a gate electrode 53 formed in the second metal layer through an opening formed in interlayer insulating film 51. . As shown in FIGS. 28 and 30, each of the drain electrode 52 and the gate electrode 53 is covered with a surface protection film 54 formed thereon. A plurality of bonding openings 55 are formed in the surface protection film 54, and a plurality of projecting electrodes 8 are electrically and mechanically connected to the drain electrode 52 and the gate electrode 53 through each of the plurality of bonding openings 55.

Each of the wirings 50A, 50B, 50C is formed by the wiring pattern shown in FIG. In FIG. 30, reference numeral 42 denotes a field insulating film.

In the power transistor 1I thus configured, the same effect as in the first embodiment can be obtained.

(Embodiment 9) In this embodiment, an example in which the present invention is applied to a wideband video amplifier which is a semiconductor device will be described. FIG. 31 is a diagram showing a schematic configuration of a wideband video amplifier according to a ninth embodiment of the present invention ((A) is a schematic plan view, (B) is a schematic cross-sectional view taken along line JJ of (A), (C) is a schematic cross-sectional view taken along the line kk of (A), FIG. 32 is an equivalent circuit diagram of the wideband video amplifier of FIG. 31, and FIG. 33 is a substrate on which the wideband video amplifier of FIG. 31 is mounted. FIG. 3 is a schematic cross-sectional view showing a state in which the device is mounted on the device.

As shown in FIG. 31, the broadband video amplifier 60A of this embodiment mainly includes a plurality of leads 61, one lead 62, a plurality of protruding electrodes 8, an insulating sheet 9, and a semiconductor chip 70. It has a configuration.

The planar shape of the semiconductor chip 70 is formed in a square shape, and in this embodiment, is formed in a rectangular shape. The semiconductor chip 70 mainly includes a semiconductor substrate, a multilayer wiring layer in which a plurality of insulating layers and wiring layers are stacked on a main surface of the semiconductor substrate, and a surface formed so as to cover the multilayer wiring layer. And a protective film.

The circuit forming surface 70X, which is the surface of the front and back surfaces (the first main surface and the second main surface) of the semiconductor chip 70 facing each other, is provided along the outer periphery of the semiconductor chip 70 along a plurality of sides. An electrode 71 is formed. Each of the plurality of electrodes 71 is formed on the uppermost wiring layer of the multilayer wiring layers of the semiconductor chip 70. The uppermost wiring layer is covered with a surface protective film formed thereon, and a bonding opening exposing the surface of the electrode 71 is formed in the surface protective film.

The amplifier circuit shown in FIG. 32 is formed on the circuit forming surface 70X of the semiconductor chip 70. The amplifier circuit mainly includes a plurality of bipolar transistors Tr1 to Tr
13, a plurality of resistance elements R1 to R5 and the like.
In FIG. 32, among the plurality of electrodes 71, 71A
Is a power supply potential terminal fixed at a power supply potential (for example, 5 [V]), 71B is a reference potential terminal fixed at a reference potential (eg, 0 [V]), and 71C and 71D are signal input terminals. 71E is an intermediate potential terminal fixed at an intermediate potential, 71F is an output stage power supply potential terminal, 71G and 71H are current output terminals, 71I is a control signal input terminal, and 71J is an intermediate potential terminal. This is an intermediate potential terminal that is fixed at a potential. A plurality of electrodes 71B are provided.

As shown in FIG. 31, a plurality of leads 61 are arranged along two long sides (70a, 70b) of the semiconductor chip 70 along the long sides facing each other. The leads 61 arranged on one long side 70a side of the semiconductor chip 70 and the other long side 70b of the semiconductor chip 70
Between the leads 61 arranged on the side of the semiconductor chip 7
The lead 62 extends so as to cross two short sides (70c, 70b) opposing each other.

The plurality of leads 61 are formed integrally with the first portion 61A located on the electrode 71 of the semiconductor chip 70, and are formed integrally with the first portion, and one of the long sides (70a or 70b) of the semiconductor chip 70 is provided. The second part 61 located outside the
B. The lead 62 includes a first portion 62A located on the electrode 71 of the semiconductor chip 70,
The semiconductor chip 7 formed integrally with the first portion 62A
0 of the second portion 62B located outside one long side 70c
And a third portion 6 formed integrally with the first portion 62A and located outside the other long side 70d of the semiconductor chip 70.
2C.

The first portion 61 A of the lead 61 is electrically and mechanically connected to the electrode 71 of the semiconductor chip 70 via the protruding electrode 8, and further, via the insulating sheet 9. Is bonded and fixed to the circuit forming surface 70X. The first portion 62A of the lead 62 is
Are electrically and mechanically connected to the electrodes 71 of the semiconductor chip 70 with the interposition thereof, and are further adhesively fixed to the circuit forming surface 70X of the semiconductor chip 70 with the insulating sheet 9 interposed. That is, the first portions (61A, 62A) of the leads 61 and 62 are held on the circuit forming surface 70X of the semiconductor chip 70 by the insulating sheet 9 and the protruding electrodes 8. One of the leads 61 is not electrically connected to the electrode 71 of the semiconductor chip 70.

The second portion 61B of the lead 61, the lead 62
The second portion 62B and the third portion 62C are bent and formed into a gull wing type which is one of the surface mount type lead shapes. That is, the second portion 61B of the lead 61, the second portion 62B and the third portion 62C of the lead 62 are projecting portions (61B1, 62B1, 62C1) projecting outside the semiconductor chip 70 from the first portions (61A, 61A). An intermediate portion (61B2, 62B2, 62C2) bent from the protruding portion toward the back surface 70Y of the semiconductor chip 70;
The mounting portion (61B3, 62B3, 62C3) extends in the same direction as the protruding portion from the intermediate portion.

The width of the lead 62 is wider than the width of the lead 61 in order to improve heat radiation. Lead 62
Is the electrode 7 which is a reference potential terminal among the plurality of electrodes 71.
1B. That is, the lead 62
It is used as a reference potential lead.

The insulating sheet 9 is composed of the leads 2 and 3
Are arranged between the respective first portions (2A, 2B) and the semiconductor chip 10 and cover the element forming surface 10X of the semiconductor chip 10 except for a region where the plurality of protruding electrodes 8 are arranged.

Broadband amplifier 60A thus configured
Is mounted on a semiconductor substrate 80 as shown in FIG. 33 (a schematic cross-sectional view showing a state of being mounted on a mounting substrate). The mounting portion 61B3 of the lead 61 is electrically and mechanically connected to a lead connection terminal (a part of a wiring) 81 of the mounting substrate 80 by a conductive adhesive (for example, a conductive material having a Pb-Sn composition) 83. . The mounting portion 61B3 of the lead 62
Although not shown, 61C3 is also electrically and mechanically connected to the lead connection terminals of the mounting board 80 by an adhesive.

According to the wideband video amplifier 60A configured as described above, the same effects as in the first embodiment can be obtained.

Further, since the electrodes 71 of the semiconductor chip 70 and the leads (61, 62) are electrically connected by the protruding electrodes 8, the conductive path between the electrodes of the semiconductor chip 70 and the leads 61 is reduced. Since the length is shortened, the speed of the wideband video amplifier 60A can be increased.

(Embodiment 10) FIG. 34 is a schematic sectional view of a broadband video amplifier according to Embodiment 10 of the present invention, and FIG. 35 is a schematic view showing a state where the wideband video amplifier of FIG. 34 is mounted on a mounting board. It is sectional drawing.

As shown in FIG. 34, the wideband video amplifier 60B according to the present embodiment has basically the same configuration as that of the ninth embodiment described above, and differs in the following configuration.

That is, on the back surface 70Y of the semiconductor chip 70,
An adhesion promoting layer 72 having wettability with the conductive adhesive is provided.

With this configuration, when the wideband video amplifier 60B is mounted on the mounting board, as shown in FIG. 35, the back surface 70Y of the semiconductor chip 70 is attached to the chip connecting lands 82 of the mounting board 80 with an adhesive. Since the connection can be made by the 83, the heat dissipation of the wideband video amplifier 60B is improved.

As described above, the invention made by the present inventor is described below.
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified without departing from the scope of the invention.

For example, the present invention can be applied to a power transistor on which a switching element such as a bipolar transistor or an insulated gate bipolar transistor is mounted.

Further, the present invention can be applied to a power IC on which circuits such as a switching element and a protection circuit are mounted.

[0141]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

According to the present invention, the thickness of the semiconductor device can be reduced. According to the present invention, the heat dissipation of the semiconductor device can be improved. According to the present invention, the on-resistance of the semiconductor device can be reduced. According to the present invention, the speed of a semiconductor device can be increased.

[Brief description of the drawings]

FIG. 1 is a schematic perspective view illustrating a schematic configuration of a power transistor according to a first embodiment of the present invention.

FIG. 2 is a schematic sectional view taken along line aa of FIG.

FIG. 3 is a schematic sectional view taken along the line bb of FIG. 1;

FIG. 4 is a schematic cross-sectional view taken along the line cc of FIG. 1;

FIG. 5 is a schematic plan view showing a schematic configuration of the semiconductor chip of FIG. 1;

FIG. 6 is a schematic bottom view showing a schematic configuration of the semiconductor chip of FIG. 1;

FIG. 7 is a schematic sectional view taken along line dd of FIG. 5;

FIG. 8 is a schematic sectional view taken along the line ee in FIG. 5;

FIG. 9 is a schematic plan view showing a plane pattern of the gate conductor layer of FIG.

FIG. 10 is a schematic plan view of a lead frame used for manufacturing the power transistor of FIG.

FIG. 11 is a schematic cross-sectional view for explaining the manufacture of the power transistor of FIG.

FIG. 12 is a schematic cross-sectional view for explaining the manufacture of the power transistor of FIG.

FIG. 13 is a schematic cross-sectional view for explaining the manufacture of the power transistor of FIG.

FIG. 14 is a schematic cross-sectional view for explaining the manufacture of the power transistor of FIG.

15 is a schematic cross-sectional view showing a state where the power transistor of FIG. 1 is mounted on a mounting substrate.

FIG. 16 is a schematic cross-sectional view for explaining a tip position of the lead of FIG. 1;

FIG. 17 is a schematic cross-sectional view for explaining a tip position of the lead of FIG. 1;

FIG. 18 is a schematic cross-sectional view for explaining another manufacture of the power transistor of FIG. 1;

FIG. 19 is a schematic perspective view showing a schematic configuration of a power transistor which is Embodiment 2 of the present invention.

FIG. 20 is a schematic perspective view illustrating a schematic configuration of a power transistor that is Embodiment 3 of the present invention.

FIG. 21 is a schematic perspective view showing a schematic configuration of a power transistor which is Embodiment 4 of the present invention.

FIG. 22 is a schematic plan view illustrating a schematic configuration of a power transistor that is Embodiment 5 of the present invention.

23 (A) is a schematic plan view, and FIG. 23 (B) is a schematic plan view of a power transistor according to a sixth embodiment of the present invention.
(A) is a schematic cross-sectional view along the line ff in (A).

FIGS. 24A and 24B are diagrams each showing a schematic configuration of a power transistor according to a seventh embodiment of the present invention (FIG. 24A is a schematic plan view), and FIG.
(A) is a schematic cross-sectional view along the gg line in (A).

FIG. 25 is a schematic cross-sectional view for explaining the tip position of the lead shown in FIG. 24.

FIG. 26 is a schematic cross-sectional view for explaining the position of the lead tip.

27A and 27B are schematic perspective views showing a schematic configuration of a power transistor according to an eighth embodiment of the present invention, and FIG.
(A) is a schematic cross-sectional view taken along the line hh in (A).

FIG. 28 is a schematic plan view showing a schematic configuration of the semiconductor chip of FIG. 27;

FIG. 29 is a schematic plan view showing a wiring pattern of the semiconductor chip of FIG. 27;

FIG. 30 is a schematic sectional view taken along line ii of FIG. 28;

FIG. 31 is a diagram showing a schematic configuration of a wideband video amplifier according to a ninth embodiment of the present invention ((A) is a schematic plan view, (B)
(A) is a schematic cross-sectional view along the line JJ, and (C) is a schematic cross-sectional view along the line kk in (A).

FIG. 32 is an equivalent circuit diagram of the wideband video amplifier of FIG. 31.

FIG. 33 is a schematic cross-sectional view showing a state where the wideband video amplifier of FIG. 31 is mounted on a mounting substrate.

FIG. 34 is a schematic sectional view showing a schematic configuration of a wideband video amplifier according to Embodiment 10 of the present invention.

FIG. 35 is a schematic sectional view showing a state in which the wideband video amplifier of FIG. 34 is mounted on a mounting substrate.

[Explanation of symbols]

1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1
I: power transistor (semiconductor device), 2, 3: lead, 2A, 3A: first portion, 2B, 3B: second portion, 2
C, 3C: third portion, 2D, 3D: fourth portion, 2AX,
3AX: Upper surface, 2B1, 2C1, 3B1, 3C1: Projecting portion (shoulder portion), 2B2, 2C2, 3B2, 3C2: Intermediate portion, 2B3, 2C3, 3B3, 3C3: Mounting portion (connecting portion), 2B4, 2C4, 3B4 , 3C4 ... tip, 2B4X, 3B4X ... upper edge, 2B4Y, 3B4Y
... lower edge, 4A, 4B ... slit, 5 ... frame body,
Reference numeral 6: lead arrangement area, 8: projecting electrode, 9: insulating sheet, 10: semiconductor chip, 10a, 10b: long side, 10
c, 10d: short side, 10X: element formation surface, 10Y: back surface, 11: semiconductor base, 11A: n + type semiconductor substrate, 11
B: n-type semiconductor layer, 12: groove, 13A: gate insulating film,
13B: insulating film, 14A: gate conductor layer, 14B: gate lead-out wiring, 15: insulating film, 16: p-type well region,
17 ... n + type semiconductor region, 18 ... interlayer insulating film, 19 ... opening, 20 ... source electrode, 21 ... gate electrode, 22 ... surface protection film, 23 ... bonding opening, 24 ... drain electrode, 30 ... heat stage, 31 ... Bonding tool, 32A: lead suppressing member, 32B: bending table 32B,
33 ... bending punch, 34 ... heat stage, 34A ... recess, 35 ... mounting board, 36 ... lead connection terminal, 37 ...
Chip connecting terminal, 38: adhesive, 40: semiconductor chip, 40X: element forming surface, 40Y: back surface, 41: semiconductor base, 41A: p + type semiconductor substrate, 41B: p- type semiconductor layer, 42: field insulating film , 43... P-type well region,
44 ... p + type semiconductor region, 45 ... gate insulating film, 46 ... gate conductor layer, 47 ... n- type semiconductor region, 48 ... n + type semiconductor region, 49 ... insulating film, 50A, 50B, 50C ... wiring,
Reference numeral 51: insulating film, 52: drain electrode, 53: gate electrode, 54: surface protective film, 55: bonding opening, 56
... Source electrode, 60A, 60B ... Broadband video amplifier (semiconductor device), 61,62 ... Lead, 61A, 62A
... 1st part, 61B, 62B ... 2nd part, 61B1, 6
2B1 ... projecting part, 61B2, 62B2 ... middle part, 6
1B3, 62B3 mounting part, 61B4, 62B4 tip part, 70 semiconductor chip, 70a, 70b long side, 7
0c, 70d: short side, 70X: circuit forming surface, 70Y: back surface, 71: electrode, 72: adhesion promoting layer, 80: mounting substrate,
81: lead connection terminal, 82: chip connection land,
83: adhesive, LF: lead frame, R1 to R5: resistance element, Tr1 to Tr12: bipolar transistor.

Continued on the front page (72) Inventor Ryoichi Kajiwara 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Masahiro Koizumi 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Hitachi, Ltd. Hitachi Research Laboratory (72) Inventor Munehisa Kishimoto 5-2-1, Kamimizuhonmachi, Kodaira-shi, Tokyo F-term in the Hitachi, Ltd. Semiconductor Group 5F044 KK16 QQ01

Claims (6)

[Claims] A semiconductor chip having a first main surface and a second main surface opposed to each other, a plurality of electrodes and a circuit formed on the first main surface, and a first chip positioned on the electrode of the semiconductor chip. A plurality of leads each having one portion, a second portion formed integrally with the first portion, and located outside the semiconductor chip; and a first portion of each of the leads and each electrode of the semiconductor chip. A plurality of protruding electrodes disposed therebetween and electrically connecting each other; and an insulating sheet disposed between a first portion of each of the leads and a first main surface of the semiconductor chip, And an insulating sheet covering a first main surface of the semiconductor chip other than a region where the plurality of protruding electrodes are arranged. 2. The semiconductor device according to claim 1, wherein the second portion of each of the leads is bent such that a tip end thereof is located on a second main surface side of the semiconductor chip. Semiconductor device. 3. The semiconductor device according to claim 1, wherein the semiconductor chip further has an adhesion promoting layer on a second main surface thereof, and each of the second portions of each of the leads has the tip portion thereof. The tip of the second portion of each of the leads is bent substantially at the same position as the second main surface of the semiconductor chip in the thickness direction of the semiconductor chip. A semiconductor device characterized by being arranged. 4. The semiconductor device according to claim 1, wherein an upper surface of the first portion of each of the leads is exposed from the insulating sheet. 5. The semiconductor device according to claim 1, wherein the insulating sheet is made of a thermosetting resin or a thermoplastic resin containing no conductive particles. 6. A semiconductor chip comprising: a first main surface and a second main surface facing each other; a plurality of electrodes and circuits formed on the first main surface; A first portion located on an electrode of the semiconductor chip, and a first portion formed integrally with the first portion and outside the first side of the first side and the second side facing each other of the semiconductor chip. A plurality of first leads having a second portion located thereon; a first portion located on an electrode of the semiconductor chip; and a first portion formed integrally with the first portion and outside a second side of the semiconductor chip. A plurality of second leads having a second portion located thereon; a first portion located on an electrode of the semiconductor chip; and a third side formed integrally with the first portion and facing the semiconductor chip. And the fourth side is located outside the third side. A third part formed integrally with the first part and located outside a fourth side of the semiconductor chip; a third part having a third part located outside the fourth side of the semiconductor chip; The electrodes are arranged between the electrodes of the semiconductor chip, between the first portions of the second leads and the electrodes of the semiconductor chip, and between the first portions of the third leads and the electrodes of the semiconductor chip. A plurality of protruding electrodes that are electrically connected to each other; and a plurality of protruding electrodes disposed between the first portions of the first lead, the second lead, and the third lead, and the first main surface of the semiconductor chip. An insulating sheet that covers a first main surface of the semiconductor chip other than a region where the semiconductor chip is arranged.