JP4654062B2 - Adhesive sheet for manufacturing semiconductor device and method for manufacturing semiconductor device - Google Patents

Adhesive sheet for manufacturing semiconductor device and method for manufacturing semiconductor device Download PDF

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JP4654062B2
JP4654062B2 JP2005099481A JP2005099481A JP4654062B2 JP 4654062 B2 JP4654062 B2 JP 4654062B2 JP 2005099481 A JP2005099481 A JP 2005099481A JP 2005099481 A JP2005099481 A JP 2005099481A JP 4654062 B2 JP4654062 B2 JP 4654062B2
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semiconductor device
adhesive sheet
manufacturing
adhesive
resin component
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JP2006278963A (en
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健 佐藤
展宏 橋本
敦史 山井
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Tomoegawa Co Ltd
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Tomoegawa Paper Co Ltd
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Priority to JP2005099481A priority Critical patent/JP4654062B2/en
Application filed by Tomoegawa Paper Co Ltd filed Critical Tomoegawa Paper Co Ltd
Priority to MYPI20061357A priority patent/MY138686A/en
Priority to SG200602019A priority patent/SG126111A1/en
Priority to KR1020060027831A priority patent/KR100776313B1/en
Priority to CN2008101777657A priority patent/CN101445707B/en
Priority to TW095110650A priority patent/TWI328030B/en
Priority to CNB2006100664027A priority patent/CN100500784C/en
Publication of JP2006278963A publication Critical patent/JP2006278963A/en
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Abstract

The present invention provides an adhesive sheet for producing a semiconductor device, a semiconductor device, and a production method for the semiconductor device, wherein the adhesive sheet for manufacturing the semiconductor device can prevent the remains of a bond, while keeping the wire bonding properties of a thermosetting adhesive and the mold flush characteristics when used in manufacturing of a semiconductor device, such as QFN etc., and which can prevent making defective products of the semiconductor device. The adhesive sheet for manufacturing the semiconductor device is releasablyput on a lead frame or wiring substrate of a semiconductor device, and includes a base material and an adhesive layer containing a thermosetting resin component (a1) and a thermoplastic resin component (b1) one of which containing fluorous olefin resin.

Description

本発明は、ＱＦＮ等の半導体装置（半導体パッケージ）を製造する際に用いて好適な半導体装置製造用接着シートに関する。   The present invention relates to an adhesive sheet for manufacturing a semiconductor device suitable for use in manufacturing a semiconductor device (semiconductor package) such as QFN.

近年、携帯型パソコン、携帯電話等の電子機器の小型化、多機能化に伴い、電子機器を構成する電子部品の小型化、高集積化の他、電子部品の高密度実装技術が必要になっている。このような背景下、従来のＱＦＰ(Quad Flat Package)やＳＯＰ(Small Outline Package)等の周辺実装型の半導体装置に代わって、高密度実装が可能なＣＳＰ(Chip Scale Pakeage)等の面実装型の半導体装置が注目されている。また、ＣＳＰの中でも特にＱＦＮ(Quad Flat Non-leaded)は、従来の半導体装置の製造技術を適用して製造できるため好適であり、主に１００ピン以下の少端子型の半導体装置として用いられている。   In recent years, along with the downsizing and multi-functionalization of electronic devices such as portable personal computers and mobile phones, it has become necessary to provide high-density mounting technology for electronic components in addition to downsizing and high integration of electronic components constituting electronic devices. ing. Under such circumstances, instead of the conventional peripheral mounting type semiconductor devices such as QFP (Quad Flat Package) and SOP (Small Outline Package), surface mounting type such as CSP (Chip Scale Pakeage) capable of high density mounting. These semiconductor devices are attracting attention. Among CSPs, QFN (Quad Flat Non-leaded) is particularly suitable because it can be manufactured by applying a conventional semiconductor device manufacturing technique, and is mainly used as a small terminal type semiconductor device having 100 pins or less. Yes.

従来、ＱＦＮの製造方法として、概略下記の方法が知られている。
はじめに、接着シート貼着工程において、リードフレームの一方の面に接着シートを貼着し、次いで、ダイアタッチ工程において、リードフレームに複数形成された半導体素子搭載部（ダイパッド部）に、ＩＣチップ等の半導体素子を各々搭載する。次に、ワイヤボンディング工程において、リードフレームの各半導体素子搭載部の外周に沿って配設された複数のリードと半導体素子とをボンディングワイヤにより電気的に接続する。次に、樹脂封止工程において、リードフレームに搭載された半導体素子を封止樹脂により封止する。その後、接着シート剥離工程において、接着シートをリードフレームから剥離することにより、複数のＱＦＮが配列されたＱＦＮユニットを形成することができる。最後に、ダイシング工程において、このＱＦＮユニットを各ＱＦＮの外周に沿ってダイシングすることにより、複数のＱＦＮを同時に製造することができる。 Conventionally, the following methods are generally known as methods for producing QFN.
First, in the adhesive sheet attaching step, an adhesive sheet is attached to one surface of the lead frame, and then in the die attach step, a plurality of semiconductor element mounting portions (die pad portions) formed on the lead frame are attached to an IC chip or the like. Each semiconductor element is mounted. Next, in the wire bonding step, the plurality of leads arranged along the outer periphery of each semiconductor element mounting portion of the lead frame and the semiconductor elements are electrically connected by bonding wires. Next, in the resin sealing step, the semiconductor element mounted on the lead frame is sealed with a sealing resin. Thereafter, in the adhesive sheet peeling step, the QFN unit in which a plurality of QFNs are arranged can be formed by peeling the adhesive sheet from the lead frame. Finally, in the dicing process, a plurality of QFNs can be manufactured simultaneously by dicing the QFN units along the outer periphery of each QFN.

従来、上記概略説明したＱＦＮの製造方法においては、シリコーン粘着剤を使用した接着シートが使用されてきた。しかし、シリコーン粘着剤に起因してワイヤボンディング性や、モールドフラッシュの問題が生じることがあった。そこで、この問題の改善を目的として、熱硬化型接着剤を適用した開発が行なわれている（例えば、特許文献１参照。）。
特開２００３−３３６０１５号公報 Conventionally, in the QFN manufacturing method outlined above, an adhesive sheet using a silicone pressure-sensitive adhesive has been used. However, problems with wire bonding and mold flash may occur due to the silicone adhesive. Therefore, for the purpose of improving this problem, development using a thermosetting adhesive has been carried out (for example, see Patent Document 1).
JP 2003-336015 A

ところで、ワイヤボンディング工程前にプラズマクリーニングを実施することで、表面に付着した不純物を除去することにより、ワイヤボンディング特性をさらに向上させることが一般化している。
しかしながら、上記構成の従来の半導体装置製造用接着シートを用いた場合、半導体装置製造用接着シートの接着剤露出面表層がプラズマクリーニングにより粗化され、半導体用接着シートの剥離時に、半導体装置の接続端子、封止樹脂面への接着剤移行（以下「糊残り」と表記することがある）が発生することがあった。このような糊残りが発生した場合に、封止樹脂により封止した部分や、その近傍のリードの外部接続端子部分に接着剤が付着するため、製造された半導体装置を配線基板等に実装する際に、接続不良が発生する恐れがあった。 By the way, it has become common to further improve the wire bonding characteristics by removing impurities adhering to the surface by performing plasma cleaning before the wire bonding step.
However, when the conventional adhesive sheet for manufacturing a semiconductor device having the above-described configuration is used, the surface of the adhesive exposed surface of the adhesive sheet for manufacturing a semiconductor device is roughened by plasma cleaning, and the semiconductor device is connected when the adhesive sheet for semiconductor is peeled off. Adhesive transfer to the terminal and the sealing resin surface (hereinafter sometimes referred to as “glue residue”) may occur. When such adhesive residue occurs, the adhesive adheres to the portion sealed with the sealing resin and the external connection terminal portion of the lead in the vicinity thereof, so the manufactured semiconductor device is mounted on a wiring board or the like. In some cases, connection failure may occur.

本発明は前記課題を解決するためになされたもので、ＱＦＮ等の半導体装置の製造に用いた場合に、熱硬化型接着剤のワイヤボンディング性、モールドフラッシュ特性を維持したまま、糊残りを防止することができ、半導体装置の不良品化を防止することができる半導体装置製造用接着シートを目的とする。   The present invention has been made to solve the above problems, and prevents adhesive residue while maintaining the wire bonding property and mold flash property of a thermosetting adhesive when used in the manufacture of semiconductor devices such as QFN. It is an object of the present invention is to provide an adhesive sheet for manufacturing a semiconductor device that can prevent a defective semiconductor device.

本発明の半導体装置製造用接着シート（以下、「接着シート」と略記することがある。）は、半導体装置のリードフレームまたは配線基板に剥離可能に貼着される半導体装置製造用接着シートにおいて、基材と、フッ素樹脂を含有した接着剤層とを具備することを特徴とするものである。
ここで、接着剤層が熱硬化性樹脂成分（ａ）と熱可塑性樹脂成分（ｂ）を含有し、該熱硬化性樹脂成分（ａ）と熱可塑性樹脂成分（ｂ）のいずれかが、フッ素を含有するオレフィン系樹脂であることが望ましい。
また、半導体装置のリードフレームに貼着して硬化した接着剤層の１５０〜２００℃における接着強度が０.０３〜５Ｎ／ｃｍであることが望ましい。
また、接着剤層の熱硬化性樹脂成分（ａ）及び熱可塑性樹脂成分（ｂ）の質量比率（ａ）／（ｂ）が０.０５〜０.４３であることが望ましい。
熱可塑性樹脂成分（ｂ）の質量平均分子量は２,０００〜１,０００,０００であることが望ましい。
接着剤層の硬化後の貯蔵弾性率は、１５０〜２５０℃にて、０.１ＭＰａ以上であることが望ましい。
基材は、ガラス転位温度が１５０℃以上、熱膨張係数が５〜５０ｐｐｍ／℃の耐熱性フィルム、又は、熱膨張係数が５〜５０ｐｐｍ／℃の金属箔であることが望ましい。
接着剤層の片面に保護フィルムが設けられていることが望ましい。
本発明の半導体装置並びにその製造方法は、上記半導体装置製造用接着シートを用いて製造することを特徴とするものである。 An adhesive sheet for manufacturing a semiconductor device according to the present invention (hereinafter sometimes abbreviated as “adhesive sheet”) is an adhesive sheet for manufacturing a semiconductor device that is detachably attached to a lead frame or a wiring board of a semiconductor device. It comprises a base material and an adhesive layer containing a fluororesin.
Here, the adhesive layer contains a thermosetting resin component (a) and a thermoplastic resin component (b), and any one of the thermosetting resin component (a) and the thermoplastic resin component (b) is fluorine. It is desirable that the olefin resin contains.
Moreover, it is desirable that the adhesive strength at 150 to 200 ° C. of the adhesive layer stuck and cured on the lead frame of the semiconductor device is 0.03 to 5 N / cm.
Moreover, it is desirable that the mass ratio (a) / (b) of the thermosetting resin component (a) and the thermoplastic resin component (b) of the adhesive layer is 0.05 to 0.43.
The mass average molecular weight of the thermoplastic resin component (b) is desirably 2,000 to 1,000,000.
The storage elastic modulus after curing of the adhesive layer is desirably 0.1 MPa or more at 150 to 250 ° C.
The substrate is preferably a heat resistant film having a glass transition temperature of 150 ° C. or higher and a thermal expansion coefficient of 5 to 50 ppm / ° C., or a metal foil having a thermal expansion coefficient of 5 to 50 ppm / ° C.
It is desirable that a protective film is provided on one side of the adhesive layer.
The semiconductor device and the manufacturing method thereof according to the present invention are manufactured using the adhesive sheet for manufacturing a semiconductor device.

本発明の半導体装置製造用接着シートであれば、接着剤層がプラズマクリーニングに曝されても、適切な剥離性を保持し、糊残りが発生しないため、本発明の接着シートを用いて、ＱＦＮ等の半導体装置を製造することにより、ワイヤボンディング不良、モールドフラッシュはもとより、糊残りを防止することができ、半導体装置の不良品化を防止できる。   With the adhesive sheet for manufacturing a semiconductor device of the present invention, even if the adhesive layer is exposed to plasma cleaning, appropriate peelability is maintained and no adhesive residue is generated. By manufacturing a semiconductor device such as the above, not only wire bonding failure and mold flash but also adhesive residue can be prevented, and the semiconductor device can be prevented from becoming defective.

以下、本発明について詳述する。
本発明の接着シートは、半導体装置のリードフレームまたは配線基板に剥離可能に貼着されるものである。ここで、リードフレームとは、金属板をエッチング又はプレス等により導体パターンを形成したものであり、配線基板とは、電気絶縁性基板の表面（または内面を含むことがある）に、導体パターンを導電性材料で形成し、固着したもののことである。
尚、以下の説明では、便宜的に、リードフレームを貼着対象として説明するが、配線基板に対しても同様である。 Hereinafter, the present invention will be described in detail.
The adhesive sheet of the present invention is detachably attached to a lead frame or a wiring board of a semiconductor device. Here, the lead frame is a conductor plate formed by etching or pressing a metal plate, and the wiring board is a conductor pattern formed on the surface (or may include the inner surface) of an electrically insulating substrate. It is made of a conductive material and fixed.
In the following description, for the sake of convenience, the description will be made with the lead frame as an object to be adhered, but the same applies to the wiring board.

本発明の接着シートは、基材と、剥離性付与のためにフッ素樹脂を含有している接着剤層とを積層した構成のものである。
基材としては、耐熱性のあるもの、例えば、耐熱性樹脂フィルムや金属箔等を挙げることができる。
本発明の接着シートを用いてＱＦＮ等の半導体装置を製造する際に、接着シートは、ダイアタッチ工程、ワイヤボンディング工程、樹脂封止工程において、１５０〜２５０℃の高温に曝されるが、基材として耐熱性樹脂フィルムを用いる場合、該耐熱性フィルムの熱膨張係数はガラス転位温度（Ｔｇ）以上になると急激に増加し、金属製のリードフレームとの熱膨張差が大きくなるため、室温に戻した際に、耐熱性フィルムとリードフレームに反りが発生する恐れがある。そして、このように、耐熱性フィルムとリードフレームに反りが発生した場合には、樹脂封止工程において、金型の位置決めピンにリードフレームを装着することができず、位置ずれ不良を起こす恐れがある。
したがって、基材として耐熱性フィルムを用いる場合、ガラス転位温度が１５０℃以上の耐熱性フィルムであることが好ましく、更に１８０℃以上であることがより好ましい。また、耐熱性フィルムの１５０〜２５０℃における熱膨張係数が５〜５０ｐｐｍ／℃であることが好ましく、更に１０〜３０ｐｐｍ／℃であることがより好ましい。かかる特性を有する耐熱性フィルムとしては、ポリイミド、ポリアミド、ポリエーテルサルフォン、ポリフェニレンサルファイド、ポリエーテルケトン、ポリエーテルエーテルケトン、トリアセチルセルロース、ポリエーテルイミド等からなるフィルムを例示することができる。 The adhesive sheet of the present invention has a structure in which a base material and an adhesive layer containing a fluororesin for imparting peelability are laminated.
As a base material, what has heat resistance, for example, a heat resistant resin film, metal foil, etc. can be mentioned.
When manufacturing a semiconductor device such as QFN using the adhesive sheet of the present invention, the adhesive sheet is exposed to a high temperature of 150 to 250 ° C. in a die attach process, a wire bonding process, and a resin sealing process. When a heat-resistant resin film is used as the material, the thermal expansion coefficient of the heat-resistant film increases rapidly when the glass transition temperature (Tg) or higher, and the difference in thermal expansion from the metal lead frame increases. When returned, the heat resistant film and the lead frame may be warped. If the heat-resistant film and the lead frame are warped as described above, the lead frame cannot be mounted on the positioning pins of the mold in the resin sealing process, which may cause misalignment. is there.
Therefore, when using a heat resistant film as a substrate, the glass transition temperature is preferably 150 ° C. or higher, more preferably 180 ° C. or higher. Moreover, it is preferable that the thermal expansion coefficient in 150-250 degreeC of a heat resistant film is 5-50 ppm / degreeC, and it is more preferable that it is 10-30 ppm / degreeC. Examples of the heat resistant film having such characteristics include films made of polyimide, polyamide, polyether sulfone, polyphenylene sulfide, polyether ketone, polyether ether ketone, triacetyl cellulose, polyether imide, and the like.

また、基材として金属箔を用いる場合においても、前記耐熱性フィルムと同様の理由から、金属箔の１５０〜２５０℃における熱膨張係数が５〜５０ｐｐｍ／℃であることが好ましく、更に１０〜３０ｐｐｍ／℃であることがより好ましい。金属としては、金、銀、銅、白金、アルミニウム、マグネシウム、チタン、クロム、マンガン、鉄、コバルト、ニッケル、亜鉛、パラジウム、カドミウム、インジウム、錫、鉛からなる箔や、これらの金属を主成分とした合金箔、あるいはこれらのメッキ箔を例示することができる。   Moreover, also when using metal foil as a base material, it is preferable that the thermal expansion coefficient in 150-250 degreeC of metal foil is 5-50 ppm / degrees C for the same reason as the said heat resistant film, and also 10-30 ppm. / ° C is more preferable. Metals include gold, silver, copper, platinum, aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, zinc, palladium, cadmium, indium, tin, lead, and these metals as the main components. Examples of the alloy foils or the plating foils thereof can be given.

また、本発明の接着シートを用いて半導体装置を製造する際に、接着シート剥離工程における糊残りを防止するためには、基材と接着剤層との接着強度Ｓａと、封止樹脂及びリードフレームと接着剤層との接着強度Ｓｂとの比（接着強度比）Ｓａ／Ｓｂが１.５以上であることが好ましい。Ｓａ／Ｓｂが１.５未満の場合では、接着シート剥離工程において糊残りが発生しやすいため好ましくない。なお、接着強度比Ｓａ／Ｓｂを１.５以上とするためには、耐熱性フィルムの場合には、接着剤層を形成する前に、耐熱性フィルムの接着剤層を形成する側の表面に、コロナ処理、プラズマ処理、プライマー処理、サンドブラスト等の、耐熱性フィルムと接着剤層との接着強度Ｓａを高くするような処理をあらかじめ施しておくことが好適である。また、金属箔の場合では、その製法から圧延金属箔と電解金属箔とに分類されるが、接着強度比Ｓａ／Ｓｂを１.５以上とするために、電解金属箔を用いると共に粗面化された側の面に接着剤層を設けて調整することが好ましい。また、電解金属箔の中でも特に、電解銅箔を用いることが特に好ましい。
また、リードフレームに対する接着剤層の硬化後の１５０〜２００℃における接着強度が０.０３〜５Ｎ／ｃｍであることがモールドフラッシュを防止できるので好ましい。０.０３Ｎ／ｃｍ未満では、モールドフラッシュが発生し易く、５Ｎ／ｃｍ超では糊残りが生じやすい。また、リードフレームに対する接着剤層の未硬化における常温の接着強度は０.９８Ｎ／ｃｍ以上であることが製造工程上、好ましい。０.９８Ｎ／ｃｍ未満では、製造工程における搬送時にリードフレームから接着剤層が剥離し易くなるからである。 Further, when manufacturing a semiconductor device using the adhesive sheet of the present invention, in order to prevent adhesive residue in the adhesive sheet peeling step, the adhesive strength Sa between the base material and the adhesive layer, the sealing resin, and the lead The ratio (adhesive strength ratio) Sa / Sb of the adhesive strength Sb between the frame and the adhesive layer is preferably 1.5 or more. When Sa / Sb is less than 1.5, an adhesive residue is likely to occur in the adhesive sheet peeling step, which is not preferable. In order to set the adhesive strength ratio Sa / Sb to 1.5 or more, in the case of a heat resistant film, before forming the adhesive layer, on the surface of the heat resistant film on the side where the adhesive layer is formed. It is preferable that a treatment for increasing the adhesive strength Sa between the heat-resistant film and the adhesive layer, such as corona treatment, plasma treatment, primer treatment, and sand blasting, is performed in advance. In the case of a metal foil, it is classified into a rolled metal foil and an electrolytic metal foil depending on the production method. In order to make the adhesive strength ratio Sa / Sb 1.5 or more, the electrolytic metal foil is used and the surface is roughened. It is preferable to adjust by providing an adhesive layer on the surface on the formed side. Moreover, it is especially preferable to use electrolytic copper foil among electrolytic metal foils.
Further, the adhesive strength at 150 to 200 ° C. after curing of the adhesive layer to the lead frame is preferably 0.03 to 5 N / cm because mold flash can be prevented. If it is less than 0.03 N / cm, mold flash tends to occur, and if it exceeds 5 N / cm, adhesive residue tends to occur. In addition, the adhesive strength at room temperature when the adhesive layer is not cured with respect to the lead frame is preferably 0.98 N / cm or more in the manufacturing process. If it is less than 0.98 N / cm, the adhesive layer easily peels off from the lead frame during conveyance in the manufacturing process.

本発明の接着剤層は、フッ素樹脂を含有したものである。ここで、フッ素樹脂とは、広く、フッ素元素を構成成分として含んだ樹脂を云う。
接着剤層は、熱硬化性樹脂成分（ａ）、熱可塑性樹脂成分（ｂ）を含有し、熱硬化性樹脂成分（ａ）または熱可塑性樹脂成分（ｂ）のいずれかがフッ素樹脂を含有していることが望ましい。この場合、熱硬化性樹脂成分（ａ）と熱可塑性樹脂成分（ｂ）の質量比率（ａ）／（ｂ）は０.０５〜０.４３が好ましく、０.１１〜０.２５がより好ましい。
（ａ）／（ｂ）が０.４３より大きい場合、フッ素を含有している樹脂成分とフッ素を含有していない樹脂成分とが、塗料作製時に分離し接着剤層が形成できなくなる恐れがある。（ａ）／（ｂ）が０.０５未満の場合、接着剤層の凝集力が低下する為、樹脂封止工程でモールドフラッシュが発生しやすくなるおそれがある。
半導体装置を製造するための樹脂封止工程においては、１５０〜２００℃に加熱しながら、５〜１０ＧＰａの圧力をかけて半導体素子を樹脂封止により封止する。そのため、接着シートの接着剤層が高温に曝される結果、接着剤層の接着力（接着剤層とリードフレームとの接着強度）が低下し、封止樹脂の圧力により、接着剤層がリードフレームから部分的に剥離してモールドフラッシュが発生する場合があるが、上記熱硬化性樹脂成分（ａ）、熱可塑性樹脂成分（ｂ）を有する接着剤層を用いた本発明の接着シートでは、接着剤層の接着力がより低下しないため上記問題は生じない。 The adhesive layer of the present invention contains a fluororesin. Here, the fluororesin widely refers to a resin containing a fluorine element as a constituent component.
The adhesive layer contains a thermosetting resin component (a) and a thermoplastic resin component (b), and either the thermosetting resin component (a) or the thermoplastic resin component (b) contains a fluororesin. It is desirable that In this case, the mass ratio (a) / (b) of the thermosetting resin component (a) and the thermoplastic resin component (b) is preferably 0.05 to 0.43, more preferably 0.11 to 0.25. .
When (a) / (b) is larger than 0.43, the resin component containing fluorine and the resin component not containing fluorine may be separated at the time of preparing the paint, and the adhesive layer may not be formed. . When (a) / (b) is less than 0.05, the cohesive force of the adhesive layer is lowered, and thus mold flash may be easily generated in the resin sealing step.
In the resin sealing step for manufacturing the semiconductor device, the semiconductor element is sealed by resin sealing while applying a pressure of 5 to 10 GPa while being heated to 150 to 200 ° C. Therefore, as a result of the adhesive layer of the adhesive sheet being exposed to high temperature, the adhesive strength of the adhesive layer (adhesive strength between the adhesive layer and the lead frame) is reduced, and the adhesive layer is lead by the pressure of the sealing resin. In some cases, mold flash may occur due to partial peeling from the frame, but in the adhesive sheet of the present invention using the adhesive layer having the thermosetting resin component (a) and the thermoplastic resin component (b), Since the adhesive force of the adhesive layer is not further lowered, the above problem does not occur.

熱硬化性樹脂成分（ａ）としては、尿素樹脂、メラミン樹脂、ベンゾグアナミン樹脂、アセトグアナミン樹脂、フェノール樹脂、レゾルシノール樹脂、キシレン樹脂、フラン樹脂、不飽和ポリエステル樹脂、ジアリルフタレート樹脂、イソシアナート樹脂、エポキシ樹脂、マレイミド樹脂、ナジイミド樹脂等を例示することができる。なお、これらの樹脂は単独で用いても良いし、２種以上を併用しても良い。この中でもエポキシ樹脂とフェノール樹脂の少なくとも１種を含有することによって、ワイヤボンディング工程における処理温度下で高弾性率を有すると共に、樹脂封止工程における処理温度下でリードフレームとの接着強度が高い接着剤層が得られるため好ましい。
また、フッ素を含有する熱硬化性樹脂成分としては、上記熱硬化性樹脂成分にフッ素を導入したものや、二フッ化ビニリデン、ヘキサフルオロプロピレン、テトラフルオロエチレン、パーフルオロメチルビニルエーテル等のオレフィン系樹脂に反応性官能基を有するモノマーを含有させた重合体またはそれらの２種類以上を組み合わせた共重合体等を例示することができる。更にエチレンやプロピレン、アルキルビニルエーテル等を加えた共重合体でも良い。これらの中でも特にフッ素含有オレフィン系樹脂が含有するフッ素量が多くワイヤボンディング前のプラズマクリーニングへの耐性が高いことからより好ましい。 As thermosetting resin component (a), urea resin, melamine resin, benzoguanamine resin, acetoguanamine resin, phenol resin, resorcinol resin, xylene resin, furan resin, unsaturated polyester resin, diallyl phthalate resin, isocyanate resin, epoxy Resins, maleimide resins, nadiimide resins and the like can be exemplified. In addition, these resin may be used independently and may use 2 or more types together. Among these, by containing at least one of an epoxy resin and a phenol resin, it has a high elastic modulus at the processing temperature in the wire bonding process and has a high adhesive strength with the lead frame at the processing temperature in the resin sealing process. Since an agent layer is obtained, it is preferable.
In addition, as the thermosetting resin component containing fluorine, olefin resins such as those obtained by introducing fluorine into the thermosetting resin component, vinylidene difluoride, hexafluoropropylene, tetrafluoroethylene, perfluoromethyl vinyl ether, etc. Examples thereof include a polymer containing a monomer having a reactive functional group, a copolymer obtained by combining two or more of them, and the like. Further, a copolymer to which ethylene, propylene, alkyl vinyl ether or the like is added may be used. Among these, the fluorine-containing olefin resin particularly contains a large amount of fluorine, which is more preferable because of high resistance to plasma cleaning before wire bonding.

熱可塑性樹脂成分（ｂ）としては、アクリロニトリル−ブタジエン共重合体（ＮＢＲ）、アクロロニトリル−ブタジエン−スチレン樹脂（ＡＢＳ）、スチレン−ブタジエン−エチレン樹脂（ＳＥＢＳ）、スチレン−ブタジエン−スチレン樹脂（ＳＢＳ）、ポリブタジエン、ポリアクリロニトリル、ポリビニルブチラール、ポリアミド、ポリアミドイミド、ポリイミド、ポリエステル、ポリウレタン、アクリルゴム等が例示できる。
また、フッ素を含有する熱可塑性樹脂成分としては、上記熱可塑性樹脂成分にフッ素を導入したものや、オレフィン系樹脂として、二フッ化ビニリデン、ヘキサフルオロプロピレン、テトラフルオロエチレン、パーフルオロメチルビニルエーテル等の重合体または２種類以上を組み合わせた共重合体を例示することができる。更にエチレンやプロピレン、アルキルビニルエーテル等を加えた共重合体でも良い。特にオレフィン系樹脂によるものがフッ素量を多くすることができ、ワイヤボンディング前のプラズマクリーニングへの耐久性が高いことからより好ましい。
また、熱可塑性樹脂成分（ｂ）の質量平均分子量が２,０００〜１,０００,０００、好ましくは５,０００〜８００,０００、更に好ましくは１０,０００〜５００,０００である場合には、接着剤層の凝集力を高めることができ、接着シート剥離工程における糊残りを更に防止することができるため好ましい。 Examples of the thermoplastic resin component (b) include acrylonitrile-butadiene copolymer (NBR), acrylonitrile-butadiene-styrene resin (ABS), styrene-butadiene-ethylene resin (SEBS), and styrene-butadiene-styrene resin (SBS). ), Polybutadiene, polyacrylonitrile, polyvinyl butyral, polyamide, polyamideimide, polyimide, polyester, polyurethane, acrylic rubber and the like.
Further, as the thermoplastic resin component containing fluorine, those obtained by introducing fluorine into the thermoplastic resin component, and olefin resins such as vinylidene difluoride, hexafluoropropylene, tetrafluoroethylene, perfluoromethyl vinyl ether, etc. A polymer or a copolymer combining two or more types can be exemplified. Further, a copolymer to which ethylene, propylene, alkyl vinyl ether or the like is added may be used. In particular, an olefin resin is more preferable because it can increase the amount of fluorine and has high durability to plasma cleaning before wire bonding.
Further, when the mass average molecular weight of the thermoplastic resin component (b) is 2,000 to 1,000,000, preferably 5,000 to 800,000, more preferably 10,000 to 500,000, This is preferable because the cohesive force of the adhesive layer can be increased and adhesive residue in the adhesive sheet peeling step can be further prevented.

また、接着剤層の熱膨張係数、熱伝導率、表面タック、接着性等を調整するために、接着剤層に無機、または有機フィラーを添加することが好ましい。ここで、無機フィラーとしては、粉砕型シリカ、溶融型シリカ、アルミナ、酸化チタン、酸化ベリリウム、酸化マグネシウム、炭酸カルシウム、窒化チタン、窒化珪素、窒化硼素、硼化チタン、硼化タングステン、炭化珪素、炭化チタン、炭化ジルコニウム、炭化モリブデン、マイカ、酸化亜鉛、カーボンブラック、水酸化アルミニウム、水酸化カルシウム、水酸化マグネシウム、三酸化アンチモン等からなるフィラー、あるいはこれらの表面にトリメチルシロキシル基等を導入したもの等を例示することができる。また、有機フィラーとしては、ポリイミド、ポリアミドイミド、ポリエーテルエーテルケトン、ポリエーテルイミド、ポリエステルイミド、ナイロン、シリコーン樹脂等からなるフィラーを例示することができる。   In order to adjust the thermal expansion coefficient, thermal conductivity, surface tack, adhesiveness, etc. of the adhesive layer, it is preferable to add an inorganic or organic filler to the adhesive layer. Here, as the inorganic filler, pulverized silica, fused silica, alumina, titanium oxide, beryllium oxide, magnesium oxide, calcium carbonate, titanium nitride, silicon nitride, boron nitride, titanium boride, tungsten boride, silicon carbide, Filler made of titanium carbide, zirconium carbide, molybdenum carbide, mica, zinc oxide, carbon black, aluminum hydroxide, calcium hydroxide, magnesium hydroxide, antimony trioxide or the like, or a trimethylsiloxyl group or the like is introduced on the surface thereof. The thing etc. can be illustrated. Moreover, as an organic filler, the filler which consists of a polyimide, polyamideimide, polyetheretherketone, polyetherimide, polyesterimide, nylon, a silicone resin etc. can be illustrated.

基材の一方の面に接着剤層を形成する方法としては、基材上に直接接着剤を塗布し、乾燥させるキャスティング法や、接着剤を離型性フィルム上に一旦塗布し、乾燥させた後、基材上に転写させるラミネート法等が好適である。なお、熱硬化性樹脂成分（ａ）、熱可塑性樹脂成分（ｂ）のいずれも有機溶剤、例えばトルエン、キシレン、クロルベンゼン等の芳香族系、アセトン、メチルエチルケトン、メチルイソブチルケトン等のケトン系、ジメチルホルムアミド、ジメチルアセトアミド、Ｎ−メチルピロリドン等の非プロトン系極性溶剤、テトラヒドロフラン等の単独あるいは混合物に対して１％以上好ましくは５％以上溶解して接着剤塗布液として使用することが好ましい。   As a method of forming an adhesive layer on one surface of the substrate, a casting method in which the adhesive is directly applied on the substrate and dried, or an adhesive is once applied on the release film and dried. Thereafter, a laminating method or the like that is transferred onto a substrate is suitable. Note that both the thermosetting resin component (a) and the thermoplastic resin component (b) are organic solvents such as aromatics such as toluene, xylene and chlorobenzene, ketones such as acetone, methyl ethyl ketone and methyl isobutyl ketone, and dimethyl. It is preferable to use 1% or more, preferably 5% or more of an aprotic polar solvent such as formamide, dimethylacetamide, N-methylpyrrolidone, or the like alone or in a mixture, and use it as an adhesive coating solution.

本発明の接着シートの接着剤層上に剥離可能な保護フィルムを貼着し、半導体装置製造直前に保護フィルムを剥離する構成としても良い。この場合には、接着シートが製造されてから使用されるまでの間に、接着剤層が損傷されることを防止することができる。保護フィルムとしては離型性を有するものであればいかなるフィルムを用いても良いが、例えばポリエステル、ポリエチレン、ポリプロピレン、ポリエチレンテレフタレート等のフィルムや、これらフィルムの表面をシリコーン樹脂又はフッ素化合物で離型処理したフィルム等を例示することができる。   It is good also as a structure which sticks the protective film which can be peeled on the adhesive bond layer of the adhesive sheet of this invention, and peels a protective film just before manufacture of a semiconductor device. In this case, it is possible to prevent the adhesive layer from being damaged after the adhesive sheet is manufactured and used. Any film may be used as long as it has releasability as the protective film. For example, films such as polyester, polyethylene, polypropylene, polyethylene terephthalate, etc., and the surface of these films are treated with a silicone resin or a fluorine compound. The film etc. which were done can be illustrated.

また、１５０℃から２５０℃の温度範囲全てにおける前記接着剤層の硬化後の貯蔵弾性率は、０.１ＭＰａ以上、好ましくは１ＭＰａ以上、更に５ＭＰａ以上であることが好ましい。なお、ここでいう硬化後とは、ダイアタッチ工程において加熱処理された状態における接着剤層のことをいう。貯蔵弾性率の測定条件等については後述する実施例で説明する。半導体装置を製造するためのワイヤボンディング工程においては、ボンディングワイヤを用いて半導体素子とリードフレームとを接続するために、該ボンディングワイヤの両端を１５０〜２５０℃に加熱して６０〜１２０ｋＨｚの超音波で融着する際、リードフレームの直下に位置する接着シートの接着剤層は、上記加熱による高温に曝されて低弾性化し、超音波を吸収し易くなり、その結果リードフレームが振動してワイヤボンディング不良が発生しやすいが、上記貯蔵弾性率を有する接着剤層をもつ接着シートの場合は、このような問題が発生しにくくなる。   Further, the storage elastic modulus after curing of the adhesive layer in the entire temperature range from 150 ° C. to 250 ° C. is 0.1 MPa or more, preferably 1 MPa or more, and more preferably 5 MPa or more. The term “after curing” as used herein refers to the adhesive layer that has been heat-treated in the die attach step. The measurement conditions and the like of the storage elastic modulus will be described in the examples described later. In a wire bonding process for manufacturing a semiconductor device, in order to connect a semiconductor element and a lead frame using a bonding wire, both ends of the bonding wire are heated to 150 to 250 ° C. and an ultrasonic wave of 60 to 120 kHz is used. At the time of fusing, the adhesive layer of the adhesive sheet located immediately below the lead frame is exposed to the high temperature due to the above heating and becomes low elastic, and easily absorbs ultrasonic waves. As a result, the lead frame vibrates and wire Although bonding failure is likely to occur, in the case of an adhesive sheet having an adhesive layer having the above storage elastic modulus, such a problem is less likely to occur.

（半導体装置の製造方法）
図１、図２に基づいて、本発明の接着シートを用いて、半導体装置を製造する方法の一例について説明する。以下、半導体装置としてＱＦＮを製造する場合を例として説明する。なお、図１はリードフレームを半導体素子を搭載する側から見たときの概略平面図であり、図２（ａ）〜（ｆ）は、図１に示すリードフレームからＱＦＮを製造する方法を示す工程図であって、リードフレームを図１のＡ−Ａ’線の拡大概略断面図である。 (Method for manufacturing semiconductor device)
An example of a method for manufacturing a semiconductor device using the adhesive sheet of the present invention will be described with reference to FIGS. Hereinafter, a case where QFN is manufactured as a semiconductor device will be described as an example. 1 is a schematic plan view of the lead frame as viewed from the side on which the semiconductor element is mounted. FIGS. 2A to 2F show a method of manufacturing QFN from the lead frame shown in FIG. It is process drawing, Comprising: A lead frame is an expansion schematic sectional drawing of the AA 'line of FIG.

はじめに、図１に示す概略構成のリードフレーム２０を用意する。リードフレーム２０は、ＩＣチップ等の半導体素子を搭載する島状の複数の半導体素子搭載部（ダイパッド部）２１を具備し、各半導体素子搭載部２１の外周に沿って多数のリード２２が配設されたものである。次に、図２（ａ）に示すように、接着シート貼着工程において、リードフレーム２０の一方の面上（下面）に、本発明の接着シート１０を接着剤層（図示略）側がリードフレーム２０側となるように貼着する。なお、接着シート１０をリードフレーム２０に貼着する方法としては、ラミネート法等が好適である。次に、図２（ｂ）に示すように、ダイアタッチ工程において、リードフレーム２０の半導体素子搭載部２１に、接着シート１０が貼着されていない側からＩＣチップ等の半導体素子３０を、ダイアタッチ剤（図示略）を用いて搭載する。   First, a lead frame 20 having a schematic configuration shown in FIG. 1 is prepared. The lead frame 20 includes a plurality of island-shaped semiconductor element mounting portions (die pad portions) 21 on which semiconductor elements such as IC chips are mounted, and a large number of leads 22 are arranged along the outer periphery of each semiconductor element mounting portion 21. It has been done. Next, as shown in FIG. 2A, in the adhesive sheet attaching step, the adhesive sheet 10 of the present invention is placed on one surface (lower surface) of the lead frame 20 with the adhesive layer (not shown) side on the lead frame. Adhere to the 20th side. As a method for adhering the adhesive sheet 10 to the lead frame 20, a laminating method or the like is suitable. Next, as shown in FIG. 2B, in the die attach step, the semiconductor element 30 such as an IC chip is attached to the semiconductor element mounting portion 21 of the lead frame 20 from the side where the adhesive sheet 10 is not adhered. It is mounted using a touch agent (not shown).

次に、ワイヤボンディング直前までにかかる熱履歴で、接着シートや、ダイアタッチ剤等から発生するアウトガス成分が、リードフレームに付着し、ワイヤの接合不良による歩留低下を防止するため、ワイヤボンディング工程実施前に、前記接着シート、ダイアタッチ剤、ＩＣチップが搭載されたリードフレームをプラズマクリーニングする。   Next, the wire bonding process prevents the outgas component generated from the adhesive sheet, die attach agent, etc. from adhering to the lead frame due to the heat history immediately before the wire bonding, and prevents the yield from being lowered due to poor bonding of the wires. Before implementation, the lead frame on which the adhesive sheet, die attach agent, and IC chip are mounted is plasma-cleaned.

次に、図２（ｃ）に示すように、ワイヤボンディング工程において、半導体素子３０とリードフレーム２０のリード２２とを、金ワイヤ等のボンディングワイヤ３１を介して電気的に接続する。次に、図２（ｄ）に示すように、樹脂封止工程において、図２（ｃ）に示す製造途中の半導体装置を金型内に載置し、封止樹脂（モールド材）を用いてトランスファーモールド（金型成型）することにより、半導体素子３０を封止樹脂４０により封止する。
次に、図２（ｅ）に示すように、接着シート剥離工程において、接着シート１０を封止樹脂４０及びリードフレーム２０から剥離することにより、複数のＱＦＮ５０が配列されたＱＦＮユニット６０を形成することができる。最後に、図２（ｆ）に示すように、ダイシング工程において、ＱＦＮユニット６０を各ＱＦＮ５０の外周に沿ってダイシングすることにより、複数のＱＦＮ５０を製造することができる。
このように本発明の接着シート１０を用いてＱＦＮ等の半導体装置を製造することにより、熱硬化型接着剤のワイヤボンディング性、モールドフラッシュ防止性を維持したまま、該接着シートがプラズマクリーニング工程を経た状態においても、糊残りを防止することができ、半導体装置の不良品化を防止することができる。 Next, as shown in FIG. 2C, in the wire bonding step, the semiconductor element 30 and the leads 22 of the lead frame 20 are electrically connected through bonding wires 31 such as gold wires. Next, as shown in FIG. 2 (d), in the resin sealing step, the semiconductor device being manufactured shown in FIG. 2 (c) is placed in a mold, and a sealing resin (molding material) is used. The semiconductor element 30 is sealed with the sealing resin 40 by transfer molding (mold molding).
Next, as shown in FIG. 2E, in the adhesive sheet peeling step, the adhesive sheet 10 is peeled from the sealing resin 40 and the lead frame 20, thereby forming a QFN unit 60 in which a plurality of QFNs 50 are arranged. be able to. Finally, as shown in FIG. 2F, a plurality of QFNs 50 can be manufactured by dicing the QFN unit 60 along the outer periphery of each QFN 50 in the dicing step.
Thus, by manufacturing a semiconductor device such as QFN using the adhesive sheet 10 of the present invention, the adhesive sheet performs the plasma cleaning process while maintaining the wire bonding property and mold flash prevention property of the thermosetting adhesive. Even in such a state, the adhesive residue can be prevented, and the defective semiconductor device can be prevented.

次に、本発明に係る実施例及び比較例について説明する。
各実施例、比較例において、接着剤を調製して接着シートを作製し、得られた接着剤層や接着シートの評価を行った。 Next, examples and comparative examples according to the present invention will be described.
In each of Examples and Comparative Examples, an adhesive was prepared to produce an adhesive sheet, and the resulting adhesive layer and adhesive sheet were evaluated.

＜実施例１、２、４＞
下記表１に示す組成及び配合比（質量部）でトルエンに混合し接着剤溶液を作製した。
次に、耐熱性基材としてポリイミド樹脂フィルム（東レ・デュポン社製 商品名：カプトン１００ＥＮ、厚さ２５μm、ガラス転移温度３００℃以上、熱膨張係数１６ｐｐｍ／℃）を用い、その上に乾燥後の厚さが６μmになるように、上記接着剤溶液を塗布した後、１２０℃で５分間乾燥させ、接着剤層を有する本発明の接着シートを得た。 <Examples 1, 2, 4>
An adhesive solution was prepared by mixing with toluene at the composition and blending ratio (parts by mass) shown in Table 1 below.
Next, a polyimide resin film (trade name: Kapton 100EN, thickness 25 μm, glass transition temperature 300 ° C. or higher, thermal expansion coefficient 16 ppm / ° C., manufactured by Toray DuPont Co., Ltd.) is used as the heat resistant substrate, and after drying, The adhesive solution was applied so that the thickness was 6 μm, and then dried at 120 ° C. for 5 minutes to obtain an adhesive sheet of the present invention having an adhesive layer.

＜実施例３、６、７＞
下記表１に示す組成及び配合比でメチルエチルケトンに混合した接着剤溶液に変更した以外は実施例１と同様にして本発明の接着シートを得た。 <Examples 3, 6, and 7>
The adhesive sheet of the present invention was obtained in the same manner as in Example 1 except that the adhesive solution was mixed with methyl ethyl ketone at the composition and mixing ratio shown in Table 1 below.

＜実施例５＞
実施例１と同様の組成及び配合比で接着剤溶液を作製し、次に耐熱性基材として３／４オンスの銅箔（三井金属鉱業社製 商品名：３ＥＣ−ＶＬＰ、厚さ２５μm、熱膨張係数１６ｐｐｍ／℃）を使用し、その粗化面上に乾燥後の厚さが８μmになるように上記接着剤溶液を塗布し、１２０℃で５分間乾燥させ、接着剤層を有する本発明の接着シートを得た。 <Example 5>
An adhesive solution was prepared with the same composition and blending ratio as in Example 1, and then 3/4 ounce copper foil (trade name: 3EC-VLP, thickness 25 μm, heat produced by Mitsui Kinzoku Mining Co., Ltd.) as a heat-resistant substrate. The above-mentioned adhesive solution is applied on the roughened surface so that the thickness after drying becomes 8 μm, and dried at 120 ° C. for 5 minutes, and the present invention has an adhesive layer. An adhesive sheet was obtained.

＜比較例１、２＞
下記表１に示す組成及び配合比でメチルエチルケトンに混合した接着剤溶液に変更した以外は実施例１と同様にして比較用の接着シートを得た。 <Comparative Examples 1 and 2>
A comparative adhesive sheet was obtained in the same manner as in Example 1 except that the adhesive solution was mixed with methyl ethyl ketone at the composition and mixing ratio shown in Table 1 below.

表１に示す各成分は次の通り。
［熱硬化性樹脂成分（ａ）］
・フッ素樹脂：旭硝子社製、商品名：ルミフロンLF２００Ｆ
・エポキシ樹脂Ａ：大日本インキ化学工業社製、商品名：HP−７２００
・エポキシ樹脂Ｂ：ジャパンエポキシレジン社製、商品名：エピコート８２８
・フェノール樹脂Ａ：昭和高分子社製、商品名：ＣＫＭ２４００
・フェノール樹脂Ｂ：新日本石油化学社製、商品名：ＤＰＰ−６０９５Ｈ
［熱可塑性樹脂成分（ｂ）］
・ＮＢＲ（アクリロニトリル−ブタジエン共重合体樹脂）：ＪＳＲ社製、商品名：ＰＮＲ−１Ｈ、質量平均分子量３３０,０００
・エチレン−メチルアクリレート−グリシジルメタクリレート共重合体樹脂：住友化学社製、商品名：ボンドファースト７Ｍ、質量平均分子量７０,０００
・アクリル酸エステル−グリシジルアクリレート−アクリロニトリル共重合体：帝国化学産業社製、ＳＧ Ｐ−３ＤＲ、質量平均分子量１,０００,０００
・ＳＢＲ（スチレン−ブタジエン共重合体）：旭化成社製、商品名：タフテックＭ１９１１、質量平均分子量１１０,０００
・フッ素ゴム：デュポン・ダウ社製、商品名：バイトン ＶＴＲ−７１１９、質量平均分子量３００,０００
［その他］
・硬化剤：日本ポリウレタン工業社製、商品名：コロネートＬ
・硬化促進剤：四国化成社製、２−エチル４−メチルイミダゾール（２Ｅ４ＭＺ） Each component shown in Table 1 is as follows.
[Thermosetting resin component (a)]
・ Fluorine resin: Asahi Glass Co., Ltd., trade name: Lumiflon LF200F
Epoxy resin A: manufactured by Dainippon Ink & Chemicals, Inc., trade name: HP-7200
-Epoxy resin B: manufactured by Japan Epoxy Resin Co., Ltd., trade name: Epicoat 828
・ Phenolic resin A: Showa Polymer Co., Ltd., trade name: CKM2400
-Phenolic resin B: Shin Nippon Petrochemical Co., Ltd., trade name: DPP-6095H
[Thermoplastic resin component (b)]
NBR (acrylonitrile-butadiene copolymer resin): manufactured by JSR, trade name: PNR-1H, mass average molecular weight 330,000
-Ethylene-methyl acrylate-glycidyl methacrylate copolymer resin: manufactured by Sumitomo Chemical Co., Ltd., trade name: Bondfast 7M, mass average molecular weight 70,000
Acrylate ester-glycidyl acrylate-acrylonitrile copolymer: manufactured by Teikoku Chemical Industry Co., Ltd., SGP-3DR, mass average molecular weight 1,000,000
SBR (styrene-butadiene copolymer): manufactured by Asahi Kasei Corporation, trade name: Tuftec M1911, mass average molecular weight 110,000
Fluoro rubber: DuPont Dow, trade name: Viton VTR-7119, weight average molecular weight 300,000
[Others]
Curing agent: manufactured by Nippon Polyurethane Industry Co., Ltd., trade name: Coronate L
Curing accelerator: Shikoku Kasei Co., Ltd., 2-ethyl 4-methylimidazole (2E4MZ)

Figure 0004654062
Figure 0004654062

＜貯蔵弾性率の測定＞
前記実施例及び比較例において得られた接着剤溶液を離型フィルム上に塗布した後、接着シートを作製する際と同じ乾燥条件にて乾燥し、更にダイアタッチ工程の熱処理条件（１７５℃で２時間）で熱処理を行い、接着剤層付き離型性フィルムを作製した。なお、乾燥後の厚さが０.１ｍｍになるように接着剤の塗布、乾燥を行った。得られたサンプルを５ｍｍ×３０ｍｍに切断し、弾性率測定装置（オリエンテック社製レオバイブロンＤＤＶ−II）を用いて、周波数１１Ｈｚ、昇温速度３℃／ｍｉｎ、測定温度範囲１５０℃〜２５０℃で測定を行い、その結果を表２に示した。なお、表２の数値は、測定温度範囲１５０℃〜２５０℃における貯蔵弾性率の最小値を示す。 <Measurement of storage modulus>
After the adhesive solutions obtained in the examples and comparative examples were applied on the release film, the adhesive solution was dried under the same drying conditions as those for producing the adhesive sheet, and further the heat treatment conditions (2 at 175 ° C. at 175 ° C.). Heat treatment was performed in (time) to prepare a release film with an adhesive layer. The adhesive was applied and dried so that the thickness after drying was 0.1 mm. The obtained sample was cut into 5 mm × 30 mm and using an elastic modulus measuring device (Orientec's Leo Vibron DDV-II) at a frequency of 11 Hz, a temperature increase rate of 3 ° C./min, and a measurement temperature range of 150 ° C. to 250 ° C. The measurement was performed and the results are shown in Table 2. In addition, the numerical value of Table 2 shows the minimum value of the storage elastic modulus in the measurement temperature range 150 degreeC-250 degreeC.

＜接着シートの評価＞
１．ワイヤボンディング不良
各実施例及び比較例において得られた接着シートを、外寸２００ｍｍ×６０ｍｍのＱＦＮ用リードフレーム（Ａｕ−Ｐｄ−ＮｉメッキＣｕリードフレーム、４×１６個（計６４個）のマトリックス配列、パッケージサイズ１０ｍｍ×１０ｍｍ、８４ピン）にラミネート法により貼着した。次いで、エポキシ系ダイアタッチ剤を用いてアルミニウムが蒸着されたダミーチップ（６ｍｍ×６ｍｍ、厚さ０.４ｍｍ）をリードフレームの半導体素子搭載部に搭載した。得られたサンプルの半数について、プラズマクリーニングを行った。プラズマクリーニング条件は、プラズマエッチング装置（ヤマト科学社製、商品名：Ｖ１０００）を用いて、使用ガス：Ａｒ、ガス流量：４５sccm、ＲＦ出力：４５０Ｗ、処理時間：５分である。その後、ワイヤボンダー（新川社製、ＵＴＣ−４７０ＢＩ）を用い、加熱温度を２１０℃、ＵＳ ＰＯＷＥＲを３０、荷重を０.５９Ｎ、処理時間を１０ｍｓｅｃ／ピンとして、ダミーチップとリードとを金ワイヤにより電気的に接続した。得られた半導体装置６４個を検査し、リード側接続不良が発生した半導体装置数を、ワイヤボンディング不良の発生個数として検出し、その結果を表２に示した。 <Evaluation of adhesive sheet>
1. Wire bonding failure Adhesive sheets obtained in each of the examples and comparative examples were arranged in a matrix arrangement of lead frames for QFN (Au—Pd—Ni plated Cu lead frames, 4 × 16 pieces (total of 64 pieces)) having an outer size of 200 mm × 60 mm. , Package size 10 mm × 10 mm, 84 pins). Next, a dummy chip (6 mm × 6 mm, thickness 0.4 mm) on which aluminum was deposited using an epoxy die attach agent was mounted on the semiconductor element mounting portion of the lead frame. About half of the obtained samples were subjected to plasma cleaning. Plasma cleaning conditions are as follows: using a plasma etching apparatus (trade name: V1000, manufactured by Yamato Kagaku Co., Ltd.), gas used: Ar, gas flow rate: 45 sccm, RF output: 450 W, processing time: 5 minutes. After that, using a wire bonder (manufactured by Shinkawa Co., Ltd., UTC-470BI), heating temperature is 210 ° C., US POWER is 30, load is 0.59 N, processing time is 10 msec / pin, dummy chip and lead are made of gold wire Electrically connected. The obtained 64 semiconductor devices were inspected, and the number of semiconductor devices in which a lead-side connection failure occurred was detected as the number of wire bonding failures, and the results are shown in Table 2.

２．モールドフラッシュ
ワイヤボンディング不良の評価後のリードフレームを用いてモールドフラッシュの評価を行った。先ずプラズマクリーニングを実施したフレームと実施しないフレームに分け、それぞれエポキシ系モールド剤（ビフェニルエポキシ系、フイラー量８５質量％）を用い、加熱温度を１８０℃、圧力を１０ＭＰａ、処理時間を３分間として、トランスファーモールド（金型成型）により、ダミーチップを封止樹脂により封止した。樹脂封止後の半導体装置６４個を検査し、リードの外部接続用部分（リードの接着シート側の面）に封止樹脂が付着している半導体装置数を、モールドフラッシュの発生個数として検出し、その結果を表２に示した。 2. Mold flash The mold flash was evaluated using the lead frame after the evaluation of the wire bonding failure. First, it is divided into a frame that has been subjected to plasma cleaning and a frame that is not to be used, each using an epoxy molding agent (biphenyl epoxy, filler amount 85 mass%), heating temperature 180 ° C., pressure 10 MPa, treatment time 3 minutes, The dummy chip was sealed with a sealing resin by transfer molding (mold molding). 64 semiconductor devices after resin sealing were inspected, and the number of semiconductor devices with sealing resin adhering to the external connection portion of the lead (the surface of the lead on the adhesive sheet side) was detected as the number of mold flash occurrences. The results are shown in Table 2.

３．糊残り
プラズマクリーニングの有無を含むモールドフラッシュの評価後のリードフレームを用い、糊残りの評価を行った。先ず接着シートをリードフレームから剥離速度５００ｍｍ／ｍｉｎの条件で剥離した。接着シートの剥離後の半導体装置６４個を検査し、リードの外部接続用部分、モールド樹脂面を含む接着シート剥離面に接着剤が付着している半導体装置個数を、糊残りの発生数として表２に示した。 3. Adhesive residue An adhesive residue was evaluated using a lead frame after evaluation of mold flash including the presence or absence of plasma cleaning. First, the adhesive sheet was peeled from the lead frame at a peeling speed of 500 mm / min. 64 semiconductor devices after peeling the adhesive sheet were inspected, and the number of semiconductor devices in which the adhesive adhered to the adhesive sheet peeling surface including the lead external connection portion and the mold resin surface was expressed as the number of remaining adhesives. It was shown in 2.

４．接着強度
各実施例及び比較例において得られた接着シートを１ｃｍ幅に切断し、５０ｍｍ×１００ｍｍ×０.２５ｍｍｔの銅板（三菱メテックス社製 商品名：ＭＦ−２０２）、及びに銅板に金メッキした板に、ロールラミネーションにより圧着させた。次にダイアタッチキュア（１７５℃ １時間）、モールド樹脂キュア（１８０℃ ４時間）相当の熱履歴後、常温に戻した。これらの板を１５０℃に加熱し、得られた積層体の接着剤層を板に対して９０°方向に引き剥がしたときの剥離強度を測定した。同様に、この剥離強度の測定を、板の加熱温度を１５０℃から２００℃まで５℃ごとに上昇させて行った。そして、１５０〜２００℃の各測定温度における剥離強度のうち最小値を接着シートの接着強度とし、その結果を表２に示した。 4). Adhesive strength The adhesive sheets obtained in each of the examples and comparative examples were cut to a width of 1 cm, and a 50 mm × 100 mm × 0.25 mmt copper plate (trade name: MF-202, manufactured by Mitsubishi Metex Co., Ltd.) and a copper plate plated with gold And crimped by roll lamination. Next, after a thermal history corresponding to die attach cure (175 ° C. for 1 hour) and mold resin cure (180 ° C. for 4 hours), the temperature was returned to room temperature. These plates were heated to 150 ° C., and the peel strength when the adhesive layer of the obtained laminate was peeled away from the plates in the 90 ° direction was measured. Similarly, this peel strength was measured by increasing the heating temperature of the plate from 150 ° C. to 200 ° C. every 5 ° C. And the minimum value was made into the adhesive strength of an adhesive sheet among the peeling strength in each measurement temperature of 150-200 degreeC, and the result was shown in Table 2.

Figure 0004654062
Figure 0004654062

表２に示すように、本発明の接着シートは、プラズマクリーニングを実施したリードフレームにおいて、ワイヤボンディング不良、モールドフラッシュ及び糊残りが全く発生しなかった。これに対し、フッ素を含有しない比較例では、糊残りの発生数が多かった。   As shown in Table 2, the adhesive sheet of the present invention had no wire bonding failure, mold flash, and adhesive residue at all in the lead frame subjected to plasma cleaning. On the other hand, in the comparative example not containing fluorine, the number of remaining adhesives was large.

本発明の半導体装置製造用接着シートを用いてＱＦＮを製造する際に用いて好適なリードフレームの一例を示す概略平面図である。It is a schematic plan view which shows an example of a suitable lead frame used when manufacturing QFN using the adhesive sheet for semiconductor device manufacture of this invention. ＱＦＮの製造工程例を示すもので、図１のＡ−Ａ’断面図である。FIG. 3 is a cross-sectional view taken along the line A-A ′ of FIG. 1, illustrating an example of a manufacturing process of QFN.

符号の説明Explanation of symbols

１０ 半導体装置製造用接着シート
２０ リードフレーム
３０ 半導体素子
３１ ボンディングワイヤ
４０ 封止樹脂 DESCRIPTION OF SYMBOLS 10 Adhesive sheet for semiconductor device manufacture 20 Lead frame 30 Semiconductor element 31 Bonding wire 40 Sealing resin

Claims (9)

半導体装置のリードフレームまたは配線基板に剥離可能に貼着した後に該リードフレームまたは配線基板から剥離される半導体装置製造用接着シートにおいて、
基材と樹脂成分を含有する接着剤層とを具備し、
前記樹脂成分が熱硬化性樹脂成分（ａ）と熱可塑性樹脂成分（ｂ）からなり、該熱硬化性樹脂成分（ａ）と熱可塑性樹脂成分（ｂ）のいずれかが、フッ素を含有するオレフィン系樹脂であることを特徴とする半導体装置製造用接着シート。 In the adhesive sheet for manufacturing a semiconductor device that is peeled off from the lead frame or the wiring board after being detachably attached to the lead frame or the wiring board of the semiconductor device,
Comprising a base material and an adhesive layer containing a resin component ;
Olefin wherein the resin component comprises a thermosetting resin component (a) and the thermoplastic resin component (b), either thermosetting resin component (a) and the thermoplastic resin component (b) is a fluorine-containing An adhesive sheet for manufacturing a semiconductor device, characterized in that it is a resin. 半導体装置のリードフレームに貼着して硬化した接着剤層の１５０〜２００℃における接着強度が０.０３〜５Ｎ／ｃｍであることを特徴とする請求項１に記載の半導体装置製造用接着シート。   2. The adhesive sheet for manufacturing a semiconductor device according to claim 1, wherein an adhesive strength at 150 to 200 ° C. of the adhesive layer adhered and cured to the lead frame of the semiconductor device is 0.03 to 5 N / cm. . 前記接着剤層の熱硬化性樹脂成分（ａ）及び熱可塑性樹脂成分（ｂ）の質量比率（ａ）／（ｂ）が０.０５〜０.４３であることを特徴とする請求項１又は２に記載の半導体装置製造用接着シート。   The mass ratio (a) / (b) of the thermosetting resin component (a) and the thermoplastic resin component (b) of the adhesive layer is 0.05 to 0.43. 2. An adhesive sheet for manufacturing a semiconductor device according to 2. 熱可塑性樹脂成分（ｂ）の質量平均分子量が２,０００〜１,０００,０００であることを特徴とする請求項１、２、３のいずれか一項に記載の半導体装置製造用接着シート。   The adhesive sheet for manufacturing a semiconductor device according to any one of claims 1, 2, and 3, wherein the thermoplastic resin component (b) has a mass average molecular weight of 2,000 to 1,000,000. 前記接着剤層の硬化後の貯蔵弾性率が、１５０〜２５０℃にて、０.１ＭＰａ以上であることを特徴とする請求項１〜４のいずれかに記載の半導体装置製造用接着シート。   The adhesive sheet for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein a storage elastic modulus of the adhesive layer after curing is 0.1 MPa or more at 150 to 250 ° C. 前記基材が、ガラス転位温度が１５０℃以上、熱膨張係数が５〜５０ｐｐｍ／℃の耐熱性フィルムであることを特徴とする請求項１〜５のいずれかに記載の半導体装置製造用接着シート。   The adhesive sheet for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein the base material is a heat resistant film having a glass transition temperature of 150 ° C or higher and a thermal expansion coefficient of 5 to 50 ppm / ° C. . 前記基材が、熱膨張係数が５〜５０ｐｐｍ／℃の金属箔であることを特徴とする請求項１〜６のいずれかに記載の半導体装置製造用接着シート。   The adhesive sheet for manufacturing a semiconductor device according to claim 1, wherein the base material is a metal foil having a thermal expansion coefficient of 5 to 50 ppm / ° C. 接着剤層の片面に保護フィルムが設けられていることを特徴とする請求項１〜７のいずれかに記載の半導体装置製造用接着シート。   The adhesive sheet for manufacturing a semiconductor device according to claim 1, wherein a protective film is provided on one surface of the adhesive layer. 請求項１〜８のいずれかに記載の半導体装置製造用接着シートを用いて製造することを特徴とする半導体装置の製造方法。   A method for manufacturing a semiconductor device, wherein the manufacturing method is performed using the adhesive sheet for manufacturing a semiconductor device according to claim 1.
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JP2009016319A (en) * 2007-07-09 2009-01-22 Sumitomo Metal Mining Co Ltd Insulated coating metal thin wire
JP2009044010A (en) * 2007-08-09 2009-02-26 Nitto Denko Corp Manufacturing method of semiconductor device
JP5551568B2 (en) * 2009-11-12 2014-07-16 日東電工株式会社 Resin-sealing adhesive tape and method for manufacturing resin-sealed semiconductor device using the same
EP2554593B1 (en) * 2010-03-31 2015-07-01 Kuraray Co., Ltd. Thermoplastic polymer composition and moldings thereof
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JP5824402B2 (en) * 2012-04-02 2015-11-25 株式会社巴川製紙所 Mask sheet for manufacturing semiconductor device and method for manufacturing semiconductor device using the same
TW201528449A (en) * 2013-11-07 2015-07-16 Asahi Glass Co Ltd Mold release film and semiconductor package manufacturing method
JP6322026B2 (en) * 2014-03-31 2018-05-09 日東電工株式会社 Die bond film, die bond film with dicing sheet, semiconductor device, and method for manufacturing semiconductor device
CN109326529B (en) * 2018-09-29 2020-04-24 中电智能卡有限责任公司 DFN/QFN production process
CN110684481B (en) * 2019-09-19 2022-03-04 浙江耀阳新材料科技有限公司 Controllable-viscosity adhesive tape and application method thereof

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001205763A (en) * 2000-01-26 2001-07-31 Teijin Ltd Protective film for prepreg
JP2001250838A (en) * 1999-12-27 2001-09-14 Nitto Denko Corp Resin dealing method for semiconductor and releasing film for sealing semiconductor
JP2002212525A (en) * 2001-01-22 2002-07-31 Hitachi Chem Co Ltd Adhesive film for semiconductor, substrate for mounting semiconductor chip and semiconductor device
JP2004289077A (en) * 2003-03-25 2004-10-14 Toray Ind Inc Semiconductor-use adhesive composition, semiconductor-use adhesive sheet using it, board for connecting semiconductor integrated circuit, and semiconductor device
JP2004296549A (en) * 2003-03-25 2004-10-21 Tomoegawa Paper Co Ltd Adhesive sheet for semiconductor device manufacture, semiconductor device using it and manufacturing method
JP2005056888A (en) * 2003-08-04 2005-03-03 Nitto Denko Corp Heat-resistant sheet

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001250838A (en) * 1999-12-27 2001-09-14 Nitto Denko Corp Resin dealing method for semiconductor and releasing film for sealing semiconductor
JP2001205763A (en) * 2000-01-26 2001-07-31 Teijin Ltd Protective film for prepreg
JP2002212525A (en) * 2001-01-22 2002-07-31 Hitachi Chem Co Ltd Adhesive film for semiconductor, substrate for mounting semiconductor chip and semiconductor device
JP2004289077A (en) * 2003-03-25 2004-10-14 Toray Ind Inc Semiconductor-use adhesive composition, semiconductor-use adhesive sheet using it, board for connecting semiconductor integrated circuit, and semiconductor device
JP2004296549A (en) * 2003-03-25 2004-10-21 Tomoegawa Paper Co Ltd Adhesive sheet for semiconductor device manufacture, semiconductor device using it and manufacturing method
JP2005056888A (en) * 2003-08-04 2005-03-03 Nitto Denko Corp Heat-resistant sheet

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