JP4649976B2 - PWM controller for power converter - Google Patents

PWM controller for power converter Download PDF

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JP4649976B2
JP4649976B2 JP2004365170A JP2004365170A JP4649976B2 JP 4649976 B2 JP4649976 B2 JP 4649976B2 JP 2004365170 A JP2004365170 A JP 2004365170A JP 2004365170 A JP2004365170 A JP 2004365170A JP 4649976 B2 JP4649976 B2 JP 4649976B2
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power converter
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current
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JP2006174625A (en
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宣之 小林
英俊 海田
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Fuji Electric Co Ltd
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この発明は、インバータ等の電力変換器を構成する半導体スイッチ素子をパルス幅変調（ＰＷＭ）制御するＰＷＭ制御装置、特に出力電圧および電流の波形改善技術に関する。   The present invention relates to a PWM control device that performs pulse width modulation (PWM) control of a semiconductor switch element that constitutes a power converter such as an inverter, and more particularly to a technique for improving waveforms of output voltage and current.

図３に、例えば特許文献１に開示されているＰＷＭインバータの例を示す。
図３において、１はインバータで、直流電源２とＵ相アーム（Ｕ相レグ）３およびＶ相アーム（Ｖ相レグ）４から構成される。Ｕ相レグ３は半導体スイッチ３ａ，３ｂと、これらに逆並列に接続されたダイオード３ｃ，３ｄからなり、Ｖ相レグ４は半導体スイッチ４ａ，４ｂと、これらに逆並列に接続されたダイオード４ｃ，４ｄからなっている。 FIG. 3 shows an example of a PWM inverter disclosed in Patent Document 1, for example.
In FIG. 3, reference numeral 1 denotes an inverter, which includes a DC power source 2, a U-phase arm (U-phase leg) 3, and a V-phase arm (V-phase leg) 4. The U-phase leg 3 includes semiconductor switches 3a and 3b and diodes 3c and 3d connected in antiparallel thereto, and the V-phase leg 4 includes semiconductor switches 4a and 4b and diodes 4c, 4c connected in antiparallel thereto. 4d.

これらの半導体スイッチ３ａ，３ｂ，４ａ，４ｂはそれぞれ、制御装置１０から出力されるゲート信号ＧＵ，ＧＸ，ＧＶ，ＧＹに基づきオン・オフ動作する。そして、このスイッチング動作により、リアクトル７およびコンデンサ８で構成されるフィルタを介して、負荷５に正弦波状の電圧を供給している。制御装置１０は加算器１１，変調波生成部１２，ゲート信号生成部１３および切替えスイッチ１４等からなる。その動作について、以下に説明する。   These semiconductor switches 3a, 3b, 4a, 4b are turned on / off based on gate signals GU, GX, GV, GY output from the control device 10, respectively. By this switching operation, a sinusoidal voltage is supplied to the load 5 through a filter composed of the reactor 7 and the capacitor 8. The control device 10 includes an adder 11, a modulation wave generation unit 12, a gate signal generation unit 13, a changeover switch 14, and the like. The operation will be described below.

加算器１１および切替えスイッチ１４は、上下アームの半導体スイッチ素子（３ａと３ｂまたは４ａと４ｂ）がともにオフする期間、すなわちデッドタイムの影響により生じる出力電圧および電流の波形歪を補償するものである。切替えスイッチ１４では、電流検出器６で検出した出力電流の検出値Ｉｏｕｔがしきい値＋Ｉｔｈよりも大きい場合（Ｉｏｕｔ＞Ｉｔｈ）は、その補償量として＋Ｖｄｔを選択し、検出値Ｉｏｕｔがしきい値−Ｉｔｈよりも小さい場合（Ｉｏｕｔ＜−Ｉｔｈ）は、その補償量として−Ｖｄｔを選択する。   The adder 11 and the changeover switch 14 compensate for the waveform distortion of the output voltage and current caused by the influence of dead time, that is, the period when both the upper and lower arm semiconductor switch elements (3a and 3b or 4a and 4b) are turned off. . In the changeover switch 14, when the detected value Iout of the output current detected by the current detector 6 is larger than the threshold value + Ith (Iout> Ith), + Vdt is selected as the compensation amount, and the detected value Iout is the threshold value. When it is smaller than -Ith (Iout <-Ith), -Vdt is selected as the compensation amount.

そして、加算器１１により、出力電圧指令Ｖｏｕｔ*に補償量を加算することで、デッドタイム補償を行なっている。また、切替えスイッチ１４は、検出値Ｉｏｕｔがしきい値−Ｉｔｈ以上で、かつ＋Ｉｔｈ以下の場合（−Ｉｔｈ≦Ｉｏｕｔ≦＋Ｉｔｈ）は、その出力として“０”を選択し、デッドタイム補償を行なわないようにしている。変調波生成部１２は、デッドタイム補償後の出力電圧指令Ｖｏｕｔ１*に基づき、Ｕ相およびＶ相の変調波ＰＷＭＵおよびＰＷＭＶを出力し、ゲート信号生成部１３は変調波ＰＷＭＵまたはＰＷＭＶを三角波キャリアと比較することにより、デッドタイムを含んだ各半導体スイッチのゲート信号ＧＵ，ＧＸ，ＧＶ，ＧＹを出力し、各半導体スイッチをオン・オフさせている。 The adder 11 adds a compensation amount to the output voltage command Vout * to compensate for dead time. Further, when the detection value Iout is not less than the threshold value −Ith and not more than + Ith (−Ith ≦ Iout ≦ + Ith), the changeover switch 14 selects “0” as the output and does not perform dead time compensation. I am doing so. Modulation wave generation unit 12 outputs U-phase and V-phase modulation waves PWMU and PWMV based on output voltage command Vout1 * after dead time compensation, and gate signal generation unit 13 uses modulation wave PWMU or PWMV as a triangular wave carrier. By comparison, gate signals GU, GX, GV, and GY of each semiconductor switch including dead time are output, and each semiconductor switch is turned on / off.

特開２００２−１５９１８５号公報（第３頁、図３，４）JP 2002-159185 A (3rd page, FIGS. 3 and 4)

ＰＷＭ制御により、一般的に出力電流にリプルが生じる。この電流リプルの山または谷のタイミングは、Ｕ相またはＶ相のデッドタイム期間であるため、山または谷の電流値がゼロ付近にあると、デッドタイム期間中のＵ相またはＶ相の上下のダイオード（３ｃ，３ｄ，４ｃ，４ｄ）はともにオンせず、その出力電位が不定となる。その結果、出力電流のゼロクロス付近において、出力電圧および電流の波形に歪が生じるという問題がある。
したがって、この発明の課題は、出力電流のゼロクロス付近における出力電圧，電流波形歪を抑制することにある。 The PWM control generally causes a ripple in the output current. Since the peak or valley timing of this current ripple is the dead time period of the U phase or the V phase, if the current value of the peak or valley is near zero, the top and bottom of the U phase or V phase during the dead time period The diodes (3c, 3d, 4c, 4d) are not turned on, and their output potentials are indefinite. As a result, there is a problem that the output voltage and current waveforms are distorted near the zero cross of the output current.
Accordingly, an object of the present invention is to suppress output voltage and current waveform distortion in the vicinity of the zero cross of the output current.

このような課題を解決するため、この発明では、出力電流リプルの山または谷の電流値がゼロ付近にあると、出力電圧および電流の波形に歪が生じることから、出力電流のゼロクロス付近において電流リプルの振幅を増やし、出力電流リプルの山または谷の電流値がゼロ付近にならないようにすることを特徴とする。   In order to solve such a problem, in the present invention, if the current value of the peak or valley of the output current ripple is near zero, the output voltage and current waveforms are distorted. The ripple amplitude is increased so that the current value of the peak or valley of the output current ripple does not become near zero.

電流リプルの振幅を増やということは、例えば図２に示すように、三角波の山と谷で（または山ごと、谷ごとに）その極性の異なる値を出力電圧指令に加算し、加算後の出力電圧指令に基づき各相の変調波を生成することで可能である。
図２は出力電圧指令２２が０Ｖの時の例を示し、三角波キャリア２１の山と谷でその極性の異なる値を出力電圧指令２２に加算すると、Ｕ相とＶ相の線間にパルス状の電圧（リプル振幅増加処理後波形：新たな出力電圧指令２３）が正負交互に出力され、出力電流２４の振幅が図示のように増加し、その平均電圧が出力電圧指令に一致して０Ｖとなる。 Increasing the amplitude of the current ripple means that, for example, as shown in FIG. 2, values having different polarities are added to the output voltage command at the peaks and valleys of the triangular wave (or for each peak and valley), This is possible by generating a modulated wave of each phase based on the output voltage command.
FIG. 2 shows an example when the output voltage command 22 is 0V. When values having different polarities at the peaks and valleys of the triangular wave carrier 21 are added to the output voltage command 22, a pulse-like waveform is formed between the U-phase and V-phase lines. Voltage (waveform after ripple amplitude increase processing: new output voltage command 23) is output alternately, and the amplitude of the output current 24 increases as shown in the figure, and the average voltage matches the output voltage command and becomes 0V. .

以上のように、三角波の山と谷でその極性の異なる値を出力電圧指令に加算することにより、出力される平均電圧を出力電圧指令に維持しながら、出力電流リプルの振幅を増加させることが可能であり、出力電圧および出力電流の波形歪を抑制することができる。また、出力電流のゼロクロス付近でそのリプルの振幅を増やすことにより、キャリア一周期の間に電流リプルが正負交互に流れ、各相においてデッドタイム期間中の電流リプルの極性は交互に変化する。これにより、各相で１キャリアあたりにデッドタイム期間は二回存在するが、その影響は互いに打ち消しあい、デッドタイムによる波形歪は発生しない。   As described above, the amplitude of the output current ripple can be increased while maintaining the average voltage to be output in the output voltage command by adding values having different polarities at the peaks and valleys of the triangular wave to the output voltage command. This is possible, and waveform distortion of the output voltage and output current can be suppressed. Further, by increasing the amplitude of the ripple near the zero crossing of the output current, the current ripple flows alternately between positive and negative during one carrier cycle, and the polarity of the current ripple in the dead time period alternately changes in each phase. As a result, there are two dead time periods per carrier in each phase, but their influences cancel each other and waveform distortion due to dead time does not occur.

この発明によれば、出力電流のゼロクロス付近において、出力電流リプルの振幅を増加させることにより、各相のデッドタイム期間と出力電流が０Ａとなるタイミングが一致することが防止され、出力電圧および出力電流の波形歪を抑制することができる。   According to the present invention, by increasing the amplitude of the output current ripple in the vicinity of the zero cross of the output current, it is possible to prevent the dead time period of each phase from coincident with the timing when the output current becomes 0 A, and the output voltage and output Current waveform distortion can be suppressed.

図１はこの発明の実施の形態を示す構成図である。
図１からも明らかなように、図３に示すものに対し切替えスイッチ１５および加算器１６を付加した点が特徴である。その他は図３と同様なので、以下ではその相違点を主に説明する。
上記切替えスイッチ１５および加算器１６は、出力電流がゼロクロス付近にあるときに、出力電流のリプルを増加させるためのもので、切替えスイッチ１５は出力電流検出値Ｉｏｕｔおよび三角波キャリアに基づき、以下のようにその出力を決定する。 FIG. 1 is a block diagram showing an embodiment of the present invention.
As is apparent from FIG. 1, the changeover switch 15 and the adder 16 are added to the configuration shown in FIG. Others are the same as in FIG. 3, and the differences will be mainly described below.
The changeover switch 15 and the adder 16 are for increasing the ripple of the output current when the output current is in the vicinity of the zero cross. The changeover switch 15 is based on the output current detection value Iout and the triangular wave carrier as follows. Determine its output.

検出値Ｉｏｕｔがしきい値＋Ｉｔｈよりも大きい（Ｉｏｕｔ＞＋Ｉｔｈ）か、またはしきい値−Ｉｔｈよりも小さい（Ｉｏｕｔ＜−Ｉｔｈ）場合は、その出力として“０”を選択する。また、検出値Ｉｏｕｔがしきい値−Ｉｔｈ以上、かつ＋Ｉｔｈ以下の場合（−Ｉｔｈ≦Ｉｏｕｔ≦＋Ｉｔｈ）で、しかも三角波キャリアが下り期間のときは、その出力として＋Ｖｏｆｓを選択し、上り期間のときはその出力として−Ｖｏｆｓを選択する。   When the detection value Iout is larger than the threshold value + Ith (Iout> + Ith) or smaller than the threshold value −Ith (Iout <−Ith), “0” is selected as the output. When the detection value Iout is not less than the threshold value −Ith and not more than + Ith (−Ith ≦ Iout ≦ + Ith), and the triangular wave carrier is in the down period, + Vofs is selected as the output thereof, and in the up period Selects -Vofs as its output.

加算器１６は、デッドタイム補償後の出力電圧指令Ｖｏｕｔ１*と切替えスイッチ１５の出力とを加算し、変調波生成部１２に対して出力電圧指令（新たな出力電圧指令）Ｖｏｕｔ２*を出力する。
以上のように、出力電圧指令Ｖｏｕｔ２*を決定することにより、出力電流のゼロクロス付近において、出力電流リプルの振幅を増加させることができ（図２参照）、出力電圧および電流の波形歪を抑制することができる。 The adder 16 adds the output voltage command Vout1 * after the dead time compensation and the output of the changeover switch 15 and outputs an output voltage command (new output voltage command) Vout2 * to the modulated wave generator 12.
As described above, by determining the output voltage command Vout2 * , the amplitude of the output current ripple can be increased in the vicinity of the zero cross of the output current (see FIG. 2), and waveform distortion of the output voltage and current is suppressed. be able to.

この発明の実施の形態を示す構成図Configuration diagram showing an embodiment of the present invention 図１の動作を説明する各部波形図Waveform diagram of each part for explaining the operation of FIG. 従来方式を示す構成図Configuration diagram showing the conventional method

符号の説明Explanation of symbols

１…インバータ、２…直流電源、３…Ｕ相アーム（Ｕ相レグ）、３ａ，３ｂ，４ａ，４ｂ…半導体スイッチ、３ｃ，３ｄ，４ｃ，４ｄ…ダイオード、４…Ｖ相アーム（Ｖ相レグ）、５…負荷、６…電流検出器、７…リアクトル、８…コンデンサ、１０…制御装置、１１，１６…加算器、１２…変調波生成部、１３…ゲート信号生成部、１４，１５…切替えスイッチ。   DESCRIPTION OF SYMBOLS 1 ... Inverter, 2 ... DC power supply, 3 ... U-phase arm (U-phase leg), 3a, 3b, 4a, 4b ... Semiconductor switch, 3c, 3d, 4c, 4d ... Diode, 4 ... V-phase arm (V-phase leg) ) 5 ... Load, 6 ... Current detector, 7 ... Reactor, 8 ... Condenser, 10 ... Control device, 11, 16 ... Adder, 12 ... Modulated wave generator, 13 ... Gate signal generator, 14, 15 ... Changeover switch.

Claims (1)

電力変換器を構成する半導体スイッチに対し、前記電力変換器の出力電流検出値に応じて、デッドタイム補償を考慮した指令値と三角波キャリアとの比較結果に基づくオン・オフ信号を与えて、パルス幅変調（ＰＷＭ）を行なう電力変換器のＰＷＭ制御装置において、
前記電力変換器の出力電流検出値の絶対値が所定値も小さいときは、前記指令値に出力電流リプルの振幅を増加させるための前記三角波キャリアの山と谷で極性が反転する所定値を加算する加算手段を設け、その加算された値を新たな指令値として、ＰＷＭ制御を行なうことを特徴とする電圧駆動型半導体素子の電圧ばらつき抑制方式。

An on / off signal based on a comparison result between a command value considering dead time compensation and a triangular wave carrier is given to the semiconductor switch constituting the power converter in accordance with the output current detection value of the power converter, and the pulse In a PWM controller for a power converter that performs width modulation (PWM),
When the absolute value of the output current detection value of the power converter is smaller than a predetermined value, a predetermined value whose polarity is inverted at the peak and valley of the triangular wave carrier for increasing the amplitude of the output current ripple is added to the command value. And a voltage variation suppression method for a voltage-driven semiconductor element, wherein PWM control is performed using the added value as a new command value.

JP2004365170A 2004-12-17 2004-12-17 PWM controller for power converter Expired - Fee Related JP4649976B2 (en)

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JP5316514B2 (en) * 2010-11-02 2013-10-16 株式会社日本自動車部品総合研究所 Power converter

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60207464A (en) * 1984-03-30 1985-10-19 Yuzuru Tsunehiro Control circuit of inverter
JP2001145368A (en) * 1999-11-18 2001-05-25 Fuji Electric Co Ltd Method for compensating dead time of voltage pwm inverter
JP2002159185A (en) * 2000-11-15 2002-05-31 Mitsubishi Heavy Ind Ltd Current control method
JP2003180083A (en) * 2001-12-10 2003-06-27 Meidensha Corp Voltage-type pwm inverter device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60207464A (en) * 1984-03-30 1985-10-19 Yuzuru Tsunehiro Control circuit of inverter
JP2001145368A (en) * 1999-11-18 2001-05-25 Fuji Electric Co Ltd Method for compensating dead time of voltage pwm inverter
JP2002159185A (en) * 2000-11-15 2002-05-31 Mitsubishi Heavy Ind Ltd Current control method
JP2003180083A (en) * 2001-12-10 2003-06-27 Meidensha Corp Voltage-type pwm inverter device

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