JP6270696B2 - Power converter - Google Patents

Description

  Embodiments described herein relate generally to a power converter that reduces low-order harmonics of an inverter output voltage.

  A three-level power converter is known as a power converter that performs conversion from DC power to AC power. This three-level power converter reduces the harmonics of the basic output on the AC side by connecting two smoothing capacitors in series on the DC side and setting the DC potential to three levels: positive, negative, and zero. Further, by applying PWM (pulse width modulation) control, it is possible to set the modulation frequency higher than the AC frequency and reduce lower harmonics.

  However, if the modulation frequency of PWM control is increased, the switching loss of the switching elements used in the three-level power converter increases, and the conversion efficiency of the three-level power converter decreases. For this reason, proposals have been made to control a three-level power converter with a fixed pulse pattern that reduces harmonic components contained in AC voltage (see Patent Documents 1 and 2). When the number of pulses per half cycle of the fundamental wave of the output voltage is 3 pulses in Patent Document 1 and 5 pulses in Patent Document 2, an optimal fixed pulse pattern in the power converter is derived.

  Patent Documents 1 and 2 propose a three-level converter. Since the circuit configuration of the inverter is the same, harmonics can be similarly reduced by a fixed pulse pattern.

JP 2002-78346 A JP2011-193583

Converter is the input frequency is fixed to the frequency of the commercial power supply, the inverter can be arbitrarily controlled as a frequency of the output frequency is input to the motor. In a three-level power converter using a pulse pattern, the width of each pulse decreases as the output frequency increases, so the number of output pulses needs to be reduced at a certain output frequency.

  According to the methods described in Patent Documents 1 and 2, the optimum fixed pulse pattern is proposed when the number of pulses per half cycle of the fundamental wave of the output voltage is 3 pulses and 5 pulses in the three-level power converter. Yes. However, when the number of pulses is switched from 3 pulses to 5 pulses or from 5 pulses to 3 pulses, the pulse pattern on the phase reference of the output voltage is different, so that the pulses become discontinuous and torque shock occurs.

  The present invention has been made to solve the above-described problem, and an object of the present invention is to provide a power conversion device capable of torque pulse-less pulse pattern transition that prevents torque shock when switching the number of pulses of a fixed pulse pattern. And

In order to achieve the above object, a power converter according to the present invention includes a three-level converter that converts AC power into DC power and a power converter that includes a three-level inverter that converts DC power into AC power. A smoothing capacitor connected to the DC power output side of the level converter and a plurality of fixed pulse patterns with different pulse patterns individually to reduce low-order harmonics of the basic output of AC power input to the three-level converter A plurality of fixed pulse pattern setting means for setting, a pulse pattern switching means for selectively switching the fixed pulse pattern set by the fixed pulse pattern setting means, and the fixed pulse pattern switched by the pulse pattern switching means in a shockless manner Shockless switching means of fixed pulse pattern to switch Fixed pulse pattern modulation means for modulating the fixed pulse pattern switched by the shockless switching means to input to the three-level converter, and AC input current of AC power input to the three-level converter at predetermined time intervals Current detecting means for detecting, current control means for outputting to the fixed pulse pattern modulating means a phase reference that minimizes a deviation between the alternating current detected by the current detecting means and a separately set current reference; The fixed pulse pattern modulating means includes a pulse set by the shockless switching means based on a control result by the current control means, and a pulse of the switching element constituting the three-level converter. applied to the gate, the shockless switching means, fixed Parusupata When switching the number of pulses, the additional pulse with a narrow width is added to both ends of the fixed pulse pattern before switching in the half cycle of the fundamental wave, and before and after the additional pulse is added, A pulse pattern set by performing an operation of narrowing the pulse width of the fixed pulse before the change is output so that the effective value of the next voltage reference is the same.

  According to the present invention, it is possible to shift the pulse pattern without torque shock when switching the number of pulses of the fixed pulse pattern.

The block diagram which shows the structure of the power converter device which concerns on a present Example. The circuit diagram of the principal part of the 3 level converter which comprises a power converter device. The graph which shows the relationship between the output frequency at the time of applying this invention to a 3 level inverter, and the number of pulses. The figure explaining the operation | movement of the switching of the conventional 3 pulse fixed pattern and a 5 pulse fixed pattern. The figure explaining the operation | movement of switching of the pulse fixed pattern which concerns on a present Example, and a 5 pulse fixed pattern. The flowchart of the pulse pattern production | generation process of a 3 level inverter by the shockless switching means of a fixed pulse pattern.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram illustrating a configuration of a power conversion apparatus 100 according to the present embodiment. The illustrated example is a block diagram of fixed pulse pattern shockless switching of the three-level power converter.

  The power converter 100 includes an AC power source 1, an input transformer 2, a three-level converter 3, smoothing capacitors 4A and 4B, a three-level inverter 5, a current detector (current detection means) 6, and a converter control unit (converter control means). 10 and an inverter control unit (inverter control means 20 or the like).

  The AC voltage supplied from the AC power source 1 is converted into an appropriate voltage by the input transformer 2 and is supplied to the three-level converter 3.

  The input transformer 2 converts, for example, a high voltage [2 kV] into a commercial voltage [100 V]. Since the input transformer 2 is composed of a primary side coil and a secondary side coil, an equivalent circuit using the inductance L (H) of the coil converted to the secondary side and the resistance R [Ω] converted to the secondary side. Can be used. The figure shows the case expressed in this way.

  The AC input current of the three-level converter 3 is detected by the current detector 6. The detected current is supplied to a current controller (current control means) 15 as a feedback current. The current controller 15 outputs a phase reference that minimizes the deviation between the feedback current and a separately set current reference, and supplies the phase reference to the fixed pulse pattern modulator (fixed pulse pattern modulation means) 16. The fixed pulse pattern modulator 16 generates a fixed pulse pattern whose phase is shifted from the phase of the AC power source 1 by the value of the phase reference, and gate pulses are applied to the switching elements Q1, Q2, Q3, Q4 constituting the three-level converter 3. give. The fixed pulse pattern used in the fixed pulse pattern modulator 16 has a configuration given by a fixed pulse pattern setter.

  In the first embodiment, a fixed pulse pattern setting device is provided with a three-pulse fixed pulse pattern setting device (fixed pulse pattern setting device) 11 and a five-pulse fixed pulse pattern setting device (fixed pulse pattern setting device) 12, As a result, an optimal three-pulse fixed pattern and a five-pulse fixed pattern are set and prepared in advance.

  The pulse pattern switcher (pulse pattern switch means) 13 switches the 3-pulse fixed pulse pattern setter 11 or the 5-pulse fixed pulse pattern setter 12 according to the calculation result of the pulse number switching condition. The pulse pattern switched by the pulse pattern switch 13 is further switched between several cycles of the fundamental wave period by a shockless switching means (shockless switching means) 14 of a fixed pulse pattern.

  The fixed pulse pattern is a method for generating the same modulation pattern, and its basic frequency is synchronized with the frequency of the AC power supply 1 or the electric frequency of the load motor. The three-phase pulses are the same pulses that are shifted from each other by 120 °, and as shown in the figure, the waveforms of each of the pulses are symmetrical with respect to each other with 90 ° between them. Also, the positive and negative pulses for the three-level converter are vertically symmetric. Therefore, if a 1/4 period pulse pattern is determined, all pulse patterns are determined.

  FIG. 2 is a circuit diagram of the main part of the three-level converter 3 that constitutes the power conversion apparatus 100. The three-level converter 3 is configured by a parallel circuit of switching legs that constitutes the three phases of the R phase, the S phase, and the T phase. Each switching leg has the same configuration, and is basically a series circuit including self-extinguishing type switching elements Q1, Q2, Q3, and Q4. Flywheel diodes D3, D4, D5, and D6 are connected in antiparallel to the switching elements Q1, Q2, Q3, and Q4, respectively. And the secondary output of each phase which the input transformer 2 respond | corresponds is connected to the intermediate point of the switching leg of each phase.

  Clamp diodes D1 and D2 are respectively connected to the midpoint of the positive arm of each phase and the midpoint of the negative arm in a direction in which current flows from the neutral point.

  A positive side capacitor 4A is connected between the positive potential end of the switching leg and the neutral point, and a negative side capacitor 4B is connected between the neutral point and the negative potential end of the switching leg. A DC voltage having three levels of potential and neutral point potential is supplied to the three-level inverter 5. Normally, the three-level converter 3 performs power conversion in the forward direction from the AC side to the DC side, but has a circuit configuration using a self-extinguishing type switching element, so that the reverse from the DC side to the AC side. Directional power conversion is also possible.

  FIG. 3 is a graph showing the relationship between the output frequency and the number of pulses when the present invention is applied to the three-level inverter 5.

  When the present invention is applied to the three-level inverter 5, an inverter control unit 20 having the same configuration as the converter control unit 10 shown in FIG. The converter control unit 10 may be configured to have the function of the inverter control unit 20. Hereinafter, the case where the present invention is applied to the three-level inverter 5 will be described.

  Further, the AC input current is detected by the current detector 7. The detected current is given to the current controller 25 as a feedback current. The illustrated example shows a case where the current detector 7 is written for only one phase.

  The current controller 25 outputs a voltage reference so as to minimize the deviation between the feedback current and the current reference, and supplies the voltage reference to the fixed pulse pattern modulator 26.

  The fixed pulse pattern modulator 26 applies a voltage generated by a pulse pattern that outputs a given voltage reference to the electric motor.

  The fixed pulse pattern is a pulse pattern synchronized with the frequency of the fundamental wave, and the harmonic width of the harmonic component decreases as the motor speed increases. For this reason, it is necessary to maintain a certain pulse width or more by reducing the number of pulses as the output frequency of the three-level inverter 5 increases. In consideration of the above, up to a predetermined frequency, a 5-pulse fixed pattern is used as a fixed pulse pattern. When the predetermined frequency is exceeded, a 3-pulse fixed pattern is used. The figure shows the state.

  FIG. 4 is a diagram for explaining a conventional switching operation between a 3-pulse fixed pattern and a 5-pulse fixed pattern. FIG. 4 (1) is a diagram showing a three-pulse fixed pattern. The three-pulse fixed pattern is output during the fundamental wave half cycle (180 °). FIG. 4B is a diagram showing a 5-pulse fixed pattern. As for the 5-pulse fixed pattern, the 5-pulse fixed pattern is output during the fundamental wave half cycle (180 °).

  As shown in FIG. 3, the 3-pulse fixed pattern and the 5-pulse fixed pattern are switched and used according to the frequency required on the load side (for example, the electric motor). Conventionally, the three-pulse fixed pattern shown in FIG. 4 (1) and the five-pulse fixed pattern shown in FIG. 4 (2) are switched and used.

  However, in the conventional pulse pattern switching method, the pulse pattern based on the phase reference of the output voltage is different at the timing of switching the pulse pattern, so that the pulse becomes discontinuous and torque shock occurs. Torque shock can occur in all the pulses A to C shown in FIG. 4 (1) or (2), but the discontinuity of the pulse C is the largest factor.

  In the present invention, a control method for pulse pattern transition without torque shock at the time of switching the number of pulses of a fixed pulse pattern is proposed.

  FIG. 5 is a diagram for explaining the switching operation between the 3-pulse fixed pattern and the 5-pulse fixed pattern according to the present embodiment. FIG. 5 (1) is a diagram showing a three-pulse fixed pattern, as in FIG. 4 (1), and a description thereof will be omitted. FIGS. 5 (2) and 5 (3) are diagrams showing how the 5-pulse fixed pattern changes.

  Hereinafter, with reference to FIG. 5, the pulse switching method will be described with reference to the 5-pulse fixed pattern shown in FIG. 5 (2) or 5 (3) from the 3-pulse fixed pattern shown in FIG. 5 (1).

  First, a narrow pulse (additional pulse) C is output to both ends in the half-cycle of the fundamental wave (see pulse C in FIG. 5 (2)). At this time, the pulse width of the pulse B is fixed, and the pulse width α of the pulse A is determined by calculating so that the effective value of the primary voltage reference is the same as before the pulse pattern switching.

  By repeating this calculation until the pulse C reaches a predetermined pulse width while slowly changing the pulse width of the pulse C, shockless pulse pattern switching is performed. FIG. 5 (3) shows a state where a predetermined pulse width is reached in this way. Therefore, in this case, the pulse width α of the pulse A is determined by calculating so that the effective value of the primary voltage reference is the same as that before the pulse pattern switching. As a result, the pulse width α becomes narrower than the initial value. FIG. 5 (3) shows a state in which the 3-pulse fixed pattern is switched to the 5-pulse fixed pattern in this way.

  FIG. 6 is a flowchart of the pulse pattern generation processing (pulse pattern generation means) of the three-level converter 3 by the shockless switching means 14 of the fixed pulse pattern. This process is the same as the flowchart of the pulse pattern generation process of the three-level inverter by the shockless switching means 24 of the fixed pulse pattern.

  In this flowchart, the fundamental wave period of the output frequency is one cycle, and the means for switching the pulse pattern between the three-pulse fixed pattern and the five-pulse fixed pattern is described. The present invention can be applied not only to switching between 3 pulses and 5 pulses, but also to switching between (2n-1) pulses and (2n + 1) pulses. n is a positive integer.

  Based on the switching determination between 3 pulses and 5 pulses, it is determined whether the speed of the motor detected by the speed sensor (not shown) is equal to or higher than the switching frequency between 3 pulses and 5 pulses (step S1 in FIG. 6). This determination can be achieved not only by the electric motor detected by the speed sensor (not shown) but also by using the estimated speed obtained in the electric motor control without the speed sensor.

  By determining whether to perform switching between 3 pulses and 5 pulses (step S1), it is determined that switching is performed (Y in step S1), and the motor speed is equal to or higher than the switching frequency between 3 pulses and 5 pulses. If it is determined (Y in step S2), if the pulse pattern is 3 pulses (step S3), it is determined that the number of pulses is normal in this speed region, and the pulse pattern generation process is not performed.

  On the other hand, if there are 5 pulses in step S3 (N in step S3), it is determined whether the width of the pulse C at both ends in the half cycle of the fundamental wave is the minimum on-pulse width that the semiconductor element can withstand (step S4). ).

  If it is the minimum on-pulse width in step S4 (Y in step S4), the pulse C is removed (step S5). On the other hand, if the pulse width is not the minimum on-pulse width in step S4 (N in step S4), the pulse width is narrowed by Δd from pulse C (step S6).

  By determining whether or not to perform switching between 3 pulses and 5 pulses (step S1), it is determined that switching is performed (Y in step S1), and the motor speed is less than the switching frequency between 3 pulses and 5 pulses. If it is determined (N in step S2), a pulse pattern generation process is performed in the frequency domain using 5 pulses as the fixed pulse pattern. This will be specifically described below.

  In step S7, if there are three pulses (Y in step S7), pulses C having the minimum on-pulse width that can be tolerated by the semiconductor element are output to both ends of the half-cycle of the fundamental wave (step S8). If it is not three pulses (N in step S7), it is determined whether or not the width of the pulse C at both ends in the half cycle of the fundamental wave is the desired pulse width d. If the pulse width is d, it is determined that the number of pulses is normal in this speed region. If the width of the pulse C is not d, the pulse width of the pulse C is increased by Δd (step S10).

  After performing the above determination, the pulse width α of the pulse A is calculated. The pulse width α is determined by calculating so that the effective value of the output voltage reference is the same as before switching the pulse width (step S11). A pulse width based on the determined pulse pattern is output to the gate of the switching element constituting the three-level inverter (step S11).

  According to the present invention, it is possible to shift the pulse pattern without torque shock when switching the number of pulses of the fixed pulse pattern.

DESCRIPTION OF SYMBOLS 1 AC power supply 2 Input transformer 3 3 level converter 4A, 4B Smoothing capacitor 5 3 level inverter 10 Converter control part 11 3 pulse fixed pulse pattern setting device 12 5 pulse fixed pulse pattern setting device 13 Pulse pattern switching device 14 Fixed pulse pattern Shockless switching means 15 Current limiter 16 Fixed pulse pattern modulator 20 Inverter controller 21 3 pulse fixed pulse pattern setter 22 5 pulse fixed pulse pattern setter 23 Pulse pattern switcher 24 Shockless switching means 25 of fixed pulse pattern Current Limiter 26 Fixed pulse pattern modulator

Claims (4)

In a power converter comprising a three-level converter for converting AC power to DC power and a three-level inverter for converting DC power to AC power,
A smoothing capacitor connected to the DC power output side of the three-level converter;
A plurality of fixed pulse pattern setting means for individually setting a plurality of fixed pulse patterns having different pulse patterns in order to reduce low-order harmonics of the basic output of AC power input to the three-level converter;
Pulse pattern switching means for selectively switching the fixed pulse pattern set by the fixed pulse pattern setting means;
A fixed pulse pattern shockless switching means for switching the fixed pulse pattern switched by the pulse pattern switching means to shockless;
Fixed pulse pattern modulating means for modulating the fixed pulse pattern switched by the shockless switching means for input to the three-level converter;
Current detection means for detecting AC input current of AC power input to the three-level converter every predetermined time;
Current control means for outputting to the fixed pulse pattern modulation means a phase reference that minimizes the deviation between the alternating current detected by the current detection means and a separately set current reference;
With
The fixed pulse pattern modulation means includes
Applying a pulse set in a pulse pattern set by the shockless switching means based on a control result by the current control means to a gate of a switching element constituting the three-level converter ;
The shockless switching means is
When switching the number of pulses of the fixed pulse pattern, in the fundamental wave half cycle, a narrow additional pulse is added to both ends of the fixed pulse pattern before switching,
Before and after adding the additional pulse, output a pulse pattern set by calculating to narrow the pulse width of the fixed pulse before the change so that the effective value of the primary voltage reference of the AC power is the same. The power converter characterized by the above-mentioned. The shockless switching means is
2. The power converter according to claim 1 , wherein when adding the additional pulse, the calculation is repeated until the pulse width of the additional pulse becomes a predetermined pulse width while changing the pulse width of the additional pulse . In a power converter comprising a three-level converter for converting AC power to DC power and a three-level inverter for converting DC power to AC power,
A smoothing capacitor connected to the DC power output side of the three-level converter;
A plurality of fixed pulse pattern setting means for individually setting a plurality of fixed pulse patterns having different pulse patterns in order to reduce low-order harmonics of the basic output of AC power output from the three-level inverter;
Pulse pattern switching means for selectively switching the fixed pulse pattern set by the fixed pulse pattern setting means;
A fixed pulse pattern shockless switching means for switching the fixed pulse pattern switched by the pulse pattern switching means to shockless;
Fixed pulse pattern modulating means for modulating the fixed pulse pattern switched by the shockless switching means to be input to the three-level inverter;
Current detection means for detecting an AC output current of AC power output from the three-level inverter every predetermined time;
Current control means for outputting to the fixed pulse pattern modulation means a phase reference that minimizes the deviation between the alternating current detected by the current detection means and the current reference;
With
The fixed pulse pattern modulation means includes
Applying a pulse set in a pulse pattern set by the shockless switching means based on a control result by the current control means to a gate of a switching element constituting the three-level inverter;
The shockless switching means is
When switching the number of pulses of a fixed pulse pattern, in the fundamental wave half cycle, add a narrow additional pulse to both ends of the fixed pulse pattern before switching,
Before and after adding the additional pulse, output a pulse pattern set by calculating to narrow the pulse width of the fixed pulse before the change so that the effective value of the primary voltage reference of the AC power is the same. The power converter characterized by the above-mentioned. The shockless switching means is
When adding the additional pulse, the additional pulse is changed while changing the pulse width of the additional pulse.
Claim scan pulse width and repeating the operation until a predetermined pulse width 3
The power converter described .

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