JP6366543B2 - DC / DC converter - Google Patents

Description

  The present invention relates to a DC / DC converter including an inverter that converts a DC voltage into a high-frequency AC voltage and a rectifier circuit that rectifies the output of the inverter.

  In a conventional DC / DC converter, a full-bridge type inverter circuit is connected in parallel to the DC power source, and the primary side of each transformer is connected to each inverter, and the secondary side of each transformer is connected in series. Then, a device in which a rectifier circuit is provided in the subsequent stage and a direct current rectified by the rectifier circuit is supplied to a load has been proposed (for example, see Patent Document 1 below).

JP 2008-11665 A

  In the prior art described in Patent Document 1, a DC / DC converter in which the secondary side has a high step-up ratio with respect to the primary side can be configured with low loss. The secondary side is connected in series, and a single rectifier circuit is connected to the subsequent stage. For this reason, even if the output voltage after being converted to DC by the rectifier circuit is detected and the output voltage of each inverter circuit on the primary side is controlled based on the detected voltage, the secondary side of the transformer before being converted to DC Therefore, there remains a problem that it is difficult to control the output voltage after DC conversion on the secondary side with high accuracy.

  The present invention has been made to solve the above-described problems, and an object thereof is to provide a DC / DC converter capable of controlling the output voltage on the secondary side of the transformer with high accuracy.

The present invention includes a first inverter circuit and a second inverter circuit connected in parallel to a DC power supply, a first insulation transformer connected to the AC side of the first inverter circuit, and the second A second insulation transformer connected to the AC side of the inverter circuit, a first rectifier circuit and a second rectifier circuit respectively connected to the first insulation transformer and the secondary winding of the second insulation transformer A rectifier circuit; a first smoothing capacitor for smoothing the output of the first rectifier circuit; and a first smoothing capacitor connected in series to the positive electrode of the first smoothing capacitor to smooth the output of the second rectifier circuit. A DC / DC converter configured to supply a total voltage of the first smoothing capacitor and the second smoothing capacitor to a load.
The voltage of the second smoothing capacitor is set higher than the voltage of the first smoothing capacitor, the first inverter circuit is set by a hard switching circuit, and the second inverter circuit is set by a soft switching circuit. It is configured.

  According to this invention, with the above configuration, fine output voltage control can be performed on the first inverter circuit on the low voltage side. As a result, the control accuracy of the entire output voltage supplied to the load is improved. Further, since the switching loss of the second inverter circuit on the high voltage side can be reduced, the loss of the entire device can be reduced. As a result, it is possible to realize a DC / DC converter that can simultaneously realize high accuracy and low loss.

It is a circuit block diagram of the DC / DC converter in Embodiment 1 of this invention. In Embodiment 1 of this invention, it is a wave form diagram which shows the voltage which generate | occur | produces on the secondary side of the isolation transformer connected to the 1st inverter circuit, and the electric current which generate | occur | produces in a reactor. In Embodiment 1 of this invention, it is a control block diagram which shows the structure of the control circuit in the case of controlling the output voltage of a 1st inverter circuit. It is explanatory drawing which shows the current pathway of the 2nd inverter circuit in Embodiment 1 of this invention. It is explanatory drawing which shows the current pathway of the 2nd inverter circuit in Embodiment 1 of this invention. It is explanatory drawing which shows the current pathway of the 2nd inverter circuit in Embodiment 1 of this invention. In Embodiment 1 of this invention, it is a control block diagram which shows a part of structure of the control circuit in the case of controlling the sum total of each output voltage obtained based on the output of the 1st, 2nd inverter circuit. In the second embodiment of the present invention, when there is a limit in controlling the output voltage by duty ratio control of the first inverter circuit, control when the duty ratio control of the second inverter circuit on the high voltage side is performed simultaneously. It is a control block diagram which shows a part of circuit structure. In Embodiment 3 of this invention, it is a control block diagram which shows a part of structure of the control circuit in the case of controlling the sum total of each output voltage obtained based on the output of the 1st, 2nd inverter circuit.

Embodiment 1 FIG.
FIG. 1 is a circuit configuration diagram of a DC / DC converter according to Embodiment 1 of the present invention.

  The DC / DC converter according to the first embodiment includes a first inverter circuit 100 and a second inverter circuit 200 connected in parallel to each other with respect to a direct-current power source 1 serving as an input.

  The first inverter circuit 100 includes four semiconductor switch elements 2a to 2d made of a self-extinguishing semiconductor such as an IGBT (Insulated Gate Bipolar Transistor) for converting DC power into high-frequency AC. The primary winding of the insulation transformer 3 is connected to the AC output side of the inverter circuit 100. A rectifier circuit 4 composed of a diode for rectifying high-frequency alternating current is connected to the secondary side winding of the insulating transformer 3, and an output smoothing reactor 5 and an output smoothing capacitor 6 are arranged on the rear side of the rectifier circuit 4. Is connected. The output smoothing capacitor 6 is provided with a voltage sensor 7 for sensing the voltage.

  In the claims, the first insulation transformer is the insulation transformer 3, the first rectifier circuit is the rectifier circuit 4, and the first output smoothing capacitor is the output smoothing capacitor 6. The first voltage sensor corresponds to the voltage sensor 7 described above.

  The second inverter circuit 200 includes four semiconductor switch elements 8a to 8d made of a self-extinguishing semiconductor such as an IGBT for converting direct current power into high frequency alternating current. Each of the semiconductor switch elements 8a to 8d includes On the other hand, snubber capacitors 9a to 9d are individually connected in parallel. Further, the reactor 10 is connected to the AC output side of the second inverter circuit 200. The snubber capacitors 9a to 9d and the reactor 10 in this case are provided in order to realize a soft switching circuit that suppresses the switching loss of each of the semiconductor switch elements 8a to 8d in the second inverter circuit 200, as will be described later. .

  The primary winding of the isolation transformer 11 is connected to the rear stage side of the reactor 10 on the AC output side of the second inverter circuit 200. A rectifier circuit 12 composed of a diode for rectifying high-frequency alternating current is connected to the secondary side winding of the insulation transformer 11, and an output smoothing reactor 13 and an output smoothing capacitor 14 are arranged on the rear side of the rectifier circuit 12. It is connected. The output smoothing capacitor 14 is provided with a voltage sensor 15 for sensing the voltage.

  In the claims, the second insulation transformer is the insulation transformer 11, the second rectifier circuit is the rectifier circuit 12, the second output smoothing capacitor is the output smoothing capacitor 14, The second voltage sensor corresponds to the voltage sensor 15 described above.

  An output smoothing capacitor 14 provided for the second inverter circuit 200 is connected in series to the positive electrode side of the output smoothing capacitor 6 provided for the first inverter circuit 100, and both outputs are further connected. An overall output smoothing capacitor 16 is connected in parallel to the series circuit of the smoothing capacitors 6 and 14. Therefore, the sum of the DC voltages of the output smoothing capacitors 6 and 14 becomes the output voltage of the overall output smoothing capacitor 16. A voltage sensor 17 is provided for sensing the voltage of the overall output smoothing capacitor 16. A load 18 is connected to the rear side of the overall output smoothing capacitor 16.

  The detection outputs of the voltage sensors 7, 15, and 17 are input to the control circuit 300 and the semiconductor switch elements 2 a to 2 d and 8 a to the first and second inverter circuits 100 and 200. The drive signal 8d is output from the control circuit 300. The control circuit 300 controls the operation of the semiconductor switch elements 2 a to 2 d and 8 a to 8 d of the first and second inverter circuits 100 and 200, thereby outputting a desired DC voltage to the load 18.

Next, the operation of the DC / DC converter having the above configuration will be described.
In the DC / DC converter according to the first embodiment, the output voltage obtained by DC smoothing the AC output of the first inverter circuit 100 is lower than the output voltage obtained by DC smoothing the AC output of the second inverter circuit 200. The first and second inverter circuits 100 and 200 are operated in combination. In this case, the low voltage side first inverter circuit 100 performs duty ratio control by hard switching, while the high voltage side second inverter circuit 200 performs soft switching by adopting a phase shift method.

  First, the first inverter circuit 100 performs power conversion by switching driving the semiconductor switch elements 2 a to 2 d constituting the first inverter circuit 100 with the input voltage from the DC power supply 1.

In this case, when the semiconductor switch elements 2a and 2d or the semiconductor switch elements 2b and 2c are simultaneously turned on among the semiconductor switch elements 2a to 2d, a voltage is generated on the primary side of the insulating transformer 3, and the power is transmitted to the secondary side. It is done. In general, the switching operation is a high-frequency PWM operation, and the semiconductor switch elements 2a and 2d or the semiconductor switch elements 2b and 2c are simultaneously turned on at the same time. When the semiconductor switch elements 2a and 2d or the semiconductor switch elements 2b and 2c are simultaneously turned on, the voltage of the DC power supply 1 is Vdc, the number of primary windings of the insulation transformer 3 is N ₁ , and the number of secondary windings is N ₂ , a voltage of Vdc × N ₂ / N ₁ as shown in FIG. 2A is generated in the secondary winding.

  Accordingly, a current as shown in FIG. 2B flows through the output smoothing reactor 5. In this case, assuming that the inductance of the output smoothing reactor 5 is L and the output voltage of the output smoothing capacitor 6 is Vout1, the peak current Δi is given by the following equation.

  In other periods, the current flows back through the path of the output smoothing reactor 5 → the output smoothing capacitor 6 → the rectifier circuit 4 → the output smoothing reactor 5, so that the current decreases.

  Next, control of the first inverter circuit 100 will be described with reference to FIG.

  The control circuit 300 senses the voltage of the output smoothing capacitor 6 with the voltage sensor 7. The control circuit 300 obtains a difference voltage ΔVout1 (= Vout1 * −Vout1), which is an error between the detected voltage value Vout1 and a preset output voltage target value Vout1 *, by the differentiator 20, and calculates the difference voltage ΔVout1. Amplification is performed by the error amplifying unit 21. Thereafter, the PWM control unit 22 generates a drive pulse having a PWM waveform corresponding to the magnitude of the difference voltage ΔVout1 to drive the semiconductor switch elements 2a to 2d. By performing such feedback control, the voltage value Vout1 of the output smoothing capacitor 6 is controlled to approach the output voltage target value Vout1 *.

  Next, the operation of the second inverter circuit 200 will be described with reference to FIGS. 4, 5, and 6. In addition, the path | route through which an electric current flows is shown by the thick continuous line in each figure.

The second inverter circuit 200 performs soft switching by adopting a phase shift method in order to suppress switching loss.
That is, for example, as shown in FIG. 4A, when the semiconductor switch elements 8a and 8d of the inverter circuit are in the ON state, the primary side of the insulation transformer 11 is connected to the DC power source 1 → the semiconductor switch element 8a → the reactor 10 → the insulation transformer A current flows through the path 11 → semiconductor switching element 8d → DC power supply 1.

  At this time, a current flows through the path of the insulating transformer 11 → the rectifier circuit 12 → the output smoothing reactor 13 → the output smoothing capacitor 14 → the rectifier circuit 12 → the insulating transformer 11 on the secondary side of the insulating transformer 11. Power is transmitted from the primary side to the secondary side.

  Next, as shown in FIG. 4B, when the semiconductor switch element 8a is turned off, the primary current path is reactor 10 → insulation transformer 11 → semiconductor switch element 8d → DC power supply 1 → snubber capacitor 9a → reactor 10 Current flows through the path of the reactor 10 → insulation transformer 11 → semiconductor switch element 8 d → snubber capacitor 9 b → reactor 10.

  At this time, the voltage across the semiconductor switch element 8a slows down due to the effect of the snubber capacitor 9a, and the current is cut off before the voltage rises, so that the switching loss is reduced. Such switching is generally referred to as zero volt switching. Further, since the sum of the voltages of the snubber capacitors 9a and 9b is equal to the voltage of the DC power supply 1, the increase in the voltage across the snubber capacitor 9a and the decrease in the voltage across the snubber capacitor 9b are substantially equal.

  Further, at this time, the secondary side current depends on the energy of the output smoothing reactor 13, the path of the output smoothing reactor 13 → the output smoothing capacitor 14 → the rectifier circuit 12 → the output smoothing reactor 13, or the output smoothing reactor 13. → Output smoothing capacitor 14 → rectifier circuit 12 → insulation transformer 11 → rectifier circuit 12 → output smoothing reactor 13

  4B flows until the voltage of the snubber capacitor 9a becomes substantially equal to the voltage of the DC power source 1 and the voltage of the snubber capacitor 9b becomes almost zero. In this state, a current flows through the path of reactor 10 → insulating transformer 11 → semiconductor switching element 8 d → reverse parallel diode of semiconductor switching element 8 b → reactor 10 shown in FIG.

  Next, as shown in FIG. 4D, the semiconductor switch element 8b is turned on, but when the semiconductor switch element 8 is an element such as an IGBT in which no current flows in the reverse direction, the current flow path is different from that in FIG. Absent. At this time, since the voltage applied to both ends of the semiconductor switch element 8b (voltage of the snubber capacitor 9b) is almost zero, the switching loss of the semiconductor switch element 8b is almost zero, resulting in zero volt switching.

  When the semiconductor switch element 8d is turned off from this state as shown in FIG. 5 (e), the primary side current path is the reactor 10, the insulating transformer 11, the snubber capacitor 9d, the semiconductor diode 8b antiparallel diode, and the reactor 10 path. And the path of the reactor 10 → the insulating transformer 11 → the snubber capacitor 9 c → the DC power source 1 → the antiparallel diode of the semiconductor switch element 8 b → the reactor 10.

  At this time, similarly to the description in FIG. 4B, the semiconductor switch element 8d performs zero volt switching. As the current continues to flow, the voltage of the snubber capacitor 9c decreases to almost zero volts. When the voltage of the snubber capacitor 9d becomes substantially equal to the voltage of the DC power source 1, the current path is as shown in FIG. 5F. The reactor 10 → the insulating transformer 11 → the antiparallel diode of the semiconductor switch element 8c → the DC power source 1 → The antiparallel diode of the semiconductor switch element 8b is changed to the reactor 10.

  Next, as shown in FIG. 5 (g), when the semiconductor switch element 8c is turned on, a reverse voltage is applied to the insulation transformer 11 and the reactor 10, and the current path is DC power supply 1 → semiconductor switch element 8c → insulation. A current flows through the path of the transformer 11, the reactor 10, the semiconductor switch element 8 b, and the DC power supply 1. At this time, since the semiconductor switch element 8c is turned on with the voltage at both ends being substantially zero, the switching is zero volt and no switching loss occurs.

  Also, at this time, the current flows through the path of the insulating transformer 11 → the rectifying circuit 12 → the output smoothing reactor 13 → the output smoothing capacitor 14 → the rectifying circuit 12 → the insulating transformer 11 on the secondary side of the insulating transformer 11. Power is transmitted from the primary side of the transformer 11 to the secondary side.

  Next, when the semiconductor switch element 8b is turned off as shown in FIG. 5 (h), the current path on the primary side is the path of the reactor 10 → the snubber capacitor 9b → the DC power source 1 → the semiconductor switch element 8c → the insulating transformer 11 → the reactor 10. , And the current flows through the path of the reactor 10 → the snubber capacitor 9 a → the semiconductor switch element 8 c → the insulating transformer 11 → the reactor 10.

  At this time, the voltage across the semiconductor switch element 8b is increased by the effect of the snubber capacitor 9b, and the voltage rises slowly, and the current is cut off before the voltage rises. Further, at this time, the secondary side current depends on the energy of the output smoothing reactor 13, and the output smoothing reactor 13 → the output smoothing capacitor 14 → the rectifier circuit 12 → the output smoothing reactor 13 or the output smoothing reactor 13 → the output smoothing. It flows in the path of the capacitor 14 → rectifier circuit 12 → insulating transformer 11 → rectifier circuit 12 → output smoothing reactor 13.

  The state of FIG. 5 (h) flows until the voltage of the snubber capacitor 9b becomes substantially equal to the voltage of the DC power supply 1 and the voltage of the snubber capacitor 9a becomes almost zero. In this state, a current flows through the path of the reactor 10 → the antiparallel diode of the semiconductor switch element 8 a → the semiconductor switch element 8 c → the insulating transformer 11 → the reactor 10 shown in FIG.

  Next, as shown in FIG. 6 (j), the semiconductor switch element 8a is turned on, but the current flow path is the same as in FIG. 6 (i). At this time, the voltage applied to both ends of the semiconductor switch element 8a (the voltage of the snubber capacitor 9a) is almost zero, so that zero volt switching is performed.

  When the semiconductor switch element 8c is turned off from this state as shown in FIG. 6 (k), the primary side current path is the path of the reactor 10 → the antiparallel diode of the semiconductor switch element 8a → the snubber capacitor 9c → the insulation transformer 11 → the reactor 10 And the path of the reactor 10 → the antiparallel diode of the semiconductor switch element 8a → the DC power source 1 → the snubber capacitor 9d → the insulating transformer 11 → the reactor 10.

  At this time, the semiconductor switch element 8c performs zero volt switching. As the current continues to flow, the voltage of the snubber capacitor 9d drops to almost zero volts, and the voltage of the snubber capacitor 9c becomes substantially equal to the voltage of the DC power source 1. Then, as shown in FIG. 6 (l), the current path is as follows: reactor 10 → anti-parallel diode of semiconductor switch element 8a → DC power supply 1 → anti-parallel diode of semiconductor switch element 8d → insulation transformer 11 → reactor 10. Thereafter, the semiconductor switch element 8d is turned on to return to the state of FIG.

  As described above, the second inverter circuit 200 operates as described above. Therefore, the semiconductor switch elements 8a and 8d that are located diagonally with respect to the semiconductor switch elements 8a to 8d that constitute the second inverter circuit 200. Alternatively, the higher the time ratio for turning on the semiconductor switch elements 8b and 8c, the higher the output voltage generated in the output smoothing capacitor 14 on the secondary side. Moreover, the second inverter circuit 200 can perform a soft switching operation with suppressed switching loss by the control of the phase shift method as described with reference to FIGS.

  Next, a method for controlling the total output voltage value, which is the sum of the voltages obtained by DC smoothing the AC outputs of the first and second inverter circuits 100 and 200, will be described.

  In the first embodiment, the total output voltage value that is the sum of the output voltage obtained by smoothing the alternating current output of the first inverter circuit 100 and the output voltage obtained by smoothing the alternating current output of the second inverter circuit 200. Is controlled to a preset total output voltage target value Vout *, the PWM operation is performed by controlling the duty ratio when switching each of the semiconductor switch elements 2a to 2d constituting the first inverter circuit 100.

  Here, as described above, the control circuit 300 receives the voltage values Vout1 and Vout2 obtained by sensing the voltages of the output smoothing capacitors 6 and 14 by the voltage sensors 7 and 15, respectively. Therefore, the control circuit 300 senses the sensed voltage values Vout1 and Vout2, the preset total output voltage target value Vout *, and the temporary target value Vout1 * of the voltage obtained by DC smoothing the AC output of the first inverter circuit 100. * Is used to calculate the output voltage target value Vout1 * for the first inverter circuit 100 as follows.

  That is, as shown in FIG. 7, the difference voltage ΔVout (= Vout * −) between the total output voltage value (= Vout1 + Vout2) that is the sum of the voltages sensed by both voltage sensors 7 and 15 and the total output voltage target value Vout *. (Vout1 + Vout2)) is obtained by the differentiator 23. The difference voltage ΔVout is added by the adder 24 to the temporary target value Vout1 ** of the voltage of the output smoothing capacitor 6 connected to the first inverter circuit 100. In this case, the provisional target value Vout1 ** is an arbitrary value between zero and a voltage that the first inverter circuit 100 can output under the maximum duty ratio. Then, the result added by the adder 24 is set as an output voltage target value Vout1 * (= Vout1 ** + ΔVout) for the new first inverter circuit 100, and this output voltage target value Vout1 * is shown in FIG. The difference voltage ΔVout1 is amplified by the error amplifying unit 21. Next, the PWM control unit 22 generates a drive pulse having a PWM waveform corresponding to the magnitude of the difference voltage ΔVout1 to drive the semiconductor switch elements 2a to 2d.

  In this case, since the electric power handled by the first inverter circuit 100 is smaller than the electric power handled by the second inverter circuit 200, the switching loss generated in each of the semiconductor switch elements 2a to 2d constituting the first inverter circuit 100. Becomes smaller. Therefore, the drive frequency of the semiconductor switch elements 2a to 2d can be set higher than the drive frequency of the semiconductor switch elements 8a to 8d constituting the second inverter circuit 200.

  As described above, the DC / DC converter according to the first embodiment includes the first inverter circuit 100 having the hard switching circuit configuration on the low voltage side as described above and the second inverter having the soft switching circuit configuration on the high voltage side. Since the second inverter circuit 200 on the high voltage side, which handles a large amount of electric power, has low loss, the first inverter circuit on the low voltage side requires fine output voltage control. 100 enables high-accuracy voltage control, and can realize low loss and high-accuracy voltage control that are generally difficult to achieve at the same time. In addition, since the drive frequency of the first inverter circuit 100 can be set high, high-accuracy control of the output voltage is also possible.

  Note that the self-extinguishing semiconductor switch elements 2a to 2d and the semiconductor switch elements 8a to 8d in the above description may be GCT, GTO, transistors, MOSFETs, or the like in addition to the IGBT. The reactor 10 may also serve as a leakage inductance of the insulating transformer 11. When the semiconductor switch elements 2a to 2d and the semiconductor switch elements 8a to 8d are formed of MOSFETs, a synchronous rectification operation that does not pass current through the antiparallel diode is performed. You may let them. Furthermore, although the first and second inverter circuits 100 and 200 are full-bridge inverter circuits, the present invention is not limited to this, and other circuit configurations such as a half-bridge inverter circuit may be used. Further, in the first embodiment, zero volt switching is performed, but zero current switching can also be performed.

Embodiment 2. FIG.
In the first embodiment, with the configuration shown in FIGS. 7 and 3, the total output that is the sum of the voltages obtained by DC smoothing the AC outputs of the first and second inverter circuits 100 and 200, respectively. In order to control the voltage value to the total output voltage target value Vout *, the method of performing the PWM operation by controlling the duty ratio when switching the semiconductor switch elements 2a to 2d of the first inverter circuit 100 has been described.

  On the other hand, in the second embodiment, when the total output voltage value (= Vout1 + Vout2) is controlled to the total output voltage target value Vout *, the semiconductor switch elements 2a to 2d constituting the first inverter circuit 100 are controlled. A control for coping with a case where the duty ratio during switching driving exceeds a preset maximum value or minimum value will be described.

  The control circuit 300 performs DC smoothing on the sensed voltage values Vout1 and Vout2, the preset total output voltage target value Vout *, and the AC output of the first inverter circuit 100, as in the case shown in FIG. The output voltage target value Vout1 * for the first inverter circuit 100 is calculated using the provisional target value Vout1 ** of the voltage.

  Unlike the case of FIG. 3, the output voltage target value Vout1 * for the first inverter circuit 100 is first determined by the duty conversion circuit 25 according to the magnitude of the output voltage target value Vout1 * as shown in FIG. The duty ratio is converted into a duty command value X1 that specifies the duty ratio.

  Here, when the duty command value X1 output from the duty conversion circuit 25 is within the range of the limiter 26 that determines the maximum value and the minimum value installed in the subsequent stage, the duty command value X1 is limited by the limiter 26 at all. Without being input to the PWM control unit 22 at the next stage. Then, a drive pulse having a PWM waveform based on the duty command value X1 is generated from the PWM control unit 22, and the semiconductor switch elements 2a to 2d constituting the first inverter circuit 100 are driven.

  On the other hand, when the duty command value X1 is outside the range of the maximum value and the minimum value specified by the limiter 26, the limit value X2 specified by the limiter 26 is set to the next stage PWM for the first inverter circuit 100. Input to the controller 22. Then, a drive pulse having a PWM waveform based on the limit value X2 is generated from the PWM control unit 22, and the semiconductor switch elements 2a to 2d constituting the first inverter circuit 100 are driven.

  Further, when the duty command value X1 output from the duty conversion circuit 25 exceeds the upper limit value or the lower limit value defined by the limiter 26, the control circuit 300 drives the second inverter circuit 200 by changing the duty ratio at the same time. By controlling, the voltage value Vout of the overall output smoothing capacitor 16 is made to follow the total output voltage target value Vout *. This point will be described below.

  First, the control of the second inverter circuit 200 when the duty command value X1 for the first inverter circuit 100 is equal to or greater than the upper limit value of the limiter 26 will be described.

  When the duty command value X1 is equal to or greater than the upper limit value of the limiter 26, the differencer 27 calculates the difference ΔX between the duty command value X1 and the upper limit value, and outputs this difference ΔX as a duty correction value. On the other hand, based on the temporary target value Vout2 ** of the voltage of the output smoothing capacitor 14 connected to the second inverter circuit 200, the duty conversion circuit 29 sets the duty ratio according to the magnitude of the temporary target value Vout2 **. It is converted into a designated duty command value X3. Then, the duty correction value ΔX is added to the duty command value X 3 by the adder 30, and the addition value X 4 is input to the PWM control unit 31. Then, the PWM control unit 31 generates a drive pulse having a PWM waveform based on the corrected duty command value X4, and drives the semiconductor switch elements 8a to 8d constituting the second inverter circuit 200. In this case, since the second inverter circuit 200 employs the phase shift method in order to suppress the switching loss, the semiconductor switch elements 8a and 8d and the semiconductor switch elements 8b and 8c located on the diagonal are turned on. The time ratio is controlled to be high.

  As a result, the voltage of the output smoothing capacitor 14 connected to the second inverter circuit 200 increases, and accordingly, the voltage of the overall output smoothing capacitor 16 also increases. Therefore, since the output voltage target value Vout1 * for the first inverter circuit 100 decreases, the duty ratio of the drive pulse having the PWM waveform that drives the first inverter circuit 100 also decreases.

  Next, the control of the second inverter circuit 200 when the duty command value X1 for the first inverter circuit 100 is equal to or lower than the lower limit value of the limiter 26 will be described.

  When the duty command value X1 is less than or equal to the lower limit value of the limiter 26, the difference ΔX between the duty command value X1 and the lower limit value is calculated by the differentiator 27 as described above, and this difference ΔX is output as a duty correction value. Is done. On the other hand, based on the temporary target value Vout2 ** of the voltage of the output smoothing capacitor 14 connected to the second inverter circuit 200, the duty conversion circuit 29 sets the duty ratio according to the magnitude of the temporary target value Vout2 **. It is converted into a designated duty command value X3. The duty correction value ΔX is added to the duty command value X3 by the adder 30. However, in this case, since the duty correction value ΔX added to the duty command value X3 is a negative value, the corrected duty command value X4 for the second inverter circuit 200 is greater than the duty command value X3 before correction. Small value.

  Next, since the corrected duty command value X4 is input to the PWM control unit 31, the PWM control unit 31 generates a drive pulse having a PWM waveform based on the corrected duty command value X4, and the second inverter The semiconductor switch elements 8a to 8d constituting the circuit 200 are driven. In this case, since the second inverter circuit 200 employs the phase shift method in order to suppress the switching loss, the semiconductor switch elements 8a and 8d and the semiconductor switch elements 8b and 8c located on the diagonal are turned on. The time ratio is controlled to be low.

  As a result, the voltage of the output smoothing capacitor 14 connected to the second inverter circuit 200 decreases, and the voltage of the overall output smoothing capacitor 16 also decreases accordingly. Therefore, since the output voltage target value Vout1 * of the first inverter circuit 100 increases, the duty ratio of the drive pulse having the PWM waveform that drives the first inverter circuit 100 also increases.

  When the above control is performed, the response speed of the duty ratio control for generating the drive pulse for the first inverter circuit 100 is the duty ratio control for generating the drive pulse for the second inverter circuit 200. It is preferable to set it so as to be faster than the response speed. Thereby, since the response speed of the duty ratio control of the first inverter circuit 100 is faster than the response speed of the duty ratio control of the second inverter circuit 200, stable output voltage control can always be realized. .

  As described above, in the second embodiment, when the duty ratio when driving the first inverter circuit 100 on the low voltage side exceeds the preset maximum value or minimum value, the high voltage side first inverter circuit 100 is controlled. Since the control to change the duty ratio is performed by the inverter circuit 200 of 2, the duty ratio of the second inverter circuit 200 is corrected even when the duty ratio control of the first inverter circuit 100 cannot be dealt with alone. The output voltage can be maintained with high accuracy, and the voltage of the overall output smoothing capacitor 16 can follow the target value.

Embodiment 3 FIG.
In the first embodiment, the total output voltage target that is the total output voltage value that is the sum of the voltages obtained by DC smoothing the AC outputs of the first and second inverter circuits 100 and 200 is set in advance. In order to control to the value Vout *, as shown in FIG. 7, the voltage values Vout1 and Vout2 sensed by the voltage sensors 7 and 15 individually provided for the output smoothing capacitors 6 and 14 are added. The total output voltage value (= Vout1 + Vout2) is used.

  In contrast, in the third embodiment, as shown in FIG. 9, the voltage value Vout sensed by the voltage sensor 17 provided for the overall output smoothing capacitor 16 is used as the total output voltage. The other configuration in FIG. 9 is the same as that shown in FIG.

  Accordingly, in the configuration of FIG. 9, as in the case of FIG. 7, the adder 24 outputs the new output voltage target value Vout1 * of the first inverter circuit 100. Therefore, this output voltage target value Vout1 * 3 is input to the above-described differentiator 20 shown in FIG. 3, and the difference voltage ΔVout1 is amplified by the error amplification unit 21, and then the PWM control unit 22 generates a drive pulse having a PWM waveform corresponding to the magnitude of the difference voltage ΔVout1. The semiconductor switch elements 2a to 2d are generated and driven.

  Thus, in the third embodiment, the total output voltage value Vout obtained by sensing with the voltage sensor 17 by the PWM operation in which the duty ratio of the first inverter circuit 100 on the low voltage side is controlled is the total output voltage. The target value Vout * is controlled.

  If the duty ratio when switching driving the first inverter circuit 100 exceeds a preset maximum value or minimum value, the second inverter circuit is the same as in the case of the second embodiment. The duty ratio when switching driving 200 is corrected.

  As described above, in the third embodiment, the duty ratio of the first inverter circuit 100 on the low voltage side is based on the voltage value Vout obtained by sensing the voltage of the overall output smoothing capacitor 16 with the voltage sensor 17. Therefore, even if the number of voltage sensors is reduced, the output voltage can be controlled with high accuracy and the configuration of the entire apparatus can be simplified.

  The present invention is not limited to the configurations of the first to third embodiments described above, and modifications may be made to some of the configurations of the first to third embodiments without departing from the spirit of the present invention. In addition, a part of the configuration can be omitted, and the configurations of the first to third embodiments can be combined as appropriate.

DESCRIPTION OF SYMBOLS 1 DC power supply, 100 1st inverter circuit, 2a-2d Semiconductor switch element,
3 Insulation transformer, 4 rectifier circuit, 5 output smoothing reactor,
6 output smoothing capacitor, 7 voltage sensor, 200 second inverter circuit,
8a to 8d semiconductor switch element, 9a to 9d snubber capacitor, 10 reactor, 11 insulation transformer, 12 rectifier circuit, 13 output smoothing reactor,
14 output smoothing capacitor, 15 voltage sensor, 16 overall output smoothing capacitor,
17 voltage sensor, 18 load, 300 control circuit.

Claims (6)

A first inverter circuit and a second inverter circuit connected in parallel to the DC power supply, a first insulation transformer connected to the AC side of the first inverter circuit, and the second inverter circuit. A second insulation transformer connected to the alternating current side; a first rectification circuit and a second rectification circuit respectively connected to the first insulation transformer and the secondary winding of the second insulation transformer; A first smoothing capacitor for smoothing the output of the first rectifier circuit, and a second smoothing capacitor connected in series to the positive electrode of the first smoothing capacitor to smooth the output of the second rectifier circuit A DC / DC converter comprising a capacitor and supplying a total voltage of the first smoothing capacitor and the second smoothing capacitor to a load,
The voltage of the second smoothing capacitor is set higher than the voltage of the first smoothing capacitor, the first inverter circuit is set by a hard switching circuit, and the second inverter circuit is set by a soft switching circuit. A DC / DC converter characterized by being configured. 2. The DC / DC converter according to claim 1, wherein a switching frequency of the first inverter circuit is set higher than a switching frequency of the second inverter circuit. A voltage sensor for sensing a total voltage of the first smoothing capacitor and the second smoothing capacitor, and the first inverter when controlling the total voltage based on a detected voltage value of the voltage sensor; 3. The DC / DC converter according to claim 1, wherein a duty ratio of the circuit is controlled. 4. The duty ratio of the second inverter circuit is increased when the duty ratio of the first inverter circuit exceeds a preset value. 5. The DC / DC converter described in 1. The duty ratio of the second inverter circuit is decreased when the duty ratio of the first inverter circuit becomes equal to or less than a preset value. The DC / DC converter according to item. The response speed when the duty ratio control of the first inverter circuit is performed is higher than the response speed when the duty ratio control of the second inverter circuit is performed. The DC / DC converter according to any one of 5.

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