JP4649531B1 - Electronic device cutting method - Google Patents

Abstract

An electronic device cutting method capable of suppressing an increase in manufacturing cost of an electronic device including a semiconductor device and preventing damage to a low dielectric film.
A method for cutting an electronic device includes: a first step of preparing an electronic device in which a plurality of insulating layers and a plurality of wiring layers are stacked on a substrate; and a step including a blast process. A second step of exposing the substrate by removing all wiring layers and all insulating layers existing in the cuttable region, and a third step of cutting the substrate exposed in the cuttable region by a blade.
[Selection] Figure 10

Description

  The present invention relates to a method for cutting an electronic device in which an insulating layer and a wiring layer are stacked on a substrate.

  In recent years, products equipped with a semiconductor device, which is one of electronic devices, have been rapidly reduced in size, thickness, and weight for use in various mobile devices such as digital cameras and mobile phones. Accordingly, for example, semiconductor devices such as memory devices, logic devices, and MPUs (Micro Processing Units) are required to be reduced in size and increased in density.

  Hereinafter, a conventionally proposed semiconductor device and a cutting method thereof will be described with reference to the drawings. FIG. 1 is a cross-sectional view illustrating a conventional semiconductor device. Referring to FIG. 1, a semiconductor device 100 includes a thinned semiconductor substrate 101 and a semiconductor integrated circuit 102.

  For example, the semiconductor substrate 101 is obtained by cutting a thinned semiconductor wafer into pieces. The semiconductor integrated circuit 102 includes a first insulating layer 103, a first wiring layer 104, a second insulating layer 105, a second wiring layer 106, a third insulating layer 107, a third wiring layer 108, and a fourth wiring layer. An insulating layer 109 is included.

  The first insulating layer 103, the first wiring layer 104, the second insulating layer 105, the second wiring layer 106, the third insulating layer 107, the third wiring layer 108, and the fourth insulating layer 109 constituting the semiconductor integrated circuit 102 are The semiconductor substrate 101 is sequentially stacked on one side (hereinafter, one side of the semiconductor substrate 101 is referred to as a main surface). The wiring layers are electrically connected as appropriate by vias (not shown). As the material of the first wiring layer 104, the second wiring layer 106, and the third wiring layer 108, for example, Al can be used.

The first insulating layer 103, the second insulating layer 105, the third insulating layer 107, and the fourth insulating layer 109 are so-called interlayer insulating films. The fourth insulating layer 109 has an opening 109x, and a part of the third wiring layer 108 is exposed in the opening 109x. The third wiring layer 108 exposed in the opening 109x functions as a pad to which a bonding wire or the like is connected. As a material of the first insulating layer 103, the second insulating layer 105, and the third insulating layer 107, for example, SiO ₂ can be used. Further, as a material of the fourth insulating layer 109 may be, for example, _{SiO 2, SiN, Si 3 N} 4 or the like.

  2 and 3 are diagrams illustrating a manufacturing process of a conventional semiconductor device. 2 and 3, the same components as those of the conventional semiconductor device 100 shown in FIG. 1 are denoted by the same reference numerals, and the description thereof may be omitted. 2 and 3, A is a plurality of semiconductor device formation regions (hereinafter referred to as “semiconductor device formation regions A”), and B is a scribe region (hereinafter “scribe region B”) that separates the plurality of semiconductor device formation regions. C) indicates a position where the dicing blade cuts the semiconductor wafer 101A or the like (hereinafter referred to as “substrate cutting position C”).

  First, in the step shown in FIG. 2, the first insulating layer 103, the first wiring layer 104, the second insulating layer 105, the second wiring layer 106, and the third insulating layer are formed on the main surface of the semiconductor wafer 101A by a known method. The layer 107, the third wiring layer 108, and the fourth insulating layer 109 are stacked to form the semiconductor integrated circuit 102. Then, the back surface (surface opposite to the main surface) of the semiconductor wafer 101A is ground and thinned.

  Next, in the step shown in FIG. 3, the structure shown in FIG. 2 is cut at a substrate cutting position C by a blade dicing method using a dicing blade 110. Thereby, a plurality of semiconductor devices 100 are manufactured. The semiconductor substrate 101 is obtained by cutting the semiconductor wafer 101A.

  Incidentally, the first insulating layer 103, the first wiring layer 104, the second insulating layer 105, the second wiring layer 106, the third insulating layer 107, the third wiring layer 108, and the fourth insulating layer 109 are also formed in the scribe region B. Exists. The first wiring layer 104, the second wiring layer 106, and the third wiring layer 108 that exist in the scribe region B are provided for use in electrical inspection of the semiconductor device 100 before separation.

Therefore, in the process shown in FIG. 3, using the dicing blade 110, the semiconductor wafer 101A, the first insulating layer 103, the first wiring layer 104, the second insulating layer 105, the second wiring layer 106, the third insulating layer 107, The third wiring layer 108 and the fourth insulating layer 109 must be cut. As described above, the material of the first wiring layer 104, the second wiring layer 106, and the third wiring layer 108 can be Al, for example. Further, as a material of the first insulating layer 103, the second insulating layer 105, the third insulating layer 107, and the fourth insulating layer 109, for example, SiO ₂ or the like can be used. Al and SiO ₂ can be easily cut using the dicing blade 110, and the dicing blade 110 is not clogged.

By the way, recent semiconductor devices are required to be small in size and high in density, and at the same time, highly priced. In addition, an increase in wiring resistance due to miniaturization of the wiring pattern and an increase in signal delay due to an increase in parasitic capacitance such as inter-wiring capacitance have become problems. Therefore, the wiring resistance is reduced by changing the material of the wiring layer from Al to Cu having a low electric resistance, and the material of the insulating layer (interlayer insulating film) is changed from SiO ₂ to a low dielectric material having a low dielectric constant (so-called Low− Reduction of inter-wiring capacitance by changing to (k material) is being studied.

  However, an insulating layer using a low dielectric material uses, for example, SiOC for the purpose of lowering the dielectric constant, and some of them have a porous structure provided with pores, and the mechanical strength is extremely low. Therefore, when the semiconductor device is cut and separated into pieces by the blade dicing method, there is a problem that chipping or the like occurs and damages the insulating layer using the low dielectric material. Further, since Cu is softer than Al, there is a problem that the dicing blade is likely to be clogged and is not suitable for cutting by the blade dicing method.

  Therefore, when cutting a semiconductor device having an insulating layer using a low dielectric material or a wiring layer using Cu, a laser dicing method, a stealth dicing method, or recently a plasma dicing method instead of the conventional blade dicing method. Laws are being used.

JP 2001-168231 A

  However, since expensive equipment is required to perform the laser dicing method, the stealth dicing method, the plasma dicing method, etc., there is a problem that the manufacturing cost of the semiconductor device is increased. In addition, it is necessary to adjust process conditions for each type or type of semiconductor device, and it is difficult to ensure stable quality. For example, due to a slight difference in the layer configuration of the semiconductor integrated circuit, peeling of the low dielectric film or chipping occurs even in the laser dicing method.

  The present invention has been made in view of the above-described problems, and can cut an electronic device capable of suppressing an increase in manufacturing cost of an electronic device including a semiconductor device and preventing damage to a low dielectric film. It aims to provide a method.

According to one aspect of the cutting method of the electronic device, the electronic device is cut by a first step of preparing an electronic device in which a plurality of insulating layers and a plurality of wiring layers are stacked on a substrate, and a step including a blast process. region to remove the entire wiring layer and full insulation layer present possess a second step of exposing the substrate, and a third step of cutting by the substrate blade which is exposed to the cutting area, the said The second step includes a 2A step of forming a resist film that exposes the severable region of the electronic device, and a blast treatment of the severable region through the resist film, so that the outermost surface existing in the severable region 2B step of exposing the wiring layer, 2C step of removing the exposed outermost wiring layer by etching, blasting the severable region again through the resist film, and cutting is possible A first 2D step of exposing the substrate to remove the entire wiring layer and full insulation layer remaining range, and requirements to include.
According to another aspect of the method for cutting the electronic device, the electronic device includes a first step of preparing an electronic device in which a plurality of insulating layers and a plurality of wiring layers are stacked on a substrate, and a step including a blast process. A second step of exposing the substrate by removing all wiring layers and all insulating layers existing in the cuttable region, and a third step of cutting the substrate exposed in the cuttable region by a blade, The second step includes a second A step of forming a resist film that exposes the severable region of the electronic device, and the outermost wiring existing in the severable region through the resist film. And a second E step of exposing the substrate by removing all wiring layers and all insulating layers existing in the severable region by wet blasting using a solvent containing a substance capable of dissolving the layer. And

  According to the disclosed technology, it is possible to provide a method for cutting an electronic device that can suppress an increase in manufacturing cost of an electronic device including a semiconductor device and can prevent damage to a low dielectric film.

It is sectional drawing which illustrates the conventional semiconductor device. It is FIG. (The 1) which illustrates the manufacturing process of the conventional semiconductor device. It is FIG. (2) which illustrates the manufacturing process of the conventional semiconductor device. 1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment. 6 is a diagram (part 1) illustrating a manufacturing process of the semiconductor device according to the first embodiment; FIG. FIG. 6 is a second diagram illustrating the manufacturing process of the semiconductor device according to the first embodiment; FIG. 6 is a diagram (part 3) illustrating the manufacturing process of the semiconductor device according to the first embodiment; FIG. 8 is a diagram (No. 4) for exemplifying the manufacturing process for the semiconductor device according to the first embodiment; FIG. 8 is a diagram (No. 5) for exemplifying the manufacturing process for the semiconductor device according to the first embodiment; FIG. 10 is a diagram (No. 6) for exemplifying the manufacturing process for the semiconductor device according to the first embodiment; FIG. 7 is a diagram (No. 7) for exemplifying the manufacturing process for the semiconductor device according to the first embodiment; FIG. 8 is a diagram (No. 8) for exemplifying the manufacturing process for the semiconductor device according to the first embodiment; It is a figure which illustrates the manufacturing process of the semiconductor device which concerns on 2nd Embodiment.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. In each of the following embodiments, an example in which the electronic device cutting method according to the present invention is applied to a semiconductor device which is one of the electronic devices will be described.

<First Embodiment>
[Structure of Semiconductor Device According to First Embodiment]
FIG. 4 is a cross-sectional view illustrating the semiconductor device according to the first embodiment. Referring to FIG. 4, the semiconductor device 10 includes a thinned semiconductor substrate 11, a semiconductor integrated circuit 12, and a notch 20.

For example, the semiconductor substrate 11 is obtained by cutting a thinned semiconductor wafer into pieces. Examples of the material of the semiconductor substrate 11 include Si, Ge, GaAs, etc., but the following description will be made with Si as an example. The thickness T ₁ of the semiconductor substrate 11 can be set to, for example, about 50 μm to 800 μm.

  The semiconductor integrated circuit 12 includes a first insulating layer 13, a first wiring layer 14, a second insulating layer 15, a second wiring layer 16, a third insulating layer 17, a third wiring layer 18, and a fourth wiring layer. The insulating layer 19 is included.

  The first insulating layer 13, the first wiring layer 14, the second insulating layer 15, the second wiring layer 16, the third insulating layer 17, the third wiring layer 18, and the fourth insulating layer 19 constituting the semiconductor integrated circuit 12 are The semiconductor substrate 11 is sequentially stacked on one side (hereinafter, one side of the semiconductor substrate 11 is referred to as a main surface). The wiring layers are electrically connected as appropriate by vias (not shown). The third wiring layer 18 is composed of metal layers 18a and 18b.

  As a material of the metal layer 18a constituting the first wiring layer 14, the second wiring layer 16, and the third wiring layer 18, for example, Cu or the like can be used. As a material of the metal layer 18b constituting the third wiring layer 18, for example, Al or the like can be used. When Cu is used as the material of the metal layer 18a constituting the first wiring layer 14, the second wiring layer 16, and the third wiring layer 18, the wiring resistance of each wiring layer is reduced as compared with the case where Al is used. It can be greatly reduced. The first wiring layer 14, the second wiring layer 16, the second wiring layer 16, and the third wiring layer 18 are prevented from diffusing Cu, which is a material of the metal layer 18 a. The metal layer 18a constituting the layer 16 and the third wiring layer 18 may be covered with Ta, TaN, or the like. Hereinafter, a case where Cu is used as a material of the metal layer 18a constituting the first wiring layer 14, the second wiring layer 16, and the third wiring layer 18 will be described as an example.

  The third wiring layer 18 is the outermost wiring layer and functions as a pad to which a bonding wire or the like is connected. Therefore, the third wiring layer 18 is often thicker than the inner layer. The thickness of the metal layer 18b constituting the first wiring layer 14, the second wiring layer 16, and the third wiring layer 18 can be set to, for example, about 0.2 μm. The thickness of the metal layer 18a constituting the third wiring layer 18 can be set to about 1.6 μm, for example.

  The first insulating layer 13, the second insulating layer 15, the third insulating layer 17, and the fourth insulating layer 19 are so-called interlayer insulating films. The fourth insulating layer 19 has an opening 19x, and a part of the third wiring layer 18 is exposed in the opening 19x. The third wiring layer 18 exposed in the opening 19x functions as a pad to which a bonding wire or the like is connected.

  As a material for the first insulating layer 13, the second insulating layer 15, the third insulating layer 17, and the fourth insulating layer 19, a low dielectric material (so-called Low-k material) having a low dielectric constant is used. An example of the low dielectric material is SiOC. Other examples of the low dielectric material include SiOF and organic polymer materials. The dielectric constant of the 1st insulating layer 13, the 2nd insulating layer 15, the 3rd insulating layer 17, and the 4th insulating layer 19 can be about 3.0-3.5, for example.

By using a low dielectric material such as SiOC as the material of the first insulating layer 13, the second insulating layer 15, the third insulating layer 17, and the fourth insulating layer 19, each wiring is compared with the case where SiO ₂ is used. Parasitic capacitance such as interlayer capacitance can be reduced, and an increase in signal delay can be suppressed. The thickness of the 1st insulating layer 13, the 2nd insulating layer 15, the 3rd insulating layer 17, and the 4th insulating layer 19 can be about 0.5-2 micrometers, for example.

The notch 20 is formed at the outer edge of the semiconductor device 10. For example, if the semiconductor substrate 11 has a quadrangular shape in plan view, the notch 20 is formed in a frame shape on the outer edge portion of the semiconductor substrate 11 in plan view. The width of the notch 20 is smaller than the width of the scribe region B (for example, about 30 to 200 μm). The depth _{D 1} of the from the main surface of the semiconductor substrate 11 of the notch 20 may be, for example 3~10μm about.

[Semiconductor Device Cutting Method According to First Embodiment]
5 to 12 are diagrams illustrating the manufacturing process of the semiconductor device according to the first embodiment. 5 to 12, the same components as those of the semiconductor device 10 shown in FIG. 4 are denoted by the same reference numerals, and the description thereof may be omitted. 5 is a plan view and FIGS. 6 to 12 are cross-sectional views.

  First, in the process shown in FIG. 5, a semiconductor wafer 11A is prepared. The semiconductor wafer 11 </ b> A has a plurality of semiconductor device formation regions A and a scribe region B that separates the plurality of semiconductor device formation regions A. C in the scribe region B indicates a position where the dicing blade or the like cuts the semiconductor wafer 11A or the like (hereinafter referred to as “substrate cutting position C”). The semiconductor wafer 11A is thinned and cut at the substrate cutting position C, whereby the semiconductor substrate 11 (see FIG. 4) described above is formed. The diameter of the semiconductor wafer 11A is, for example, 6 inches (about 150 mm), 8 inches (about 200 mm), 12 inches (about 300 mm), or the like. The thickness of the semiconductor wafer 11A is, for example, 0.625 mm (diameter = 6 inches), 0.725 mm (diameter = 8 inches), 0.775 mm (diameter = 12 inches), or the like.

Next, in the step shown in FIG. 6, the first insulating layer 13, the first wiring layer 14, the second insulating layer 15, the second wiring layer 16, and the third insulating layer are formed on the main surface of the semiconductor wafer 11A by a known method. 17, the third wiring layer 18, and the fourth insulating layer 19 are stacked to form the semiconductor integrated circuit 12. Then, the back surface (surface opposite to the main surface) of the semiconductor wafer 11A is ground and thinned. The thickness T ₁ of the semiconductor wafer 11A can be set to, for example, about 50 μm to 800 μm.

  Here, Cu is used as the material of the metal layer 18a constituting the first wiring layer 14, the second wiring layer 16, and the third wiring layer 18. The third wiring layer 18 is the outermost wiring layer and functions as a pad to which a bonding wire or the like is connected. Therefore, the third wiring layer 18 is often thicker than the inner layer. The thickness of the metal layer 18b constituting the first wiring layer 14, the second wiring layer 16, and the third wiring layer 18 can be set to, for example, about 0.2 μm. The thickness of the metal layer 18a constituting the third wiring layer 18 can be set to about 1.6 μm, for example.

  As a material of the first insulating layer 13, the second insulating layer 15, the third insulating layer 17, and the fourth insulating layer 19, a low dielectric material (so-called Low-k material) having a low dielectric constant is used. An example of the low dielectric material is SiOC. The dielectric constant of the 1st insulating layer 13, the 2nd insulating layer 15, the 3rd insulating layer 17, and the 4th insulating layer 19 can be about 3.0-3.5, for example. The thickness of the 1st insulating layer 13, the 2nd insulating layer 15, the 3rd insulating layer 17, and the 4th insulating layer 19 can be about 0.5-2 micrometers, for example.

  Note that the first insulating layer 13, the first wiring layer 14, the second insulating layer 15, the second wiring layer 16, the third insulating layer 17, the third wiring layer 18, and the fourth insulating layer 19 are also formed in the scribe region B. Exists. The first wiring layer 14, the second wiring layer 16, and the third wiring layer 18 existing in the scribe region B are provided for use in electrical inspection of the semiconductor device 10 before singulation. Since the first wiring layer 14, the second wiring layer 16, and the third wiring layer 18 existing in the scribe region B are used only in the wafer process, they are removed when the semiconductor device 10 is separated.

  Next, in the process shown in FIG. 7, a resist is applied on the fourth insulating layer 19 and the third wiring layer 18 exposed in the opening 19x, and the applied resist is exposed and developed to remove the scribe region B. A resist film 25 is formed on the fourth insulating layer 19 and the third wiring layer 18 exposed in the opening 19x. The resist film 25 functions as a mask for blasting in the steps shown in FIGS. 8 and 10 to be described later, but part of the surface of the resist film 25 is also shaved by blasting. Therefore, the resist film 25 needs to be formed to a thickness that can maintain the function as a mask even if a part of the surface is shaved by blasting. The thickness of the resist film 25 can be set to, for example, about 50 μm. As the resist film 25, for example, a urethane-based dry film can be used.

  Next, in the step shown in FIG. 8, blasting is performed using the resist film 25 as a mask to remove at least the fourth insulating layer 19 and the metal layer 18b constituting the third wiring layer 18 present in the scribe region B, The metal layer 18a constituting the wiring layer 18 is exposed. Grooves 26 are formed on both sides of the metal layer 18a constituting the third wiring layer 18 by blasting. The cross-sectional shape of the groove portion 26 is, for example, a U shape.

Here, the blasting process is a process of mechanically adjusting the surface roughness of the object to be processed by spraying an abrasive on the object to be processed at a high pressure. The blasting, e A chromatography blasting, shot blasting, there is a wet blasting treatment or the like, in particular, the surface of the abrasive alumina abrasive grains and spherical silica abrasive grains or the like is dispersed in a solvent such as water to be treated It is preferable to use a wet blasting process in which a fine region is polished by being collided with each other. This is because, when wet blasting is used, polishing that is extremely dense and less damaged than air blasting or shot blasting is possible. Further, in the wet blasting process, the abrasive is dispersed in a solvent such as water, so that the abrasive is not scattered in the air as dust like the air blasting process or the shot blasting process.

  The particle size of an abrasive such as alumina abrasive grains or spherical silica abrasive grains used for wet blasting can be set to about 5 to 20 μm, for example. The concentration of the abrasive such as alumina abrasive grains and spherical silica abrasive grains dispersed in a solvent such as water can be set to 14 vol%, for example. Moreover, the injection pressure at the time of injecting the abrasive | polishing agent disperse | distributed to solvents, such as water, to the surface of a to-be-processed object can be 0.25 MPa, for example.

  Next, in the process shown in FIG. 9, wet etching is performed using the resist film 25 as a mask, and the metal layer 18a constituting the third wiring layer 18 existing in the scribe region B is removed. For the wet etching, for example, a ferric chloride aqueous solution or an ammonium sulfate-based Cu etching solution can be used.

  Note that the metal layer 18a constituting the third wiring layer 18 is not removed by blasting in the step shown in FIG. 8 but removed by wet etching in the step shown in FIG. 9 for the following reason. That is, the metal layer 18b (for example, thickness 0.2 μm) constituting the third wiring layer 18 is extremely thinner than the metal layer 18a (for example, thickness 1.6 μm) constituting the third wiring layer 18, and Since the material is Al which is harder than Cu, it can be completely removed only by blasting. On the other hand, the metal layer 18a constituting the third wiring layer 18 is made of soft Cu as compared with Al, and is extremely thick compared with the metal layer 18b constituting the third wiring layer 18, so that only the blasting process is performed. This is because it is difficult to remove completely.

Next, in the process shown in FIG. 10, blasting is performed again using the resist film 25 as a mask to remove all wiring layers and all insulating layers remaining in the scribe region B, thereby exposing the semiconductor wafer 11A. Grooves 27 are formed in the scribe region B by blasting. The cross-sectional shape of the groove portion 27 is, for example, a U shape. The groove part 27 is finally cut in the vicinity of the center part to become the notch part 20. The width of the groove 27 is substantially the same as the width of the scribe region B (for example, about 30 to 200 μm). Groove 27 depth _{D 1} of the from the main surface of the semiconductor wafer 11A of may be, for example 3~10μm about. The first wiring layer 14 and the second wiring layer 16 (for example, thickness 0.2 μm) are extremely thin compared to the metal layer 18 a (for example, thickness 1.6 μm) constituting the third wiring layer 18. Even if the material is Cu which is softer than Al, it can be completely removed only by blasting.

Next, in a step shown in FIG. 11, the resist film 25 shown in FIG. 10 is removed.
When a dry film is used as the resist film 25, it can be removed, for example, by swelling and peeling with an alkaline aqueous solution. However, when selecting the alkaline aqueous solution, it is necessary to select a solution that does not etch or corrode the metal layer 18b. Therefore, sodium hydroxide (NaOH) and general monoethanolamine cannot be selected.

  Next, in the process shown in FIG. 12, the structure shown in FIG. Thereby, a plurality of semiconductor devices 10 are manufactured. The semiconductor substrate 11 is obtained by cutting the semiconductor wafer 11A. A cutout portion 20 is formed in the outer edge portion of the separated semiconductor device 10. The notch portion 20 is formed by cutting the groove portion 27 in the vicinity of the center portion.

  Here, the first insulating layer 13, the first wiring layer 14, the second insulating layer 15, the second wiring layer 16, the third insulating layer 17, the third wiring layer 18, and the first wiring layer provided in the scribe region B are provided. The four insulating layers 19 are all removed by the step shown in FIG. Accordingly, in the step shown in FIG. 12, only the semiconductor wafer 11A may be cut at the substrate cutting position C by the blade dicing method using the dicing blade 28. That is, it is not necessary to cut each insulating layer made of a low dielectric material with extremely low mechanical strength and each wiring layer made of Cu softer than Al with a dicing blade. As a result, damage to the insulating layer made of a low dielectric material such as chipping or clogging of the dicing blade does not occur, so the semiconductor device is cut using the same blade dicing method as before. Can be singulated.

  Note that in this application, when an electronic device including a semiconductor device is singulated, a region that does not affect characteristics or the like even if it is cut may be referred to as a cuttable region. In the present embodiment, the cuttable area is included in the scribe area B.

  As described above, according to the semiconductor device cutting method according to the first embodiment, a part of the insulating layer existing in the scribe region is removed by blasting to expose the outermost wiring layer. Then, after the outermost wiring layer is removed by wet etching, all the wiring layers and all the insulating layers remaining in the scribe region are removed by blasting again. Then, only the semiconductor wafer exposed in the scribe region is cut by a blade dicing method using a dicing blade. As a result, damage to the insulating layer using a low dielectric material such as chipping and clogging of the dicing blade do not occur. Therefore, a low dielectric material is used for the insulating layer and Cu is used for the wiring layer. The conventional semiconductor device can be cut into individual pieces by using the same blade dicing method as in the prior art.

  That is, a semiconductor device using a low-dielectric material for the insulating layer and Cu for the wiring layer, a laser dicing method, a stealth dicing method, or a plasma dicing method that requires expensive equipment and increases the manufacturing cost of the semiconductor device. Without using the above, it is possible to cut and separate into pieces using the same blade dicing method as in the past, and it is possible to suppress an increase in manufacturing cost of the semiconductor device.

<Second Embodiment>
In the second embodiment, a method for manufacturing the semiconductor device 10 by using a semiconductor device cutting method different from that of the first embodiment will be described.

  FIG. 13 is a diagram illustrating a manufacturing process of the semiconductor device according to the second embodiment. In FIG. 13, the same components as those of the semiconductor device 10 shown in FIG.

First, steps similar to those in FIGS. 5 to 7 of the first embodiment are performed to manufacture the structure shown in FIG. Next, in the step shown in FIG. 13, the structure shown in FIG. 7 is subjected to wet blasting using the resist film 25 as a mask to remove all wiring layers and all insulating layers, thereby exposing the semiconductor wafer 11A. Grooves 27 are formed in the scribe region B by wet blasting. The cross-sectional shape of the groove portion 27 is, for example, a U shape. The groove part 27 is finally cut in the vicinity of the center part to become the notch part 20. The width of the groove 27 is substantially the same as the width of the scribe region B (for example, about 30 to 200 μm). Groove 27 depth _{D 1} of the from the main surface of the semiconductor substrate 11 may be, for example 3~10μm about.

  In the wet blast treatment, an abrasive such as alumina abrasive grains or spherical silica abrasive grains is usually dispersed in a solvent such as water. However, in the step shown in FIG. 13, a polishing agent such as alumina abrasive grains or spherical silica abrasive grains is dispersed in a solvent such as water, and a substance capable of dissolving Cu constituting the outermost wiring layer is further mixed. As a substance capable of dissolving Cu, for example, ferric chloride or ammonium sulfate-based Cu etching solution can be used. Thus, a solvent such as water in which an abrasive such as alumina abrasive grains or spherical silica abrasive grains is dispersed contains, for example, ferric chloride or ammonium sulfate, and Cu can be removed. As a result, the third wiring layer 18 is made of soft Cu compared to Al, extremely thick compared to other wiring layers, and difficult to remove by blasting alone in the first embodiment. All the wiring layers and all the insulating layers including the metal layer 18a to be formed can be completely removed by only one wet blasting process, and the semiconductor wafer 11A can be exposed to the scribe region B.

  Next, a plurality of semiconductor devices 10 are manufactured by performing the same steps as those in FIGS. 11 and 12 of the first embodiment.

  As described above, the semiconductor device cutting method according to the second embodiment has the same effects as the semiconductor device cutting method according to the first embodiment, but further has the following advantages.

  That is, a relatively thick Cu wiring layer, which is difficult to remove by blasting alone, can be dissolved by performing wet blasting on the scribe region using a solvent containing a substance capable of dissolving Cu. Therefore, the entire wiring layer (including the relatively thick Cu wiring layer) and the entire insulating layer existing in the scribe region are completely removed by one wet blast process. As a result, the process can be simplified as compared with the semiconductor device cutting method according to the first embodiment, which requires two blast treatments, and the increase in the manufacturing cost of the semiconductor device is further suppressed. be able to.

  The preferred embodiment of the present invention has been described in detail above. However, the present invention is not limited to the above-described embodiment, and various modifications can be made to the above-described embodiment without departing from the scope of the present invention. And substitutions can be added.

  For example, in the first and second embodiments, an example in which a semiconductor device made of Si or the like is cut has been described. However, the present invention can be applied to cutting an electronic device including a semiconductor device. The electronic device referred to here includes, in addition to a semiconductor device, an interposer (such as a Si interposer) in which a wiring layer and an insulating layer are formed, a glass wafer, a sapphire substrate, a ceramic substrate (such as LTCC), and a quartz substrate. When the present invention is applied to such an electronic device, the same effects as when the present invention is applied to a semiconductor device can be obtained.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Semiconductor substrate 11A Semiconductor wafer 12 Semiconductor integrated circuit 13 1st insulating layer 14 1st wiring layer 15 2nd insulating layer 16 2nd wiring layer 17 3rd insulating layer 18 3rd wiring layer 18a, 18b Metal layer 19 1st 4 Insulating layer 19x Opening 20 Notch 25 Resist film 26, 27 Groove 28 Dicing blade A Semiconductor device formation area B Scribe area C Substrate cutting position D ₁ depth T ₁ thickness

Claims (8)

A first step of preparing an electronic device in which a plurality of insulating layers and a plurality of wiring layers are stacked on a substrate;
A second step of exposing the substrate by removing all wiring layers and all insulating layers present in the cuttable region of the electronic device by a step including blasting;
Have a, and a third step of cutting by the substrate blade which is exposed to the cutting area,
The second step includes
Forming a resist film that exposes the severable region of the electronic device; and
2B step of blasting the severable region through the resist film to expose the outermost wiring layer present in the severable region;
A 2C step of removing the exposed outermost wiring layer by etching;
A second D step of blasting the severable region again through the resist film to remove all wiring layers and all insulating layers remaining in the severable region to expose the substrate; Method. A first step of preparing an electronic device in which a plurality of insulating layers and a plurality of wiring layers are stacked on a substrate;
A second step of exposing the substrate by removing all wiring layers and all insulating layers present in the cuttable region of the electronic device by a step including blasting;
Have a, and a third step of cutting by the substrate blade which is exposed to the cutting area,
The second step includes
Forming a resist film that exposes the severable region of the electronic device; and
All the wiring layers present in the severable region are subjected to wet blasting using the solvent containing a substance capable of dissolving the outermost wiring layer present in the severable region through the resist film. And a second E step of removing the entire insulating layer to expose the substrate . It said plurality of insulating layers, the cutting method of an electronic device according to claim 1 or 2, wherein is configured to include a low dielectric material. The wiring layer of the uppermost present in the cutting area, the cutting method of the electronic device according to any one of claims 1 to 3 is configured to include a Cu. Outermost wiring layers, the cutting method of the cleavable thickness than the other wiring layer existing region is thicker claims 1 to an electronic device according to one of 4 present in the cutting area. The electronic device cutting method of an electronic device according to any one of claims 1 to 5 which is a semiconductor device. A plurality of the semiconductor devices are formed on a semiconductor wafer, and a scribe region is disposed between the plurality of semiconductor devices,
The electronic device cutting method according to claim 6 , wherein the severable region is included in the scribe region. The electronic device cutting method according to claim 7 , wherein the plurality of semiconductor devices are separated into pieces by the third step.

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