JP4642912B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko gaming machine or a coin gaming machine in which a game is performed in accordance with a player's operation, and more particularly to a gaming machine in which a game is performed in accordance with a player's operation in a gaming area on a gaming board. .

  As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a prize area such as a prize opening provided in the game area, a predetermined number of prize balls are paid out to the player. There is something to be done. Further, a variable display unit capable of changing the display state is provided, and is configured to give a predetermined game value to the player when the display result of the variable display unit becomes a predetermined specific display mode There is.

  The display result of the variable display unit that displays the special symbol is a combination of a specific display mode that is determined in advance. Note that the game value is the right that the state of the variable winning ball device provided in the gaming area of the gaming machine is advantageous for a player who is likely to win a ball, or the advantageous state for a player. It is to generate.

  When the big hit occurs, for example, the big winning opening is opened a predetermined number of times, and the game shifts to a big hit gaming state where the hit ball is easy to win. And in each open period, if there is a prize for a predetermined number (for example, 10) of the big prize opening, the big prize opening is closed. And the number of times the special winning opening is opened is fixed to a predetermined number (for example, 16 rounds). An opening time (for example, 29.5 seconds) is determined for each opening, and even if the number of winnings does not reach a predetermined number, the big winning opening is closed when the opening time elapses. Further, when a predetermined condition (for example, winning in the V zone provided in the big prize opening) is not established at the time when the big prize opening is closed, the big hit gaming state is ended.

  In addition, among the combinations of display modes other than the “big hit” combination, the variable display in which the display result has already been derived and displayed at the stage where some of the display results of the plurality of variable display units have not yet been derived and displayed. A state in which the display mode of the part satisfies a display condition that is a combination of specific display modes is referred to as “reach”. Then, if the display result of the identification information variably displayed on the variable display portion does not satisfy the condition of “reach”, it becomes “missing”, and the variable display state ends. A player plays a game while enjoying how to generate a big hit.

  In such a gaming machine, a speaker is provided and various sound effects are emitted from the speaker as the game progresses in order to enhance the gaming effect. In addition, light emitters such as lamps and LEDs are provided in the game area and frame of the gaming machine, and the light emitters are turned on and off as the game progresses in order to enhance the game effect. Since each light-emitting body is displayed and controlled in accordance with the progress of the game, the light-on / off control of the light-emitting body is generally performed by a game control means for controlling the progress of the game. Hereinafter, the game control means and the other control means may be referred to as electrical component control means, respectively.

  Game control means for controlling the progress of a game is generally realized by a microcomputer. And in order to prevent the program runaway etc. resulting from noise, it is comprised so that a game control program may be restarted repeatedly for every predetermined period (for example, 2 ms). The game control program includes various processing programs. Also, interrupt processing may be used to effectively perform game control. For example, if each predetermined period of 2 ms is referred to as a single program execution time, it will be executed once before execution of all the processing programs constituting the game control program due to the occurrence of interrupt processing or the like. The program execution time may elapse. When such a situation occurs, processing that is not executed in a single program execution time occurs, which impedes game control.

Therefore, an object of the present invention is to provide a gaming machine that can reduce the control burden of the game control means.

The gaming machine according to the present invention includes a variable display unit that variably displays a plurality of types of identification information that can identify each of them, and displays and displays a display result, and a game is displayed when a specific display result is derived and displayed on the variable display unit. A game machine that controls a specific gaming state that is advantageous to the player, a game control means for controlling the progress of the game, a display control means for controlling the variable display section, and a stored content for a predetermined period even when the power supply is stopped The fluctuation data storage means for storing fluctuation data generated when the game control means performs control, the first power supply used in the gaming machine is monitored, and the voltage of the first power supply is monitored. First power monitoring means for outputting a detection signal when the voltage becomes equal to or lower than the first detection voltage, and a second power supply having a voltage lower than the voltage of the first power supply is monitored, and the voltage of the second power supply is the first detection voltage. Lower than the second detection voltage And a second power supply monitoring means for outputting an operation stop signal at a time, wherein the game control means includes a command output means for outputting a command indicating that the variable display unit is controlled to the display control means. In response to the detection signal from the power supply monitoring means, processing for stopping power supply for saving the data for restoring the control state in the fluctuation data storage means is executed, and the operation stop signal from the second power supply monitoring means is When the operation is stopped and power supply is started, recovery control is executed to restore the control state to the state before starting the power supply stop process based on the stored contents stored in the fluctuation data storage means. The command output means, when starting the variable display of the identification information, a variable display pattern command for specifying the variable display pattern of the identification information in the variable display section, and A display result command for specifying the display result of the identification information in the variable display section is output, and when the variable information display is terminated, a stop command indicating the stop of the identification information is output, and a variable display pattern command and display are displayed. After the result command is output and before the stop command is output, the variable display command is not output, and the display control means performs variable display of the identification information on the variable display unit based on the variable display pattern command. The display result of the identification information specified by the display result command is stopped and displayed on the variable display unit based on the start and stop commands .
According to the present invention, there is an effect that the control burden of the game control means can be reduced.

It is the front view which looked at the pachinko game machine from the front. It is the front view which looked at the game board of the pachinko machine from the front. It is the rear view which looked at the mechanism board of the pachinko game machine from the back. It is a block diagram which shows the circuit structural example of a game control board (main board). It is a block diagram which shows the circuit structure in a display control board. It is a block diagram which shows the circuit structure in an audio | voice control board. It is a block diagram which shows the circuit structure in a lamp control board. It is a block diagram which shows one structural example of CPU periphery for a power supply monitoring and a power supply backup. It is a block diagram which shows one structural example of a power supply board. It is a flowchart which shows the example of the main process which CPU in a main board | substrate performs. It is explanatory drawing which shows the example of the determination method of whether to perform a game state restoration process. It is a flowchart which shows the example of an initialization process. It is a flowchart which shows the example of an initialization process. It is a flowchart which shows the example of a 2ms timer interruption process. It is a flowchart which shows the example of a game control process. It is explanatory drawing which shows each random number. It is a flowchart which shows the process which determines that the hit ball won the start winning opening. It is a flowchart which shows the process which determines the stop symbol of variable display, and the process which determines a reach kind. It is a flowchart which shows the process of jackpot determination. It is a flowchart which shows a special symbol process process. It is a flowchart which shows a normal symbol process process. It is a flowchart which shows a gate switch process. It is explanatory drawing which shows the hit / off of the random number for hit determination regarding a normal symbol. It is a flowchart which shows the example of a power failure generation | occurrence | production NMI process. It is explanatory drawing for demonstrating the example of the backup parity data creation method. It is a flowchart which shows the example of a game state restoration process. It is a timing diagram which shows the relationship between the fluctuation | variation of a special symbol, and a display control command. It is explanatory drawing which shows an example of the command form of a display control command. It is explanatory drawing which shows an example of the content of a display control command. It is a timing diagram which shows an example of the transmission form of a display control command. It is explanatory drawing which shows an example of the command form of an audio | voice control command. It is explanatory drawing which shows an example of the content of a voice control command. It is a timing diagram which shows an example of the transmission form of an audio | voice control command. It is explanatory drawing which shows an example of the command form of a lamp control command. It is explanatory drawing which shows an example of the content of a lamp control command. It is a timing diagram which shows an example of the transmission form of a lamp control command. It is a flowchart which shows the command control process in a game control process. It is a flowchart which shows an example of a data output process. It is a flowchart which shows a command transmission subroutine. It is a flowchart which shows the main process which CPU for audio | voice control performs. It is a flowchart which shows a timer interruption process. It is a flowchart which shows a command reception interruption process. It is a flowchart which shows an audio | voice control process. It is a flowchart which shows the main process which CPU for lamp control performs. It is a flowchart which shows a timer interruption process. It is a flowchart which shows a command reception interruption process. It is a flowchart which shows a lamp control process. It is a flowchart which shows an example of a lamp and LED control process.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
First, the overall configuration of a pachinko gaming machine that is an example of a gaming machine will be described. 1 is a front view of the pachinko gaming machine 1 as seen from the front, FIG. 2 is an overall rear view showing the internal structure of the pachinko gaming machine 1, and FIG. 3 is a rear view of the gaming board of the pachinko gaming machine 1 as seen from the back. In the following embodiments, a pachinko gaming machine will be described as an example. However, the gaming machine according to the present invention is not limited to a pachinko gaming machine, and may be a coin gaming machine, for example. It can also be applied to image-type gaming machines and slot machines.

  As shown in FIG. 1, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2 is a hitting ball supply tray 3. Under the hitting ball supply tray 3, there are provided an extra ball receiving tray 4 for storing the stored balls overflowing from the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing the hitting ball. A game board 6 is detachably attached to the rear side of the glass door frame 2. A game area 7 is provided in front of the game board 6.

  Near the center of the game area 7, there is provided a variable display device 8 including a variable display section 9 for variably displaying a plurality of kinds of symbols and a variable display 10 using 7 segment LEDs. Further, a passage memory display (ordinary symbol memory display) 41 composed of four LEDs is provided below the variable display 10. In this embodiment, the variable display section 9 has three symbol display areas of “left”, “middle”, and “right”. A passing gate 11 for guiding a hit ball is provided on the side of the variable display device 8. The hit ball that has passed through the passage gate 11 is guided to the start winning opening 14 through the ball outlet 13. In the path between the passing gate 11 and the ball outlet 13, there is a gate switch 12 that detects a hit ball that has passed through the passing gate 11. The winning ball that has entered the start winning opening 14 is guided to the back of the game board 6 and detected by the start opening switch 17. A variable winning ball device 15 that opens and closes is provided below the start winning opening 14. The variable winning ball device 15 is opened by a solenoid 16.

  An open / close plate 20 that is opened by a solenoid 21 in a specific gaming state (big hit state) is provided below the variable winning ball device 15. In this embodiment, the opening / closing plate 20 is a means for opening and closing the special winning opening. Of the winning balls guided from the opening / closing plate 20 to the back of the game board 6, the winning ball entering one (V zone) is detected by the V count switch 22. A winning ball from the opening / closing plate 20 is detected by the count switch 23. At the bottom of the variable display device 8, a start winning memory display 18 having four display units for displaying the number of winning balls that have entered the start winning opening 14 is provided. In this example, with the upper limit being four, each time there is a start prize, the start prize storage display 18 increases the number of lit display units one by one. Then, each time the variable display of the variable display unit 9 is started, the lit display unit is reduced by one.

  The game board 6 is provided with a plurality of winning openings 19, 24, and winning of the game balls to the winning openings 19, 24 is detected by winning opening switches 19a, 24a. Decorative lamps 25 blinking during the game are provided around the left and right sides of the game area 7, and an outlet 26 for absorbing a hit ball that has not won a prize is provided below. Two speakers 27 that emit sound effects are provided on the left and right upper portions outside the game area 7. On the outer periphery of the game area 7, a game effect LED 28a and game effect lamps 28b and 28c are provided.

  In this example, a prize ball lamp 51 that is lit when a prize ball is paid out is provided in the vicinity of one speaker 27, and a ball break lamp 52 that is lit when a supply ball is cut out in the vicinity of the other speaker 27. Is provided. Further, FIG. 1 also shows a card unit 50 that is installed adjacent to the pachinko gaming machine 1 and enables lending of a ball by inserting a prepaid card.

  The card unit 50 has a usable indicator lamp 151 indicating whether or not it is in a usable state, and when the remaining amount information recorded in the card has a fraction (a number less than 100 yen), the fraction is indicated as a hitting tray. 3, a fraction display switch 152 for displaying on a frequency display LED provided in the vicinity of 3, a connecting table direction indicator 153 indicating which side of the pachinko gaming machine 1 corresponds to the card unit 50, in the card unit 50 Check the card insertion indicator lamp 154 indicating that a card is inserted, the card insertion slot 155 into which a card as a recording medium is inserted, and the mechanism of the card reader / writer provided on the back of the card insertion slot 155. In some cases, a card unit lock 156 is provided for releasing the card unit 50.

  The hit ball fired from the hit ball launching device enters the game area 7 through the hit ball rail, and then descends the game area 7. When the hit ball is detected by the gate switch 12 through the passing gate 11, the display number of the variable display 10 changes continuously. Further, when the hit ball enters the start winning opening 14 and is detected by the start opening switch 17, the symbol in the variable display portion 9 starts to rotate if the variation of the symbol can be started. If it is not in a state where the change of the symbol can be started, the start winning memory is increased by one.

  The rotation of the image in the variable display unit 9 stops when a certain time has elapsed. If the combination of images at the time of the stop is a combination of jackpot symbols, the game shifts to a jackpot gaming state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or a predetermined number (for example, 10) of hit balls wins. When the hit ball enters the specific winning area while the opening / closing plate 20 is opened and is detected by the V count switch 22, a right to continue is generated and the opening / closing plate 20 is opened again. The generation of the continuation right is allowed a predetermined number of times (for example, 15 rounds).

  When the combination of images in the variable display section 9 at the time of stop is a combination of jackpot symbols with probability fluctuations, the probability of the next jackpot increases. That is, it becomes a more advantageous state for the player in a high probability state. Further, when the stop symbol on the variable display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the high probability state, the probability that the stop symbol in the variable display 10 becomes a winning symbol is increased, and the opening time and the number of times of opening of the variable winning ball device 15 are increased.

Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG.
On the back surface of the variable display device 8, as shown in FIG. 2, a game ball tank 38 is provided on the upper part of the mechanism plate 36, and a game ball is received from above in a state where the pachinko game machine 1 is installed on the game machine installation island. It is supplied to the game ball tank 38. The game balls in the game ball tank 38 pass through the guide rod 39 and reach the ball dispensing device 97.

  The mechanism plate 36 includes a variable display control unit 29 for controlling the variable display unit 9 via the relay board 30, a game control board (main board) 31 covered with a board case 32 and mounted with a game control microcomputer, etc. A payout control board 37 on which a relay board 33 for relaying signals between the variable display control unit 29 and the game control board 31 and a payout control microcomputer for performing payout control of prize balls and the like is installed. ing. Further, at the lower part of the mechanism plate 36, a hitting ball launching device 34 that launches a hitting ball into the game area 7 using the rotational force of the motor, game effect lamps / LEDs 28a, 28b, 28c, a prize ball lamp 51, and a ball break lamp A lamp control board 35 for sending a signal to 52 is installed.

  FIG. 3 is a rear view of the mechanism plate of the pachinko gaming machine 1 as seen from the back. As shown in FIG. 3, the game ball passing through the guide rod 39 passes through the ball break detectors (ball break switches) 187a and 187b, and reaches the ball dispensing device 97 via the ball supply rods 186a and 186b. The ball break switches 187a and 187b are switches that detect the presence or absence of a game ball in the game ball passage, but a ball break detection switch 167 that detects a shortage of supply balls in the ball tank 38 is also provided. The game balls paid out from the ball payout device 97 are supplied to the hitting ball supply tray 3 provided on the front surface of the pachinko gaming machine 1 through the connection port 45. A surplus ball passage 46 communicating with the surplus ball receiving tray 4 provided on the front surface of the pachinko gaming machine 1 is formed on the side of the communication port 45. A lot of premium balls based on the winnings are paid out and the hitting ball supply tray 3 becomes full. Finally, when the game balls reach the contact port 45 and further game balls are paid out, the game balls pass through the surplus ball passage 46. It is guided to the surplus ball receiving tray 4. When the game ball is further paid out, the sensing lever 47 presses the full tank switch 48 and the full tank switch 48 is turned on. In this state, the rotation of the stepping motor in the ball dispensing device 97 is stopped, the operation of the ball dispensing device 97 is stopped, and the driving of the hitting ball launching device 34 is stopped as necessary.

  In this embodiment, a ball payout device 97 for paying out game balls by rotation of a stepping motor is used as a ball payout device for paying out game balls by driving an electric drive source. A ball payout device having a structure for delivering a game ball may be used, or a ball payout device having a structure in which a stopper is removed by driving of an electric drive source and the game ball is paid out by its own weight may be used.

  In order to perform prize ball payout control, signals from the prize opening switches 19 a and 24 a, the start opening switch 17 and the V count switch 22 are sent to the main board 31. The CPU 56 of the main board 31 knows that a winning corresponding to six prize ball payout has occurred when the start port switch 17 is turned on. Further, when the count switch 23 is turned on, it is known that a winning corresponding to 15 prize ball payouts has occurred. Then, when the winning opening switch is turned on, it is known that a winning corresponding to ten winning ball payouts has occurred. In this embodiment, for example, a game ball won in the winning opening 24 is detected by a winning opening switch 24 a provided in a winning ball flow path from the winning opening 24 and won in the winning opening 19. Is detected by a winning port switch 19a provided in a winning ball flow path from the winning port 19.

  FIG. 4 is a block diagram illustrating an example of a circuit configuration in the main board 31. 4 also shows a payout control board 37, a lamp control board 35, a sound control board 70, a launch control board 91, and a display control board 80. The main board 31 includes a basic circuit 53 that controls the pachinko gaming machine 1 according to a program, a gate switch 12, a start port switch 17, a V count switch 22, a count switch 23, winning port switches 19a and 24a, and a winning ball count switch 301A. And a solenoid circuit 59 for driving a solenoid 16 for opening / closing the variable winning ball apparatus 15 and a solenoid 21 for opening / closing the opening / closing plate 20 in accordance with a command from the basic circuit 53. Has been.

  Further, according to the data given from the basic circuit 53, the jackpot information indicating the occurrence of the jackpot, the effective starting information indicating the number of starting winning balls used for starting the image display of the variable display unit 9, and the fact that the probability variation has occurred. An information output circuit 64 is provided for outputting the probability variation information and the like to a host computer such as a hall management computer.

  The basic circuit 53 includes a ROM 54 that stores a game control program and the like, a RAM 55 that is an example of storage means used as a work memory, a CPU 56 that performs control operations according to the program, and an I / O port unit 57. In this embodiment, the ROM 54 and RAM 55 are built in the CPU 56. That is, the CPU 56 is a one-chip microcomputer. The one-chip microcomputer only needs to incorporate at least the RAM 55, and the ROM 54 and the I / O port unit 57 may be externally attached or built-in.

  Further, the main board 31 has a system reset circuit 65 for resetting the CPU 56 when the power is turned on, and an address signal supplied from the basic circuit 53 to decode any I / O of the I / O port unit 57. An address decoding circuit 67 that outputs a signal for selecting a port is provided. Note that there is switch information input to the main board 31 from the ball dispensing device 97, but these are omitted in FIG.

  A ball hitting device for hitting and launching a game ball is driven by a drive motor 94 controlled by a circuit on the launch control board 91. Then, the driving force of the drive motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the firing control board 91 is controlled so that the hit ball is fired at a speed corresponding to the operation amount of the operation knob 5.

  In this embodiment, the lamp control means mounted on the lamp control board 35 controls the display of the start memory indicator 18, the gate passing memory indicator 41 and the decoration lamp 25 provided on the game board. At the same time, display control of the game effect lamps / LEDs 28a, 28b, 28c, the prize ball lamp 51 and the ball-out lamp 52 provided on the frame side is performed. Here, the lamp control means is an example of a light emitter control means. Further, display control of the variable display unit 9 for variably displaying the special symbol and the variable display 10 for variably displaying the normal symbol is performed by display control means mounted on the display control board 80.

  The decorative lamp 25 and the game effect lamps / LEDs 28a, 28b, and 28c are variously decoratively controlled as the game progresses. In addition, the display state of the start memory display 18 and the gate passing memory display 41 is changed when a predetermined condition is satisfied as the game progresses. Further, the prize ball lamp 51 and the ball break lamp 52 are also displayed and controlled in accordance with the state of the gaming machine. In this embodiment, lamp control means provided separately from the game control means performs display control of the decoration lamp 25 and the game effect lamps / LEDs 28a, 28b, 28c, and further, the start memory display 18, the gate passing Display control of the memory display 41, the prize ball lamp 51 and the ball break lamp 52 is also performed. Therefore, the game control means does not have to perform specific lighting / extinguishing control of the light emitters provided in the gaming machine, and the control burden on the light emitter control of the game control means is greatly reduced.

  FIG. 5 shows the circuit configuration in the display control board 80, which is an LCD (liquid crystal display device) 82, a variable display 10, and an output port (ports A and B) 571 of the main board 31, which is an example of realizing the variable display unit 9. , 572 and output buffer circuits 63A and 63B. The output port 571 outputs 8-bit data, and the output port 572 outputs a 1-bit strobe signal (INT signal).

  The display control CPU 101 operates in accordance with a program stored in the control data ROM 102. When an INT signal is input from the main board 31 via the noise filter 107 and the input buffer circuit 105B, display control is performed via the input buffer circuit 105A. Receive commands. As the input buffer circuits 105A and 105B, for example, general-purpose ICs 74HC540 and 74HC14 can be used. When the display control CPU 101 does not have an I / O port, an I / O port is provided between the input buffer circuits 105A and 105B and the display control CPU 101.

  Then, the display control CPU 101 performs display control of the screen displayed on the LCD 82 in accordance with the received display control command. Specifically, a command corresponding to the display control command is given to the VDP 103. The VDP 103 reads out necessary data from the character ROM 86. The VDP 103 generates image data to be displayed on the LCD 82 according to the input data, and outputs R, G, B signals and a synchronization signal to the LCD 82.

  5 also shows a reset circuit 83 for resetting the VDP 103, an oscillation circuit 85 for supplying an operation clock to the VDP 103, and a character ROM 86 for storing frequently used image data. The frequently used image data stored in the character ROM 86 is, for example, a person, animal, or an image made up of characters, figures, symbols, or the like displayed on the LCD 82.

  The input buffer circuits 105 </ b> A and 105 </ b> B can pass signals only in the direction from the main board 31 toward the display control board 80. Therefore, there is no room for signals to be transmitted from the display control board 80 side to the main board 31 side. That is, the input buffer circuits 105A and 105B constitute irreversible information input means together with the input ports. Even if the tampering is added to the circuit in the display control board 80, the signal output by the tampering is not transmitted to the main board 31 side.

  Note that the outputs of the output ports 571 and 572 may be output to the display control board 80 as they are. However, by providing output buffer circuits 63A and 63B capable of transmitting signals only in one direction, the main board 31 and the display control board 80 are provided. One-way signal transmission can be made more reliable. That is, the output buffer circuits 63A and 63B constitute irreversible information output means together with the output ports.

  In addition, for example, a three-terminal capacitor or a ferrite bead is used as the noise filter 107 that cuts off the high-frequency signal. However, even if noise is added to the display control command between the substrates due to the presence of the noise filter 107, the influence is removed. Is done. A noise filter may be provided also on the output side of the buffer circuits 63A and 63B of the main board 31.

  FIG. 6 is a block diagram showing a configuration example of the voice control command signal transmission portion of the main board 31 and the voice control board 70. In this embodiment, a voice control command for instructing voice output from the speaker 27 provided outside the gaming area 7 is output from the main board 31 to the voice control board 70 as the game progresses.

  As shown in FIG. 6, the voice control command is output from the output ports (output ports C and D) 573 and 574 of the I / O port unit 57 in the basic circuit 53. The output port 573 outputs 8-bit data, and the output port 574 outputs a 1-bit INT signal. In the audio control board 70, each signal from the main board 31 is input to the audio control CPU 701 via the input buffer circuits 705 and 705B. When the audio control CPU 701 does not have an I / O port, an I / O port is provided between the input buffer circuits 705A and 705B and the audio control CPU 701.

  Then, for example, a voice synthesis circuit 702 using a digital signal processor generates voice and sound effects according to instructions from the voice control CPU 701 and outputs them to the volume switching circuit 703. The volume switching circuit 703 sets the output level of the audio control CPU 701 to a level corresponding to the set volume and outputs the level to the volume amplification circuit 704. The volume amplifier circuit 704 outputs the amplified audio signal to the speaker 27.

  As the input buffer circuits 705A and 705B, for example, 74HC540 and 74HC14, which are general-purpose CMOS-ICs, are used. The input buffer circuits 705A and 705B can pass signals only in the direction from the main board 31 toward the audio control board 70. Therefore, there is no room for signals to be transmitted from the voice control board 70 side to the main board 31 side. Therefore, even if unauthorized modification is added to the circuit in the voice control board 70, a signal output by the unauthorized modification is not transmitted to the main board 31 side. A noise filter may be provided on the input side of the input buffer circuits 705A and 705B.

  In the main board 31, buffer circuits 67A and 67B are provided outside the output ports 573 and 574. As the buffer circuits 67A and 67B, for example, general-purpose CMOS-ICs 74HC250 and 74HC14 are used. According to such a configuration, since a signal input from the outside to the inside of the main board 31 is blocked, it is possible to further reliably eliminate a signal line from which a signal may be given from the voice control board 70 to the main board 31. be able to. A noise filter may be provided on the output side of the buffer circuits 67A and 67B.

  FIG. 7 is a block diagram showing signal transmission / reception portions in the main board 31 and the lamp control board 35. In this embodiment, the game effect LED 28a, the game effect lamps 28b and 28c provided on the outside of the game area 7, and the decoration lamp 25 provided on the game board are turned on / off, and the prize ball lamp 51 and the ball are out of play. A lamp control command indicating turning on / off of the lamp 52 is output from the main board 31 to the lamp control board 35. Further, a lamp control command indicating the number of lighting of the start memory display 18 and the gate passing memory display 41 is also output from the main board 31 to the lamp control board 35.

  As shown in FIG. 7, the lamp control command related to the lamp control is output from the output ports (output ports E and F) 575 and 576 of the I / O port unit 57 in the basic circuit 53. The output port 575 outputs 8-bit data, and the output port 576 outputs a 1-bit INT signal. In the lamp control board 35, a control command from the main board 31 is input to the lamp control CPU 351 via the input buffer circuits 355A and 355B. When the lamp control CPU 351 does not include an I / O port, an I / O port is provided between the input buffer circuits 355A and 355B and the lamp control CPU 351.

  In the lamp control board 35, the lamp control CPU 351 performs the game effect LED 28 a and the game effect lamp according to the turn-on / off pattern of the game effect LED 28 a, the game effect lamps 28 b and 28 c and the decoration lamp 25 defined according to each control command. 28b, 28c, and the decoration lamp 25 are turned on / off signals. The on / off signal is output to the game effect LED 28a, the game effect lamps 28b and 28c, and the decoration lamp 25. The on / off pattern is stored in the built-in ROM or external ROM of the lamp control CPU 351.

  In the main board 31, the CPU 56 outputs a control command instructing lighting of the prize ball lamp 51 when there is an unpaid prize ball remaining in the stored contents of the RAM 55, and the above-mentioned payout ball passage 186a, When the ball break switches 187a and 187b (see FIG. 3) installed upstream of 186b no longer detect a game ball, a control command is output to instruct the ball break lamp 52 to be lit. In the lamp control board 35, each control command is input to the lamp control CPU 351 via the input buffer circuits 355A and 355B. The lamp control CPU 351 turns on / off the prize ball lamp 51 and the ball-out lamp 52 in accordance with these control commands. The on / off pattern is stored in the built-in ROM or external ROM of the lamp control CPU 351.

  Further, the lamp control CPU 351 outputs a light on / off signal to the start memory display 18 and the gate passage memory display 41 in accordance with the control command.

  As the input buffer circuits 355A and 355B, for example, 74HC540 and 74HC14 which are general-purpose CMOS-ICs are used. The input buffer circuits 355A and 355B can pass signals only in the direction from the main board 31 toward the lamp control board 35. Therefore, there is no room for signals to be transmitted from the lamp control board 35 side to the main board 31 side. Even if unauthorized modification is added to the circuit in the lamp control board 35, the signal output by the unauthorized modification is not transmitted to the main board 31 side. Note that a noise filter may be provided on the input side of the input buffer circuits 355A and 355B.

  In the main board 31, buffer circuits 62A and 62B are provided outside the output ports 575 and 576. As the buffer circuits 62A and 62B, for example, general-purpose CMOS-ICs 74HC250 and 74HC14 are used. According to such a configuration, since a signal input from the outside to the inside of the main board 31 is blocked, a signal line that can give a signal from the lamp control board 70 to the main board 31 is further reliably eliminated. be able to. A noise filter may be provided on the output side of the buffer circuits 62A and 62B.

  FIG. 8 is a block diagram showing an example of the configuration around the CPU 56. As shown in FIG. 8, the voltage drop signal from the first power supply monitoring circuit (power supply monitoring means) is connected to the non-maskable interrupt terminal (XNMI terminal) of the CPU 56. The first power supply monitoring circuit is a circuit that monitors the voltage of any one of the various DC power supplies used by the gaming machine and detects a power supply voltage drop. In this embodiment, the power supply voltage of VSL is monitored, and a low level voltage drop signal is generated when the voltage value falls below a predetermined value. VSL is the largest DC voltage used in gaming machines, and is + 30V in this example. Therefore, the CPU 56 can confirm the occurrence of power interruption by the interrupt process. In this embodiment, the first power supply monitoring circuit is mounted on a power supply board described later.

  Although the system reset circuit 65 is also shown in FIG. 8, in this embodiment, the system reset circuit 65 also serves as a second power supply monitoring circuit. That is, when the power is turned on, the reset IC 651 sets the output to the low level for a predetermined time determined by the capacity of the external capacitor, and sets the output to the high level when the predetermined time elapses. That is, the reset signal is raised to a high level to make the CPU 56 operable. The reset IC 651 monitors the power supply voltage of VSL, which is the power supply voltage equal to the power supply voltage monitored by the first power supply monitoring circuit, and the voltage value is a predetermined value (the first power supply monitoring circuit outputs a voltage drop signal). When the voltage is lower than the power supply voltage value), a low level voltage drop signal is generated. Therefore, the CPU 56 performs a predetermined power supply stop process in response to the voltage drop signal from the first power supply monitoring circuit, and then the system is reset. In this embodiment, the reset signal and the voltage drop signal from the second power supply monitoring circuit are the same signal.

  As shown in FIG. 8, the reset signal from the reset IC 651 is input to the NAND circuit 947 and also input to the clear terminal of the counter IC 941 via the inverting circuit (NOT circuit) 944. The counter IC 941 counts the clock signal from the oscillator 943 when the input to the clear terminal becomes low level. The Q5 output of the counter IC 941 is input to the NAND circuit 947 via the NOT circuits 945 and 946. The Q6 output of the counter IC 941 is input to the clock terminal of the flip-flop (FF) 942. The D input of the flip-flop 942 is fixed at a high level, and the Q output is input to an OR circuit (OR circuit) 949. The output of the NAND circuit 947 is introduced into the other input of the OR circuit 949 via the NOT circuit 948. The output of the OR circuit 949 is connected to the reset terminal of the CPU 56. According to such a configuration, since the reset signal (low level signal) is given twice to the reset terminal of the CPU 56 when the power is turned on, the CPU 56 surely starts operation.

  For example, the detection voltage of the first power supply monitoring circuit (voltage that outputs a voltage drop signal) is + 22V, and the detection voltage of the second power supply monitoring circuit is + 9V. In such a configuration, since the first power monitoring circuit and the second power monitoring circuit monitor the voltage of the same power supply VSL, the timing when the first voltage monitoring circuit outputs the voltage drop signal. And the timing at which the second voltage monitoring circuit outputs the voltage drop signal can be reliably set to a desired predetermined period. The desired predetermined period is a period from when the power supply stop process is started in response to the voltage drop signal from the first power supply monitoring circuit until the power supply stop process is reliably completed.

  In this example, the first detection condition for the first power supply monitoring means to output the detection signal is that the + 30V power supply voltage has dropped to + 22V, and the second power supply monitoring means outputs the detection signal. The second detection condition that becomes is that the + 30V power supply voltage is lowered to + 9V. However, the voltage value used here is an example, and other values may be used.

  However, although the monitoring range is narrowed, it is also possible to use a + 5V power supply voltage as the monitoring voltage of the first voltage monitoring circuit and the second voltage monitoring circuit. Also in that case, the detection voltage of the first voltage monitoring circuit is set higher than the detection voltage of the second voltage monitoring circuit.

  While power is not supplied from the + 5V power source that is the driving power source of the CPU 56 or the like, at least a part of the RAM is backed up by the backup power source supplied from the power supply board, and the contents are preserved even if the power to the gaming machine is cut off. The When the +5 V power supply is restored, a reset signal is issued from the system reset circuit 65, so that the CPU 56 returns to a normal operation state. At that time, since necessary data is stored in the backup RAM, it is possible to return to the gaming state at the time of occurrence of the power failure when recovering from the power failure.

  Although FIG. 8 shows a configuration in which a reset signal (low level signal) is given to the reset terminal of the CPU 56 when the power is turned on, the reset release is surely released even if the reset signal rises only once. When using the CPU to be used, the circuit elements denoted by reference numerals 941 to 949 are not necessary. In that case, the output of the reset IC 651 is directly connected to the reset terminal of the CPU 56.

  The CPU 56 used in this embodiment also incorporates an I / O port (PIO) and a timer / counter circuit (CTC). The PIO has 4 bits PB0 to PB3 and 1 byte port PA0 to PA7. The ports PB0 to PB3 and PA0 to PA7 can be set to either input / output. However, the built-in PIO is not used in this embodiment. In that case, for example, all the ports are set to the input mode, and all the ports are connected to the ground level. When the power is turned on, the PIO is automatically set to the input mode.

  FIG. 9 is a block diagram illustrating a configuration example of the power supply board 910 of the gaming machine. The power supply board 910 is installed independently of the electric component control boards such as the main board 31, the display control board 80, the voice control board 70, the lamp control board 35, and the payout control board 37, and each electric component control board in the gaming machine and Generates voltage used by mechanical components. In this example, AC24V, VSL (DC + 30V), DC + 21V, DC + 12V, and DC + 5V are generated. A capacitor 916 serving as a backup power supply is charged from a line of power supply for driving DC + 5V, that is, an IC or the like on each substrate.

  The transformer 911 converts AC voltage from the AC power source into 24V. The AC 24V voltage is output to the connector 915. The rectifier circuit 912 also generates a DC voltage of +30 V from AC 24 V and outputs it to the DC-DC converter 913 and the connector 915. The DC-DC converter 913 generates + 22V, + 12V, and + 5V and outputs them to the connector 915. The connector 915 is connected to, for example, a relay board, and power of a voltage necessary for each electric component control board and the mechanism component is supplied from the relay board. Note that a power switch 918 for stopping or starting the power supply to the gaming machine is installed on the input side of the transformer 911.

  The + 5V line from the DC-DC converter 913 branches to form a backup + 5V line. A large-capacitance capacitor 916 is connected between the backup + 5V line and the ground level. Capacitor 916 has power so that the storage state can be maintained with respect to the backup RAM of the electrical component control board when the power supply to the gaming machine is cut off (RAM that is backed up by power, that is, storage means that can be in the storage content storage state). Backup power supply. Further, a backflow preventing diode 917 is inserted between the + 5V line and the backup + 5V line.

  A battery that can be charged from a + 5V power supply may be used as the backup power supply. In the case of using a battery, a rechargeable battery is used in which the capacity disappears when a state in which no power is supplied from the +5 V power source continues for a predetermined time.

  The power supply board 910 is mounted with a power monitoring IC 902 that constitutes the first power monitoring circuit described above. The power monitoring IC 902 detects the occurrence of power interruption by introducing the VSL power supply voltage and monitoring the VSL power supply voltage. Specifically, when the VSL power supply voltage becomes equal to or lower than a predetermined value (+22 V in this example), a voltage drop signal is output because power supply is cut off. The power supply voltage to be monitored is preferably higher than the power supply voltage (+5 V in this example) of the circuit element mounted on each electric component control board. In this example, VSL, which is a voltage immediately after being converted from AC to DC, is used. The voltage drop signal from the power monitoring IC 902 is supplied to the main board 31, the payout control board 37, and the like.

  The predetermined value for the power monitoring IC 902 to detect the power-off is lower than the normal voltage, but is a voltage that allows the CPU on each electrical component control board to operate for a while. Further, the power monitoring IC 902 is configured to monitor a voltage that is higher than a voltage for driving a circuit element such as a CPU (+5 V in this example) and immediately after being converted from AC to DC. Therefore, the monitoring range can be expanded for the voltage required by the CPU. Therefore, more precise monitoring can be performed. Furthermore, when VSL (+ 30V) is used as the monitoring voltage, the voltage supplied to the various switches of the gaming machine is + 12V, so that it can be expected to prevent erroneous switch-on detection at the time of instantaneous power interruption. That is, when the voltage of the + 30V power supply is monitored, it is possible to detect a decrease in the level before + 12V created after the creation of + 30V starts to drop. Therefore, when the voltage of the + 12V power supply decreases, the switch output becomes an on-state. However, if the power-off is recognized by monitoring the + 30V power supply voltage that decreases faster than + 12V, the switch output is turned on before the switch output shows the on-state. It is possible to enter a state of waiting for recovery and not detect switch output.

  Further, since the power monitoring IC 902 is mounted on the power supply board 910 separate from the electric component control board, the voltage drop signal can be supplied from the first power supply monitoring circuit to the plurality of electric component control boards. Even if there are any number of electrical component control boards that require a voltage drop signal, it is only necessary to provide one first power supply monitoring means. Therefore, each electrical component control means in each electrical component control board performs the return control described later. Even if it goes, the cost of the gaming machine does not rise so much.

  In the configuration shown in FIG. 9, the detection output (voltage drop signal) of the power supply monitoring IC 902 is supplied to the respective electric component control boards (for example, the main board 31 and the payout control board 37) via the buffer circuits 918 and 919. However, for example, a configuration may be adopted in which one detection output is transmitted to the relay board and the same signal is distributed from the relay board to each electric component control board. Further, a buffer circuit corresponding to the number of substrates that require a voltage drop signal may be provided.

Next, the operation of the gaming machine will be described.
FIG. 10 is a flowchart showing main processing executed by the CPU 56 on the main board 31. When the power to the gaming machine is turned on, in the main process, the CPU 56 first performs necessary initial settings (step S1).

  Then, it is confirmed whether or not data protection processing (for example, power failure occurrence NMI processing such as addition of parity data) has been performed in the backup RAM area when the power is turned off (step S2). When an unexpected power interruption occurs, processing for protecting data in the backup RAM area is performed as will be described later. When such protection processing is performed, it is assumed that there is a backup. After confirming that there is no backup, the CPU 56 executes an initialization process (steps S2 and S3). In this embodiment, whether or not there is backup data in the backup RAM area is confirmed by the state of the backup flag set in the backup RAM area when the power is turned off. For example, if “55H” is set in the backup flag area, it means that there is a backup (ON state), and if a value other than “55H” is set, it means that there is no backup (OFF state).

  When there is backup data in the backup RAM area, the CPU 56 performs data check (for example, parity check) in the backup RAM area (step S4). In the case of recovery after an unexpected power failure, the data in the backup RAM area should have been saved, so the check result is normal. If the check result is not normal, the internal state cannot be returned to the state when the power is cut off, and therefore an initialization process that is executed when the power is turned on not when the power failure is restored is executed (steps S5 and S3).

  If the check result is normal, the CPU 56 performs a game state restoration process for returning the internal state to the state at the time of power-off (step S6). As shown in FIG. 11, when the value of the backup flag is set to “55H” and the check result is normal, the gaming state recovery process in step S6 is executed. Then, the saved value of the PC (program counter) stored in the backup RAM area is set in the PC, and the address is restored (step S7).

  When the execution of the normal initialization process (step S3) is completed, the main process proceeds to a loop process in which the monitoring of the timer interrupt flag (step S9) is confirmed. In the loop, display random number update processing (step S8) is also executed.

  In this embodiment, after the presence or absence of backup data is confirmed in step S2, the backup area is checked in step S4 when the backup data exists. Conversely, the check result of the backup area is After confirming that the backup data is normal, the presence or absence of backup data may be checked. Further, it may be determined whether or not to execute the power failure recovery process by confirming either one of the presence / absence of backup data or the check of the backup area.

  Further, for example, in the parity check (step S4) when determining whether or not to execute the power failure recovery process, that is, when determining whether or not to restore the gaming state, a special process in the stored RAM data It is confirmed that the gaming machine is in the game standby state (not changing the special symbol, not playing the big hit game, not changing the probability, or not having the start winning memory) by the flag or the starting winning memory number data. Then, the initialization process may be executed without performing the game state restoration process.

  FIG. 12 is a flowchart showing the initial setting process in step S1. In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1a). When the interrupt is prohibited, the CPU 56 sets the interrupt mode to the interrupt mode 2 (step S1b), and sets the stack pointer designation address in the stack pointer (step S1c). Then, the CPU 56 initializes the built-in device register (step S1d). Further, after initialization (step S1e) of CTC (counter / timer) and PIO (parallel input / output port) which are built-in devices (built-in peripheral circuits), the RAM is set to an accessible state (step S1f). Interrupt mode 2 is a mode provided by the CPU 56 used here, and jumps to an interrupt address generated from the set value of a specific register and an interrupt vector when an interrupt occurs. is there.

  FIG. 13 is a flowchart showing the normal initialization process (step S3). As shown in FIG. 13, in the initialization process, a RAM clear process is performed (step S3a). Next, based on the address value of the work area initial setting table, it is initialized to a predetermined work area (for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol left middle right symbol buffer, a payout command storage pointer, etc.) An initial value setting process (step S3b) for setting a value is performed. Then, a CTC register set in the CPU 56 is set so that a timer interrupt is periodically generated every 2 ms (step S3c). That is, a value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value. Since the interruption is prohibited (see FIG. 12) in the initial setting process (step S1), the interruption is permitted before the initialization process is completed (step S3d).

  Therefore, in this embodiment, the built-in CTC of the CPU 56 is set to repeatedly generate a timer interrupt. In this embodiment, the repetition period is set to 2 ms. Then, as shown in FIG. 14, when a timer interrupt occurs, the CPU 56 sets a timer interrupt flag (step S12).

  When detecting that the timer interrupt flag is set in step S9, the CPU 56 resets the timer interrupt flag (step S10) and executes a game control process (step S11). With the above control, in this embodiment, the game control process is started every 2 ms. In this embodiment, only the flag is set in the timer interrupt process, and the game control process is executed in the main process, but the game control process may be executed in the timer interrupt process.

  As described above, in this embodiment, since it is determined whether or not to restore the power-off state depending on the state of the backup data, when the power is turned on when the power is restored after a power failure, etc. It can be determined whether or not to restore the power-off state according to the state of the contents of the backup data storage area.

  FIG. 15 is a flowchart showing the game control process of step S11. In the game control process, the CPU 56 first inputs the states of the gate sensor 12, the start port sensor 17, the count sensor 23, and the winning port switches 19a and 24a via the switch circuit 58, and wins each winning port and winning device. It is determined whether or not there has been (switching process: step S21).

  Next, various abnormality diagnosis processes are performed by the self-diagnosis function provided in the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error process: step S22).

  Next, a process of updating each counter indicating each determination random number such as a big hit determination random number used for game control is performed (step S23). The CPU 56 further performs a process of updating a display random number such as a random number that determines the type of stop symbol (step S24).

  Further, the CPU 56 performs special symbol process processing (step S25). In the special symbol process control, corresponding processing is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state. Further, normal symbol process processing is performed (step S26). In the normal symbol process, the corresponding process is selected and executed in accordance with the normal symbol process flag for controlling the variable display 10 using the 7-segment LED in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state.

  Further, the CPU 56 performs a process of setting a control command sent to the display control board 80 or the like in a predetermined area of the RAM 55 (command control process: step S27).

  Next, the CPU 56 performs a process of outputting the contents of the storage area for various output data to each output port (data output process: step S29). The CPU 56 also performs processing for outputting data such as jackpot information, start information, probability variation information, and the like output to the hall management computer, for example.

  Further, the CPU 56 performs solenoid output processing for outputting a drive signal to the solenoid circuit 59 when a predetermined condition is satisfied (step S30). The solenoid circuit 59 drives the solenoids 16 and 21 in accordance with the drive signal, thereby opening or closing the variable winning ball apparatus 15 or the opening / closing plate 20.

  Further, the CPU 56 sets the number of prize balls based on the detection of the winning ports 17, 23, 19a, 24a (step S31). That is, when a predetermined condition is satisfied, control for outputting a payout control command to the payout control board 37 is performed. The payout control CPU 371 mounted on the payout control board 37 drives the ball payout device 97 according to the payout control command.

  As described above, the main process includes a process for determining whether or not to shift to the game control process, and the timer control process based on the timer interrupt periodically generated by the internal timer of the CPU 56 is used for the game control process. Since a flag for determining whether or not to shift is set, all the game control processes are executed reliably. In other words, until all the game control processes are executed, it is not determined whether or not to shift to the next game control process, so it is guaranteed that all the processes in the game control process are completed. ing.

  Conventional general game control processing is forcibly returned to the initial state by an external interrupt that occurs periodically. If it demonstrates in accordance with the example shown by FIG. 15, for example, even if it was during the process of step S31, it was forcibly returned to the process of step S21. In other words, there is a possibility that the next game control process will be started before all the processes in the game control process are completed.

  Here, the game control process executed by the CPU 56 of the main board 31 is executed according to the flag set in the timer interrupt process based on the timer interrupt that the internal timer of the CPU 56 periodically generates. A hardware circuit that generates a signal periodically (for example, every 2 ms) is provided, a signal from the circuit is introduced into an external interrupt terminal of the CPU 56, and it is determined whether or not to shift to a game control process by the interrupt signal. A flag may be set for this purpose.

  Even in such a configuration, the determination of the flag is not performed until all of the game control processes are executed, so that it is guaranteed that all the processes in the game control process are completed.

FIG. 16 is an explanatory diagram showing random numbers such as jackpot determination random numbers used for game control. Each random number is used as follows.
(1) Random 1: Decide whether or not to generate a big hit (for big hit determination)
(2) Random 2-1 to 2-3: For determining the left and right out-of-line symbols (3) Random 3: For determining the symbol combination at the time of big hit (for big hit symbol determination)
(4) Random 4: Decide whether or not to make a probable big hit (for probable judgment)
(5) Random 5: Decide whether or not to reach when falling off (for reach determination)
(6) Random 6: Reach type is determined (for reach type determination)
(7) Random 7: Decide whether or not to win based on normal symbols (for hit determination)

  In order to enhance the game effect, random numbers other than the random numbers (1) to (7) are also used. In step S23, the CPU 56 uses a counter for generating a jackpot determination random number (1), a jackpot symbol determination random number (3), a probability variation determination random number (4), and a hit determination random number (7). Count up (add 1). That is, they are determination random numbers whose counter values are updated in step S23. Other random numbers (display random numbers) are updated in step S8 of the main process. In step S8, random 2-1 is incremented by 1, and random 2-2 is a carry of random 2-1. Sometimes 1 is added, and random 2-3 is added 1 when the carry of random 2-2. The reach type determination random 6 is incremented by 3 in step S8 in order to prevent synchronization with the symbol determined based on the random number. In this embodiment, the counter value is added to generate a random number. However, the counter value may be subtracted.

  Next, a method for determining a symbol (special symbol) variably displayed on the variable display unit 9 based on winning at the start winning opening 14 will be described with reference to the flowcharts of FIGS. FIG. 17 shows a process for determining that the hit ball has won the start winning opening 14, and FIG. 18 shows a process for determining a variable display stop symbol of the variable display unit 9. FIG. 19 is a flowchart showing a process for determining whether or not to win. Here, in the case of a big hit, the stop symbol is determined after determining whether or not to make a probable change, but the big hit stop symbol may be determined regardless of the probable big hit. Good. In this case, the determination as to whether or not to change the probability may be performed separately after the big hit determination (for example, immediately after the big hit determination or after the big hit state ends).

  When the hit ball wins the start winning opening 14 provided in the game board 6, the start opening sensor 17 is turned on. In the special symbol process in step S25 of the game control process, as shown in FIG. 17, when the CPU 56 determines that the start port sensor 17 is turned on via the switch circuit 58 (step S71), the start winning memory number is It is confirmed whether the maximum value of 4 has been reached (step S72). If the starting winning memory number has not reached 4, the starting winning memory number is increased by 1 (step S73), and the value of the big hit determination random number is extracted. Then, it is stored in a random value storage area corresponding to the value of the number of start winning prizes stored (step S74). When the start winning memory number has reached 4, the process for increasing the starting win memory number is not performed. That is, in this embodiment, it is possible to store the number of hit balls that have been won in a maximum of four start winning holes 17.

  As shown in FIG. 18, the CPU 56 confirms the value of the number of start winning prizes in the special symbol process processing in step S25 (step S81). If the starting winning memory number is not 0, the value stored in the random number value storage area corresponding to the starting winning memory number = 1 is read (step S82), the value of the starting winning memory number is decreased by 1, and each The value in the random value storage area is shifted (step S83). That is, the value stored in the random number value storage area corresponding to the starting winning memory number = n (n = 2, 3, 4) is stored in the random number value storing area corresponding to the starting winning memory number = n−1. .

  Then, the CPU 56 determines the winning / losing based on the value read in step S82, that is, the extracted value of the big hit determining random number (step S84). Here, the jackpot determination random number takes a value in the range of 0-299. As shown in FIG. 19, at the time of low probability, for example, when the value is “3”, it is determined as “big hit”, and when it is other than that, it is determined as “out of”. When the probability is high, for example, when the value is any one of “3”, “7”, “79”, “103”, “107”, “big hit” is determined. It is determined that it is out of place.

  When the big hit is determined, the CPU 56 determines whether or not to make the big hit based on the value of the random number for probability variation determination (random 4) (step S85). If it is determined that the probability variation is a big hit (step S86), the probability variation flag is set (step S87). The probability variation flag is used for selecting the reach type. Also, a jackpot symbol determining random number (random 3) is extracted, and the jackpot symbol is determined according to the value (step S88). Further, a reach type determining random number (random 6) is extracted, and the reach type is determined based on the extracted value (step S89).

  If it is determined to be out of place, the CPU 56 determines whether or not to reach (step S90). For example, when the value of random 4, which is a random number for reach determination, is any one of “105” to “1530”, it is determined not to reach. If the value of the reach determination random number is any one of “0” to “104”, it is determined to reach. When determining to reach, the CPU 56 determines the reach symbol.

  In this embodiment, the left and right symbols are determined according to the value of random 2-1 (step S91). Further, the medium symbol is determined according to the value of random 2-2 (step S92). That is, any symbol corresponding to 0 to 15 of random 2-1 and random 2-2 is determined as a stop symbol. Here, when the determined middle symbol matches the left and right symbols, the symbol corresponding to the value obtained by adding 1 to the random number value corresponding to the middle symbol is set as the determined symbol of the middle symbol so as not to match the jackpot symbol To do.

  Further, the CPU 56 extracts a reach type determination random number (random 6) and determines a reach type based on the value (step S89). If it is decided not to reach in step S90, the left and right middle symbols are decided according to the random values 2-1 to 2-3 (step S93).

  As described above, it is determined whether the display mode of the symbol variation based on the start winning is the big hit, the reach mode, or the off mode, and the combination of the respective stop symbols is determined.

  In the high probability state, the probability of the next big hit increases, the time until the variable display of the variable display 10 is confirmed by the 7-segment LED is shortened, and based on the variable display result of the variable display 10. The pachinko gaming machine 1 may be configured to increase the number of times and the opening time of the variable winning ball device 15 at the time of hitting, and the probability of winning based on the variable display result of the variable display 10 is increased. It may be configured. Further, it may be a pachinko gaming machine 1 in which only one or a plurality of states of them occurs.

  Further, the random number and the range of the random value used in this embodiment are merely examples, and any random number may be used, and the range setting is also arbitrary.

  FIG. 20 is a flowchart illustrating an example of a special symbol process processing program executed by the CPU 56. The special symbol process shown in FIG. 20 is a specific process of step S25 in the flowchart of FIG. When performing the special symbol process, the CPU 56 performs any one of the steps S300 to S309 shown in FIG. 20 according to the internal state after performing the fluctuation shortening timer subtraction process (step S310).

  In the fluctuation shortening timer subtraction process in step S310, whether or not a condition for shortening the variation time of the special symbol is satisfied (for example, a predetermined time elapses from the start winning detection until the process based on the start winning is executed). The process of subtracting the fluctuation shortening timer for confirming whether or not) is performed. And in each process of step S300-S309, the following processes are performed.

Special symbol variation waiting process (step S300): Waiting for the start opening sensor 17 to be turned on after hitting the start winning opening 14 (the winning opening of the variable winning ball apparatus 15 in this embodiment). When the start sensor 17 is turned on, if the start winning memory number is not full, the start winning memory number is incremented by 1 and a big hit determining random number is extracted. That is, the process shown in FIG. 17 is executed.
Special symbol determination process (step S301): When variable symbol special display can be started, the number of start winning memories is confirmed. If the start winning memorized number is not 0, it is determined whether to win or not according to the extracted value of the big hit determination random number. That is, the first half of the process shown in FIG. 18 is executed.
Stop symbol setting process (step S302): The stop symbol of the middle left and right symbols is determined. That is, the middle half of the process shown in FIG. 18 is executed.

  Reach operation setting process (step S303): It is determined whether or not a reach operation is performed according to the value of the reach determination random number, and a change period during reach is determined according to the value of the reach type determination random number. That is, the second half of the process shown in FIG. 18 is executed.

  All symbol variation start processing (step S304): Control is performed so that the variation display unit 9 starts variation of all symbols. At this time, the left / right middle final stop symbol and the information for instructing the variation mode are transmitted to the display control board 80. When the process is finished, the internal state (process flag) is updated to shift to step S305.

  All symbol stop waiting process (step S305): When a predetermined time (the time indicated by the fluctuation shortening timer in step S310) elapses, control is performed so that all symbols displayed on the variable display section 9 are stopped. If the stop symbol is a combination of jackpot symbol, the internal state (process flag) is updated to shift to step S306. If not, the internal state is updated to shift to step S300.

  Big winning opening opening process (step S306): Control for opening the big winning opening is started. Specifically, the counter and the flag are initialized, and the solenoid 21 is driven to open the special winning opening. Also, a big hit flag (a flag indicating that a big hit is being made) is set. When the process is finished, the internal state (process flag) is updated to shift to step S307.

  Processing during opening of the special winning opening (step S307): Control for sending display control command data of the large winning opening round display to the display control board 80, processing for confirming establishment of the closing condition of the special winning opening, and the like are performed. If the final closing condition of the big prize opening is satisfied, the internal state is updated to shift to step S308.

  Specific area valid time processing (step S308): The presence or absence of passage of the V count switch 22 is monitored, and processing for confirming that the big hit gaming state continuation condition is satisfied is performed. If the condition for continuing the big hit gaming state is satisfied and there are still remaining rounds, the internal state is updated to shift to step S306. In addition, when the big hit gaming state continuation condition is not satisfied within a predetermined effective time, or when all rounds are finished, the internal state is updated to shift to step S309.

  Big hit end process (step S309): A display for notifying the player that the big hit gaming state has ended is performed. When the display is completed, the internal state is updated to shift to step S300.

  As described above, when a hitting ball is won at the start winning opening 14, the CPU 56 determines whether or not to make a big hit, stop symbol, reach mode, or probability change in the special symbol process in step S25 (see FIG. 15). Whether or not to do so is determined, but a control command such as a display control command according to the determination is sent to an electrical component control means such as a display control means. For example, in the display control means, display control of the variable display unit 9 is performed in accordance with a display control command from the main board 31.

  FIG. 21 is a flowchart showing the normal symbol process (step S26). In the normal symbol process, the CPU 56 executes one of the processes shown in steps S62 to S66 according to the value of the normal symbol process flag after executing the gate switch process in step S61.

  As shown in FIG. 22, in the gate switch process, it is detected that the gate switch 12 is turned on based on the passing of the hit ball of the passing gate 11 which is a condition for starting the normal symbol variation (step S611). If the gate switch 12 is on, it is checked whether or not the gate passing memory counter has reached the maximum value (“4” in this example) (step S612). If not reached, the value of the gate passage storage counter is incremented by 1 (step S613). Note that the LED of the passage memory indicator 41 is turned on according to the value of the gate passage memory counter. Then, the CPU 56 extracts the value of the random number for random determination (random 7) and stores the value (S614).

  In the normal symbol variation waiting process in step S62, the CPU 56 updates the value of the normal symbol process flag if the value of the normal symbol passage storage counter is other than zero. If the value of the normal symbol passage storage counter is 0, nothing is done.

  FIG. 23 is an explanatory diagram showing the relationship between the hit determination random number (random 7) and the hit / off in this embodiment. As shown in FIG. 23, the hit value is any of 3 to 12 when the probability is high, and is 3, 5 or 7 when the probability is low. If the value of the random number for hit determination matches the hit value, it is determined to be a win.

FIG. 24 is a flowchart showing an example of a power failure occurrence NMI process executed in response to the NMI based on the voltage change signal from the power supply monitoring circuit of the power supply board 910. In the power failure occurrence NMI process, the CPU 56 first stores the contents of the interrupt prohibition flag in the parity flag in order to back up the interrupt permission / prohibition state immediately before the power failure such as a power failure (step S41). Next, interrupt prohibition is set (step S42). In the power failure occurrence NMI processing, checksum generation processing is performed to ensure the storage of the RAM contents. If another interrupt process is performed during that process, it is possible that the CPU will not operate before the checksum generation process is completed. Setting is made so as not to occur. In addition, steps S44 to S50 in the power failure occurrence NMI process are an example of a process when power supply is stopped.
Note that the processing in step S42 is not necessary when a CPU having a specification that does not cause other interrupts during the interrupt processing is used.

  Next, the CPU 56 checks whether or not the backup flag has already been set (step S42). If the backup flag is already set, no further processing is performed. If the backup flag is not set, the following power supply stop process is executed. That is, the processing from step S44 to step S50 is executed.

  First, the contents of each register are stored in the backup RAM area (step S44). Thereafter, a backup flag is set (step S45). Then, an appropriate initial value is set in the backup check data area of the backup RAM area (step S46), the exclusive value is sequentially obtained for the initial value and the data in the backup RAM area, and then inverted (step S47). The calculated value is set in the backup parity data area (step S48). Further, the RAM access is prohibited (step S49). When the power supply voltage is lowered, the level of various signal lines may become unstable and the contents of the RAM may be altered, but if the RAM access is prohibited in this manner, the data in the backup RAM will be altered. There is no.

  Further, the CPU 56 outputs a clear signal to all output ports mounted on the main board 31. Then, all the output ports are cleared by a clear signal and turned off (step S50).

  Next, the CPU 56 enters a loop process. That is, no processing is performed. Therefore, the operation is internally stopped before the operation is disabled from the outside by the system reset signal from the reset IC 651 shown in FIG. Therefore, the CPU 56 reliably stops operation when the power is turned off. As a result, the RAM access prohibition control and the operation stop control described above can reliably prevent the RAM contents from being destroyed due to an abnormal operation that may occur as the power supply voltage decreases. .

  In this embodiment, in the power failure occurrence NMI processing, the program is looped at the final part, but a halt (HALT) instruction may be issued.

  Further, as described above, the backup flag that is set after the register contents are stored in the RAM area determines whether or not there is backup data to be restored when the power is turned on (whether or not it is restored from a power failure). Used when. Further, the processing of steps S41 to S50 is completed before the CPU 56 receives the system reset signal from the system reset circuit 65. In other words, the detection voltage of the voltage monitoring circuit is set so as to be completed before receiving the system reset signal from the system reset circuit 65.

  In this embodiment, the backup flag is confirmed at the start of the power supply stop process. If the backup flag is already set, the power supply stop process is not executed. As described above, the backup flag is a flag indicating that the backup of necessary data has been completed and the power supply stop process has been completed thereafter. Therefore, for example, even if NMI occurs again for some reason in a loop waiting for reset, the power supply stop process is not repeatedly executed.

  However, if a CPU with specifications that do not cause other interrupts during interrupt processing is used, the determination in step S43 is unnecessary.

  FIG. 25 is an explanatory diagram for explaining an example of a backup parity data creation method. However, in the example shown in FIG. 25, for the sake of simplicity, the size of data in the backup data RAM area is 3 bytes. In the power failure generation process based on the power supply voltage drop, as shown in FIG. 25, initial data (00H in this example) is set in the backup check data area. Next, an exclusive logical sum of “00H” and “F0H” is taken, and an exclusive logical sum of “16H” is obtained. Further, an exclusive OR of the result and “DFH” is taken. Then, a value (“C6H” in this example) obtained by inverting the result (“39H” in this example) is set in the backup parity data area.

  When power is turned on again, parity diagnosis is performed in the power failure recovery process. If all the data in the backup area is stored as it is, parity data as shown in FIG. 25 is set in the backup area when the power is turned on again.

  In the process of step S4 of the main process, the CPU 56 performs the same process as the process executed in the power generation NMI process. That is, initial data (00H in this example) is set in the backup check data area, an exclusive OR of “00H” and “F0H” is taken, and an exclusive OR of “16H” is taken with the result. . Further, an exclusive OR of the result and “DFH” is taken. Then, a final calculation result obtained by inverting the result (“39H” in this example) is obtained. If all the data in the backup area is stored as it is, the final calculation result matches “C6H”, that is, the parity data set in the backup check data area. If a bit error has occurred in the data in the backup RAM area, the final calculation result is not “C6H”.

  Therefore, the CPU 56 compares the final calculation result with the parity data set in the backup check data area, and if they match, the parity diagnosis is normal. If they do not match, the parity diagnosis is abnormal.

  As described above, in this embodiment, the game control means is provided with a storage means (a backup RAM in this example) that is backed up for a predetermined period even when the power of the gaming machine is cut off. The CPU 56 (specifically, a program executed by the CPU 56) is configured to perform a game state recovery process (step S6) for recovering the game state based on the backup data if the storage means is in the backup state.

  In this embodiment, a power supply monitoring circuit is mounted on the power supply board 910 as shown in FIG. 9, and a system reset circuit 65 is mounted on the main board 31 as shown in FIG. When the power supply voltage is lowered, the system reset circuit 65 generates a low level system reset signal when the power supply monitoring circuit (in this example, the power monitoring IC 902) outputs a low level NMI interrupt signal. It is set to be later than the time of occurrence. Further, a low level system reset signal from the system reset circuit 65 is input to the reset terminal of the CPU 56.

  Then, the CPU 56 enters the loop state after executing the power failure generation processing (processing when the power supply is stopped) based on the voltage drop signal from the power monitoring means (power monitoring IC 902). Will enter. That is, the operation of the CPU 56 is completely stopped. Below the + 5V power supply voltage value, normal operation of the CPU 56 cannot be guaranteed (that is, a state in which the operation cannot be managed occurs), but the CPU 56 is in a reset state when power that can operate normally is supplied. Therefore, abnormal operation based on indefinite data is prevented.

  As described above, in this embodiment, the CPU 56 enters a loop state in accordance with the detection output input from the power supply monitoring circuit, and is reset in accordance with the detection output input from the system reset circuit 65. It is configured. Therefore, reliable data storage is performed when the power is turned off, and a disadvantage to the player is prevented.

  In this embodiment, the power monitoring IC 902 and the system reset circuit 65 monitor the same power supply voltage, but may monitor different power supply voltages. For example, the power supply monitoring circuit on the power supply board 910 may monitor the + 30V power supply voltage, and the system reset circuit 65 may monitor the + 5V power supply voltage. Then, the threshold level (system reset) of the system reset circuit 65 is set so that the timing at which the system reset circuit 65 generates a low level system reset signal is delayed with respect to the timing at which the power supply monitoring circuit generates an NMI interrupt signal. The voltage level that generates the signal is set. For example, the threshold is 4.25V. 4.25 V is lower than the normal voltage, but is a voltage that allows the CPU 56 to operate for a while. The power monitoring circuit adjusts the delay time of the delay means provided in the system reset circuit 65 (in this example, the capacitance of the capacitor) so that the system reset circuit 65 generates a low-level system reset signal. You may make it delay with respect to the timing which generate | occur | produces an interruption signal.

  In the above embodiment, the CPU 56 detects the NMI interrupt signal (NMI interrupt signal from the power supply monitoring means) from the power supply board via the non-maskable interrupt terminal (XNMI terminal). An interrupt signal may be introduced to a maskable interrupt interrupt terminal (INT terminal). In that case, the power supply stop process is executed in the interrupt process (INT process). Further, an NMI interrupt signal from the power supply board may be detected via the input port. In that case, the input port is monitored in the main process.

  When an interrupt signal from the power supply board is detected via the INT terminal instead of the NMI interrupt signal, an interrupt mask is set at the start of the game control process in step S11 of the main process, and the game control process The interrupt mask may be canceled at the end of. By doing so, an interruption is applied before and after the start of the game control process, and the game control process is not interrupted. Therefore, the command transmission is not interrupted when the payout control command is sent to the payout control board 37. Therefore, even when a power failure occurs, the payout control command and the like are reliably transmitted.

  Further, in this embodiment, in the power failure occurrence process (power supply stop process), when the backup flag indicating that the data has already been backed up and the power supply stop process has already been executed is set, the power supply is performed. It is configured not to execute the stop process. In the process of turning off the power, NMI may occur again. Then, when the backup flag is not confirmed in the power failure generation process, the power supply stop process is executed again by the NMI that has occurred again.

  In the normal power supply stop process executed first, a process of storing the contents of the register in the backup RAM is performed (see step S44 in FIG. 24). Since the power supply voltage gradually decreases in the reset waiting state after the first power supply stop process executed first, the contents of the register may be destroyed. That is, there is a possibility that the register value has changed from the state at the time when the power interruption is detected (when NMI first occurs). If the power supply stop process is executed again in such a state, a value different from the register value in the state when the power supply is detected is stored in the backup RAM. Then, in the power failure recovery process executed when the power is restored, a value different from the register value in the state when the power failure is detected is restored to the register. As a result, there is a possibility that a gaming state different from the gaming state when the power is turned off is reproduced.

Hereinafter, the gaming state restoration process will be described.
FIG. 26 is a flowchart showing an example of the gaming state restoration process shown in step S6 of FIG. In this example, the CPU 56 restores the value stored in the backup RAM to each register (step S51). Then, based on the data stored in the backup RAM, the gaming state at the time of power failure is confirmed and returned. That is, based on the data stored in the backup RAM, the solenoid 16 and the solenoid 21 are driven via the solenoid circuit 59 to restore the open / closed state of the start winning opening 14 and the open / close plate 20 (steps S52 and S53). . In addition, according to the values of the special symbol process flag and the normal symbol process flag that were saved even when the power was turned off, the control commands corresponding to the progress status of the special symbol process and the progress status of the normal symbol process when the power was turned off, The data is sent to the display control board 80, the lamp control board 35, and the sound control board 70 (step S53).

  As described above, in the game state restoration process, the state of various electrical components is restored according to the restored internal state, and the display control board 80, the lamp control board 35, and the voice control board 70 are controlled. A control command for returning the state to the state at the time of power-off (control command for causing a control state at the time of power-off) is sent out. Such control commands are generally one or more control commands that were last sent prior to a power failure.

  As a result, in this embodiment, the following state recovery is possible by the game state recovery process.

  The states of the start winning opening 14 and the big winning opening (opening / closing plate 20) are restored. The display state of the normal symbol (display state of the variable display 10) controlled by the display control means is restored except when it is changing at the time of power-off. The display state of the special symbol controlled by the display control means (display state of the variable display unit 9) is restored except when it is changing when the power is turned off. Further, the background and characters displayed on the variable display unit 9 are restored except when the special symbol is changing and the big hit game is being played.

  When the power is cut off during the change of the special symbol, information on the change time (for example, 10 seconds) of the variable display pattern and the already executed time (for example, 4 seconds) is backed up. Then, the CPU 56 of the main board 31 outputs a display control command indicating a display pattern and a display control command indicating a stop pattern to the display control board 80 at the time of recovery, and stops the pattern after the remaining time (for example, 6 seconds) has elapsed. Therefore, display control commands are output. Therefore, if the special symbol is changing when the power is turned off, the variable display unit 9 performs variable display according to the remaining time (for example, 6 seconds) at the time of recovery. The display control command indicating the display pattern output to the display control board 80 at the time of recovery may be the same as the display control command indicating the display pattern output before the power is turned off. It may be a command for displaying an image such as “In”. In that case, “power failure recovery is in progress” is displayed for the remaining time (for example, 6 seconds). Note that the same control is performed for the display state of the normal symbol when the power is cut off during the variation of the special symbol.

  Even if the power is cut off during the big hit game, the remaining time of the interval during the round or between rounds is displayed, sound, Control of the lamp, solenoid 21 and the like is performed. In that case, the CPU 56 of the main board 31 outputs to the display control board 80 a display control command for designating the final design (stopped design) output before the power is turned off. Therefore, it is possible to produce a jackpot symbol during a round or between rounds (for models that produce a jackpot symbol with a jackpot symbol), and the display control means can also recognize a symbol that is displayed at the start of variation after the jackpot ends.

  At the time of recovery from an unexpected power interruption, the display states of the decoration lamp 25, the start memory display 18, the gate passing memory display 41, the prize ball lamp 51, and the ball break lamp 52 controlled by the lamp control means are also restored. In addition, the display state of the game effect lamps / LEDs 28a, 28b, 28c is restored except when the special symbol is changing and the big hit game is being played. However, if the game is a big hit game when the power is turned off, it can be restored to the initial state of each control section. Each control section is, for example, a jackpot start notification state, a state before the big winning opening is opened, a state where the big winning opening is open, and a big hit end notification state. When the power is turned off and the special symbol is changing, and the power is restored, the game effect lamps / LEDs 28a, 28b, Although the display state of 28c may be controlled, it may be turned on / flashing in a pattern peculiar when the light is turned off or power is restored.

  At the time of recovery from an unexpected power failure, the sound generation state controlled by the voice control means is restored except during special symbol fluctuation and big hit games. However, if the game is a big hit game when the power is turned off, it can be restored to the initial state of each control section. If the special symbol is changing when the power is turned off and the power is restored, the sound generation state is controlled for the remaining time as in the display control of the variable display unit 9 and the variable display device 10 described above. However, a sound pattern peculiar to silence or power failure recovery (for example, “sound recovery from power failure”) may be output.

  In this embodiment, a control command for restoring the state is sent from the game control means of the main board 31 to the display control means, the lamp control means and the sound control means at the time of recovery from the power interruption. When the display control means, the lamp control means and the sound control means are backed up, the display control means, the lamp control means and the sound control means independently restore the control state without using the control command from the main board 31. You may comprise.

  In this embodiment, when the gaming state is restored to the power-off state, the CPU 56 uses the parity flag stored in the backup RAM to restore the interrupt enable / disable state at the time of the previous power-off. The value is confirmed (step S55). If the parity flag is clear, interrupt permission setting is performed (step S56). On the other hand, if the parity flag is on, the gaming state restoration process is finished as it is (while keeping the interrupt disabled state set in step S1a).

  In FIG. 26, when the game state restoration process is completed, the process returns to the main process. However, actually, the stack area (in the backup RAM area) pointed to by the stack pointer stored in the process at the time of power supply stoppage is returned. Since the address stored at (there is an address executed when the NMI interrupt occurs when the power is cut off) is written back to the program counter and the RET instruction is issued, the address returned when the NMI occurs is returned.

  As described above, after the initial setting process is started, before the restoration process is completed or until the initialization process is completed, the interrupt disabled state is set. Therefore, it is possible to prevent the processing from being interrupted by an interrupt. As a result, it is possible to reliably complete the initial setting, the determination as to whether or not to restore the power-off state, which is performed according to the contents of the backup data storage area, and the restoration process (or initialization process). Note that even if the interrupt is disabled until the recovery process is completed as described above, the interrupt disabled / permitted state at power-off is stored in the parity flag. It is possible to reliably restore the interrupt disabled / permitted state when the power is turned off.

  In the above embodiment, the case where the data storage process and the restoration process are performed in the game control means has been described, but part of the RAM in the payout control means, the sound control means, the lamp control means, and the display control means is also included. The power supply is backed up, and the payout control means, the display control means, the sound control means, and the lamp control means may perform the processing as described above. However, the payout control means, the display control means, the sound control means, and the lamp control means do not need to perform command transmission processing at the time of recovery.

  Hereinafter, control commands sent from the game control means to other electrical component control means and processing based on the control commands will be described.

  FIG. 27 is a timing chart showing the relationship between the special symbol variation and the display control command. As shown in FIG. 27, at the start of variation, commands for variation pattern designation, left symbol designation, middle symbol designation, and right symbol designation are transmitted from the main board 31 to the display control board 80. At the end of the change, a command indicating all symbol stops is transmitted. Thus, in this embodiment, five commands are transmitted for one change.

  FIG. 28 is an explanatory diagram showing an example of a command form of the display control command. In this embodiment, the display control command has a 2-byte configuration, the first byte represents MODE (command classification), and the second byte represents EXT (command type).

  FIG. 29 is an explanatory diagram of an example of the content of the display control command. In the example shown in FIG. 29, commands 8000 (H) to 8022 (H) and 8100 (H) to 8122 (H) are display controls for designating a special symbol variation pattern in the variable display section 9 for variably displaying the special symbol. It is a command. Note that the command for specifying the variation pattern also serves as a variation start instruction. The command 88XX (X = any value of 4 bits) is a display control command relating to a variation pattern of a normal symbol variably displayed on the variable display 10. The command 89XX is a display control command for designating a normal symbol stop symbol. Command 8AXX (X = any value of 4 bits) is a display control command for instructing stop of variable symbol display.

  Commands 91XX, 92XX, and 93XX are display control commands for designating a stop symbol in the middle left of the special symbol. The command A0XX is a display control command for instructing to stop the special symbol variable display. The command BXXX is a display control command that is sent from the start of the big hit game to the end of the big hit game. The commands C000 and EXXX are display control commands relating to the display state of the variable display unit 9 that is not related to special symbol fluctuations and jackpot games. When the display control means of the display control board 80 receives the above-mentioned display control command from the game control means of the main board 31, the display state of the variable display section 9 and the variable display 10 is changed according to the contents shown in FIG. To do.

  FIG. 30 is a timing chart showing an example of a display control command transmission form. In this embodiment, a display control command is output by 8-bit display control signals CD to CD7. Then, when the first byte and the second byte of the display control command are output, the INT signal is turned on (low level in this example). The ON period of the INT signal is 1 μs or more, for example, and a period of 4 μs or more is provided between the first byte and the second byte. The display control means inputs the display control signals CD to CD7 by an interrupt process according to the INT signal.

  The display control command is sent only once so that the display control means can recognize (can be received). In this example, “recognizable (receivable)” means that the INT signal is turned on, and “recognizable (receivable) is sent once” means that in this example, the INT signal is only once. It is to turn on. Since the game control means is configured to send the command only once, the load required for sending the command is reduced also from this point. However, since it need only be sent once so that it can be recognized, other sending methods may be used.

  FIG. 31 is an explanatory diagram showing an example of a command form of a voice control command sent from the main board 31 to the voice control board 70. In this embodiment, the voice control command has a 2-byte structure, and the first byte represents MODE (command classification), and the second byte represents EXT (command type).

  FIG. 32 is an explanatory diagram showing an example of the contents of a voice control command. In the example shown in FIG. 32, a command 8XXX (X = any value of 4 bits) is a voice control command for designating a sound generation pattern in a special symbol variation period. The command BXXX (X = any value of 4 bits) is a voice control command for designating a sound generation pattern from the start of the jackpot game to the end of the jackpot game. Other commands are voice control commands that are not related to special symbol changes and jackpot games. When the voice control means of the voice control board 70 receives the above-described voice control command from the game control means of the main board 31, the voice output state is changed according to the contents shown in FIG.

  FIG. 33 is a timing chart showing an example of a transmission form of the voice control command. In this embodiment, an audio control command is output by 8-bit audio control signals CD to CD7. Then, when the first byte and the second byte of the voice control command are output, the INT signal is turned on (low level in this example). The ON period of the INT signal is, for example, 2 μs or longer, and a period of 30 μs or longer is provided between the first byte and the second byte. The voice control means inputs the voice control signals CD to CD7 by interruption processing according to the INT signal. The voice control command is sent only once so that the voice control means can recognize it.

  FIG. 34 is an explanatory diagram showing an example of a command form of the lamp control command. In this embodiment, the lamp control command has a 2-byte structure, the first byte represents MODE (command classification), and the second byte represents EXT (command type).

  FIG. 35 is an explanatory diagram showing an example of the contents of the lamp control command. In the example shown in FIG. 35, commands 8000 (H) to 8022 (H) and 8100 (H) to 8122 (H) designate a lamp / LED display control pattern corresponding to the variation pattern of the special symbol in the variable display unit 9. This is the lamp control command to be performed. The command A0XX (X = any value of 4 bits) is a lamp control command for instructing a lamp / LED display control pattern when the variable symbol special display is stopped. The command BXXX is a lamp control command for instructing a lamp / LED display control pattern from the start of the jackpot game to the end of the jackpot game. The command C000 is a lamp control command for instructing a lamp / LED display control pattern during a customer waiting demonstration.

  The commands 8XXX, AXXX, BXXX and CXXX are ramp control commands sent from the game control means in accordance with the game progress status. When the lamp control means receives the above-described lamp control command from the game control means of the main board 31, the lamp / LED display state is changed according to the contents shown in FIG.

  The command E0XX is a lamp control command indicating the number of lighting of the start memory display 18. For example, the lamp control means turns on the number of displays designated by “XX” in the start memory display 18. The command E1XX is a lamp control command indicating the number of lighting of the gate passing memory display 41. For example, the lamp control means turns on the number of displays designated by “XX” in the gate passing storage display 41. That is, these commands are commands for instructing the control of the light emitters provided for informing the information of the reserved number. In addition, the command regarding the number of lighting of the start memory | storage display 18 and the gate passage memory | storage display 41 may be comprised so that increase / decrease in the number of lighting may be shown.

  The commands E200 and E201 are lamp control commands related to the display state of the winning ball lamp 51, and the commands E300 and E301 are lamp control commands related to the display state of the ball-out lamp 52. When the lamp control means receives the lamp control command of “E201” from the game control means of the main board 31, the lamp control means sets the display state of the prize ball lamp 51 as a predetermined display state when there is a prize ball remaining, and “E200” When the lamp control command is received, the display state of the prize ball lamp 51 is set to a display state determined in advance as a case where no prize ball remains. When the lamp control command “E300” is received from the game control means of the main board 31, the display state of the ball break lamp 52 is changed to the display state with a ball, and when the lamp control command “E301” is received, the ball break lamp 52 is displayed. The display state of is the display state when the ball is out. That is, commands E200 and E201 are commands indicating control of a light-emitting body provided for notifying a player or the like that there is a non-prize ball, and commands E300 and E301 are supply balls. This is a command indicating that a light-emitting body provided for notifying a player or a game clerk that the game has expired is controlled.

  The command E400 is changed from a specific gaming state (high probability state or short-time state, high probability state in this example) to a normal state (low probability state or non-time-short state, low probability state in this example) when the gaming machine is turned on. This is a lamp control command for instructing a lamp / LED display control pattern at the time of transition. The command E401 is a lamp / LED display when a transition is made from a normal state (low probability state or non-time-short state, in this example low probability state) to a specific gaming state (high probability state or time-short state, in this example high probability state). This is a lamp control command for designating a control pattern. The command E402 is a lamp control command for instructing a lamp / LED display control pattern when an error occurring during the big hit game is canceled. The command E403 is a lamp control command for instructing a lamp / LED display control pattern when an error of the count switch 23 occurs. That is, these commands are commands for instructing to notify the gaming state by the light emitter. In this embodiment, when the lamp control means receives a command instructing to notify the gaming state, the lamp control means uses a part or all of the decoration lamp 25, the game effect LED 28a, and the game effect lamps 28b and 28c, Turn on / off control to notify the gaming state. The decorative lamp 25, the game effect LED 28a, and the game effect lamps 28b, 28c may each be composed of a plurality of light emitters. In this case, the decorative lamp 25, the game effect LED 28a, and the game effect lamp 28b, Notifying the gaming state using a part of 28c also means that, for example, a part of a plurality of light emitters constituting the decorative lamp 25 may be used.

  FIG. 36 is a timing chart showing an example of a lamp control command transmission form. In this embodiment, the lamp control command is output by the 8-bit lamp control signals CD to CD7. Then, when the first byte and the second byte of the lamp control command are output, the INT signal is turned on (low level in this example). The ON period of the INT signal is, for example, 2 μs or longer, and a period of 30 μs or longer is provided between the first byte and the second byte. The ON period of the INT signal is, for example, 1 μs or longer. The lamp control means inputs the lamp control signals CD to CD7 by interruption processing according to the INT signal. The lamp control command is sent only once so that the lamp control means can recognize it.

  FIG. 37 is a flowchart showing an example of the command control process (step S27 in the game control process) in the game control process shown in FIG. Here, each control command (display control command, voice control command, lamp control command) related to the variation of the special symbol, the lamp control command related to the start winning memory, and the lamp control command related to the gate passing memory will be described as examples. In the command control process, the CPU 56 determines whether there is any change in the audio data (step S701). The voice data is changed when the voice switching timing occurs in, for example, the special symbol process (step S25 in the game control process).

  If there is a change in the audio data, the CPU 56 reads out the audio control command data corresponding to the changed audio data (step S702). Each voice control command data is stored in a ROM, for example. Then, the read voice data is set in the buffer area # 2 provided for storing the voice control command (step S703). Also, a voice control command transmission request is set (step S704).

  Next, the CPU 56 determines whether or not the lamp data is changed (step S711). The lamp data is also changed when, for example, the lamp / LED control switching timing occurs in the special symbol process.

  If there is a change in the lamp data, the CPU 56 reads out lamp control command data corresponding to the changed lamp data (step S712). Then, the read lamp data is set in the buffer area # 1 provided for storing the lamp control command (step S713). Also, a lamp control command transmission request is set (step S714).

  Next, the CPU 56 determines whether or not there has been a change (increase / decrease) in the start winning memory (step S715). If there is a change, a lamp control command indicating the number of memories after the change is set in the buffer area # 1 (step S716), and a lamp control command transmission request is set (step S717). Further, it is determined whether or not there is a change (increase / decrease) in the gate passage memory (step S718). If there is a change, a lamp control command indicating the number of memories after the change is set in the buffer area # 1 (step S719), and a lamp control command transmission request is set (step S720).

  Further, the CPU 56 determines whether or not the display control data has changed (step S721). The display control data is also changed when the display control switching timing occurs, for example, in the special symbol process.

  When there is a change in the display control data, the display control data corresponding to the changed display control data is read (step S722). Then, the read display control data is set in the buffer area # 3 provided for storing the display control command (step S723). Also, a display control control command transmission request is set (step S724).

  As described above, when it is time to send a command, the command to be sent is set in the corresponding buffer area. As for the lamp control command, command setting to the buffer area # 1 may be performed other than the special symbol process. For example, for initialization lamp designation, command setting is performed in the initialization process of the main process, and for gate passing memory number lamp designation, command setting is performed in the normal symbol process process (step S26) in the game control process.

  FIG. 38 is a flowchart showing an example of a data output process for outputting a command set in the buffer area (step S29 of the game control process shown in FIG. 15). In the data output process, the CPU 56 checks whether or not a display control command transmission request is set (step S771). If set, a value corresponding to 1 μs is set in the specific register # 1, a value corresponding to 4 μs is set in the specific register # 2, and “03” is set in the specific register # 3 (step S772). An ON period of the INT signal is set in the specific register # 1. In the specific register # 2, the interval between the first byte and the second byte of the command is set. A value indicating which control command should be sent is set in the specific register # 3.

  Next, the display control command transmission request is reset (step S773), and the command transmission subroutine is called (step S774).

  Next, the CPU 56 checks whether or not a voice control command transmission request is set (step S776). If set, a value corresponding to 2 μs is set in the specific register # 1, a value corresponding to 30 μs is set in the specific register # 2, and “02” is set in the specific register # 3 (step S777). Further, the voice control command transmission request is reset (step S778), and the command transmission subroutine is called (step S779).

  Subsequently, the CPU 56 checks whether or not a lamp control command transmission request is set (step S781). If set, a value corresponding to 2 μs is set in the specific register # 1, a value corresponding to 30 μs is set in the specific register # 2, and “01” is set in the specific register # 3 (step S782). Further, the lamp control command transmission request is reset (step S783), and the command transmission subroutine is called (step S784).

  FIG. 39 is a flowchart showing a command transmission subroutine. In the command sending subroutine, the CPU 56 sets the buffer area corresponding to the value set in the specific register # 3 (for example, if “03” is set, the buffer area # 3 = the buffer area for storing display control commands). The first byte of the stored data is output to the corresponding output port (step S790). The corresponding output port is the output port 575 if a lamp control command is sent (see FIG. 7).

  Then, the corresponding INT signal is turned on (step S791). Further, after a delay time corresponding to the value set in the specific register # 1 (step S792), the INT signal is turned off (step S793).

  Next, the value set in the specific register # 2 is confirmed (step S794). When it is confirmed that 0 is set, the process is terminated. If a value other than 0 is set, the second byte of the data set in the buffer area corresponding to the value set in the specific register # 3 is output to the corresponding output port (step S795), and the specific register After a delay time corresponding to the value set in # 2 (step S796), the corresponding INT signal is turned on (step S797). Further, after a delay time corresponding to the value set in the specific register # 1 (step S798), the INT signal is turned off (step S799).

  Through the processing as described above, the control command is sent from the main board 31 at the timing as shown in FIGS. 30, 33 and 36.

  In this embodiment, since a common subroutine is called for the display control command, the voice control command, and the lamp control command, the command output process to be sent can be shared. As a result, the load required for command transmission in the game control means is further reduced. In addition, even if it is not common to all control commands, if the process of outputting any two or more control commands (for example, lamp control command and voice control command) is common, otherwise In comparison, the load required for command transmission in the game control means can be reduced.

  Hereinafter, the operation of each electric component control means mounted on the sub board (in this example, the display control board 80, the sound control board 70, the lamp control board 37, and the payout control board 37) will be described. However, the operation of each electric component control means (sound control means and lamp control means) mounted on the sound control board 70 and the lamp control board 37 will be mainly described below.

  First, the operation of the voice control means will be described. FIG. 40 is a flowchart showing main processing executed by the voice control CPU 701. In the main process, first, an initial value setting process such as clearing the RAM area is performed (step S201). Thereafter, in this embodiment, the voice control CPU 701 proceeds to a loop process for checking the timer interrupt flag (step S202). As shown in FIG. 41, when a timer interrupt occurs, the voice control CPU 701 sets a timer interrupt flag (step S207). If the timer interrupt flag is set in the main processing, the voice control CPU 701 clears the flag (step S203) and performs voice control processing (step S205).

  In this embodiment, it is assumed that the timer interrupt takes every 2 ms. That is, the voice control process is started every 2 ms.

  FIG. 42 is a flowchart showing voice control command reception processing by interrupt processing. A voice control INT signal from the main board 31 is input to an interrupt terminal of the voice control CPU 701. Therefore, when the INT signal from the main board 31 is turned on, the voice control CPU 701 is interrupted and the voice control command reception process shown in FIG. 42 is started.

  In the voice control command reception process, the voice control CPU 701 first reads data from an input port assigned to input voice control command data (step S221). Then, it is confirmed whether or not the first byte of the two-byte voice control command has already been received (step S222). Whether the data has already been received can be confirmed by checking whether valid data is set in the first byte of the reception buffer.

  If the first byte has not been received yet, it is confirmed whether or not bit 7 of the received 1 byte is “1” (step S223). Bit 7 must be “1” in the MODE byte (first byte) of the 2-byte voice control command (see FIG. 31). If bit 7 is “1”, it is determined that a valid first byte has been received, and the received command is stored in the first byte of the reception buffer (step S224).

  If the first byte has already been received, it is checked whether bit 7 of the received 1 byte is “0” (step S225). Bit 7 should be “0” in the EXT byte (second byte) of the 2-byte voice control command (see FIG. 31). In this case, if bit 7 is “0”, it is determined that a valid second byte has been received, and the received command is stored in the second byte of the reception buffer (step S226). In addition, a communication end flag is set (step S227). The communication end flag is a flag indicating that the voice control command has been normally received.

  If bit 7 of the received data is not “0” in step S225, the received data is stored again in the first byte of the reception buffer (step S228).

  As described above, in this embodiment, the voice control command is sent from the main board 31 only once so that the receiving side can recognize it. Then, the possibility of garbled data due to noise or the like cannot be denied. Therefore, in this embodiment, bit 7 of the first byte (MODE) in the 2-byte voice control command is set to “1”, bit 7 of the second byte (EXT) is set to “0”, and the receiving side Thus, it is possible to identify whether the first byte or the second byte has been received. If data corruption or the like occurs in the first byte and bit 7 is no longer “1”, such data is discarded according to the determination in step S223. In addition, when data is garbled in the second byte and the bit 7 is not “0”, that is, when it becomes “1”, the received data becomes 1 by the processing of step S225 and step S228. Judged to be the byte.

  Thereafter, the first byte of the next voice control command is transmitted from the main board 31 side. If the first byte can be correctly received, the reception is again performed by the processing of step S225 and step S228. It is determined that the data is the first byte. That is, from that point on, it is determined that the first byte sent from the main board 31 is the first byte on the receiving side. Therefore, even if data corruption occurs between the boards, one command is not correctly received on the receiving side. Thereafter, on the receiving side, the second byte of the command sent from the main board 31 is the first byte (MODE). ) And the first byte of the command is not determined to be the second byte (EXT).

  FIG. 43 is a flowchart showing the voice control process (step S205). In the voice control process, the voice control CPU 701 checks whether a communication end flag is set (step S231). The fact that the communication end flag is set means that a voice control command has been received.

  Therefore, if the communication end flag is set, it is cleared (step S232), and after the reception command is read from the reception buffer, the pattern data corresponding to each voice control command is set in the voice pattern table. Pattern data corresponding to the received command is read (step S233). Then, control data corresponding to the read pattern data is read from the ROM (step S234), and the following voice control is performed based on the read control data. The control data is data such as sound type and sound duration, and is set in the ROM corresponding to each pattern data.

  In this embodiment, the speech synthesis circuit 702 is controlled by a transfer request signal (SIRQ), a serial clock signal (SICK), a serial data signal (SI), and a transfer end signal (SRDY). When the SIRQ becomes low level, the voice synthesis circuit 702 captures SI one bit at a time in synchronization with SICK, and when SRDY becomes low level, interprets data composed of each SI received as one voice reproduction data. To do. Therefore, the voice control CPU 701 turns on SIRQ (low level) (step S235), outputs the control data read from the ROM as SI in synchronization with SICK (step S236), and when output is completed, sets SRDY to low. The level is set (step S237). When the voice synthesis circuit 702 receives control data by SI, the voice synthesis circuit 702 generates a voice corresponding to the received control data.

  Next, the operation of the lamp control means will be described. FIG. 44 is a flowchart showing main processing executed by the lamp control CPU 351. In the main process, first, an initial value setting process such as clearing the RAM area is performed (step S241). Thereafter, in this embodiment, the CPU 351 for lamp control shifts to a loop process for confirming the monitoring of the timer interrupt flag (step S242). Then, as shown in FIG. 45, when a timer interrupt occurs, the lamp control CPU 351 sets a timer interrupt flag (step S247). If the timer interrupt flag is set in the main process, the lamp control CPU 351 clears the flag (step S243) and performs the lamp control process (step S245).

  In this embodiment, it is assumed that the timer interrupt takes every 2 ms. That is, the lamp control process is started every 2 ms.

  FIG. 46 is a flowchart showing lamp control command reception processing by interrupt processing. The lamp control INT signal from the main board 31 is input to the interrupt terminal of the lamp control CPU 351. Therefore, when the INT signal from the main board 31 is turned on, the lamp control CPU 351 is interrupted and the lamp control command reception process shown in FIG. 46 is started.

  In the lamp control command reception process, the lamp control CPU 351 first reads data from an input port assigned to input of lamp control command data (step S251). Then, it is confirmed whether or not the first byte of the 2-byte lamp control command has been received (step S252). Whether the data has already been received can be confirmed by checking whether valid data is set in the first byte of the reception buffer.

  If the first byte has not been received yet, it is confirmed whether or not bit 7 of the received 1 byte is “1” (step S253). The bit 7 being “1” should be the MODE byte (first byte) in the ramp control command having a 2-byte configuration (see FIG. 34). If bit 7 is “1”, it is determined that a valid first byte has been received, and the received command is stored in the first byte of the reception buffer (step S254).

  If the first byte has already been received, it is confirmed whether bit 7 of the received 1 byte is “0” (step S255). Bit 7 must be “0” in the EXT byte (second byte) of the 2-byte lamp control command (see FIG. 34). In this case, if bit 7 is “0”, it is determined that a valid second byte has been received, and the received command is stored in the second byte of the reception buffer (step S256). Also, a communication end flag is set (step S257). The communication end flag is a flag indicating that the lamp control command has been normally received.

  If bit 7 of the received data is not “0” in step S255, the received data is newly stored in the first byte of the reception buffer (step S258).

  FIG. 47 is a flowchart showing the lamp control process (step S245). In the lamp control process, the lamp control CPU 351 checks whether or not a communication end flag is set (step S261). The fact that the communication end flag is set means that a lamp control command has been received.

  Therefore, if the communication end flag is set, it is cleared (step S262), the reception command is read from the reception buffer, and then received in the lamp pattern table in which pattern data corresponding to each lamp control command is set. Pattern data corresponding to the command is read (step S263). If the pattern data exists, that is, if the pattern data is described (step S264), the corresponding control pattern is changed (step S265). For example, when a lamp control command of “8000” is received, the control pattern related to the decoration lamp is changed, and the other start memory display 18, gate passage display 41, prize ball lamp 51 and out of ball lamp 52 are changed. Do not change the control pattern. Then, a lamp / LED control process (step S266) is executed.

  FIG. 48 is a flowchart showing an example of the lamp / LED control process (step S266). In the lamp / LED control process, the lamp control CPU 351 first checks whether or not it is lit (step S271). If it is lit, it is checked whether or not the actual lighting time has passed the lighting time set in the lamp / LED control pattern (step S272). If it has elapsed, the lamp / LED to be controlled is turned off (step S273).

  If it is not lit, it is checked whether the actual turn-off time has passed the turn-off time set in the lamp / LED control pattern (step S274). If it has elapsed, the lamp / LED to be controlled is turned on (step S275).

  This example is a simple example of repeating lighting and extinguishing, but even when a more complicated lighting / extinguishing pattern is realized, pattern data corresponding to the lamp control command is set in the lamp pattern table, Arbitrary lighting / extinguishing patterns can be realized by preparing a lamp / LED control pattern (a table in which specific lighting times and the like are set) corresponding to each pattern data.

  As described above, the lamp control means and the sound control means are provided separately from the game control means, and the game control means executes the game control program in response to an internal timer interrupt that occurs periodically. Therefore, the burden on the lamp / LED control and sound generation control of the game control means is reduced, and the cost of the gaming machine is reduced because a circuit for generating an external interrupt is not required.

  The lamp control means (light emitter control means) controls not only the light emitters provided in the frame of the gaming machine but also lighting control of the light emitters provided in the game board. Therefore, the game control means does not need to control the light emitters provided on the game board, and the control load on the game control means is reduced.

  The illuminant control means performs illuminant lighting control for notifying at least the number of memories for establishing the special symbol variation start condition and the number of memories for establishing the normal symbol variation start condition. Therefore, even when the game control unit is configured to detect and store the establishment of the conditions, the game control unit does not have to perform the light emitter lighting control for notifying the number of the storages. In addition to the fact that it is not necessary to turn on / off the stunning light emitter to enhance the game effect as the game progresses, it is not necessary to turn on / off the memory number. Is further reduced.

  Further, the game control means inputs the output signal of the power supply monitoring means via the input port, and if the signal indicates that the power supply voltage has dropped, the RAM check data is created and stored in the RAM, and then the RAM access prohibited state Set to. In addition, when the power is turned on, a RAM check is performed based on the RAM check data to check whether the data has been stored correctly. When it is confirmed that the game has been saved correctly, the gaming state is restored to the state when the power is cut off. Therefore, the gaming state at the time of power-off is saved, and the accuracy at the time of restoration is guaranteed. Therefore, even if the power is cut off during the game, the game is resumed from the power-off state at the time of recovery, so that it is possible to prevent the player from being disadvantaged.

  In the above embodiment, the following gaming machines are also disclosed.

A gaming machine capable of giving a game result value to a player as a result of performing a predetermined game, wherein the game control means for controlling the progress of the game and the game control means are provided separately and provided at least on the game board The light emitter control means for performing lighting control corresponding to the command sent from the game control means for a part of the light emitters being provided, and the command sent from the game control means provided separately from the game control means And a sound control means for performing sound output control, wherein at least at the game control means, a game control program is periodically executed, and a timer interrupt is used to periodically execute the game control program.
According to such a configuration, all the processing programs constituting the game control program are surely executed, the control burden on the game control means can be reduced, and the cost can be reduced.

The game control means includes a game control microcomputer for executing a game control program for performing game control. The game control program includes at least a main routine, a subroutine called during execution of the main routine, and a timer interrupt. The main routine includes at least an initialization process, a game control process for controlling the gaming state of the gaming machine, and a transition condition for shifting to the game control process. A game machine including a sign setting process for setting a flag for determining whether the transition condition is satisfied in the determination process.
According to such a configuration, it is not determined whether or not to shift to the next game control process until all the game control processes are executed, and all the processes in the game control process are completed. There is an effect that it is guaranteed.

A gaming machine that executes a determination process while repeatedly executing other processes when the game control microcomputer determines in the main routine that a transition condition for shifting to a game control process is satisfied.
According to such a configuration, it is possible to effectively utilize the remaining time of the execution time of the game control process.

A gaming machine that includes at least processing for updating numerical data used for game control.
According to such a configuration, the surplus time of the execution time of the game control process can be used effectively, and the randomness can be improved with respect to numerical data that requires randomness.

The RAM of the game control means is backed up so that the gaming state can be restored upon recovery after the power supply of the gaming machine is stopped, and the gaming machine monitors the power state and outputs a detection signal when a predetermined condition is detected A gaming machine comprising monitoring means, wherein the gaming control microcomputer is configured to execute predetermined power supply stop processing in response to a detection signal from the power supply monitoring means.
According to such a configuration, even if the power supply is stopped, necessary data is reliably saved, so that it is possible to prevent the player from being disadvantaged.

A gaming machine in which the RAM access prevention process is included in the power supply stop process.
According to such a configuration, there is an effect that data in the RAM is not destroyed when power supply is stopped.

A game machine in which the power supply stop process includes a check data creation process for creating and storing check data obtained as a result of a calculation related to the contents stored in the RAM.
According to such a configuration, it is possible to check whether the data is destroyed based on the check data when the power is restored, and it is possible to improve the reliability of the stored data.

The game control microcomputer is configured to check the RAM storage contents based on the check data in the process at the start of power supply, and if the check result is normal, the game state return processing is performed based on the RAM storage contents A gaming machine that has been.
According to such a configuration, since the gaming state return process is always performed based on the normal stored contents, there is an effect that the gaming state return process is correctly performed.

A gaming machine in which the gaming control microcomputer is configured to execute an initialization process if a check result is not normal.
According to such a configuration, there is an effect that the gaming state return process based on the abnormal stored contents is not performed.

A gaming machine configured such that the detection signal of the power monitoring means is input to the interrupt terminal of the gaming control microcomputer, and the process at the time of power supply stop is executed by the interrupt process based on the detection signal to the interrupt terminal .
According to such a configuration, since the power supply stop process is immediately started regardless of the operation state of the game control microcomputer, before the power supply voltage drops to a voltage at which the game control microcomputer cannot operate. In addition, the process when the power supply is stopped is surely completed.

DESCRIPTION OF SYMBOLS 1 Pachinko machine 18 Start memory display 31 Main board 35 Lamp control board 41 Gate passage memory display 70 Voice control board 53 Basic circuit 56 CPU
570 Input port 902 Power monitoring IC
910 Power supply board 916 Capacitor

Claims (1)

A specific game state having a variable display unit for variably displaying a plurality of types of identification information that can identify each of them and deriving and displaying the display result, and advantageous for the player when the specific display result is derived and displayed on the variable display unit A gaming machine to control
Game control means for controlling the progress of the game;
Display control means for controlling the variable display unit;
Even if the power supply is stopped, the stored data can be retained for a predetermined period, and the fluctuation data storage means for storing the fluctuation data generated when the game control means performs control,
First power supply monitoring means for monitoring a first power supply used in the gaming machine and outputting a detection signal when the voltage of the first power supply is equal to or lower than a first detection voltage;
A second power supply having a voltage lower than the voltage of the first power supply is monitored, and an operation stop signal is output when the voltage of the second power supply falls below a second detection voltage lower than the first detection voltage. Second power supply monitoring means,
The game control means includes
Command output means for outputting a command indicating that the variable display section is controlled to the display control means;
In response to the detection signal from the first power supply monitoring means, a process for stopping power supply for saving data for restoring the control state in the fluctuation data storage means is executed,
The operation is stopped in response to the operation stop signal from the second power supply monitoring means,
When power supply is started, a recovery control is executed to restore the control state to the state before starting the power supply stop process based on the stored contents stored in the fluctuation data storage means,
The command output means includes
When starting variable display of identification information, a variable display pattern command for specifying a variable display pattern of identification information in the variable display section, and a display result for specifying a display result of identification information in the variable display section Output the command
When the variable display of identification information is terminated, a stop command indicating that the identification information is stopped is output,
After outputting the variable display pattern command and the display result command, until the stop command is output, variable display command output is not performed.
The display control means includes
Based on the variable display pattern command, start variable display of identification information in the variable display unit,
A gaming machine , wherein a display result of identification information specified by the display result command is stopped and displayed on the variable display unit based on the stop command .

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