JP4636174B2 - Analog-digital conversion device, analog-digital conversion method, imaging device, driving method thereof, and camera - Google Patents

Description

  The present invention relates to an analog-digital conversion device and a conversion method thereof, an imaging device, a driving method thereof, and a camera. More specifically, the present invention relates to an analog-digital conversion apparatus that converts an analog value into a digital value by converting an analog signal into time, and a conversion method thereof. The present invention also relates to an imaging apparatus including such an analog-digital conversion apparatus, a driving method thereof, and a camera including such an analog-digital conversion apparatus.

  FIG. 13 is a schematic diagram for explaining a conventional CMOS image sensor. The CMOS image sensor shown here includes a pixel array unit 202, a vertical scanning circuit 203, a column signal processing unit 204, and a horizontal scanning circuit. 206 (for example, refer to Patent Document 1).

  Here, the pixel array unit 202 is configured by a large number of pixels 201 having photoelectric conversion elements arranged in a matrix, and the vertical scanning circuit 203 selects each pixel of the pixel array unit 202 row by row. Controls the shutter operation and readout operation of each pixel.

  The column signal processing unit 204 reads out signals from the pixel array unit 202 row by row and performs predetermined signal processing for each column.

  Further, the horizontal scanning circuit 206 is configured to select the signal of the column signal processing unit one row at a time and guide it to the horizontal signal line 205. From the horizontal signal line 205 by the data signal processing unit (not shown). The data is converted to the intended output form.

  By the way, an electric signal corresponding to the signal charge is sequentially read from each pixel 201 of the pixel array unit 202. That is, a method is generally employed in which an analog electrical signal read from each pixel 201 is converted into a digital signal by an analog-to-digital converter (ADC) and output to the outside.

Hereinafter, an example of a conventional ADC will be described with reference to the drawings.
A conventional ADC 301 shown in FIG. 14 includes a counter clock supply line 302, a comparator 304, and a counter 305.

  Here, a counter clock is supplied to the counter clock supply line 302, and a digital-to-analog converter (DAC) 303 is connected to the counter clock supply line 302. The comparator 304 is connected to the DAC 303, and the counter 305 is connected to the comparator 304 and the counter clock supply line 302.

  A counter clock (see “counter clock” in FIG. 15) is input to the above-described DAC 303 via the counter clock supply line 302. A ramp wave (analog signal) whose output value decreases at a constant rate at the rising and falling timings of the counter clock is output (see “DAC output (ramp wave)” in FIG. 15). .) Note that the ramp wave output from the DAC 303 is supplied to all the comparators 304 in common.

  The comparator 304 receives a pixel output (refer to “pixel output value” in FIG. 15) and a ramp wave, which are analog signals read from the pixel array unit 202 (pixel 201). When the relationship between the pixel output and the ramp wave is “(ramp wave)> (pixel output)”, a high level (H level) signal is output, and when “(ramp wave) <(pixel output)”. Is configured to output a low level (L level) signal (see "Comparator Output" in FIG. 15).

  Further, the counter 305 described above is a DDR (Double Date Rate) counter, and is configured to count at both the rising timing and falling timing of the input counter clock ("Counter output" in FIG. 15). reference.). The counter 305 is configured to stop counting when the output signal from the comparator 304 becomes L level.

  The ADC configured as described above stops counting at the timing when the output of the comparator is inverted from the H level signal to the L level signal, that is, when the ramp wave becomes smaller than the pixel output. The count value at that time is output as a digital value of the pixel output, and the analog signal (pixel output) can be converted into a digital value (count value) by converting the pixel output (electric signal) into time.

  Hereinafter, a specific description will be given with reference to FIG. Here, symbol V in the figure indicates the pixel output (analog value), and symbol L in the figure indicates the waveform of the ramp wave.

In the ADC configured as described above, in order to digitally convert the reset level of the pixel, the count value of the intersection P (the timing at which the output values become the same) of the ramp wave output from the DAC and the reset level is determined. . Further, in order to digitally convert the signal level of the pixel, the count value of the intersection D (the timing when the output values become the same) between the ramp wave output from the DAC and the signal level is determined.
As described above, the pixel output (electric signal) is converted into time, and the analog value (pixel output) is converted into a digital value (count value).

  Here, in the conventional ADC, the output waveform (ramp wave) from the DAC is always the same regardless of the pixel output. That is, regardless of the pixel output value, the period required for digital conversion of the reset level (P-phase readout period) and the period required for digital conversion of the signal level (D-phase readout period) are constant. is there.

JP 10-1226697 A

  By the way, unless the image is uniform in the horizontal direction, the pixel output (electrical signal) differs from column to column, and therefore it is necessary to perform scanning using a ramp wave that can cope with the pixel outputs of all columns.

  However, the empty scanning time after converting the analog values (pixel outputs) of all the columns into digital values (count values) is obviously useless. Specifically, when the pixel output Va in the A column, the pixel output Vb in the B column, and the pixel output Vc in the C column are digitally converted, the empty scanning period after the ramp wave L crosses Va, Vb, and Vc It can be said that the period (indicated by the symbol X in FIG. 17) is obviously useless.

  The present invention has been devised in view of the above points, and is an ADC that can reduce the sweeping of the ramp wave, a conversion method thereof, an imaging device including such an ADC, a driving method thereof, and such an ADC. The object is to provide a camera equipped.

  In order to achieve the above object, an analog-to-digital converter according to the present invention is provided corresponding to each analog signal to be converted into a digital signal, and a voltage value of the analog signal to be converted into a digital signal and a predetermined value A comparison unit that compares the voltage value of the reference signal, a counter that is provided corresponding to each comparison unit and counts a count value when the comparison process by the comparison unit is completed, and all the comparison units A determination unit that determines a time point when the comparison process is completed.

  In order to achieve the above object, an imaging apparatus according to the present invention includes a pixel array unit in which pixels that accumulate analog signals corresponding to incident light are arranged in a matrix, and each pixel that is read out. A comparison unit that is provided correspondingly and compares the voltage value of the analog signal generated by the pixel that has been read out with the voltage value of the predetermined reference signal, and is provided corresponding to each comparison unit. A counter that counts the count value at the time when the comparison process is completed, and a determination unit that determines the time point when all the comparison units have completed the comparison process.

  In order to achieve the above object, a camera according to the present invention includes a pixel array unit in which pixels that store analog signals corresponding to incident light are arranged in a matrix, and guides incident light to the pixel array unit. An optical system, a comparison unit that is provided corresponding to each pixel to be read out, compares a voltage value of an analog signal generated in the pixel from which reading is performed, and a voltage value of a predetermined reference signal; A counter that is provided corresponding to the comparison unit and counts a count value at the time when the comparison process by the comparison unit is completed, and a determination unit that determines a time point when all the comparison units have completed the comparison process. .

  Here, the timing at which all the analog-to-digital conversion processes are completed can be determined by determining when all the comparison units have completed the comparison process by the determination unit.

  In order to achieve the above object, the analog-digital conversion method according to the present invention includes a comparison step of comparing a voltage value of each analog signal converted into a digital signal with a predetermined reference signal, A count counting step for counting a count value at the time when the comparison step is completed, and a determination step for determining a time point when all the comparison steps are completed.

  Furthermore, in order to achieve the above object, a driving method of an imaging apparatus according to the present invention includes an accumulation step of accumulating an analog signal corresponding to incident light in pixels arranged in a matrix, and the reading is performed. A comparison process for comparing the voltage value of the analog signal generated by the pixel with a predetermined reference signal, a count counting process for counting a count value at the time when each comparison process is completed, and all comparison processes are completed. A determination step of determining a time point.

  Here, the timing at which all the analog-digital conversion processes are completed can be determined by the determination process for determining when all the comparison processes are completed.

  In the ADC to which the present invention is applied and its driving method, the imaging apparatus and its driving method, and the camera, it is possible to reduce the idle scanning period of the ramp wave.

The best mode for carrying out the invention (hereinafter referred to as “embodiment”) will be described below. The description will be given in the following order.
1. First Embodiment 2. FIG. Modified example (1) of the first embodiment (when the frame rate is fixed)
3. Modification (1) of the first embodiment (when the ramp wave is not reset)
4). Modified example (3) of the first embodiment (in the case of up-counting)
5. Second embodiment 6. 6. Modification of second embodiment Third embodiment

<1. First Embodiment>
[Imaging device]
FIG. 1 is a schematic diagram for explaining a CMOS image sensor which is an example of an imaging apparatus to which the present invention is applied. The CMOS image sensor shown here mainly includes a pixel array unit 22, a vertical scanning circuit 23, a column signal processing unit 24, a determination circuit 9, and a horizontal scanning circuit 26.

[Pixel array section]
Here, the pixel array unit 22 is configured by a large number of pixels 21 having photoelectric conversion elements arranged in a matrix, and the vertical scanning circuit 23 selects each pixel of the pixel array unit 22 row by row. Controls the shutter operation and readout operation of each pixel.

  Further, as shown in FIG. 2, each pixel 21 of the pixel array unit 22 has a circuit configuration including four transistors of a transfer transistor 12, a reset transistor 13, an amplification transistor 14, and a selection transistor 15 in addition to the photoelectric conversion element 11. It has become. Here, a circuit example using n-channel MOS transistors as the transistors 12 to 15 is shown. For example, a photodiode can be considered as the photoelectric conversion element.

  Here, the transfer transistor 12 is connected between the cathode electrode of the photodiode 11 and the floating diffusion part (FD part) 16, and the gate electrode is connected to the transfer control line 17 to which the transfer gate pulse TG is applied. In the reset transistor 13, a drain electrode is connected to the power source Vdd, a source electrode is connected to the FD unit 16, and a gate electrode is connected to a reset control line 18 to which a reset pulse RS is applied.

  Further, the amplification transistor 14 has a gate electrode connected to the FD portion 16, a drain electrode connected to the power supply Vdd, and a source electrode connected to the drain electrode of the selection transistor 15. The selection transistor 15 has a gate electrode connected to a selection control line 19 to which a selection pulse SEL is applied and a source electrode connected to a vertical signal line 30. The vertical signal line 30 is connected to a constant current source 31 that supplies a constant current to the vertical signal line, and is also connected to a column signal processing unit 24.

  FIG. 3 is a schematic diagram showing a cross-sectional structure of a pixel portion excluding the amplification transistor 14 and the selection transistor 15.

N-type diffusion regions 132, 133, and 134 are formed in the surface layer portion of the p-type substrate 131. In addition, on the p-type substrate 131, a gate electrode 135 is provided above the space between the n-type diffusion region 132 and the n-type diffusion region 133, and above the space between the n-type diffusion region 133 and the n-type diffusion region 134. Each of the gate electrodes 136 is formed via a gate oxide film (SiO ₂ ) (not shown).

  In correspondence with FIG. 2, the photodiode 11 is formed by a pn junction between a p-type substrate 131 and an n-type diffusion region 132. The transfer transistor 12 is formed by an n-type diffusion region 132 and an n-type diffusion region 133 and a gate electrode 135 therebetween. The reset transistor 13 is formed by an n-type diffusion region 133 and an n-type diffusion region 134 and a gate electrode 136 therebetween.

  The n-type diffusion region 133 becomes the FD portion 16 and is electrically connected to the gate electrode of the amplification transistor 14. A power supply potential Vdd is applied to the n-type diffusion region 134 serving as the drain region of the reset transistor 13. The upper surface of the p-type substrate 131 excluding the photodiode 11 is covered with a light shielding layer 137.

  Next, based on the cross-sectional view of FIG. 3, the circuit operation of the pixel 21 will be described using the waveform diagram of FIG.

  As shown in FIG. 3, when the photodiode 11 is irradiated with light, a pair of electrons (−) and holes (+) is induced according to the intensity of the light (photoelectric conversion). In FIG. 4, the selection pulse SEL is applied to the gate electrode of the selection transistor 15 at the time T <b> 1, and the reset pulse RS is simultaneously applied to the gate electrode of the reset transistor 13. As a result, the reset transistor 13 becomes conductive, and the FD unit 16 is reset to the power supply potential Vdd at time T2.

  When the FD unit 16 is reset, the potential of the FD unit 16 at the time of reset is output to the signal line 30 via the amplification transistor 14 as a reset level. This reset level corresponds to the inherent noise component of the pixel 21. The reset pulse RS is in an active (“H” level) state only for a predetermined period (time T1 to T3). The FD unit 16 maintains a reset state even after the reset pulse RS transitions from an active state to an inactive state (“L” level). The period in this reset state is the reset period.

  Next, the transfer gate pulse TG is applied to the gate electrode of the transfer transistor 12 at time T4 while the selection signal SEL remains in the active state. Then, the transfer transistor 12 becomes conductive, photoelectrically converted by the photodiode 11, and the accumulated signal charge is transferred to the FD unit 16. As a result, the potential of the FD portion 16 changes according to the amount of signal charges (time T4 to T5). The potential of the FD unit 16 at this time is output as a signal level to the signal line 30 via the amplification transistor 14 (signal readout period). The difference RSI1 between the signal level and the reset level becomes a pure pixel signal level from which the noise component is removed.

  Note that, generally, when a bright object is imaged, more charge is accumulated in the photodiode 11 than when a dark object is imaged, the level difference RSI1 on the vertical signal line 30 becomes larger.

  By the way, an electric signal corresponding to the signal charge is sequentially read from each pixel 21 of the pixel array unit 22. As described above, the analog electric signal read from each pixel 21 is generally converted into a digital signal by the ADC and output to the outside. For example, Japanese Patent Application Laid-Open No. 2000-152082 and Japanese Patent Application Laid-Open No. 2002-232291 describe the point of being converted into a digital signal by the ADC and output to the outside.

[About column signal processor]
The column signal processing unit 24 reads signals from the pixel array unit 22 row by row and performs predetermined signal processing for each column. Signal processing includes, for example, CDS processing (processing for removing fixed pattern noise caused by variations in threshold values of pixel transistors), AGC (auto gain control) processing, analog-digital conversion processing, and the like.

  Here, the analog-digital conversion processing is performed by the ADC 1 provided corresponding to each vertical signal line 30. Each ADC 1 includes a comparator 4 and a counter 5. Each vertical signal line 30 is connected to a MOS transistor 6 that functions as a load.

  Here, a count clock is supplied to a count clock supply line (not shown), and the DAC 3 is connected to the counter clock supply line. The comparator 4 is connected to the DAC 3, and the counter 5 is connected to the comparator 4 and the counter clock supply line.

  A counter clock is input to the above-described DAC 3 via a counter clock supply line. A down-count ramp wave (analog signal) whose output value decreases at a constant rate at the rising timing and falling timing of the counter clock is output. Specifically, it is configured to be able to output a down-count ramp wave that decreases at a constant rate from a fixed predetermined initial voltage value (ramp wave start voltage value). The ramp wave output from the DAC 3 is supplied to all the comparators 4 in common.

  Further, in the above-described comparator 4, a pixel output and a ramp wave that are analog signals read from the pixel array unit 22 (pixel 21) are input. When the relationship between the pixel output and the ramp wave is “(ramp wave)> (pixel output)”, an H level signal is output, and when “(ramp wave) <(pixel output)”, the L level signal is output. Is output.

  Further, the counter 5 described above is a DDR counter, and is configured to count at both the rising timing and falling timing of the input counter clock. The counter 5 is configured to stop counting at the timing when the output signal from the comparator 4 becomes L level.

  In the column signal processing unit 24 configured as described above, the count is stopped at the timing when the output of the comparator 4 is inverted from the H level signal to the L level signal, that is, when the ramp wave becomes smaller than the pixel output. The count value at that time is output as a digital value of the pixel output, and the analog signal (pixel output) can be converted into a digital value (count value) by converting the pixel output (electric signal) into time.

[About judgment circuit]
The determination circuit 9 is configured to determine the timing at which the outputs of all the comparators 5 are inverted from the H level signal to the L level signal. Specifically, it is configured to detect the timing at which the digital conversion is completed for all analog signals to be digitally converted by taking the logical product of the outputs of all the comparators 5.

  Further, when the determination circuit 9 detects the timing when all the analog-digital conversions are completed, the analog-digital conversion process is stopped. The timing for stopping the analog-digital conversion process may be immediately after all the analog-digital conversion processes are completed by the determination circuit, or even after a predetermined period after the analog-digital conversion process is completed. good.

[Horizontal scanning circuit]
Further, the horizontal scanning circuit 26 is configured to select each signal of the column signal processing unit 24 and guide it to the horizontal signal line 25. The horizontal signal line is displayed by the data signal processing unit (not shown). The data is converted into an output form intended for the signal from 25.

[Driving Method of Imaging Device]
The analog-digital conversion method in the CMOS image sensor to which the present invention is applied will be described below with reference to FIG. That is, an example of an analog-digital conversion method to which the present invention is applied and an example of a driving method for an imaging apparatus to which the present invention is applied will be described. Here, symbol Va in FIG. 5 indicates a pixel output in the A column, Vb indicates a pixel output in the B column, Vc indicates a pixel output in the C column, and symbol L in the drawing indicates a ramp wave. The waveform is shown. In FIG. 5, for convenience of explanation, all of Va, Vb, and Vc are shown, but actually, the digital conversion of Va is performed by the ADC 1 corresponding to the A column, and the digital conversion of Vb corresponds to the B column. The ADC 1 performs the digital conversion of Vc by the ADC 1 corresponding to the C column.

  In an example of the driving method of the imaging apparatus to which the present invention is applied, in order to digitally convert the reset level Pa of the pixel output value Va, the intersection of the reset level Pa and the ramp wave L (timing when the output values become the same) is counted. Determine the value. That is, the count starts when the ramp wave L decreases, and the count value at the intersection of the reset level Pa of the pixel output value Va and the ramp wave L is determined as the count value (digital value) of the reset level Pa of the pixel output value Va. .

  Specifically, the count starts with the decrease of the ramp wave L at the timing indicated by the symbol t1 in FIG. Then, the count is stopped at the intersection (point indicated by the symbol Pa) between the reset level Pa of the pixel output value Va and the ramp wave L, and the count value at that time is the count value (digital value) of the reset level Pa of the pixel output value Va. Determine as.

  Similarly to Va described above, in order to digitally convert the reset level Pb of the pixel output value Vb, the count value of the intersection (the timing at which the output value becomes the same) of the reset level Pb and the ramp wave L is determined. That is, the count starts when the ramp wave L decreases, and the count value at the intersection of the reset level Pb of the pixel output value Vb and the ramp wave L is determined as the count value (digital value) of the reset level Pb of the pixel output value Vb. .

  Specifically, the count starts with the decrease of the ramp wave L at the timing indicated by the symbol t1 in FIG. Then, the count is stopped at the intersection (point indicated by the symbol Pb) between the reset level Pb of the pixel output value Vb and the ramp wave L, and the count value at that time is the count value (digital value) of the reset level Pb of the pixel output value Vb. Determine as.

  Similar to Va and Vb described above, in order to digitally convert the reset level Pc of the pixel output value Vc, the count value of the intersection (the timing at which the output values become the same) of the reset level Pc and the ramp wave L is determined. That is, the count starts when the ramp wave L decreases, and the count value at the intersection of the reset level Pc of the pixel output value Vc and the ramp wave L is determined as the count value (digital value) of the reset level Pc of the pixel output value Vc. .

  Specifically, the count starts with the decrease of the ramp wave L at the timing indicated by the symbol t1 in FIG. Then, the count is stopped at the intersection (point indicated by the symbol Pc) of the reset level Pc of the pixel output value Vc and the ramp wave L, and the count value at that time is the count value (digital value) of the reset level Pc of the pixel output value Vc. Determine as.

  When the determination circuit detects that the digital conversion of the reset level of all the pixel output values has been completed, each process for digitally converting the reset level is stopped, and a P-phase readout period in which the reset level is digitally converted is set. Abort and finish. Specifically, each process for digitally converting the reset level is stopped at the timing indicated by reference sign t2 in FIG.

  Subsequently, in order to digitally convert the signal level Da of the pixel output value Va, the count value of the intersection (the timing at which the output values become the same) of the signal level Da and the ramp wave L is determined. That is, the count starts with the decrease of the ramp wave L, and the count value at the intersection of the signal level Da of the pixel output value Va and the ramp wave is determined as the count value (digital value) of the signal level Da of the pixel output value Va.

  Specifically, the count starts with the decrease of the ramp wave L at the timing indicated by the symbol t3 in FIG. Then, the count is stopped at the intersection (point indicated by symbol Da) between the signal level Da of the pixel output value Va and the ramp wave L, and the count value at that time is the count value (digital value) of the signal level Da of the pixel output value Va. Determine as.

  Similarly to Va described above, in order to digitally convert the signal level Db of the pixel output value Vb, the count value of the intersection (the timing at which the output value becomes the same) of the signal level Db and the ramp wave L is determined. That is, the count starts when the ramp wave L decreases, and the count value at the intersection of the signal level Db of the pixel output value Vb and the ramp wave L is determined as the count value (digital value) of the signal level Db of the pixel output value Vb. .

  Specifically, the count starts with the decrease of the ramp wave L at the timing indicated by the symbol t3 in FIG. Then, the count is stopped at the intersection (point indicated by symbol Db) between the signal level Db of the pixel output value Vb and the ramp wave L, and the count value at that time is the count value (digital value) of the signal level Db of the pixel output value Vb. Determine as.

  Similarly to the above Va and Vb, in order to digitally convert the signal level Dc of the pixel output value Vc, the count value of the intersection (the timing at which the output value becomes the same) of the signal level Dc and the ramp wave L is determined. That is, the count starts when the ramp wave L decreases, and the count value at the intersection of the signal level Dc of the pixel output value Vc and the ramp wave L is determined as the count value (digital value) of the signal level Dc of the pixel output value Vc. .

  Specifically, the count starts with the decrease of the ramp wave L at the timing indicated by the symbol t3 in FIG. Then, the count is stopped at the intersection (point indicated by symbol Dc) between the signal level Dc of the pixel output value Vc and the ramp wave L, and the count value at that time is the count value (digital value) of the signal level Dc of the pixel output value Vc. Determine as.

  When the determination circuit detects that the digital conversion of the signal levels of all the pixel output values has been completed, each process for digital conversion of the signal levels is stopped, and the D phase readout period is terminated. Specifically, each process for digitally converting the signal level is stopped at the timing indicated by reference numeral t4 in FIG.

  In the CMOS image sensor to which the present invention is applied, the P-phase readout period is shortened in order to terminate the P-phase readout period when the digital conversion of the reset levels of all the pixel output values is completed. The analog-digital conversion time can be shortened. Similarly, in the CMOS type image sensor to which the present invention is applied, the D-phase reading period is shortened in order to terminate the D-phase reading period when the digital conversion of the signal levels of all the pixel output values is completed. As a result, the analog-digital conversion period can be shortened.

  Further, by shortening the analog-digital conversion period, the readout period for the same number of pixels is shortened, and the frame rate can be improved. Furthermore, the power consumption required for reading out the same number of pixels can be reduced.

<2. Modification Example of First Embodiment (1)>
In the first embodiment described above, the P-phase readout period is terminated when the digital conversion of the reset level of all the pixel output values is completed, and the D-phase readout period for performing the digital conversion of the signal level of the pixel output value is started. The case is described as an example. However, it is not always necessary to change the frame rate, and when it is desired to fix the frame rate, it is not necessary to end the P-phase readout period even if the digital conversion of the reset levels of all the pixel output values is completed.

  For example, as shown in FIG. 6, when the digital conversion of the reset level of all the pixel output values is completed, the operations of the DAC 3, the counter 5, the comparator 4, and the load MOS 6 are stopped, and the P-phase readout period is set in this state. By continuing, reduction of power consumption will be realized. Similarly, as shown in FIG. 6, when the digital conversion of the signal levels of all the pixel output values is completed, the operations of the DAC 3, the counter, the comparator 4 and the load MOS 6 are stopped, and the D-phase readout period is set in this state. By continuing, reduction of power consumption will be realized.

<3. Modification Example of First Embodiment (2)>
In the first embodiment described above, the case where the ramp wave L is decreased from the initial voltage value in the D phase readout period is described as an example. However, the signal level of the pixel output value is generally higher than the reset level of the pixel output value. Therefore, as shown in FIG. 7A, in the D-phase readout period, the output value of the ramp wave L when the P-phase readout period is terminated may be successively decreased. By adopting such a driving method, the D phase readout period can be further shortened.

  Here, as described above, the signal level of the pixel output value is generally higher than the reset level of the pixel output value, but the signal level of the pixel output value may be lower than the reset level of the pixel output value. In such a case, as shown in FIG. 7 (b), it is sufficient to decrease the ramp wave L from the initial voltage value after the ramp wave L has fallen in the D phase readout period.

<4. Modification Example (3) of First Embodiment>
In the first embodiment described above, a case where a down-count ramp wave is used is described as an example. However, the down-count ramp wave is not necessarily required, and an up-count ramp wave may be used. .

<5. Second Embodiment>
In the first embodiment, the frame rate can be improved by optimizing the end points of the P-phase readout period and the D-phase readout period. Here, in the second embodiment, the end point of the P-phase readout period and the D-phase readout period is optimized, and the initial voltage value of the ramp wave L is optimized to further improve the frame rate. Is realized.

[Imaging device]
FIG. 8 is a schematic diagram for explaining a CMOS type image sensor which is another example of an imaging apparatus to which the present invention is applied. The CMOS image sensor shown here has a configuration in which a memory 8 is added to the CMOS image sensor of the first embodiment described above.

[About memory]
Here, the memory 8 is configured to be able to store the voltage value of the analog signal indicating the maximum voltage value among the analog signals digitally converted by each ADC at the previous timing.

  Then, a voltage value higher than the voltage value stored in the memory 8 by a predetermined voltage is set as an initial voltage value (ramp wave start voltage value), and a down-count ramp wave that decreases at a constant rate from the initial voltage value is output from the DAC 3. Will be.

[About the ramp wave]
A ramp wave output from the DAC 3 of the CMOS image sensor to which the present invention is applied will be described below with reference to FIG. Here, reference symbol V _(N−1) in FIG. 9 indicates a pixel output value indicating the maximum voltage value among the pixel output values (analog values) in the (N−1) th row. This is a pixel output value corresponding to the pixel output value Va shown in FIG. 5 of the first embodiment. In the figure, symbol L _(N-1) indicates the waveform of the ramp wave when the pixel in the (N-1) th row is output, and symbol L _N in the diagram indicates the waveform of the ramp wave when the pixel in the Nth row is output. The waveform is shown.

Further, the output value of the reset level of the pixel output value V _(N−1) of the (N−1) th row is denoted by P _(N−1) , and the pixel output value V ₍ N ₎ of the (N−1) th row. the output value of the signal levels of the _N-1) are shown in _{D (N-1).}

  In the following description, the analog / digital conversion of the signal charges generated in the pixels in the (N−1) th row is performed, and then the analog / digital conversion of the signal charges generated in the pixels in the Nth row is performed. An example will be described. That is, the analog / digital conversion of the signal charges generated in the pixels of the (N−1) th row is performed at the previous timing, and the analog / digital conversion of the signal charges generated in the pixels of the Nth row is performed at the later timing. The case where it is made is described as an example.

In the DAC configured as described above, the reset level output value P _(N−1) and the signal level output value D _(N−1) are stored in the memory 8, and the P _{(N− Based on 1)} and N _(N−1) , the ramp wave L _N at the time of pixel output in the Nth row is generated.

Specifically, as shown in Figure 9, a large voltage value predetermined voltage (d1) only than P _(N-1) as an initial voltage D _P, the ramp wave starts counting down from the initial voltage value D _P Is generated. In this manner, the ramp wave _LN of the digital conversion period (P-phase readout period) of the output value of the reset level of the pixel output value of the Nth row is generated. Moreover, a large voltage value predetermined voltage (d2) only than D _(N-1) as an initial voltage D _D, to generate a ramp wave that starts counting down from the initial voltage value D _D. In this way, the ramp wave _LN in the digital conversion period (D-phase readout period) of the signal level of the pixel output value in the Nth row is generated.

Here, the “predetermined voltage d1” is a voltage value generally considered as a difference in reset level between an analog signal that has been digitally converted at the previous timing and an analog signal that has been digitally converted at the later timing. The initial voltage value D _P is determined such predetermined voltage d1 is added with P _(N-1). Thus, the analog signal subjected to digital conversion at a timing later is considered to be less than the initial voltage value D _P.

Similarly, the “predetermined voltage d2” is a voltage value generally considered as a difference in signal level between an analog signal that has been digitally converted at the previous timing and an analog signal that has been digitally converted at the later timing. The initial voltage value D _D is determined such predetermined voltage value d2 by adding a D _(N-1). Thus, the analog signal subjected to digital conversion at a timing later is considered to be less than the initial voltage value D _D.

[Driving method of imaging apparatus]
Except for using the ramp wave _LN generated as described above, this is the same as the driving method of the imaging device in the first embodiment described above. Is omitted.

In the CMOS image sensor to which the present invention is applied, when generating the ramp wave _LN used at the time of digital conversion of the pixel output value of the Nth row, the initial voltage value is calculated from the pixel output value of the (N−1) th row. Therefore, the analog-digital conversion period can be further shortened.
That is, by predicting the range of the pixel output value of the Nth row from the pixel output value of the (N−1) th row and generating the ramp wave L _N that scans the prediction range, the analog-digital conversion period is further increased. Shortening is possible.

Here, when the ramp wave L _(N−1) is used for digital conversion of the pixel output value V _N of the N-th row, the count value of the reset level of the pixel output value V _N is determined. A P-phase readout period indicated by reference numeral T1 in 10 (a) is required. Moreover, D-phase readout period shown in FIG. 10 (a) Medium code T2 to determine the count value of the signal level of the pixel output value V _N is required.

Note that “when the ramp wave L _(N−1) is used for digital conversion of the pixel output value V _N of the Nth row” means that the pixel output value of the (N−1) th row is Nth. This means that the range of pixel output values in the row is not predicted.

In contrast, when a digital conversion of the N-th row of the pixel output value V _N, when using the ramp L _N is 10 in order to determine the count value of the reset level of the pixel output value V _N ( b) The P-phase readout period indicated by the middle code T3 is sufficient. Further, in order to determine the count value of the signal level of the pixel output value V _N , a D-phase readout period indicated by a symbol T4 in FIG.

Note that “when the ramp wave L _N is used for digital conversion of the pixel output value V _N in the N-th row” means that the pixel in the N-th row from the pixel output value in the (N−1) -th row. This means that the range of output values is predicted.

Here, a first N-th row of the reset level is a high voltage to the predicted range (d1) or more pixel output values, when was a voltage value higher than the initial voltage value D _P is the ramp L _N There will be no intersection, and the count value of the reset level cannot be determined.
In such a case, it is sufficient to take measures to detect the intersection with the reset level by outputting a down-count ramp wave from the maximum voltage value (> initial voltage value) of the DAC 3.

Similarly, the signal level of the N-th row of the pixel output value is a high voltage to the expected range (d2) above, if a voltage higher than the initial voltage value D _D is the ramp L _N There will be no intersection, and the count value of the signal level cannot be determined.
In such a case, it is sufficient to take measures to detect the intersection with the signal level by outputting a down-count ramp wave from the maximum voltage value (> initial voltage value) of the DAC 3.

  Specifically, as shown in FIG. 11, in order to digitally convert the signal level of the pixel output value in the Nth row, the ramp wave starts to decrease at the timing indicated by reference numeral t5 in FIG. Assume that the minimum voltage value of the DAC is reached without finding an intersection with the signal level. In such a case, a down-count ramp wave is output from the maximum voltage value of the DAC. By doing so, the intersection D between the ramp wave and the signal level is found, and the count value of the signal level of the pixel output value in the Nth row is determined.

<6. Modification of Second Embodiment>
In the second embodiment described above, the case where the memory 8 stores the voltage value of the analog signal indicating the maximum voltage value among the analog signals digitally converted by each ADC at the previous timing is taken as an example. I am explaining. However, it is sufficient that a ramp wave at a later timing can be generated with reference to an analog signal that has been digitally converted at the earlier timing, and the initial voltage value may be stored in the memory 8. That may be configured to initial voltage value D _P and D _D obtained by adding a predetermined voltage d1 and d2 to the voltage value of the analog signal indicative of the maximum voltage value to be stored.

  In the second embodiment described above, the signal charges generated by the pixels in the (N−1) th row at the previous timing are read out and generated by the pixels in the Nth row at the later timing. The case where the signal charges are read is described as an example. However, the signal charges generated by the pixels in the (N−1) th row are not necessarily read out at the previous timing. Therefore, the signal charge generated at the pixel in the Nth row at the previous timing may be read out, and the signal charge generated at the pixel at the (N−1) th row at the later timing may be read out. .

  Furthermore, in the second embodiment described above, an analog that is digitally converted at a later timing with respect to adjacent pixels, such as a pixel belonging to the (N-1) th row and a pixel belonging to the Nth row. The case where the signal range is predicted is described as an example. However, it is not always necessary to predict the range of the analog signal based on adjacent pixels. For example, a pixel belonging to the (N-3) th row and a pixel belonging to the Nth row can be analog based on non-adjacent pixels. The signal range may be predicted. However, in the case of two adjacent pixels, since it is generally considered that the difference is small, the analog-digital conversion period can be expected to be further shortened by predicting the range of the analog signal based on the adjacent pixels. It is.

  In the second embodiment described above, as described above, an analog signal for pixels in the same frame, such as a pixel belonging to the (N−1) th row and a pixel belonging to the Nth row, is used. The case where the prediction is performed is described as an example. However, it is not always necessary to target pixels in the same frame. For example, an analog signal in a subsequent frame in the same pixel may be predicted based on an analog signal in a previous frame in the same pixel.

  In the second embodiment described above, the case where a down-count ramp wave is used is described as an example. However, it is not always necessary to use a down-count ramp wave. Also good. When an up-count ramp wave is used, a voltage value that is smaller by a predetermined voltage than the voltage value of the analog signal indicating the minimum voltage value among the analog signals digitally converted at the previous timing is set as the initial voltage. .

<7. Third Embodiment>
[Camera configuration]
FIG. 12 is a schematic view for explaining a CMOS type camera 50 which is an example of a camera to which the present invention is applied. The CMOS type camera 50 shown here is the same as the CMOS type image sensor of the first embodiment described above. It is used as an imaging device.

  In the CMOS type camera 50 to which the present invention is applied, light enters the imaging area of the CMOS type image sensor 53 through an optical system such as a lens 51 and a mechanical shutter 52. The mechanical shutter 52 is for determining the exposure period by blocking the incidence of light to the imaging area of the CMOS type solid-state imaging device 53.

  Here, as the CMOS image sensor 53, the CMOS image sensor according to the first embodiment described above is used.

  The output signal of the CMOS type image sensor 53 is subjected to various signal processing such as automatic white balance adjustment by a next-stage signal processing device (DSP: Digital Signal Processor) 55, and is then derived to the outside as an imaging signal. Will be. The opening / closing control of the mechanical shutter 52, the control of the DSP 55, and the like are performed by a central processing unit (CPU) 56.

  Since the CMOS type camera 50 to which the present invention is applied employs the above-described CMOS type image sensor to which the present invention is applied, the P-phase readout period and the D-phase readout period can be shortened. The conversion period can be shortened.

It is a schematic diagram for demonstrating the CMOS type image sensor which is an example of the imaging device to which this invention is applied. It is a schematic diagram for demonstrating a pixel array part. It is a schematic diagram which shows the cross-section of the pixel part except an amplification transistor and a selection transistor. It is a schematic diagram for demonstrating the circuit operation | movement of a pixel. It is a schematic diagram for demonstrating an example of the analog-digital conversion method to which this invention is applied. It is a schematic diagram for demonstrating the modification (1) of 1st Embodiment. It is a schematic diagram (1) for demonstrating the modification (2) of 1st Embodiment. It is a schematic diagram (2) for demonstrating the modification (2) of 1st Embodiment. It is a schematic diagram for demonstrating the CMOS type image sensor which is another example of the imaging device to which this invention is applied. It is a schematic diagram for demonstrating the ramp wave output by DAC of the CMOS type image sensor to which this invention is applied. It is a schematic diagram for demonstrating shortening of a P-phase read-out period and a D-phase read-out period. It is a schematic diagram for demonstrating the case where the ramp wave of a down count is produced | generated from the maximum voltage value of DAC. It is a schematic diagram for demonstrating the CMOS type camera which is an example of the camera to which this invention is applied. It is a schematic diagram for demonstrating the conventional CMOS type image sensor. It is a schematic diagram for demonstrating the conventional ADC. It is a schematic diagram for demonstrating the principle of conventional ADC. It is a schematic diagram for demonstrating the conventional analog-digital conversion. It is a schematic diagram for demonstrating the idle scanning period in the conventional analog digital conversion.

Explanation of symbols

1 ADC
Reference Signs List 4 comparator 5 counter 6 MOS transistor 8 memory 9 determination circuit 11 photoelectric conversion element 12 transfer transistor 13 reset transistor 14 amplification transistor 15 selection transistor 16 FD unit 17 transfer control line 18 reset control line 19 selection control line 21 pixel 22 pixel array unit 23 Vertical scanning circuit 24 Column signal processing unit 25 Horizontal signal line 26 Horizontal scanning circuit 30 Vertical signal line 31 Constant current source 50 CMOS type camera 51 Lens 52 Mechanical shutter 53 CMOS type image sensor 55 DSP
56 CPU
131 p-type substrate 132, 133, 134 n-type diffusion region 135, 136 gate electrode 137 light shielding layer

Claims (16)

A comparison unit that is provided corresponding to each analog signal converted into a digital signal and compares the voltage value of the analog signal converted into the digital signal with the voltage value of a predetermined reference signal;
A counter that is provided corresponding to each comparison unit and counts a count value at the time when the comparison process by the comparison unit is completed;
An analog-to-digital conversion apparatus comprising: a determination unit that determines when all the comparison units have completed the comparison process. Generates a down-count reference signal with a voltage value that is a predetermined voltage higher than the voltage value of the analog signal indicating the maximum voltage value among the plurality of analog signals converted into digital signals at the previous timing. Alternatively, an up-count reference signal is generated with a voltage value that is a predetermined voltage lower than the analog signal indicating the minimum voltage value among a plurality of analog signals converted into digital signals at the previous timing as an initial voltage value. A reference signal generator,
2. The analog-to-digital converter according to claim 1, wherein the comparison unit compares a voltage value of an analog signal converted into a digital signal at a later timing with a voltage value of a reference signal generated by the reference signal generation unit. . When the reference signal generation unit does not complete the comparison process by the comparison unit even if the down-count reference signal reaches the minimum voltage value, the reference signal generation unit calculates the reference signal for the down-count from the maximum voltage value of the reference signal generation unit. Or when the comparison process by the comparison unit is not completed even when the up-count reference signal reaches the maximum voltage value, the up-count reference signal is calculated from the minimum voltage value of the reference signal generation unit. The analog-digital conversion device according to claim 2 to be generated. Among the plurality of analog signals converted into digital signals at the previous timing, the voltage value of the analog signal indicating the maximum voltage value is stored as the maximum voltage value, or the plurality of analog signals converted into digital signals at the previous timing Among analog signals, a voltage value storage unit that stores a voltage value of an analog signal indicating a minimum voltage value as a minimum voltage value;
A reference signal for down-counting with a voltage value that is larger than the maximum voltage value stored in the voltage value storage unit by a predetermined voltage as an initial voltage value is generated, or the minimum voltage stored in the voltage value storage unit A reference signal generation unit that generates a reference signal of up-count with a voltage value smaller than a value by a predetermined voltage as an initial voltage value;
2. The analog-to-digital converter according to claim 1, wherein the comparison unit compares a voltage value of an analog signal converted into a digital signal at a later timing with a voltage value of a reference signal generated by the reference signal generation unit. . Among the plurality of analog signals converted into digital signals at the previous timing, a voltage value that is larger than the voltage value of the analog signal indicating the maximum voltage value by a predetermined voltage is stored as the maximum voltage value, or at the previous timing Among a plurality of analog signals converted into digital signals, a voltage value storage unit that stores a voltage value smaller than the voltage value of the analog signal indicating the minimum voltage value by a predetermined voltage as the minimum voltage value;
A reference signal for down-counting using the maximum voltage value stored in the voltage value storage unit as an initial voltage value is generated, or up using the minimum voltage value stored in the voltage value storage unit as an initial voltage value. A reference signal generator for generating a reference signal for counting,
The digital-analog converter according to claim 1, wherein the comparison unit compares a voltage value of an analog signal that is converted into a digital signal at a later timing with a voltage value of a reference signal generated by the reference signal generation unit. . A comparison step of comparing the voltage value of each analog signal converted into a digital signal with a predetermined reference signal;
A count counting step for counting the count value at the time when each comparison step is completed;
An analog-to-digital conversion method comprising: a determination step of determining when all the comparison steps are completed. The comparison step or the count counting step at the time when it is determined that all the comparison steps are completed by the determination step, or when a predetermined period has elapsed from the time when it is determined that all the comparison steps are completed by the determination step. The analog-to-digital conversion method according to claim 6, wherein at least one of the two is stopped. The comparison step and the count counting step at the time when it is determined that all the comparison steps are completed by the determination step or when a predetermined period has elapsed from the time when it is determined that all the comparison steps are completed by the determination step. The analog-digital conversion method according to claim 6. A pixel array unit in which pixels that accumulate analog signals corresponding to incident light are arranged in a matrix;
A comparison unit that is provided corresponding to each pixel to be read, and that compares the voltage value of the analog signal generated by the pixel from which the reading has been performed with the voltage value of a predetermined reference signal;
A counter that is provided corresponding to each comparison unit and counts a count value at the time when the comparison process by the comparison unit is completed;
An imaging apparatus comprising: a determination unit that determines a point in time when all the comparison units have completed the comparison process. Down-count reference with an initial voltage value that is a predetermined voltage higher than the voltage value of the analog signal indicating the maximum voltage value among the analog signals generated by a plurality of pixels that have been read at the previous timing The initial voltage is a voltage value that is smaller than the voltage value of the analog signal indicating the minimum voltage value among the analog signals generated by a plurality of pixels that have generated signals or read at the previous timing. A reference signal generation unit that generates a reference signal of an upcount as a value,
The comparison unit according to claim 9, wherein the comparison unit compares the voltage value of the analog signal generated by the pixel that has been read out at a later timing with the voltage value of the reference signal generated by the reference signal generation unit. Imaging device. Of the analog signals generated by the plurality of pixels read out at the previous timing, the voltage value of the analog signal indicating the maximum voltage value is stored as the maximum voltage value, or read out at the previous timing. Among the analog signals generated by the plurality of pixels, a voltage value storage unit that stores the voltage value of the analog signal indicating the minimum voltage value as the minimum voltage value;
A reference signal for down-counting with a voltage value that is larger than the maximum voltage value stored in the voltage value storage unit by a predetermined voltage as an initial voltage value is generated, or the minimum voltage stored in the voltage value storage unit A reference signal generation unit that generates a reference signal of an upcount with a voltage value that is smaller than the value by a predetermined voltage as an initial voltage value,
The comparison unit according to claim 9, wherein the comparison unit compares the voltage value of the analog signal generated by the pixel that has been read out at a later timing with the voltage value of the reference signal generated by the reference signal generation unit. Imaging device. Among analog signals generated by a plurality of pixels that have been read at the previous timing, store a voltage value that is larger than the voltage value of the analog signal indicating the maximum voltage value by a predetermined voltage as the maximum voltage value, or Voltage value storage that stores, as a minimum voltage value, a voltage value that is smaller than a voltage value of an analog signal indicating the minimum voltage value among analog signals generated by a plurality of pixels that have been read at the previous timing by a predetermined voltage And
A reference signal for down-counting using the maximum voltage value stored in the voltage value storage unit as an initial voltage value is generated, or up using the minimum voltage value stored in the voltage value storage unit as an initial voltage value. A reference signal generator for generating a reference signal for counting,
The comparison unit according to claim 9, wherein the comparison unit compares the voltage value of the analog signal generated by the pixel that has been read out at a later timing with the voltage value of the reference signal generated by the reference signal generation unit. Imaging device. The imaging device according to claim 10, wherein the pixel that has been read at a later timing is adjacent to the pixel that has been read at a previous timing. The imaging device according to claim 10, 11 or 12, wherein a pixel that has been read at a previous timing and a pixel that has been read at a later timing are the same pixel. An accumulation step of accumulating analog signals according to incident light in pixels arranged in a matrix;
A comparison step of comparing the voltage value of the analog signal generated in the pixel that has been read out with a predetermined reference signal;
A count counting step for counting the count value at the time when each comparison step is completed;
And a determination step of determining when all the comparison steps are completed. A pixel array unit in which pixels that accumulate analog signals corresponding to incident light are arranged in a matrix;
An optical system for guiding incident light to the pixel array unit;
A comparison unit that is provided corresponding to each pixel to be read, and that compares the voltage value of the analog signal generated by the pixel from which the reading has been performed with the voltage value of a predetermined reference signal;
A counter that is provided corresponding to each comparison unit and counts a count value at the time when the comparison process by the comparison unit is completed;
A determination unit that determines a point in time when all the comparison units have completed the comparison process.

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