JP2010056707A - Analog/digital converter, analog/digital conversion method, imaging device, and driving method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an analog/digital converter which can perform high-speed processing. <P>SOLUTION: Among a plurality of analog signals to which an analog/digital conversion is performed in a previous timing, a down count ramp wave L<SB>N</SB>in which a voltage value which is larger than a voltage value V<SB>(N-1)</SB>indicating a maximum voltage value by a predetermined voltage d (d1 and d2) is made an initial voltage value (D<SB>p</SB>and D<SB>D</SB>)is generated. By using the ramp wave L<SB>N</SB>thus generated, the analog/digital conversion is performed in a subsequent timing. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an analog-to-digital converter (ADC), an analog-digital conversion method, an imaging apparatus, and a driving method thereof. Specifically, the present invention relates to an ADC that converts an analog value into a digital value by converting an analog signal into time, a conversion method thereof, an imaging apparatus including such an ADC, and a driving method thereof.

  In recent years, solid-state imaging devices such as CMOS (Complementary Metal Oxide Semiconductor) type image sensors have been widely used. Specifically, for example, it is widely used as an image input device (image pickup device) of an image pickup apparatus mounted on various portable terminal devices such as a mobile phone or an image pickup apparatus such as a digital still camera or a digital video camera (for example, , See Patent Document 1).

  FIG. 6 is a schematic diagram for explaining a CMOS image sensor. The CMOS image sensor shown here includes a pixel array unit 202, a vertical scanning circuit 203, a column signal processing unit 204, and a horizontal scanning circuit 206.

  Here, the pixel array unit 202 is configured by a large number of pixels 201 having photoelectric conversion elements arranged in a matrix, and the vertical scanning circuit 203 selects each pixel of the pixel array unit 202 row by row. Controls the shutter operation and readout operation of each pixel.

  The column signal processing unit 204 reads out signals from the pixel array unit 202 row by row and performs predetermined signal processing for each column. Signal processing includes, for example, CDS processing (processing for removing fixed pattern noise caused by variations in threshold values of pixel transistors), AGC (auto gain control) processing, analog-digital conversion processing, and the like.

  Further, the horizontal scanning circuit 206 is configured to select the signals of the column signal processing unit one by one and guide them to the horizontal signal line 205. From the horizontal signal line 205 by the data signal processing unit (not shown), The data is converted to the intended output form.

  Further, each pixel 201 in the pixel array unit has a circuit configuration including four transistors of a transfer transistor 102, a reset transistor 103, an amplification transistor 104, and a selection transistor 105 in addition to the photoelectric conversion element 101, as shown in FIG. It has become. Here, a circuit example using n-channel MOS transistors as these transistors 102 to 105 is shown. For example, a photodiode can be considered as the photoelectric conversion element.

  Here, the transfer transistor 102 is connected between the cathode electrode of the photodiode 101 and the FD (floating diffusion) unit 106, and the gate electrode is connected to the transfer control line 111 to which the transfer gate pulse TG is applied. In the reset transistor 103, a drain electrode is connected to the power source Vdd, a source electrode is connected to the FD unit 106, and a gate electrode is connected to a reset control line 112 to which a reset pulse RS is applied.

  Further, in the amplification transistor 104, the gate electrode is connected to the FD portion 106, the drain electrode is connected to the power supply Vdd, and the source electrode is connected to the drain electrode of the selection transistor 105. The selection transistor 105 has a gate electrode connected to a selection control line 113 to which a selection pulse SEL is applied and a source electrode connected to a vertical signal line 216. The vertical signal line is connected to a constant current source 217 that supplies a constant current to the vertical signal line, and is also connected to a column signal processing unit.

  FIG. 8 is a schematic diagram showing a cross-sectional structure of a pixel portion excluding the amplification transistor 104 and the selection transistor 105.

N-type diffusion regions 132, 133, and 134 are formed in the surface layer portion of the p-type substrate 131. In addition, on the p-type substrate 131, a gate electrode 135 is provided above the space between the n-type diffusion region 132 and the n-type diffusion region 133, and above the space between the n-type diffusion region 133 and the n-type diffusion region 134. gate electrode 136 is formed via a respective not shown gate oxide film (SiO _2).

  In correspondence with FIG. 7, the photodiode 101 is formed by a pn junction between a p-type substrate 131 and an n-type diffusion region 132. The transfer transistor 102 is formed by an n-type diffusion region 132 and an n-type diffusion region 133 and a gate electrode 135 therebetween. The reset transistor 103 is formed by an n-type diffusion region 133 and an n-type diffusion region 134 and a gate electrode 136 therebetween.

  The n-type diffusion region 133 becomes the FD portion 106 and is electrically connected to the gate electrode of the amplification transistor 104. A power supply potential Vdd is applied to the n-type diffusion region 134 which becomes the drain region of the reset transistor 103. The upper surface of the p-type substrate 131 excluding the photodiode 101 is covered with a light shielding layer 137.

  Next, the circuit operation of the pixel 201 will be described using the waveform diagram of FIG. 9 based on the cross-sectional view of FIG.

  As shown in FIG. 8, when the photodiode 101 is irradiated with light, a pair of electrons (−) and holes (+) is induced according to the intensity of light (photoelectric conversion). In FIG. 9, the selection pulse SEL is applied to the gate electrode of the selection transistor 105 at the time T <b> 1, and the reset pulse RS is simultaneously applied to the gate electrode of the reset transistor 103. As a result, the reset transistor 103 becomes conductive, and the FD portion 106 is reset to the power supply potential Vdd at time T2.

  When the FD unit 106 is reset, the potential of the FD unit 106 at the time of reset is output to the signal line 216 through the amplification transistor 104 as the reset level Vn. This reset level corresponds to a noise component specific to the pixel 201. The reset pulse RS is in an active (“H” level) state only for a predetermined period (time T1 to T3). The FD unit 106 maintains the reset state even after the reset pulse RS transitions from the active state to the inactive ("L" level) state. The period in this reset state is the reset period.

  Next, the transfer gate pulse TG is applied to the gate electrode of the transfer transistor 102 at time T4 while the selection signal SEL remains active. Then, the transfer transistor 102 becomes conductive, photoelectrically converted by the photodiode 101, and the accumulated signal charge is transferred to the FD unit 106. As a result, the potential of the FD portion 106 changes according to the amount of signal charges (time T4 to T5). The potential of the FD unit 106 at this time is output as a signal level Vs to the signal line 216 through the amplification transistor 104 (signal reading period). The difference RSI1 between the signal level Vs and the reset level Vn becomes a pure pixel signal level from which noise components are removed.

  Usually, when a bright object is imaged, more charge is accumulated in the photodiode 101 than when a dark object is imaged, so the level difference RSI1 on the vertical signal line 216 is larger.

  By the way, an electric signal corresponding to the signal charge is sequentially read from each pixel 201 of the pixel array unit 202. The analog electric signal read from each pixel 201 is converted into a digital signal by the ADC. Thus, a method of outputting to the outside is generally adopted. For example, Patent Document 2 and Patent Document 3 describe the point of being converted into a digital signal by the ADC and output to the outside.

  Hereinafter, an example of a conventional ADC will be described with reference to the drawings. FIG. 10 is a schematic diagram for explaining the configuration of the conventional ADC, and FIG. 11 is a schematic diagram for explaining the principle of the conventional ADC.

  A conventional ADC 301 shown in FIG. 10 includes a counter clock supply line 302, a comparator 304, and a counter 305.

  Here, a counter clock is supplied to the counter clock supply line 302, and a digital-to-analog converter (DAC) 303 is connected to the counter clock supply line 302. The comparator 304 is connected to the DAC 303, and the counter 305 is connected to the comparator 304 and the counter clock supply line 302.

  A counter clock (see “counter clock” in FIG. 11) is input to the above-described DAC 303 via the counter clock supply line 302. A ramp wave (analog signal) whose output value decreases at a constant rate at the rising and falling timings of the counter clock is output (see “DAC output (ramp wave)” in FIG. 11). .) Note that the ramp wave output from the DAC 303 is supplied to all the comparators 304 in common.

  The comparator 304 receives a pixel output (refer to “pixel output value” in FIG. 11) and a ramp wave, which are analog signals read from the pixel array unit 202 (pixel 201). When the relationship between the pixel output and the ramp wave is “(ramp wave)> (pixel output)”, a high level (H level) signal is output, and when “(ramp wave) <(pixel output)”. Is configured to output a low level (L level) signal (see "Comparator Output" in FIG. 11).

  Further, the counter 305 is a DDR (Double Date Rate) counter, and is configured to count at both the rising timing and falling timing of the input counter clock ("counter output" in FIG. 11). reference.). The counter 305 is configured to stop counting when the output signal from the comparator 304 becomes L level.

  In the ADC configured as described above, the count is stopped at the timing when the output of the comparator is inverted from the H level signal to the L level signal, that is, when the ramp wave becomes smaller than the pixel output. The count value at that time is output as a digital value of the pixel output, and the analog value (pixel output) is converted into a digital value (count value) by converting the pixel output (electric signal) into time.

Hereinafter, a specific description will be given with reference to FIG. Here, symbol V _(N−1) in the figure indicates the pixel output (analog value ₎ of the (N−1) th row, and symbol V _N in the figure indicates the pixel output (analog value) of the Nth row. ing. In the figure, the symbol L indicates the waveform of the ramp wave. In FIG. 12, for convenience of explanation, both V _(N−1) and V _N are shown, but in reality, V _N is output after V _(N−1) is output.

  In the ADC configured as described above, in order to digitally convert the reset level Vn of the pixels in the (N−1) -th row, the intersection of the ramp wave output from the DAC and the reset level Vn (with the same output value) Count value) is determined. That is, the count is started as the ramp wave decreases, and the count value at the intersection of the reset level Vn of the pixel on the (N-1) th row and the ramp wave is set to the reset level of the pixel on the (N-1) th row. It is determined as the count value (digital value) of Vn.

Specifically, the count starts with the decrease of the ramp wave at the timing indicated by the symbol t1 in FIG. Then, the count is stopped at the intersection of the reset level Vn of the pixel in the (N−1) th row and the ramp wave _(the point indicated by the symbol P _(N−1) ), and the count value at that time is the (N−1) th count value. This is determined as the count value (digital value) of the reset level Vn of the pixels in the row.

  Further, in order to digitally convert the signal level Vs of the pixel on the (N−1) th row, the count value of the intersection (the timing at which the output value becomes the same) of the ramp wave output from the DAC and the signal level Vs is calculated. decide. That is, the count starts with the decrease of the ramp wave, and the count value at the intersection of the signal level Vs of the pixel in the (N−1) th row and the ramp wave is the signal level of the pixel in the (N−1) th row. It is determined as the count value (digital value) of Vs.

Specifically, the count starts with the decrease of the ramp wave at the timing indicated by the symbol t2 in FIG. Then, the count is stopped at the intersection of the signal level Vs of the pixel in the (N−1) th row and the ramp wave _(the point indicated by the symbol D _(N−1) ), and the count value at that time is the (N−1) th count value. It is determined as the count value (digital value) of the signal level Vs of the pixel in the row.

  Similarly, in order to digitally convert the reset level Vn of the pixel in the Nth row, the count value of the intersection (the timing at which the output value becomes the same) between the ramp wave output from the DAC and the reset level Vn is determined. That is, the count starts when the ramp wave decreases, and the count value at the intersection of the reset level Vn of the pixel in the Nth row and the ramp wave is the count value (digital value) of the reset level Vn of the pixel in the Nth row. Determine as.

Specifically, the count starts with the decrease of the ramp wave at the timing indicated by the symbol t3 in FIG. Then, the count at the intersection between the reset level Vn and the ramp wave of the N-th row of pixels (points indicated by a symbol P _N) stops, the count value of the reset level Vn of the N-th row of the pixel count value at that time It is determined as (digital value).

  Further, in order to digitally convert the signal level Vs of the pixel in the Nth row, the count value of the intersection (the timing at which the output value becomes the same) between the ramp wave output from the DAC and the signal level Vs is determined. That is, the count starts when the ramp wave decreases, and the count value at the intersection of the signal level Vs of the pixel in the Nth row and the ramp wave is the count value (digital value) of the signal level Vs of the pixel in the Nth row. Determine as.

Specifically, the count starts with the decrease of the ramp wave at the timing indicated by the symbol t4 in FIG. Then, the N-th row of stops counting at the intersection (the point indicated by a symbol D _N) between the signal level Vs and the ramp wave of the pixel, the count value of the signal level Vs of the N-th row of the pixel count value at that time It is determined as (digital value).

  As described above, the pixel output (electric signal) is converted into time, and the analog value (pixel output) is converted into a digital value (count value).

  Here, the case where the value of the ramp wave decreases at a constant rate (in the case of the down-count ramp wave) is described as an example, but the up-count ramp wave whose output value increases at a constant rate is described. May be used.

  In the conventional ADC, the output waveform (ramp wave) from the DAC is always the same regardless of the pixel output. That is, even when the pixel output of the (N-1) th row is converted from analog to digital, or when the pixel output of the Nth row is converted from analog to digital, the ramp wave indicated by the symbol L in the figure. Is used.

  Accordingly, regardless of the pixel output, the period required for digital conversion of the reset level Vn (P-phase readout period) and the period required for digital conversion of the signal level Vs (D-phase readout period) are constant. It is.

JP 10-1226697 A JP 2000-152082 A JP 2002-232291 A

  Incidentally, in recent years, there has been a strong demand for an improvement in the processing speed of the imaging apparatus, and accordingly, an improvement in the processing speed in the ADC has been demanded.

  The present invention has been made in view of the above points, and an object thereof is to provide an ADC and an analog-digital conversion method capable of high-speed processing, an imaging apparatus capable of high-speed processing, and a driving method thereof. To do.

  In order to achieve the above object, in the analog-digital converter according to the present invention, among the plurality of analog signals converted into digital signals at the previous timing, the voltage value of the analog signal indicating the maximum voltage value is predetermined. Generate a down-count reference signal with a voltage value that is larger than the voltage as the initial voltage value, or the voltage value of the analog signal that indicates the minimum voltage value among the multiple analog signals converted to digital signals at the previous timing A reference signal generator for generating an up-count reference signal with a voltage value smaller than a predetermined voltage as an initial voltage value, and corresponding analog signals to be converted into digital signals. A comparison unit that compares the voltage value of the analog signal converted into a signal with the voltage value of the reference signal generated by the reference signal generation unit; And a counter for counting a count value when the comparison processing by the comparing unit is completed.

  In the analog-digital converter according to the present invention, among the plurality of analog signals converted into digital signals at the previous timing, the voltage value of the analog signal indicating the maximum voltage value is stored as the maximum voltage value, or Among a plurality of analog signals converted into digital signals at the previous timing, voltage value storage means for storing the voltage value of the analog signal indicating the minimum voltage value as the minimum voltage value, and stored in the voltage value storage means Generate a down-count reference signal with a voltage value larger than the maximum voltage value by a predetermined voltage as an initial voltage value, or a voltage value smaller by a predetermined voltage than the minimum voltage value stored in the voltage value storage means Corresponding to each analog signal converted to a digital signal A comparison unit that compares the voltage value of the analog signal that is provided and is converted to a digital signal at a later timing with the voltage value of the reference signal generated by the reference signal generation unit, and the comparison processing by the comparison unit is completed And a counter for counting the count value at the time point.

  In the analog-digital converter according to the present invention, the voltage value larger than the voltage value of the analog signal indicating the maximum voltage value by a predetermined voltage among the plurality of analog signals converted into the digital signal at the previous timing is maximized. Store as a voltage value or store a voltage value smaller than the voltage value of the analog signal indicating the minimum voltage value as a minimum voltage value among a plurality of analog signals converted into digital signals at the previous timing. Generating a voltage value storage means and a reference signal for down-counting using the maximum voltage value stored in the voltage value storage means as an initial voltage value, or the minimum voltage value stored in the voltage value storage means Corresponding to each analog signal converted to a digital signal A comparison unit that compares the voltage value of the analog signal that is provided and is converted to a digital signal at a later timing with the voltage value of the reference signal generated by the reference signal generation unit, and the comparison processing by the comparison unit is completed And a counter for counting the count value at the time point.

  Here, the reference signal generation unit generates the reference signal based on the analog signal indicating the maximum voltage value or the analog signal indicating the minimum voltage value among the analog signals converted into digital signals at the previous timing. As a result, the count operation period can be shortened. That is, by predicting a range of an analog signal converted into a digital signal at a later timing from an analog signal converted into a digital signal at a previous timing, and generating a reference signal that scans the predicted range, Shortening is realized.

  In addition, in the case of a down-count reference signal, a plurality of analog signals converted into digital signals at the previous timing in order to use the reference signal generated by the reference signal generation unit in common with a plurality of comparison units. Of these, the voltage value of the analog signal indicating the maximum voltage value is used as a reference. Similarly, in the case of an up-count reference signal, a plurality of analog signals converted into digital signals at the previous timing in order for a plurality of comparison units to use the reference signal generated by the reference signal generation unit in common. Among the signals, the voltage value of an analog signal indicating the minimum voltage value is used as a reference.

  Note that the difference (predetermined voltage) between the reference voltage value and the initial voltage value is converted into a digital signal at a timing predicted based on the analog signal converted into a digital signal at the previous timing. Determined from the range of the analog signal.

  In order to achieve the above object, in the analog-digital conversion method according to the present invention, among the plurality of analog signals converted into digital signals at the previous timing, the voltage value of the analog signal indicating the maximum voltage value is used. Generates a reference signal for down-counting with a voltage value larger by a predetermined voltage as an initial voltage value, or an analog signal indicating the minimum voltage value among a plurality of analog signals converted into digital signals at the previous timing. A reference signal generation step of generating an up-count reference signal using a voltage value smaller than the voltage value by a predetermined voltage as an initial voltage value, a voltage value of an analog signal converted into a digital signal at a later timing, and the reference signal A comparison step for comparing the reference signal generated in the generation step and a count counter for counting the count value at the time when the comparison step is completed Provided with a door.

  Here, by generating the reference signal based on the analog signal indicating the maximum voltage value or the analog signal indicating the minimum voltage value among the analog signals converted into the digital signals at the previous timing by the reference signal generation step. Thus, the count operation period can be shortened. That is, by predicting a range of an analog signal converted into a digital signal at a later timing from an analog signal converted into a digital signal at a previous timing, and generating a reference signal that scans the predicted range, Shortening is realized.

  In order to achieve the above object, in the imaging apparatus according to the present invention, readout is performed at a timing earlier with a pixel array unit in which pixels that accumulate analog signals corresponding to incident light are arranged in a matrix. Generating a down-count reference signal with an initial voltage value that is a voltage value larger than the voltage value of the analog signal indicating the maximum voltage value among the analog signals generated by a plurality of pixels, or Up-count reference signal with a voltage value that is a predetermined voltage smaller than the voltage value of the analog signal indicating the minimum voltage value among the analog signals generated by the plurality of pixels read out at the timing of And a reference signal generation unit for generating a pixel and a pixel which is provided corresponding to each pixel to be read out and read out at a later timing A comparison unit that compares the voltage value of the analog signal and the voltage value of the reference signal generated by the reference signal generation unit, and a counter that counts the count value when the comparison processing by the comparison unit is completed Prepare.

  In the imaging device according to the present invention, an analog signal generated by a pixel array unit in which pixels that accumulate analog signals corresponding to incident light are arranged in a matrix and a plurality of pixels that have been read out at the previous timing. Among the signals, the voltage value of the analog signal indicating the maximum voltage value is stored as the maximum voltage value, or the minimum voltage value among the analog signals generated by a plurality of pixels read out at the previous timing Voltage value storage means for storing a voltage value of an analog signal indicating the minimum voltage value, and a down-counting operation using a voltage value that is larger than the maximum voltage value stored in the voltage value storage means by a predetermined voltage as an initial voltage value. Generates a reference signal or counts up using a voltage value that is smaller than the minimum voltage value stored in the voltage value storage unit by a predetermined voltage as an initial voltage value A reference signal generation unit that generates a reference signal, a voltage value of an analog signal that is provided corresponding to each pixel that is read out and is read out at a later timing, and the reference signal generation A comparison unit that compares the voltage value of the reference signal generated by the unit, and a counter that counts the count value when the comparison process by the comparison unit is completed.

  In the imaging device according to the present invention, an analog signal generated by a pixel array unit in which pixels that accumulate analog signals corresponding to incident light are arranged in a matrix and a plurality of pixels that have been read out at the previous timing. Among the signals, a voltage value larger than the voltage value of the analog signal indicating the maximum voltage value by a predetermined voltage is stored as the maximum voltage value, or an analog generated by a plurality of pixels read out at the previous timing Among the signals, voltage value storage means for storing a voltage value smaller than the voltage value of the analog signal indicating the minimum voltage value by a predetermined voltage as the minimum voltage value, and the maximum voltage value stored in the voltage value storage means Generate a down-count reference signal with an initial voltage value, or up-count with the minimum voltage value stored in the voltage value storage means as an initial voltage value A reference signal generation unit that generates a reference signal, a voltage value of an analog signal that is provided corresponding to each pixel that is read out and is read out at a later timing, and the reference signal generation A comparison unit that compares the voltage value of the reference signal generated by the unit, and a counter that counts the count value when the comparison process by the comparison unit is completed.

Here, the reference signal generation unit generates the reference signal based on the analog signal indicating the maximum voltage value among the analog signals generated in the pixels that have been read out at the previous timing. Is shortened. Similarly, the reference signal generation unit generates the reference signal based on the analog signal indicating the minimum voltage value among the analog signals generated in the pixels that have been read out at the previous timing. Is shortened.
That is, the analog signal generated at the pixel read out at a later timing is predicted from the analog signal generated at the pixel read out at the previous timing, and a reference signal for scanning the predicted range is generated. By doing so, the count operation period can be shortened.

  In order to achieve the above object, in the driving method of the imaging apparatus according to the present invention, an accumulation process for accumulating analog signals corresponding to incident light in pixels arranged in a matrix and reading at the previous timing are performed. A reference signal for down-counting is generated with a voltage value that is a predetermined voltage larger than the voltage value of the analog signal indicating the maximum voltage value among the analog signals generated by the plurality of pixels performed, or Of the analog signals generated by the plurality of pixels that have been read out at the previous timing, the initial voltage value is a voltage value that is a predetermined voltage smaller than the voltage value of the analog signal indicating the minimum voltage value. A reference signal generation step for generating a reference signal, a voltage value of an analog signal generated by a pixel read out at a later timing, and the reference signal generation Comprising a comparison step for comparing the reference signal generated by the extent, and a count counting step for counting a count value of the time the comparison process is completed.

Here, the reference signal generation step generates the reference signal based on the analog signal indicating the maximum voltage value among the analog signals generated by the pixels that have been read out at the previous timing. Shortening is realized. Similarly, the reference signal generation step generates the reference signal based on the analog signal indicating the minimum voltage value among the analog signals generated by the pixels that have been read out at the previous timing. Shortening is realized.
That is, the analog signal generated at the pixel read out at a later timing is predicted from the analog signal generated at the pixel read out at the previous timing, and a reference signal for scanning the predicted range is generated. By doing so, the count counting step can be shortened.

  In the ADC and analog-to-digital conversion method to which the present invention is applied, the imaging apparatus, and the driving method thereof, the count operation period (count counting process) is shortened, and high-speed processing can be supported.

Hereinafter, embodiments of the present invention will be described with reference to the drawings to facilitate understanding of the present invention.
FIG. 1 is a schematic diagram for explaining a CMOS image sensor which is an example of an imaging apparatus to which the present invention is applied. The CMOS image sensor shown here includes a pixel array unit 22, a vertical scanning circuit 23, a column signal processing unit 24, a horizontal scanning circuit 26, a DAC 3, and a memory 8.

  Here, the pixel array unit 22 is configured by a large number of pixels 21 having photoelectric conversion elements arranged in a matrix, and the vertical scanning circuit 23 selects each pixel of the pixel array unit 22 row by row. Controls the shutter operation and readout operation of each pixel.

  The column signal processing unit 24 reads signals from the pixel array unit 22 row by row and performs predetermined signal processing for each column. Signal processing includes CDS processing, AGC processing, analog-digital conversion processing, and the like, as in a conventional CMOS image sensor.

  Further, the horizontal scanning circuit 26 is configured to select each signal of the column signal processing unit and guide it to the horizontal signal line 25. The horizontal signal line 25 is selected by a data signal processing unit (not shown). The data is converted to the intended output form.

  Each pixel 21 of the pixel array unit has a circuit configuration including four transistors, that is, a transfer transistor 12, a reset transistor 13, an amplification transistor 14, and a selection transistor 15 in addition to the photoelectric conversion element 11, as in the conventional case. (See FIG. 7). Here, a circuit example using n-channel MOS transistors as the transistors 12 to 15 is shown. For example, a photodiode can be considered as the photoelectric conversion element.

  Here, the transfer transistor 12 is connected between the cathode electrode of the photodiode 11 and the FD unit 16, and the gate electrode is connected to the transfer control line 17 to which the transfer gate pulse TG is applied. In the reset transistor 13, a drain electrode is connected to the power source Vdd, a source electrode is connected to the FD unit 16, and a gate electrode is connected to a reset control line 18 to which a reset pulse RS is applied.

  Further, the amplification transistor 14 has a gate electrode connected to the FD portion 16, a drain electrode connected to the power supply Vdd, and a source electrode connected to the drain electrode of the selection transistor 15. The selection transistor 15 has a gate electrode connected to a selection control line 19 to which a selection pulse SEL is applied and a source electrode connected to a vertical signal line 30. The vertical signal line is connected to a constant current source 31 that supplies a constant current to the vertical signal line, and is also connected to a column signal processing unit.

  Note that the cross-sectional structure of the pixel portion is exactly the same as the above-described conventional structure, and thus description thereof is omitted (see FIG. 8).

  Further, the ADC 1 provided for each vertical signal line 30 in the column signal processing unit 24 includes a comparator 4 and a counter 5 like the conventional ADC.

  Here, a counter clock is supplied to a counter clock supply line (not shown), and the DAC 3 is connected to the counter clock supply line. The comparator 4 is connected to the DAC 3, and the counter 5 is connected to the comparator 4 and the counter clock supply line.

A counter clock is input to the above-described DAC 3 via a counter clock supply line. A down-count ramp wave (analog signal) whose output value decreases at a constant rate at the rising timing and falling timing of the counter clock is output. Specifically, a voltage value higher than the voltage value stored in the memory 8 by a predetermined voltage is set as an initial voltage value (ramp wave start voltage), and a down-count ramp wave that decreases at a constant rate from the initial voltage value is output. It is configured to do.
The ramp wave output from the DAC 3 is supplied to all the comparators 4 in common.

  Further, the memory 8 is configured to be able to store the voltage value of an analog signal indicating the maximum voltage value among the analog signals digitally converted by each ADC at the previous timing.

The ramp wave output from the DAC of the CMOS image pickup apparatus to which the present invention is applied will be specifically described below with reference to the drawings. Here, the symbol V _(N−1) in the figure indicates the pixel output value indicating the maximum voltage value among the pixel output values (analog values) in the (N−1) th row. In the figure, symbol L _(N-1) indicates the waveform of the ramp wave when the pixel of the (N-1) th row is output, and symbol L _N in the diagram indicates the waveform of the ramp wave when the pixel of the Nth row is output. The waveform is shown.

Further, the output value of the reset level of the pixel output value V _(N−1) of the (N−1) th row is denoted by P _(N−1) , and the pixel output value V ₍ N ₎ of the (N−1) th row. the output value of the signal levels of the _N-1) are shown in _{D (N-1).}

  In the following, the analog / digital conversion of the signal charges generated in the pixels in the (N−1) th row is performed, and then the analog / digital conversion of the signal charges generated in the pixels in the Nth row is performed. An example will be described. That is, the analog / digital conversion of the signal charges generated in the pixels of the (N−1) th row is performed at the previous timing, and the analog / digital conversion of the signal charges generated in the pixels of the Nth row is performed at the later timing. An explanation will be given by taking the case of being made as an example.

In the DAC configured as described above, the reset level output value P _(N−1) and the signal level output value D _(N−1) are stored in the memory 8, and the P _{(N− Based on 1)} and D _(N−1) , the ramp wave L _N at the time of pixel output in the Nth row is generated.

Specifically, as shown in Figure 2, P a large voltage value predetermined voltage (d1) only than _(N-1) as an initial voltage value D _p, lamp starts down clock from the initial voltage value D _p Generate a wave. In this way, generating a ramp wave of the digital conversion period of the output value P _N of the reset level of the N-th row of the pixel output values (P phase readout period). Also, the initial voltage value a large voltage value predetermined voltage (d2) only than D _(N-1), to generate a ramp wave starts down clock from the initial voltage value D _D. In this way, generating a ramp wave of the digital conversion period of the output value D _N of the signal level of the N-th row of the pixel output values (D-phase readout period).

Here, the “predetermined voltage d1” is a voltage value generally considered as a difference between an analog signal digitally converted at the previous timing and an analog signal digitally converted at the later timing. The initial voltage value D _P is determined such predetermined voltage d1 is added with P _(N-1). Accordingly, the analog signals subjected to digital conversion timing after is considered to be equal to or less than the initial voltage value D _P.

Similarly, the “predetermined voltage d2” is a voltage value generally considered as a difference between an analog signal that has been digitally converted at a previous timing and an analog signal that has been digitally converted at a later timing. The initial voltage value D _D is determined such predetermined voltage value d2 by adding a D _(N-1). Accordingly, the analog signals subjected to digital conversion timing after is considered to be equal to or less than the initial voltage value D _D.

Hereinafter, an analog-to-digital conversion method of the pixel output value of the Nth row using the ramp wave _LN generated as described above will be described with reference to FIG.
First, the reset level P _N of the N-th row of pixel output values to digital conversion, the count of the intersection of the ramp L _N and the reset level P _N which is output from the DAC (the timing at which the output value is the same) Determine the value. That starts counting with decreasing ramp, count reset level P _N of the count value of the intersection between the reset level P _N and the ramp wave of the N-th row of the pixel output values the N-th row of the pixel output values Determined as a value (digital value).

Specifically, the count starts with the decrease of the ramp wave at the timing indicated by the symbol t1 in FIG. Then, the count is stopped at the intersection (point indicated by the symbol P) between the reset level P _N of the pixel output value of the Nth row and the ramp wave L _N, and the count value at that time is the value of the pixel output value of the Nth row. determined as the count value of the reset level P _N (digital value).

Further, the signal level D _N of the N-th row of pixel output values to digital conversion, the count of the intersection of the ramp L _N and the signal level D _N output from the DAC (the timing at which the output value is the same) Determine the value. That starts counting with decreasing ramp, the count of the N-th row of the signal level of the pixel output values D _N and the signal level of the N-th row of pixel output values, the count value of the intersection of the ramp wave D _N Determined as a value (digital value).

Specifically, the count starts with the decrease of the ramp wave at the timing indicated by the symbol t2 in FIG. Then, the count at the intersection of the first N signal level of the pixel of row output value D _N and ramp L _N (a point indicated by a symbol D) is stopped, the count value at that time of the N-th row of the pixel output values determined as a count value of the signal level D _N (digital value).

Here, in the CMOS type image sensor of this embodiment, the voltage value of the analog signal indicating the maximum voltage value among the analog signals digitally converted by each ADC at the previous timing is stored in the memory 8 as an example. The explanation is given. However, it is sufficient that a ramp wave at a later timing can be generated on the basis of an analog signal that has been digitally converted at the previous timing, and the initial voltage value may be stored in the memory 8. That may be configured to initial voltage value D _P and D _D obtained by adding a predetermined voltage d1 and d2 to the voltage value of the analog signal indicative of the maximum voltage value to be stored.

  In the CMOS image sensor of the present embodiment, the signal charges generated by the pixels in the (N−1) th row are read at the previous timing, and are generated by the pixels at the Nth row at the later timing. The case where the signal charges are read is described as an example. However, the signal charges generated by the pixels in the (N−1) th row are not necessarily read out at the previous timing. Therefore, the signal charge generated at the pixel in the Nth row at the previous timing may be read out, and the signal charge generated at the pixel at the (N−1) th row at the later timing may be read out. .

  Further, in the CMOS image sensor of this embodiment, an analog which is digitally converted at a later timing with respect to adjacent pixels, such as a pixel belonging to the (N-1) th row and a pixel belonging to the Nth row. The case where the signal range is predicted is described as an example. However, it is not always necessary to predict the range of the analog signal based on adjacent pixels. For example, a pixel belonging to the (N-3) th row and a pixel belonging to the Nth row can be analog based on non-adjacent pixels. The signal range may be predicted. However, in the case of two adjacent pixels, since the difference is generally considered to be small, it is expected that the count operation period can be further shortened by predicting the range of the analog signal based on the adjacent pixels. is there.

  In the CMOS type image sensor of this embodiment, as described above, an analog signal for pixels in the same frame, such as a pixel belonging to the (N-1) th row and a pixel belonging to the Nth row, is used. The case where the prediction is performed is described as an example. However, it is not always necessary to target pixels in the same frame. For example, an analog signal in a subsequent frame in the same pixel may be predicted based on an analog signal in a previous frame in the same pixel.

  In the CMOS type image sensor of this embodiment, a case where a down-count lamp is used has been described as an example. However, it is not always necessary to use a down-count lamp. good. When an up-count ramp wave is used, a voltage value that is smaller by a predetermined voltage than the voltage value of the analog signal indicating the minimum voltage value among the analog signals digitally converted at the previous timing is set as the initial voltage. .

In the CMOS image sensor to which the present invention is applied, when generating the ramp wave _LN used at the time of digital conversion of the pixel output value of the Nth row, the initial voltage value is calculated from the pixel output value of the (N−1) th row. Therefore, the count operation period can be reduced.
That is, in the conventional ADC, the output waveform from the DAC is always constant irrespective of the pixel output period during which the counter is operated to digital conversion of the P _N has a period shown in Figure 12 in sign L _PN . Further, the period for operating the counter to digitally convert _DN is a period indicated by the symbol _DPN in FIG. On the other hand, in the CMOS type image sensor to which the present invention is applied, the initial voltage value is determined from the pixel output value of the (N−1) th row, and the counter is operated to digitally convert _PN . period is a period shown in Figure 3 reference numeral M _PN. The period during which the counter is operated to digital conversion of the D _N is a period indicated in Figure 3 reference numeral M _DN.

Specifically, when a ramp L _(N-1) were also utilized to digital conversion of the N-th row of pixel output values, the count value of the reset level P _N of the N-th row of the pixel output values for determining, it is necessary period indicated in Fig sign T _P. Further, in order to determine the count value of the signal level D _N of the N-th row of pixel output values, it is necessary period indicated by a symbol T _D in FIG.
In contrast, the ramp L _N when using the digital conversion of the N-th row of pixel output values, to determine the count value of the reset level P _N of the N-th row of pixel output values, it is a period indicated in Figure 3 reference numeral _{M PN.} Further, in order to determine the count value of the signal level D _N of the N-th row of pixel output values, a period indicated in Figure 3 reference numeral M _DN.

  As described above, by shortening the operation period of the counter, it is possible to shorten the analog-digital conversion time of each pixel, thereby realizing a high-speed operation of the CMOS imaging device. Become.

  In view of the fact that the counter occupies most of the power consumption of the ADC, the reduction of the power consumption of the ADC is realized by realizing the shortening of the operation period of the counter. Reduction of the power consumption of the apparatus will be realized.

Here, a reset level P _N is a high voltage to the predicted range (d1) or more of the N-th row of pixel output values, when was a voltage value higher than the initial voltage value D _P is ramp L _N becomes that there is no intersection between the count value of the reset level P _N is not be determined.
In such a case, it is sufficient to correspond to detect an intersection point between the reset level P _N by outputting a ramp wave down-count from the maximum voltage value of the DAC (> initial voltage value).

Likewise, a signal level D _N is a high voltage to the predicted range (d2) above the N-th row of pixel output values, when was a voltage value higher than the initial voltage value D _D is ramp L _N It becomes that there is no intersection between the count value of the signal level D _N is can not be determined.
In such a case, it is sufficient to correspond to detect the intersection of the signal level D _N by outputting a ramp wave down-count from the maximum voltage value of the DAC (> initial voltage value).

Specifically, as shown in Figure 5, in order to digital conversion of the signal level D _N of the N-th row of pixel output values, to start the reduction of the ramp at the timing shown in FIG. 5, reference numeral t5, ramp and the intersection between the wave and the signal level D _N reaches a minimum voltage value of the DAC without finding. In such a case, a down-count ramp wave is output from the maximum voltage value of the DAC at the timing when the minimum voltage value of the DAC is reached (timing indicated by the symbol t6 in FIG. 5). By doing so, it found intersection D between the ramp and the signal level D _N, so that the digital value of the N-th row of the pixel output value is determined.

  Even when a down-count ramp wave is output from the maximum voltage value of the DAC, the count operation period does not increase as compared with the conventional ADC. That is, in the conventional ADC, the maximum voltage value of the DAC is used as the initial voltage value to generate a down-count ramp wave. For example, after reaching the minimum voltage value, the down-count ramp wave is output from the maximum voltage value. However, this is only a counting operation period between the conventional ADC and the synchronization.

It is a schematic diagram for demonstrating the CMOS type image sensor which is an example of the imaging device to which this invention is applied. It is a schematic diagram for _{demonstrating} the production _| generation of the ramp wave _LN . It is a schematic diagram for demonstrating the analog-digital conversion of the pixel output value of the Nth line. It is a schematic diagram for explaining an analog-to-digital conversion when using ramp L _(N-1). It is a schematic diagram for demonstrating the case where the ramp wave of a down count is produced | generated from the maximum voltage value of DAC. It is a schematic diagram for demonstrating the conventional CMOS type image sensor. It is a schematic diagram for demonstrating a pixel array part. It is a schematic diagram for demonstrating the cross-sectional structure of a pixel part. It is a schematic diagram for demonstrating the circuit operation | movement of a pixel. It is a schematic diagram for demonstrating the conventional ADC. It is a schematic diagram for demonstrating the principle of conventional ADC. It is a schematic diagram for demonstrating the conventional analog-digital conversion.

Explanation of symbols

1 ADC
3 DAC
DESCRIPTION OF SYMBOLS 4 Comparator 5 Counter 8 Memory 11 Photoelectric conversion element 12 Transfer transistor 13 Reset transistor 14 Amplification transistor 15 Selection transistor 16 FD part 17 Transfer control line 18 Reset control line 19 Selection control line 21 Pixel 22 Pixel array part 23 Vertical scanning circuit 24 Column signal Processing unit 25 Horizontal signal line 26 Horizontal scanning circuit 30 Vertical signal line 31 Constant current source

Claims (11)

Generates a down-count reference signal with a voltage value that is a predetermined voltage higher than the voltage value of the analog signal indicating the maximum voltage value among the plurality of analog signals converted into digital signals at the previous timing. Or, an up-count reference signal in which a voltage value that is smaller by a predetermined voltage than a voltage value of an analog signal indicating the minimum voltage value among a plurality of analog signals converted into a digital signal at the previous timing is an initial voltage value A reference signal generation unit for generating
A voltage value of an analog signal provided corresponding to each analog signal converted into a digital signal and converted into a digital signal at a later timing, and a voltage value of the reference signal generated by the reference signal generation unit A comparison section to compare;
An analog-digital converter comprising: a counter that counts a count value when the comparison processing by the comparison unit is completed. The reference signal generation unit generates a down-count reference signal from the maximum voltage value of the reference signal generation unit when the comparison process by the comparison unit is not completed even when the down-count reference signal reaches a minimum voltage value. Alternatively, if the comparison process by the comparison unit is not completed even when the up-count reference signal reaches a maximum voltage value, the up-count reference signal is generated from the minimum voltage value of the reference signal generation unit. The analog-digital converter according to 1. Among the plurality of analog signals converted into digital signals at the previous timing, the voltage value of the analog signal indicating the maximum voltage value is stored as the maximum voltage value, or the plurality of analog signals converted into digital signals at the previous timing Among analog signals, voltage value storage means for storing the voltage value of the analog signal indicating the minimum voltage value as the minimum voltage value;
A reference signal for down-counting with a voltage value that is larger than the maximum voltage value stored in the voltage value storage means by a predetermined voltage as an initial voltage value is generated, or the minimum voltage stored in the voltage value storage means A reference signal generation unit that generates an up-count reference signal with a voltage value smaller than the value by a predetermined voltage as an initial voltage value;
A voltage value of an analog signal provided corresponding to each analog signal converted into a digital signal and converted into a digital signal at a later timing, and a voltage value of the reference signal generated by the reference signal generation unit A comparison section to compare;
An analog-digital converter comprising: a counter that counts a count value when the comparison processing by the comparison unit is completed. Among the plurality of analog signals converted into digital signals at the previous timing, a voltage value that is larger than the voltage value of the analog signal indicating the maximum voltage value by a predetermined voltage is stored as the maximum voltage value, or at the previous timing Voltage value storage means for storing, as a minimum voltage value, a voltage value smaller than a voltage value of an analog signal indicating a minimum voltage value among a plurality of analog signals converted into a digital signal by a predetermined voltage;
Generate a down-count reference signal with the maximum voltage value stored in the voltage value storage means as an initial voltage value, or increase the minimum voltage value stored in the voltage value storage means as an initial voltage value A reference signal generator for generating a reference signal for counting;
A voltage value of an analog signal provided corresponding to each analog signal converted into a digital signal and converted into a digital signal at a later timing, and a voltage value of the reference signal generated by the reference signal generation unit A comparison section to compare;
An analog-digital converter comprising: a counter that counts a count value when the comparison processing by the comparison unit is completed. Generates a down-count reference signal with a voltage value that is a predetermined voltage higher than the voltage value of the analog signal indicating the maximum voltage value among the plurality of analog signals converted into digital signals at the previous timing. Or, an up-count reference signal in which a voltage value that is smaller by a predetermined voltage than a voltage value of an analog signal indicating the minimum voltage value among a plurality of analog signals converted into a digital signal at the previous timing is an initial voltage value A reference signal generation step for generating
A comparison step of comparing a voltage value of an analog signal converted into a digital signal at a later timing with a reference signal generated in the reference signal generation step;
A count counting step of counting a count value at the time when the comparison step is completed. A pixel array unit in which pixels that accumulate analog signals corresponding to incident light are arranged in a matrix;
Down-count reference with an initial voltage value that is larger than the voltage value of the analog signal indicating the maximum voltage value among the analog signals generated by a plurality of pixels that have been read out at the previous timing. A voltage value that is smaller than the voltage value of the analog signal indicating the minimum voltage value among the analog signals generated by a plurality of pixels that have generated signals or read at the previous timing by an initial voltage. A reference signal generation unit for generating a reference signal of an upcount as a value;
A voltage value of an analog signal that is provided corresponding to each pixel to be read and is generated at a later timing and a voltage value of a reference signal that is generated by the reference signal generation unit A comparison unit for comparing
An imaging apparatus comprising: a counter that counts a count value when the comparison processing by the comparison unit is completed. A pixel array unit in which pixels that accumulate analog signals corresponding to incident light are arranged in a matrix;
Among analog signals generated by a plurality of pixels that have been read out at the previous timing, the voltage value of the analog signal indicating the maximum voltage value is stored as the maximum voltage value, or read out at the previous timing. Voltage value storage means for storing the voltage value of the analog signal indicating the minimum voltage value among the analog signals generated by the plurality of pixels as the minimum voltage value;
A reference signal for down-counting with a voltage value that is larger than the maximum voltage value stored in the voltage value storage means by a predetermined voltage as an initial voltage value is generated, or the minimum voltage stored in the voltage value storage means A reference signal generation unit that generates an up-count reference signal with a voltage value smaller than the value by a predetermined voltage as an initial voltage value;
A voltage value of an analog signal that is provided corresponding to each pixel to be read and is generated at a later timing and a voltage value of a reference signal that is generated by the reference signal generation unit A comparison unit for comparing
An imaging apparatus comprising: a counter that counts a count value when the comparison processing by the comparison unit is completed. A pixel array unit in which pixels that accumulate analog signals corresponding to incident light are arranged in a matrix;
Among analog signals generated by a plurality of pixels that have been read out at the previous timing, store a voltage value that is larger than the voltage value of the analog signal indicating the maximum voltage value by a predetermined voltage as the maximum voltage value, or Voltage value storage that stores, as a minimum voltage value, a voltage value that is smaller than a voltage value of an analog signal indicating the minimum voltage value by a predetermined voltage among the analog signals generated by a plurality of pixels that have been read out at the previous timing. Means,
Generate a down-count reference signal with the maximum voltage value stored in the voltage value storage means as an initial voltage value, or increase the minimum voltage value stored in the voltage value storage means as an initial voltage value A reference signal generator for generating a reference signal for counting;
A voltage value of an analog signal that is provided corresponding to each pixel to be read and is generated at a later timing and a voltage value of a reference signal that is generated by the reference signal generation unit A comparison unit for comparing
An imaging apparatus comprising: a counter that counts a count value when the comparison processing by the comparison unit is completed. The imaging device according to claim 6, 7 or 8, wherein a pixel that has been read at a later timing is adjacent to a pixel that has been read at a previous timing. The imaging device according to claim 6, 7, or 8, wherein the pixel that has been read at the previous timing and the pixel that has been read at the later timing are the same pixel. An accumulation step of accumulating analog signals according to incident light in pixels arranged in a matrix;
Down-count reference with an initial voltage value that is larger than the voltage value of the analog signal indicating the maximum voltage value among the analog signals generated by a plurality of pixels that have been read out at the previous timing. A voltage value that is smaller than the voltage value of the analog signal indicating the minimum voltage value among the analog signals generated by a plurality of pixels that have generated signals or read at the previous timing by an initial voltage. A reference signal generation step of generating a reference signal of upcount as a value;
A comparison step of comparing a voltage value of an analog signal generated in a pixel read out at a later timing with a reference signal generated in the reference signal generation step;
And a count counting step of counting a count value at the time when the comparison step is completed.

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