JP2020028117A - Solid-state imaging device - Google Patents

Abstract

To prevent the blackening phenomenon of an image while reducing the circuit scale.SOLUTION: A solid-state imaging device includes a comparator circuit (31) that determines whether a reset potential is higher or lower than a specific reference potential among two different potentials of a reset potential and a signal potential in a pixel read potential, and a latch circuit (32) that holds the determination result of the comparator circuit (31).SELECTED DRAWING: Figure 2

Description

  The present invention relates to a solid-state imaging device such as a CMOS (complementary metal oxide semiconductor) image sensor.

  A conventional CMOS image sensor has a floating diffusion layer and an amplifier for each pixel arranged in a matrix. As the output of the CMOS image sensor, a column-parallel output type in which one row in a pixel array is selected and simultaneously read in a column direction is mainly used. The output read in the column direction is converted into a digital signal by an analog-to-digital converter for each column.

  2. Description of the Related Art Various types of analog-to-digital converters mounted on a column parallel output type CMOS image sensor have conventionally been proposed. Among them, an analog-to-digital converter having a configuration realizing low noise characteristics by performing analog-to-digital conversion on the two data after the initial state and after the signal accumulation and performing a subtraction process (digital CDS (correlated double sampling)) on each of them. Mainstream.

  CDS is a method in which a difference between a reset state (initialized state) of a pixel and a signal state of a state where light is input to the pixel is used to cancel variation for each pixel and extract only a component input to the pixel. is there. However, when intense light such as sunlight is input to the solid-state imaging device, the element isolation state between pixels cannot be maintained, and as a result, the reset state becomes abnormal. Since the reset state becomes abnormal, the difference between the reset state and the signal state does not give a correct result. In the case of intense light such as sunlight, the white output of the image is erroneously output as the black output (image Blackening phenomenon).

  Patent Document 1 discloses that a reset voltage during a no-signal period is detected to determine whether or not an ultra-high light quantity (when intense light is input), and only when an ultra-high light quantity is used, the no-signal voltage is replaced or before the voltage drops. There is disclosed a solid-state imaging device that clips a voltage and uses the reset voltage as a reset voltage to prevent a blackening phenomenon of an image that has occurred when a light amount is extremely large.

Japanese Patent Application Laid-Open No. 2000-287131 (released on October 13, 2000)

  However, the conventional technique requires a pulse synthesizer, a selector, a voltage generator, and the like at a stage subsequent to the comparator, and has a problem that the circuit scale becomes large.

  One embodiment of the present invention has been made in view of the above problems, and has as its object to realize a solid-state imaging device capable of preventing a blackening phenomenon of an image while reducing a circuit scale. .

  (1) One embodiment of the present invention is a solid-state imaging device including an A / D conversion circuit that performs analog-to-digital conversion of a potential obtained by a pixel reading operation. A solid-state imaging device comprising: a determination circuit that determines whether the reset potential is higher or lower than a specific reference potential; and a latch circuit that holds a determination result of the determination circuit.

  (2) In one embodiment of the present invention, in addition to the configuration of (1), a potential drop that prevents the reset potential from becoming lower than the specific reference potential according to an output result of the latch circuit. A solid-state image sensor having a prevention circuit.

  (3) In one embodiment of the present invention, in addition to the configuration of (1), a specific digital code is output according to the output result of the latch circuit regardless of the output result of the A / D conversion circuit. A solid-state imaging device having a post-processing logic circuit for outputting.

  (4) In one embodiment of the present invention, in addition to the configuration of (2), the determination circuit includes a comparator circuit that compares the reset potential with the specific reference potential, and the potential drop prevention circuit Is a solid-state imaging device including a field-effect transistor.

  One embodiment of the present invention has an effect that blackening of an image can be prevented while a circuit size is reduced.

1 is a circuit diagram illustrating a schematic configuration of a solid-state imaging device according to an embodiment of the present invention. FIG. 3 is a circuit diagram illustrating an example (Embodiment 1) of a sun black determination circuit provided in the solid-state imaging device. It is a circuit diagram showing another example (Embodiment 2) of the sun blackening determination circuit. FIG. 3 is a circuit diagram illustrating an example of a specific configuration of a latch circuit included in the sun black determination circuit. 6 is a timing chart showing a change in output voltage of each signal line from reception of light to reading of electric charges in the operation of the solid-state imaging device. FIG. 3 is a diagram illustrating a general four-transistor configuration (selectable type) as an example of a pixel configuration. It is a figure which shows the selectless type pixel structure as another example of a pixel structure.

  An embodiment according to the present invention will be described below with reference to FIGS.

[Configuration of solid-state imaging device 1]
FIG. 1 is a circuit diagram showing a schematic configuration of a solid-state imaging device 1 on which an analog-to-digital converter according to an embodiment of the present invention is mounted. As shown in FIG. 1, the solid-state imaging device 1 includes a pixel unit 2, a row selection circuit 3, sun black determination circuits 3a and 3b, a constant current circuit 4, an AD converter (analog-digital converter; A / D conversion circuit). 6, a column selection circuit 7, and a sensor amplifier 72. The pixel unit 2 includes a plurality of unit pixels 21 arranged in a matrix. In addition, the AD converter 6 includes a plurality of comparators (for ADC) 61 and a counter circuit / latch circuit 63.

  The row selection circuit 3 outputs a selection signal for selecting any one row of the unit pixels 21 to the pixel unit 2. Each unit pixel 21 to which the selection signal is input converts the incident light into an analog signal, and transfers the analog signal to the corresponding AD converter 6 through the corresponding vertical signal line 22. Note that the horizontal signal lines are composed of three lines of an RST line, a TX line, and a VR line, and each of the three lines is connected to the row selection circuit 3, but is not shown in FIG. I have.

  The sun black determination circuits 3a and 3b are circuits that determine whether or not an image blackening phenomenon occurs, and execute processing for preventing the image blackening phenomenon when the image blackening phenomenon occurs. The details of the sun black determination circuits 3a and 3b will be described later.

  The comparator 61 compares the voltage of the input analog signal with a ramp voltage (RAMP) whose voltage value changes in accordance with the reference clock, and outputs the output signal when the ramp voltage exceeds the analog signal voltage. Turn it over.

  The counter / latch circuit 63 latches digital data corresponding to the counter data, triggered by the time when the output of the comparator 61 is inverted. The counter / latch circuit 63 stops counting the counter data, triggered by the output of the comparator 61 being inverted again.

  Each of the AD converters 6 performs analog-to-digital conversion of a potential obtained by a pixel read operation. Specifically, the AD converter 6 converts the input analog signal into a digital signal and outputs the digital signal to the sensor amplifier 72 through a horizontal signal line. Note that there are two different pixel read potentials, a reset potential and a signal potential.

  In the solid-state imaging device 1 illustrated in FIG. 1, each AD converter 6 is arranged for one column (one column) of the pixel unit 2. However, the arrangement of the AD converter 6 is not limited to this. The AD converter 6 can be arranged for at least one column or at least one unit pixel 21. In other words, the AD converters 6 can be arranged for each unit pixel 21 or for each of the plurality of unit pixels 21, and the plurality of unit pixels 21 corresponding to each AD converter 6 are all A combination of an arbitrary number of unit pixels 21 selected from the unit pixels 21 may be used.

  The column selection circuit 7 selects any one of the unit pixels 21 included in any one of the plurality of columns. In the example shown in FIG. 1, the column selection circuit 7 is a circuit that selects at least one AD converter 6. If the AD converter 6 is arranged for each unit pixel 21, a pixel selection circuit for individually selecting one unit pixel 21 is provided instead of the column selection circuit 7.

[Embodiment 1: Regarding the sun black determination circuit 3a]
FIG. 2 shows a circuit diagram of a sun blackening determination circuit 3a which is an example of the sun blackening determination circuit included in the solid-state imaging device 1. As shown in the figure, the sun black determination circuit 3a of the present embodiment includes a comparator circuit (determination circuit) 31, a latch circuit 32, and an FET (field effect transistor; potential drop prevention circuit) 33.

  The comparator circuit 31 compares the pixel reset signal potential (reset potential) with the RefV potential (reference potential) to determine whether the pixel reset signal potential is abnormal. Specifically, when the pixel reset signal potential is higher than the RefV potential, it is determined that the pixel reset signal is normal. This is because the pixel reset signal potential becomes a potential determined by the pixel power supply and the threshold potential of the reset transistor in a normal state, whereas the potential drops as a saturation signal is output from the pixel in an abnormal state. .

  As described above, by determining whether the pixel reset signal potential is higher or lower than the RefV potential, the comparator circuit 31 can determine whether an image blackening phenomenon occurs.

  The latch circuit 32 holds the determination result of the comparator circuit 31, and controls the gate of the FET 33 according to the determination result during the sampling period of the pixel reset signal potential. As described above, since the latch circuit 32 holds the determination result of the comparator circuit 31, it is possible to store the determination result of whether or not the image blackening phenomenon occurs.

  In the configuration of FIG. 2, the latch circuit 32 does not output a specific digital code, but holds a determination result as to whether or not an image blackening phenomenon occurs. Control the gate. Thus, when the blackening phenomenon of the image is detected, the blackening phenomenon of the image can be prevented by replacing the lowered pixel reset signal potential with the pixel power supply.

  The FET 33 prevents the pixel reset signal potential from becoming lower than the RefV potential according to the output result of the latch circuit 32. More specifically, the FET 33 is controlled in accordance with the gate voltage input based on the determination result held in the latch circuit 32.

  When the determination result held in the latch circuit 32 is normal, the operation of the FET 33 is turned off. On the other hand, when the determination result held in the latch circuit 32 is abnormal, the pixel signal line is driven so as to be suspended from the pixel power supply, thereby preventing the pixel reset signal potential from lowering.

  More specifically, when the blackening phenomenon occurs (the pixel reset signal potential falls below the determination potential RefV), the gate potential of the FET 33 becomes HIGH and the FET 33 turns on. (The source potential of the FET 33).

  As a result, the potential sampled during the sampling period of the pixel reset signal potential becomes the pixel power supply potential (potential higher than the pixel reset signal potential), and the potential sampled during the next sampling period of the pixel signal signal potential becomes the pixel saturation. Therefore, the difference potential between the two signal potentials obtained by the analog CDS becomes equal to or higher than the pixel saturation potential, and the occurrence of blackening of an image can be prevented (a white output is output as an image).

  Conversely, when the blackening phenomenon does not occur (normal), the gate potential of the FET 33 becomes Low and the FET 33 turns off. Therefore, during the sampling period of the pixel reset signal potential, a normal potential corresponding to the pixel reset potential is sampled. (Does not interfere with normal operation).

  As described above, by preventing the reset potential from being lower than the specific reference potential by the FET 33, the blackening phenomenon of the image can be prevented. Thus, the blackening phenomenon of the image can be prevented while reducing the circuit scale. In addition, as a connection destination candidate of the source terminal of the FET 33, a pixel power supply (a power supply regulated for the pixel), a specific reference voltage, an analog power supply, and the like can be exemplified.

[Embodiment 2: Regarding the sun black determination circuit 3b]
FIG. 3 shows a circuit diagram of a sun blackening determination circuit 3b which is an example of the sun blackening determination circuit provided in the solid-state imaging device 1. As shown in the figure, the sun black determination circuit 3b of the present embodiment includes a comparator circuit (determination circuit) 31, a latch circuit 32, and a post-processing logic circuit (potential drop prevention circuit) 37.

  The sun blackening determination circuit 3b according to the present embodiment determines whether the post-processing logic circuit 37 outputs an AD conversion result according to the determination result of the blackening phenomenon, or outputs the AD conversion result by replacing it with a full code. The control is different from the sun black determination circuit 3a of the first embodiment in control.

  Specifically, the comparator circuit 31 detects whether or not the pixel reset signal potential is lower than the RefV potential, holds the determination result in the latch circuit 32, and outputs the result to the post-processing logic circuit 37.

  The post-processing logic circuit 37 outputs the output result (AD conversion result 36) of the AD converter 6 according to the output of the pixel signal line when normal (when the output of the latch circuit 32 is High), When the output of the circuit 32 is Low), a process of outputting a full code irrespective of the AD conversion result 36 is performed, thereby preventing the occurrence of the blackening phenomenon.

  The output result of the latch circuit 32 has been described as a High output in a normal state and a Low output in an abnormal state based on the example of the circuit configuration in FIG. 4. It is also possible to determine the blackening phenomenon as a High output at the time of abnormality. Thus, the blackening phenomenon of the image can be prevented while reducing the circuit scale.

(About the latch circuit 32)
Next, the configuration of the latch circuit 32 will be described with reference to FIG. As shown in the figure, the latch circuit 32 includes an inverter circuit 321, a clocked inverter circuit 323, and a CMOS switch 322. The inverter circuit 321 is a circuit that inverts the positive / negative of the input signal, amplifies and outputs the inverted signal.

  The clocked inverter circuit 323 is an inverter circuit whose ON / OFF is controlled by the LATIN_EN signal and the XLATIN_EN signal. It has a circuit configuration in which the output of the inverter circuit 321 and the output of the clocked inverter circuit 323 are connected to the input of each other. Switch whether to keep the output result of.

  Specifically, when the LATIN_EN signal is High (the XLATIN_EN signal is Low), the output of the comparator circuit 31 is enabled and the clocked inverter circuit 323 is turned off, so that the inverter circuit 321 inverts the output of the comparator circuit 31. Perform output.

  On the other hand, when the LATIN_EN signal is Low (the XLATIN_EN signal is High), the output of the comparator circuit 31 becomes invalid (open state), and the clocked inverter circuit 323 is turned on, so the inverter circuit 321 switches the LATIN_EN signal to Low. Keep previous output.

  The CMOS switch 322 controls, based on the BSUN_EN signal, whether or not to enable the output of the result of the sun black determination by the comparator circuit 31. Only during the period when the BSUN_EN signal is High, an output (normal: High, or abnormal: Low) is output from the latch circuit in accordance with the result of the sun black determination. In addition, the output is fixed to High while the BSUN_EN signal is Low.

  FIG. 5 is a waveform chart (timing chart) showing changes in the voltage waveforms of the four types of wirings (RST wiring, VR wiring, TX wiring, LATIN_EN wiring, and BSUN_EN wiring) and the voltage VSIG of the vertical signal line 22. .

  As shown in the figure, when it is determined that the reset potential is lower than a specific reference potential during the solar blackening determination period (when solar blackening occurs), the pixel signal line is driven to be suspended from the pixel power supply. .

  Next, a four-transistor configuration (selectable type) will be described with reference to FIG. The pixel 12a is a unit pixel of a CMOS (Complementary Metal Oxide Semiconductor) image sensor including four transistors. The pixel 12a corresponds to the unit pixel 21 described above.

  The pixel 12a has, for example, a photodiode 200 as a photoelectric conversion element.

  The pixel 12a has four active transistors for one photodiode 200: a transfer transistor 201 as a transfer element, a reset transistor 202 as a reset element, an amplification transistor 203, and a selection transistor 204.

  The photodiode 200 photoelectrically converts incident light into electric charges (here, electrons) in an amount corresponding to the light amount.

  The transfer transistor 201 is connected between the photodiode 200 and a floating diffusion FD as an output node.

  The transfer transistor 201 transfers the electrons photoelectrically converted by the photodiode 200, which is a photoelectric conversion element, to the floating diffusion FD when the drive signal TX is applied to the gate (transfer gate) of the transfer transistor LTx through the transfer control line LTx.

  The reset transistor 202 is connected between the power supply line PVDD and the floating diffusion FD.

  The reset transistor 202 resets the potential of the floating diffusion FD to the potential of the power supply line PVDD by receiving the reset RST at its gate through the reset control line LRST.

  The gate of the amplification transistor 203 is connected to the floating diffusion FD. The amplification transistor 203 is connected to the pixel signal line 205 via the selection transistor 204, and forms a source follower with a constant current source outside the pixel unit.

  Then, a control signal (address signal or select signal) SEL is supplied to the gate of the selection transistor 204 through the selection control line LSEL, and the selection transistor 204 is turned on.

  When the selection transistor 204 is turned on, the amplification transistor 203 amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the potential to the pixel signal line 205. The voltage output from each pixel via the pixel signal line 205 is output to a column ADC as a pixel signal reading unit.

  These operations are performed simultaneously and in parallel for each row of pixels because, for example, the gates of the transfer transistor 201, the reset transistor 202, and the selection transistor 204 are connected in units of rows. FIG. 7 shows a selectless pixel structure as another example of the pixel structure. The pixel configuration shown in FIG. 7 is different from the pixel configuration shown in FIG. 6 in that the selection transistor 204 is not provided. The pixel configurations shown in FIGS. 6 and 7 are merely examples, and the image configurations are not limited to these examples.

[Summary]
A solid-state imaging device according to an aspect 1 of the present invention is a solid-state imaging device including an A / D conversion circuit that performs analog-to-digital conversion of a potential by a pixel read operation, and has two different readout potentials, a reset potential and a signal potential. A determination circuit that determines whether the reset potential is higher or lower than a specific reference potential, and a latch circuit that holds a determination result of the determination circuit.

  According to the configuration, the determination circuit determines whether the reset potential is higher or lower than the specific reference potential, thereby determining whether or not an image blackening phenomenon occurs. Since the latch circuit holds the determination result of the determination circuit, the determination result as to whether or not the image blackening phenomenon occurs can be stored. This makes it possible to prevent the blackening phenomenon of the image while reducing the circuit scale.

  The solid-state imaging device according to a second aspect of the present invention, in the first aspect, further includes a potential drop prevention circuit that prevents the reset potential from being lower than the specific reference potential according to an output result of the latch circuit. Is preferred.

  According to the above configuration, the blackening phenomenon of the image can be prevented by preventing the reset potential from being lower than the specific reference potential by the potential drop prevention circuit.

  The solid-state imaging device according to a third aspect of the present invention, in the first aspect, wherein the post-processing logic outputs a specific digital code according to the output result of the latch circuit regardless of the output result of the A / D conversion circuit. A circuit may be mounted. According to the above configuration, it is possible to prevent an image from being blackened due to sun blackening.

  In the solid-state imaging device according to a fourth aspect of the present invention, in the second aspect, the determination circuit includes a comparator circuit that compares the reset potential with the specific reference potential, and the potential drop prevention circuit includes a field-effect transistor May be included.

  According to the configuration, it is possible to prevent the blackening phenomenon of the image by preventing the reset potential from being lower than the specific reference potential by the field effect transistor.

[Appendix]
The present invention is not limited to the embodiments described above, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention. Furthermore, new technical features can be formed by combining the technical means disclosed in each embodiment.

DESCRIPTION OF SYMBOLS 1 Solid-state image sensor 2 Pixel part 3 Row selection circuit 3a, 3b Sun black determination circuit 4 Constant current circuit 6 AD converter (A / D conversion circuit)
7 Column selection circuit 21 Unit pixel 22 Vertical signal line 31 Comparator circuit 32 Latch circuit 33 FET (potential drop prevention circuit)
37 Post-processing logic circuit (potential drop prevention circuit)
61 Comparator 63 Counter circuit / Latch circuit 72 Sensor amplifier

Claims (4)

A solid-state imaging device including an A / D conversion circuit that performs analog-to-digital conversion of a potential by a pixel read operation,
The pixel readout potential has two different potentials, a reset potential and a signal potential,
A determination circuit that determines whether the reset potential is higher or lower than a specific reference potential,
And a latch circuit for holding a determination result of the determination circuit.   2. The solid-state imaging device according to claim 1, further comprising a potential drop prevention circuit that prevents the reset potential from being lower than the specific reference potential according to an output result of the latch circuit. 3.   The solid-state imaging device according to claim 1, further comprising a post-processing logic circuit that outputs a specific digital code according to an output result of the latch circuit, regardless of an output result of the A / D conversion circuit. .   3. The solid-state imaging device according to claim 2, wherein the determination circuit includes a comparator circuit that compares the reset potential with the specific reference potential, and the potential reduction prevention circuit includes a field-effect transistor.

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