WO2012026097A1 - Solid-state imaging device and imaging system - Google Patents

Abstract

One embodiment of this solid-state imaging device and imaging system comprises: a plurality of pixels arranged in a matrix; and UD counters (117) that are provided correspondingly to each column of the plurality of pixels or to each of a plurality of columns, and that count up and down. Said solid-state imaging device is provided with: a column A/D conversion circuit (106) that controls the counting by the UD counters (117), and converts analog signals from the corresponding pixels to digital signals; a reset signal level distribution acquisition circuit (119) that acquires distribution information representing the distribution of pixel reset signal levels for the plurality of pixels that have undergone A/D conversion by the column A/D conversion circuit (106); and a control unit (116)that alters various assigned count ranges in order to count the pixel reset levels and the pixel signal levels in counter bit widths that are predefined for the UD counters (117) on the basis of the acquired distribution information.

Description

Solid-state imaging device and imaging system

The present invention relates to a solid-state imaging device and an imaging system.

Development and use of MOS (Metal Oxide Semiconductor) type image sensors (hereinafter referred to as “MOS sensors”) as well as CCDs (Charge Coupled Devices) as key devices that play the role of “eye” in digital cameras and video cameras. It is widespread. Unlike a CCD sensor manufactured using a special semiconductor process, the MOS sensor can be manufactured using a general-purpose semiconductor process. Therefore, one feature of the MOS sensor is that it has a usability that allows a timing control circuit and an analog or digital signal processing circuit to be mounted (that is, mixed) on the same semiconductor chip.

In recent years, in a MOS sensor, both CDS (Correlated Double Sampling) processing and A / D (Analog / Digital) conversion, which are indispensable after signal output from a pixel, take advantage of the mixed loading that is the feature of both, Technological development is being carried out so that it can be performed on the same chip as the MOS sensor. Here, the CDS processing means reading out a pixel signal level and a reset signal level from the same pixel, and subtracting the reset signal level from the pixel signal level, thereby removing a true pixel signal level that excludes an offset of a readout voltage that differs for each pixel. It is processing for taking out.

In addition, since the miniaturization of semiconductor processes directly contributes to the advancement of digital circuit technology, there is also a technological trend of performing processing that was performed in the analog domain as much as possible in the digital domain.

In such a background, a column ADC circuit technique in which CDS processing conventionally performed in the analog domain is performed in accordance with A / D conversion is disclosed (for example, Patent Document 1 and Patent Document 2). . Hereinafter, as an example, a column ADC circuit disclosed in Patent Document 1 will be described.

FIG. 12 is a diagram illustrating a configuration of a solid-state imaging device including a column A / D conversion circuit disclosed in Patent Document 1. In FIG.

The solid-state imaging device 920 includes a row scanning unit 914, a plurality of pixels 930 including a light receiving element that outputs a signal corresponding to the amount of incident light, a column scanning unit 946, an up counter 950, and a column A / D conversion circuit 940. And a DAC (Digital Analog Converter) circuit 960. The column A / D conversion circuit 940 includes a comparison circuit 942 and an up / down counter 944.

The column A / D conversion circuit 940 operates by a method called lamp type A / D conversion. Specifically, a reference potential (VREF) called a monotonically increasing or monotonically decreasing ramp wave generated from the DAC circuit 960 is compared with a signal potential 915 read from the pixel 930 by a comparison circuit 942 provided in each column. To do. Then, the up-down counter 944 of each column measures the time from the reference potential sweep start timing to the pixel signal potential and reference potential matching timing. The column A / D conversion circuit 940 particularly switches from the operation of A / D converting the “reset signal level” read from the pixel 930 to the operation of A / D converting the pixel signal potential of the “pixel signal level”. At this time, it is characterized in that subtraction can be realized simultaneously with A / D conversion by changing the counting direction while holding the counter value indicating the pixel signal potential at the reset signal level.

Here, in the solid-state imaging device 920, the pixel signal potential of “reset signal level” and the pixel signal potential of “pixel signal level” are read from each pixel 930, and the “reset signal level” is calculated from the pixel signal potential of “pixel signal level”. The process of subtracting the pixel signal potential of “true” to extract the pixel signal potential of “true pixel signal level” is called correlated double sampling (CDS). A method of digitally performing this processing (CDS) is called digital CDS more limitedly. The subtraction by the counter described above is one method for realizing this digital CDS.

US Pat. No. 5,877,715 JP 2005-323331 A

However, when digital CDS is realized by the above-described conventional technology, there are some problems described below.

Hereinafter, this will be described with reference to FIG. FIG. 13 is a timing diagram for explaining an A / D conversion operation using a conventional solid-state imaging device. FIG. 13 shows operation waveforms of the column A / D conversion circuit 940. The upper vertical axis indicates the A / D conversion signal output (digital value), and the lower vertical axis indicates the A / D conversion input potential (analog). The horizontal axis shows time in both the upper and lower stages.

Here, the counter bit width used in each column, that is, in each column A / D conversion circuit 940 is fixed. For example, if the counter bit width is 10 bits, the column A / D conversion circuit 940 (up / down counter 944) can represent 1024 values. In the column A / D conversion circuit 940 (up / down counter 944), the counter value in this range is changed from the negative minimum value for down counting corresponding to the reset signal level range to the positive maximum value for up counting. Will cover.

That is, for example, the default value of the up / down counter 944 is set to zero, and the down count is set to 128 corresponding to the variation in the reset signal level. Then, as shown in FIG. 13, since the minus side minimum value is −128, the plus side maximum is +895, and the plus side maximum, that is, the digital value used in the A / D conversion output is reduced compared to 1024. Become. This is not a problem that occurs only in the column A / D conversion circuit 940 including the up / down counter 944, but is a problem of range reduction common to the digital CDS (first D range reduction problem).

Also, the column A / D conversion circuit 940, that is, the column A / D conversion circuit 940 including the up / down counter 944 for each column performs digital CDS. However, when up-counting is performed in order to A / D convert the pixel signal level, there is an effect of variations in the result of A / D conversion of the preceding reset signal level. Specifically, as shown in FIG. 13, when the column A / D conversion circuit 940 performs up-counting for A / D conversion of the pixel signal level, the timing at which the counter value changes between CV_Rmax and CV_Rmin. It can be seen that variations occur in the columns (for each column A / D conversion circuit 940). This is because, even if all columns (column A / D conversion circuit 940) have the same “true pixel signal level”, the up / down counter 944 of each column reaches the value of the true pixel signal level. This means that the timing will vary.

For example, consider a case where the reset signal level is the lowest (CV_Rmin) in the predetermined pixel 930. In that case, in the column A / D conversion circuit 940 corresponding to the predetermined pixel 930, the up count number of the up / down counter 944 needs to be set to 895 in order to stop the maximum value in the up count at the above-described +895. On the other hand, the case where the reset signal level is the highest (CV_Rmax) in another pixel 930 is considered. In that case, in the column A / D conversion circuit 940 corresponding to another pixel 930, even if the pixel signal level of the pixel has reached the saturation level, that is, until the end is detected by comparing the ramp wave with the pixel signal. Even if the timing does not come, since the maximum number of upcounts is 895, the value of “true pixel signal level” is 895−128 = 767.

Therefore, when the pixel signal level is saturated, if no processing is performed, the “true pixel signal level” varies from 767 to 895 corresponding to the variation in the reset signal level. .

Then, for example, the pixel 930 at a location that should be saturated in the image, such as a location that should be completely white, has a high reset signal level. The value of the pixel signal level at which the pixel is saturated is insufficient, resulting in coloration and deterioration of image quality. For this reason, it is necessary to perform saturation level slicing on the value after A / D conversion (all pixel signals having values of 767 to 895 are set to 767).

That is, if the reset signal level range is secured to 1/8 of the entire output bit width range of A / D conversion including CDS operation, the range corresponding to the variation of the saturation level is also 1/8. Since this (range corresponding to the variation in saturation level) needs to be cut, the effective D range that can actually be used is cut to 3/4.

In view of the above, it is clear that the narrower the range of the reset signal level, the better. However, in actual products, variations in the reset signal level inevitably increase due to variations in process, power supply voltage, and temperature (PVT). If the variation exceeds the A / D conversion range of the reset signal level, the digital CDS does not operate correctly, causing vertical stripes in the image and greatly degrading the image quality. In other words, since the A / D conversion range (reset level Rres) of the reset signal level needs to be sufficiently wider than the variation including the PVT, there is a problem that the effective D range (effective output range Reff) is reduced ( There is also a problem of the second D range reduction. This problem is specific to the case where the digital CDS is realized by the up / down counter of the column A / D conversion circuit.

Also, this A / D conversion of the reset signal level is one factor that increases the A / D conversion period, and hinders the speeding up of the A / D conversion. Therefore, this is an obstacle to increasing the frame rate of the solid-state imaging device 920. In particular, in the column A / D conversion circuit 940 provided with the up / down counter 944, in addition to the period for converting the same effective D range as in the case where the up / down counter 944 is not provided, the conversion is twice as long as the period for down-counting. Since a period is required, there is another problem that the A / D conversion period becomes longer.

The present invention has been made in view of the above circumstances, and provides a high-speed solid-state imaging device and imaging system having high pixel signal level bit accuracy and high speed without changing the hardware configuration of the column A / D conversion circuit. The purpose is to provide.

In order to solve the above problems, a solid-state imaging device according to an aspect of the present invention is a solid-state imaging device including a plurality of pixels arranged in a matrix, and corresponds to each column or each column of the plurality of pixels. And an up / down counter that counts in the up-count direction and the down-count direction, and the analog signal output from the corresponding pixel is A / D converted into a digital signal by causing the up / down counter to count. An A / D conversion unit, a distribution information acquisition unit that acquires distribution information indicating a distribution of pixel reset signal levels of a plurality of pixels A / D converted by the column A / D conversion unit, and the distribution information acquisition unit Based on the acquired distribution information, a pixel reset signal level and a predetermined counter bit width of the up / down counter are set. And a control unit for changing the respective count range assigned to count fine pixel signal level.

According to this configuration, the distribution of the reset signal level is determined during operation, and the A / D conversion range assigned to the reset signal level and the pixel signal level can be optimized. As a result, a high-speed solid-state imaging device with high pixel signal level bit accuracy can be realized without changing the hardware configuration of the column A / D conversion circuit.

Further, the solid-state imaging device changes the count direction of the up / down counter for each pixel in each row, thereby giving the difference value between the pixel signal level and the pixel reset signal level to the column A / D converter. A pixel signal output mode in which the output is performed by / D conversion, and a pixel reset output mode in which only the pixel reset signal level is A / D converted and output by the column A / D conversion unit for each pixel in each row. It may be.

The distribution information acquisition unit includes pixel reset signal levels of the plurality of pixels and partial pixels of the plurality of pixels that are A / D converted by the column A / D conversion unit based on the count range. By acquiring a reset signal level of a reference pixel, first distribution information indicating a distribution of pixel reset signal levels of a plurality of pixels A / D converted by the column A / D converter is acquired, and the count range The reference pixel A / D-converted by the column A / D converter by further acquiring the reset signal level of only the reference pixel A / D-converted by the column A / D converter based on 2nd distribution information indicating only the reset signal level distribution is acquired, and the control unit changes the count range from the first distribution information and the second distribution information, and the solid-state imaging Location, based on the changed count range by the control unit, and a pixel reset signal level and the pixel signal level of a plurality of pixels in the column A / D converter may be converted A / D.

Further, the distribution information acquisition unit includes a maximum value and a minimum value of reset signal levels of the plurality of pixels that have been A / D converted by the column A / D conversion unit, and an A / D conversion unit that performs A / D conversion. The plurality of pixels subjected to A / D conversion by the column A / D conversion unit by obtaining a maximum value and a minimum value of a reset signal level of a reference pixel that is a part of the plurality of pixels subjected to D conversion The distribution information indicating the distribution of the pixel reset signal level may be acquired.

In addition, the distribution information acquisition unit includes an average value and standard deviation of reset signal levels of the plurality of pixels that have been A / D converted by the column A / D conversion unit, and an A / D conversion unit that performs A / D conversion. The plurality of pixels subjected to A / D conversion by the column A / D conversion unit by obtaining an average value and a standard deviation of a reset signal level of a reference pixel which is a partial pixel of the plurality of D-converted pixels The distribution information indicating the distribution of the pixel reset signal level may be acquired.

Note that the present invention may be realized not only as an apparatus but also as a system or an integrated circuit including processing means included in such an apparatus.

According to the present invention, it is possible to realize a high-speed solid-state imaging device with high pixel signal level bit accuracy without changing the hardware configuration of the column A / D conversion circuit.

FIG. 1 is a block diagram illustrating a configuration of the solid-state imaging device according to the first embodiment. FIG. 2 is a flowchart for explaining the optimization operation of the A / D conversion range of the solid-state imaging device according to the first embodiment. FIG. 3 is a timing diagram for explaining the A / D conversion operation in the all-pixel reset signal level distribution acquisition mode of the present invention. FIG. 4 is a graph showing a reset signal level distribution calculation model in the first embodiment. FIG. 5 is a diagram for explaining a change in code assignment before and after adjustment of the A / D conversion range. FIG. 6 is a diagram illustrating a state of a normal read operation including a reset signal level distribution acquisition operation. FIG. 7 is a diagram for explaining the effect of A / D conversion range optimization. FIG. 8 is a diagram for explaining the effect of A / D conversion range optimization. FIG. 9 is a flowchart for explaining an optimization operation of the A / D conversion range of the solid-state imaging device according to the modification of the first embodiment. FIG. 10 is a graph showing a reset signal level distribution calculation model in a modification of the first embodiment. FIG. 11 is a block diagram showing the configuration of the camera system according to Embodiment 2 of the present invention. FIG. 12 is a block diagram illustrating a configuration of a conventional solid-state imaging device. FIG. 13 is a timing diagram for explaining an A / D conversion operation using a conventional solid-state imaging device.

Hereinafter, a solid-state imaging device and an imaging system in each embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
Hereinafter, the configuration of the solid-state imaging device according to the first embodiment will be described.

FIG. 1 is a block diagram showing an imaging system according to the first embodiment.

The imaging system shown in FIG. 1 includes an optical system 200 and a solid-state imaging device 100.

The optical system 200 collects light from a subject to be imaged and forms an image on the imaging region of the solid-state imaging device 100, and is positioned on the optical path between the lens 201 and the solid-state imaging device 100. The shutter 202 is a mechanical shutter that controls the amount of light guided onto the imaging region.

A solid-state imaging device 100 shown in FIG. 1 is a solid-state imaging device including a plurality of pixels arranged in a matrix, for example, a MOS sensor. The solid-state imaging device 100 includes a pixel array 102, a column A / D conversion circuit 106, a ramp generation circuit 108, an output buffer 109, a digital preprocessing circuit 113, a clock generation circuit 114, a mode terminal 115, A control unit 116, a reset signal level distribution acquisition circuit 119, a timing generation circuit 120, and an output signal bus 126 are provided. Further, the solid-state imaging device 100 controls output of digital signals converted and held by a row scanning unit (not shown) for selecting one or more rows of pixels to be read and a column A / D conversion circuit 106. Column scanning means (not shown).

The pixel array 102 is a pixel array in which pixels (also referred to as sensitive elements) 101 including photoelectric conversion elements that photoelectrically convert incident visible light into a charge amount corresponding to the amount of light are arranged in a matrix (matrix shape). Also called a sensitive element array). In the pixel array 102, a readout signal line 103 for transmitting a signal output from the corresponding pixel 101 is formed for each column of the plurality of pixels 101.

Here, the pixel 101 includes at least a photosensitive element such as a photodiode or a photogate, and a device structure for reading a signal generated by photoelectric conversion or a structure that enables an initialization operation is provided as necessary. Unit element. In general, a device having an array structure is generally provided with a dummy pattern particularly at an end thereof in order to ensure stability in a semiconductor process formation process. This pixel array 102 is no exception. Here, only a pixel having a function of actually reading is referred to as a pixel 101. Note that the pixel 101 is separated into the following two types from the viewpoint of light sensitive characteristics. One is a normal pixel with normal photosensitivity characteristics, and the other is a pixel signal level that determines the black level of the image because the photosensitivity area of the pixel is shielded by a metal wiring layer, etc. This is a shading pixel capable of

Further, as shown in FIG. 1, a reference pixel region 112 is provided in a part of the pixel region of the pixel array 102. In the pixel area of the pixel array 102, an effective pixel area for acquiring a signal that directly constitutes an image and a black level signal for determining the black level of the image are acquired in an area excluding the reference pixel area 112. It is assumed that a so-called OB pixel region composed of light-shielding pixels is provided.

The reference pixel area 112 is used for reading out a reset signal level to a reset signal level distribution acquisition circuit 119 described later. Here, the pixel 101 included in the reference pixel region 112 may have the same element structure as the above-described normal pixel or may be a light-shielded pixel. Note that the reference pixel region 112 is configured by a row unit, that is, one row or a plurality of rows of pixels for the convenience of simultaneously reading out pixels for one row and performing processing in parallel as a reading method of the solid-state imaging device 100. Has been.

The ramp generation circuit 108 includes a binary counter 104 and a DAC circuit 105 which is a D / A conversion circuit, and supplies a reference signal 122 called a ramp wave to the column A / D conversion circuit 106.

In the ramp generation circuit 108, by setting an initial value and an end value of the binary counter 104, a potential range of the reference signal 122 can be designated. The binary counter 104 serving as the ramp generation circuit 108 supplies a binary value to the DAC circuit 105 in synchronization with the clock signal (ramp generation circuit clock signal 121b) input by the timing generation circuit 120.

The DAC circuit 105 generates an analog ramp voltage of a ramp wave (reference signal 122), specifically, a triangular wave, according to the input (supplied) binary value. The analog ramp voltage (reference signal 122) is input to the comparator 107 of the column A / D conversion circuit 106 as a reference potential.

The column A / D conversion circuit 106 is provided for each column or for each of the plurality of pixels 101, and includes a comparator 107 and a UD counter 117. The column A / D conversion circuit 106 receives a signal output from the corresponding pixel 101 via the readout signal line 103, and converts the input signal from the corresponding pixel into a digital signal.

In the comparator 107, the analog ramp voltage (reference signal 122) generated by the DAC circuit 105 is input to one input terminal, and read from the pixel 101 via the read signal line 103 to the other input terminal. The pixel signal is input. The comparator 107 inputs the output to the UD counter 117. Note that the read signal line 103 and the comparator 107 are connected to stabilize the potential (read potential) of the pixel signal read from the pixel 101 or to amplify the pixel signal read from the pixel 101. A sample hold circuit or an amplifier circuit may be provided between them.

The UD counter 117 is connected to the output terminal of the comparator 107 and the signal line 123. By counting in the up direction or the down direction, the input potentials input to the two input terminals of the comparator 107 match. Measure the time to complete.

In this way, the column A / D conversion circuit 106 acquires a digital signal corresponding to the input signal.

The output signal bus 126 is for transmitting a digital signal output from the column A / D conversion circuit 106.

The clock generation circuit 114 generates a clock signal used in the solid-state imaging device 100. Here, this clock signal generated by the clock generation circuit 114 becomes a reference signal in the solid-state imaging device 100.

The digital pre-processing circuit 113 has an input connected to the output signal bus 126, and for example, pixel defect correction or digital processing is performed on the data (digital signal) A / D converted by the column A / D conversion circuit 106. Perform processing such as signal amplification. The digital preprocessing circuit 113 outputs the processed data (output data) to the output buffer 109.

The output buffer 109 is connected to the output of the digital preprocessing circuit 113, receives the output data (output signal) of the digital preprocessing circuit 113, and outputs it to the outside of the solid-state imaging device 100. The output buffer 109 may be a buffer configured by arranging the output data from the digital preprocessing circuit 113 by the bit width. Further, the output buffer 109 may be a buffer that converts output data from the digital preprocessing circuit 113 into bit serial data and outputs the data at high speed with a small amplitude differential output such as LVDS (Low voltage differential signaling). .

The reset signal level distribution acquisition circuit 119 is a characteristic part of the present invention. In this embodiment, a case where the reset signal level distribution acquisition circuit 119 is connected to the output signal bus 126 will be described. The reset signal level distribution acquisition circuit 119 acquires reset signal level distribution information indicating the distribution of reset signal levels of the plurality of pixels 101 that have been A / D converted by the column A / D conversion circuit 106. Specifically, the reset signal level distribution acquisition circuit 119 sets the maximum reset signal level for all the pixels that are all the pixels 101 in the pixel area of the pixel array 102 and the reference pixels that are the pixels 101 in the reference pixel area 112. Comparators (for example, MIN computing unit 195, MAX) that compare values held in registers (for example, all pixel MIN register 191 to reference pixel MAX register 194) that hold values and minimum values with input reset signal levels A computing unit 196). With this configuration, the reset signal level distribution acquisition circuit 119 can monitor the maximum value and the minimum value of the pixel signal potential value (reset signal level) of the reset signal as an index of the reset signal level distribution.

The reset signal level distribution acquisition circuit 119 may be connected not to the output signal bus 126 but to the output side of the digital preprocessing circuit, depending on the processing contents of the digital preprocessing circuit 113.

The mode terminal 115 is a terminal outside the chip constituting the solid-state imaging device 100, for example. Then, the operation mode of the solid-state imaging device 100 is set by applying a predetermined potential to the mode terminal 115. Note that the mode terminal 115 is not necessarily a terminal outside the chip. For example, when the solid-state imaging device 100 is an SOC (System-on-a-Chip) type device including an image signal processing processor including an imaging element such as the pixel 101 and its control function, the mode terminal 115 is connected to the image signal processing This means an in-chip connection terminal for the processor and the image sensor.

Based on the reset signal level distribution information acquired by the reset signal level distribution acquisition circuit 119, the control unit 116 is assigned to count the reset signal level and the pixel signal level within a predetermined counter bit width of the UD counter 117. Each A / D conversion range (count range) is changed. The control unit 116 controls the operation of the entire solid-state imaging device 100. Specifically, the control unit 116 writes a setting via a serial I / F circuit (not shown) in an electronic circuit such as an I2C (Inter-Integrated Circuit) setting for applying a potential to the mode terminal 115 of the solid-state imaging device 100. The operation mode of the solid-state imaging device 100 is performed according to the register setting to be performed. In addition, the control unit 116 manages the cooperative operation of each circuit in each operation mode, the transition of the operation state of each circuit, and the like. For example, the control unit 116 controls the row scanning unit and the column scanning unit in accordance with the image acquisition mode. Also, the control unit 116 initializes the UD counter 117 (counter reset) of the column A / D conversion circuit 106, for example, by giving a counter reset signal to the UD counter 117. The UD switching signal is supplied to the UD counter 117, thereby controlling the switching of the count direction of the UD counter 117 of the column A / D conversion circuit 106. In addition, the control unit 116 initializes the ramp generation circuit 108, performs range switching control of the ramp generation circuit 108 by giving a reference potential range switching control signal, or performs A / D of the timing generation circuit 120. The mask timing control of the clock signal corresponding to the conversion range is performed.

The timing generation circuit 120 generates various timing signals to control the timing of each circuit constituting the solid-state imaging device 100. In particular, the timing generation circuit 120 generates a clock signal 121 as a timing signal to be supplied to the ramp generation circuit 108 and the UD counter 117 based on the reference clock signal generated by the clock generation circuit 114. Specifically, the timing generation circuit 120 generates the clock signal 121 based on the reference clock signal by, for example, gating the reference clock signal, and sends it to the ramp generation circuit 108 for the ramp generation circuit. The clock signal 121b is supplied to the UD counter 117 as the UD counter clock signal 121a. Here, the UD counter clock signal 121a and the ramp generation circuit clock signal 121b are described as common signals, but the present invention is not limited thereto. The wiring for transmitting the UD counter clock signal 121a and the ramp generation circuit clock signal 121b may be integrated and mounted in a common circuit, or may be separately mounted.

As described above, the solid-state imaging device 100 is configured.

Next, a characteristic operation of the solid-state imaging device 100 configured as described above will be described.

FIG. 2 is a flowchart for explaining the optimization operation of the A / D conversion range of the solid-state imaging device 100 according to the first embodiment. Hereinafter, each control step will be described with reference to FIG. In the following description, for convenience of explanation, it is assumed that the initial operation frame is 0, and the subsequent frames are assigned serial numbers 1, 2,...

First, for example, using the mode terminal 115, the solid-state imaging device 100 is set to the A / D conversion range optimization mode. Then, the flow shown in FIG. 2 is “activated”. The setting of the operation mode including the A / D conversion range optimization mode is not limited to the mode terminal 115. As described above, it may be performed by register setting for writing via a serial input I / F circuit such as I2C.

Next, immediately after activation, the operation mode of the solid-state imaging device 100 is set to “all pixel reset signal level distribution acquisition mode” (step S01). Then, the A / D conversion range, which is a range of digital values used by the column A / D conversion circuit 106 for A / D conversion output, is set to a default value. This is because the A / D conversion range in the initial state of the solid-state imaging device 100 should be sufficiently wide immediately after activation. Here, for simplification of description, it is assumed that the voltage step per gradation is 1 mV, the analog input voltage range is 1.024 V, and the corresponding output bit range is 1024 gradations (10 bits). The analog input voltage range with respect to the reset signal level is assigned to 128 mV, and the output bit range is assigned to 128 gradations (7 bits), but the number of gradations may be secured wider as necessary.

In this all-pixel reset signal level distribution acquisition mode, the solid-state imaging device 100 reads out only the reset signal level. Therefore, the solid-state imaging device 100 is changed from the control for performing normal image reading as follows. That is, in this all-pixel reset signal level distribution acquisition mode, the reset signal level is read not only from the reference pixel region 112 but also from all rows of the pixel array 102 including the OB pixel region and the effective pixel region. However, readout of the pixel signal level is unnecessary and is not performed. That is, in this all-pixel reset signal level distribution acquisition mode, it is not necessary to control the exposure start and the exposure period of the pixel 101. For example, when the pixel 101 has a pixel configuration including a normal selection transistor, the source follower Reset control on the gate potential side (floating diffusion: FD) of the transistor may be performed, and readout control from the photodiode (PD) to the FD becomes unnecessary. Note that the sequential vertical scanning of all the rows is the same as the normal readout control.

Next, the minimum value RMIN (0) and the maximum value RMAX (0) of the reset signal level of the pixel 101 in the reference pixel region 112, the minimum value PMIN (0) of the reset signal level of all the pixels 101 in the pixel array 102, and The maximum value PMAX (0) is acquired (step S02).

The details will be described below.

First, the operation in which the reset signal level is read, A / D converted by the column A / D conversion circuit 106 of each column, and input to the reset signal level distribution acquisition circuit 119 will be described.

First, the solid-state imaging device 100 reads the reset signal level of the pixel 101 to one terminal of the comparator 107 of the column A / D conversion circuit 106 via the readout signal line 103, and after the level is stabilized, the comparator An analog ramp voltage (reference signal 122), which is a ramp wave input to the other terminal 107, is swept. Here, the analog ramp voltage is generated by a triangular wave potential.

Subsequently, in the column A / D conversion circuit 106, the UD counter 117 measures the time until the input potentials input to the two terminals of the comparator 107 (the potential of the reset signal and the reference signal 122) match. In this way, the column A / D conversion circuit 106 acquires a digital value corresponding to the reset signal level of the pixel 101. Here, the method of A / D converting the signal read from the pixel 101 by the column A / D conversion circuit 106 is the above-described lamp type A / D conversion.

In step S02, the column A / D conversion circuit 106 may read the reset signal level of the pixel 101 output from the comparator 107 as it is, so that the UD counter 117 switches the count direction (U / D). Drive in one direction only up or down. Therefore, in the following, in order to simplify the description, the UD counter 117 will be described as performing counting in the up direction starting from zero.

Here, the timing waveform of the input potential input to the comparator 107 of the column A / D conversion circuit 106 will be described with reference to FIG.

FIG. 3 is a timing diagram for explaining the A / D conversion operation in the all-pixel reset signal level distribution acquisition mode of the present invention.

FIG. 3A shows timing waveforms of the read signal line potential and the reference potential in a normal image acquisition mode to which the present invention is not applied for reference. Here, the vertical axis of the upper stage indicates the read signal line potential, that is, the A / D conversion signal input potential (analog), and the vertical axis of the lower stage indicates the A / D conversion reference input potential (analog). The horizontal axis shows time in both the upper and lower stages.

Further, in the lower part of FIG. 3A, as in the figure shown in the lower part of FIG. 12, the period required for the A / D conversion operation of the pixels 101 for one row, specifically, the digital by the UD counter 117 is displayed. A horizontal scanning period including a reset level comparison period tr and a signal level comparison period ts necessary for CDS is shown. Then, the image for one frame is output by repeating this one horizontal scanning period for the number of rows of the pixels 101 to be subjected to normal image reading. On the other hand, in the upper part of FIG. 3A, the reset signal level acquisition operation for acquiring the reset signal component of the target pixel 101 (for example, the pixel 101 in the Nth row) in the reset level comparison period tr of one horizontal scanning period, A pixel signal level acquisition operation for acquiring the pixel signal component of the target pixel 101 in the signal level comparison period ts of one horizontal scanning period is shown.

FIG. 3 (b) shows a timing waveform for reading only the reset signal level in the present embodiment. Note that the vertical and horizontal axes in the upper and lower stages are the same as those in FIG.

As shown in FIG. 3B, the timing waveform for reading only the reset signal level can be obtained by masking the pixel signal level acquisition operation in the timing waveform of FIG. When the timing for reading only the reset signal level is obtained by this method, except for the signal waveform mask related to the pixel signal level acquisition operation, the timing completely matches the readout timing of the normal image acquisition mode. The time such as the period and one vertical scanning period (one frame) does not change. Therefore, it is easy and preferable to switch control by this method.

FIG. 3C shows another example of timing waveforms for reading only the reset signal level in the present embodiment. FIG. 3C shows a timing waveform in the case where the time that was originally the pixel signal level acquisition timing is used for reading the reset signal level. 3C masks the pixel signal level acquisition operation in the timing waveform of FIG. 3A, and then performs the reset signal level acquisition operation (cycle) during the vacant pixel signal level acquisition operation. ) Is added.

This is because the reset signal acquisition operation can be performed because the comparison period is shorter than the pixel signal acquisition operation. In the case shown in FIG. 3C, two reset signal level acquisition operations (cycles) can be added in one horizontal scanning period compared to the case shown in FIG. Can be read. That is, in the case shown in FIG. 3C, the reset signal level distribution for one frame can be acquired in one-third time. Alternatively, using the same time of one frame as in FIG. 3B, the reset signal level variation can be acquired three times as the data amount. However, it should be noted that if the frequency of this reading is increased, it is necessary to increase the frequency at the time of output from the column A / D conversion circuit 106 to the next stage circuit via the output signal bus 126. In particular, in the normal read operation, when the bandwidth of the output signal bus 126 is rate-controlled rather than the read operation from the pixel 101 or the A / D conversion operation, the read timing shown in FIG. Is good.

Note that, here, the bit width of the reset signal level is 7 bits as described above. Therefore, it is possible to stop the higher-order bus, mask the higher-order bit transfer operation, and the like, and it is possible to suppress the power consumption from the normal operation.

Thus, the reset signal level output from the pixel 101 is A / D converted by the column A / D conversion circuit 106 of each column and input to the reset signal level distribution acquisition circuit.

Next, the operation of the reset signal level distribution acquisition circuit 119 will be specifically described.

First, in step S01, when the all-pixel reset signal level distribution acquisition mode is started, the reset signal level distribution information in the reset signal level distribution acquisition circuit 119 is initialized. That is, all the pixel MAX registers 192 and the reference pixel MAX registers 194 in the reset signal level distribution acquisition circuit 119 are both set to the minimum value (in this case, zero), and all the pixel MIN registers 191 and the reference pixel MIN registers 193 Are set to the maximum value (127 in this case).

Here, as described above, the row scanning means such as a vertical scanning circuit performs control to select one or more rows of the pixels 101 of the pixel array 102 to be read. That is, the readout control of the row scanning means such as the vertical scanning circuit is sequentially performed from the top to the bottom row in the pixel array 102 shown in FIG. Therefore, the first reading of one frame is performed from the reference pixel region 112. Then, the read pixel signals (here, reset signals) of the pixels 101 are sequentially input to the reset signal level distribution acquisition circuit 119 via the column A / D conversion circuit 106 one pixel at a time.

The signal (reset signal) input to the reset signal level distribution acquisition circuit 119 is compared with the value held in the all-pixel MAX register 192 by the MAX calculator 196 (MAX calculation is performed), and the result is the all-pixel MAX. It is written to the register 192. At the same time, the signal (reset signal) input to the reset signal level distribution acquisition circuit 119 is compared with the value held in the all-pixel MIN register 191 by the MIN calculator 195 (MIN calculation is performed), and the result is It is written in the all pixel MIN register 191.

Further, a reference pixel MAX is output by a MAX calculator 196 to a signal (reset signal) input from the pixel 101 in the reference pixel area 112 to the reset signal level distribution acquisition circuit 119 via the column A / D conversion circuit 106. A MAX operation with the value held in the register 194 is performed, and the result is written in the reference pixel MAX register 194. At the same time, the value held in the reference pixel MIN register 193 and the MIN calculation are performed by the MIN calculator 195, and the result is written in the reference pixel MIN register 193.

Note that the maximum value of the reset signal level of the pixel 101 in the reference pixel area 112 in the initial state acquired in step S02 is RMAX (0), the minimum value is RMIN (0), and the maximum value of the reset signal level in all the pixels 101 is The following description will be made assuming that PMAX (0) and the minimum value are PMIN (0). The 0 in parenthesis corresponds to i = 0 in this frame.

As described above, the reset signal level distribution acquisition circuit 119 acquires the MAX value and the MIN value of all the pixel regions, and the MAX value and the MIN value of the pixel 101 in the reference pixel region 112.

In other words, by sequentially processing each pixel 101 (hereinafter referred to as a reference pixel) in the reference pixel area 112, the MAX value of the reference pixel is stored in the reference pixel MAX register 194 and the reference pixel MIN register 193 at the end of reading the reference pixel. And the MIN value can be acquired. For all the pixels 101 (hereinafter referred to as all pixels) in the entire pixel area of the pixel array 102 excluding the reference pixel area 112, the calculation with the reference pixel MAX register 194 and the reference pixel MIN register 193 is not performed ( Only the operation with all pixel MAX registers 192 and all pixel MIN registers 191 is continued. In this manner, the MAX value and the MIN value of all pixel regions can be acquired when reading of all pixels for one frame is completed.

In the above description, when the reset signal level of the reference pixel is output (when the reference pixel is output), the reference pixel register (reference pixel MAX register 194 and reference pixel MIN register 193) and all pixel registers (in one pixel cycle) Although the method of performing comparison with the register values of both the all-pixel MAX register 192 and all-pixel MIN register 191) in a time division manner has been described, the present invention is not limited to this. For example, as one method, two comparators may be provided in parallel and operated in parallel. Another method is to output reference pixels. Only comparison with the reference pixel registers (reference pixel MAX register 194 and reference pixel MIN register 193) may be performed. For example, when the reset signal level of the pixel 101 other than the reference pixel is output, only comparison with all pixel registers (all pixel MAX register 192 and all pixel MIN register 191) is performed. Then, immediately after the reading of all the pixels is completed, the MAX calculation of the values of the reference pixel MAX register 194 and the all pixel MAX register 192 may be performed, and the result may be the final result of the MAX value of all the pixels 101. The same applies to the MIN side.

Next, an all-pixel reset distribution model formula is set based on the initial state data indicating the all-pixel reset level distribution acquired in step S02 (step S03).

Specifically, first, in step S02, initial state data indicating the reset signal level distribution of all the pixels in one frame is acquired as the MAX value / MIN value, and the initial state indicating the reset signal level distribution of the reference pixel. Are acquired as MAX value / MIN value. Next, with respect to the initial state data acquired in step S02, for example, as shown in FIG. Approximate the relationship. As a result, the following all-pixel reset distribution model expression for calculating the reset signal level distribution of all the pixels from the distribution of the reset signal level of the reference pixel can be derived (Expression 1). FIG. 4 is a graph showing a reset signal level distribution calculation model in the first embodiment.

Y = (PMAX (0) −PMIN (0)) / (RMAX (0) −RMIN (0)) × (X−RMIN (0)) + PMIN (0) (Formula 1)

Next, the operation mode of the solid-state imaging device 100 is set to “reference pixel reset signal level distribution acquisition mode” (step S04). Here, the frame is 1 (i = 1). In this operation mode, that is, the reference pixel reset signal level distribution acquisition mode, the A / D range is set to a default value as in step S01.

In step S04, the operation of acquiring the reference pixel reset signal level distribution is performed in the same manner as described in step S02. The row scanning means such as the vertical scanning circuit, the column A / D conversion circuit 106, and the reset signal level distribution acquisition circuit. There is an operation with 119. However, the operations of the row scanning means such as the vertical scanning circuit and the column A / D conversion circuit 106 are the same as those described in step S02 except that only the reference pixel region 112 is accessed. Is omitted. The operation of the reset signal level distribution acquisition circuit 119 is almost the same as that described in step S02, but will be briefly described below.

First, in step S04, when the reference pixel reset signal level distribution acquisition mode is started, the reference pixel MAX register 194 in the reset signal level distribution acquisition circuit 119 is set to the minimum value (in this case, zero), and the reference pixel MIN register 193 is set to the maximum value. (In this case, 127) is set. In step 04, unlike in step 02, the initialization of all pixel MAX register 192 and all pixel MIN register 191 is not performed. As described above, the row scanning unit such as a vertical scanning circuit performs control to select one or more rows of the pixels 101 of the pixel array 102 to be read. That is, the readout control of the row scanning means such as the vertical scanning circuit is sequentially performed from the top to the bottom row in the pixel array 102 shown in FIG. Therefore, the first reading of one frame is performed from the reference pixel region 112. The read pixel signals (here, reset signals) of the pixels 101 are sequentially input to the reset signal level distribution acquisition circuit 119 via the column A / D conversion circuit 106 one pixel at a time.

Next, the signal (reset signal) input to the reset signal level distribution acquisition circuit 119 is subjected to a MAX operation with the value held in the reference pixel MAX register 194 by the MAX calculator 196, and the result is the reference pixel MAX register. 194 is written. At the same time, the MIN calculator 195 performs a MIN calculation with the value held in the reference pixel MIN register 193 and writes the result in the reference pixel MIN register 193.

As described above, the reset signal level distribution acquisition circuit 119 acquires the MAX value and the MIN value of the pixel 101 in the reference pixel region 112.

In other words, by sequentially processing each pixel 101 in the reference pixel region 112 in step S04, the reference pixel MAX register 194 and the reference pixel MIN register 193 store the pixel 101 in the reference pixel region 112, that is, the reference, at the end of reading the reference pixel. The MAX value and MIN value of the pixel can be acquired. In this way, the reference pixel reset signal level distribution could be acquired as the MAX value / MIN value. The maximum value of the reference pixel acquired here is RMAX (1), and the minimum value is RMIN (1).

Next, the maximum value and the minimum value of all the pixels are calculated using the data indicating the reference pixel reset level distribution acquired in step S04 and the all pixel reset signal level distribution model formula (step S05).

Specifically, the maximum values RMAX (1) and RMIN (1) of the reference pixels acquired in step S04 are input to X in (expression 1), which is the all-pixel reset signal level distribution model expression derived in step S03. (Formula 2) and (Formula 3) are obtained. Then, the maximum value PMAX (1) and the minimum value PMIN (1) of all the pixels are calculated by these (Expression 2) and (Expression 3).

PMAX (1) = (PMAX (0) −PMIN (0)) / (RMAX (0) −RMIN (0)) × (RMAX (1) −RMIN (0)) + PMIN (0) (Equation 2 )
PMIN (1) = (PMAX (0) −PMIN (0)) / (RMAX (0) −RMIN (0)) × (RMIN (1) −RMIN (0)) + PMIN (0) (Equation 3 )

Next, the operation mode of the solid-state imaging device 100 is set to “A / D conversion range switching step”, and the A / D conversion range of the reset signal level is optimized (step S06). Specifically, an upper limit value and a lower limit value of the A / D conversion range of the reset signal level are set.

This is because the analog voltage range on the input side of A / D conversion corresponds to the range setting of the DAC circuit 105 that generates the reference potential. However, since there are restrictions on the circuit configuration for setting the range and restrictions from the timing related to the reset signal level comparison operation, the above (Expression 2) and (Expression 3) are not necessarily used as the upper limit value of the A / D conversion range. It cannot be set to the lower limit. Therefore, for example, when the DAC circuit 105 has a restriction that switching can be performed only in steps of 16 steps, the reset signal level range (also referred to as reference pixel potential) of the DAC circuit 105 is expressed by the following (Expression 4) and (Expression 5). Set. That is, the upper limit value of the reset signal level range of the DAC circuit 105 is set by (Expression 4), and the lower limit value is set by (Expression 4).

MMAX (i) = [(PMAX (i) ÷ 16) +1] × 16 (Expression 4)
MMIN (i) = [(PMIN (i) ÷ 16)] × 16 (Expression 5)

Here, [] is a Gaussian symbol, which is a function that returns the largest integer that does not exceed the number in parentheses.

For example, assuming that PMAX (i) = 54 and PMIN (i) = 19, MMAX = 64 and MMIN = 16 are obtained by calculating using (Expression 4) and (Expression 5). In this case, the initial value of the binary counter 104 is set to MMIN = 16, and the reset signal level is set to be counted until MMAX = 64.

Thereby, the ramp generation circuit 108 performs voltage sweep of the reset signal level from 16 mV to 64 mV. Then, the UD counter 117 corresponding to this operation starts counting from zero at the time of A / D conversion of the normal pixel signal, and the maximum value is 64-16 = 48. That is, since the A / D conversion range of the reset signal level is reduced from 128 to 48, the A / D conversion period is also reduced.

As described above, in step S06, the reset signal level A / D conversion range is optimized by setting the upper and lower limits of the reset signal level A / D conversion range.

Next, the A / D conversion range of the pixel signal level is optimized (step S07). Specifically, in the A / D conversion range of the pixel signal level, the gradation on the minus range side reduced in step S06 is assigned to the plus range side. This is because the conversion range reduction of the reset signal level performed in step S06 means that the minus range of the digital value of the UD counter 117 can be reduced, so that the plus range can be increased by the amount of reduction of the minus range. is there. Hereinafter, this will be described with reference to FIG.

FIG. 5 is a diagram for explaining a change in code assignment before and after adjustment of the A / D conversion range. Here, in FIG. 5, all codes of 10-bit binary representation 0000000000000 to 1111111111 are written doubly on the plus side and the minus side. In actual interpretation as a signed binary number, only one of the expressions needs to be valid. Therefore, in FIG. 5, the invalid portion is indicated by hatching.

Fig. 5 (a) shows the assignment of the sign of the count value at the time of default setting (when the negative range is up to 128). FIG. 5B shows the code assignment of the count value after optimization in step S07 in which the minus range is up to 48.

In this way, in the UD counter 117, the reduced gradations on the minus range side can be assigned to the plus range side.

The sign determination for determining whether the assigned gradation is in the minus range or the plus range is performed by the digital pre-processing circuit 113 in the subsequent stage, so the circuit of the column A / D conversion circuit 106 and the ramp generation circuit There is no need to change the configuration or control. For example, in the case shown in FIG. 5, the digital pre-processing circuit 113 in the subsequent stage sets the most significant bit of the 10-bit count value of the UD counter 117 to b9 and the least significant bit to b0 at the time of default setting (the minus range is up to 128). In the case of b) = b8 = b7 = 1, it is only necessary to have a sign determination logic for determining a negative value. Further, the digital pre-processing circuit 113 in the subsequent stage is negative when b9 = b8 = b7 = b6 = 1 AND (b5 = 1 OR b4 = 1) when the range optimization is set (when the negative range is up to 48). What is necessary is just to provide the mechanism switched to the code | symbol determination logic determined to be a value.

The post-stage digital preprocessing circuit 113 includes the code determination logic and the mechanism described above, but is not limited thereto. The digital circuit including the code determination logic and the mechanism may be included in the logic circuit in the solid-state imaging device 100, or the image signal processor side that receives the output of the solid-state imaging device 100 and performs image signal processing It is good also as a structure contained in. However, in order to perform the minimum digital signal processing in the solid-state imaging device 100, it is better to perform the code determination before the minimum digital signal processing. That is, it is preferable that the solid-state imaging device 100 includes the code determination logic and the mechanism.

As described above, in step S07, the A / D conversion range of the pixel signal level is optimized.

In the reference signal generation at the time of A / D conversion of the pixel signal level in step S07, if the lower limit value of the A / D conversion range of the pixel signal level is not zero, the A / D conversion range of the reset signal level is determined in step S06. It is preferable to perform the processing as described in the case where the lower limit value is not zero (MMIN = 16).

Next, the solid-state imaging device 100 starts a normal reading operation for all pixels except the reference pixel (step S08).

Specifically, after the optimization process of the A / D conversion range of the reset signal level and the pixel signal level is executed in steps S01 to S07, the normal reading operation is started for all the pixels except the reference pixel. Here, the “normal readout operation” means a readout operation of the pixel signals constituting the image data acquired by the normal imaging operation.

As described above, the solid-state imaging device 100 performs the normal reading operation for all the pixels except the reference pixel after optimizing the A / D conversion range.

In other words, the reset signal level distribution acquisition circuit 119 is based on the A / D conversion range (count range) and the reset signal levels of the plurality of pixels 101 A / D converted by the column A / D conversion circuit 106 and the plurality of reset signal levels. A first reset indicating a distribution of reset signal levels of a plurality of pixels A / D converted by the column A / D conversion circuit 106 by acquiring a reset signal level of a reference pixel that is a partial pixel of the pixel 101 Get signal level distribution information. The reset signal level distribution acquisition circuit 119 further acquires the reset signal level of only the reference pixels A / D converted by the column A / D conversion circuit 106 based on the A / D conversion range (count range). Thus, the second reset signal level distribution information indicating the distribution of the reset signal level of only the reference pixels A / D converted by the column A / D conversion circuit 106 is acquired. The control unit 116 changes the A / D conversion range (count range) from the first reset signal level distribution information and the second reset signal level distribution information. The solid-state imaging device 100 includes a plurality of pixels 101 in the column A / D conversion circuit 106 based on the changed A / D conversion range (count range), that is, based on the optimized A / D conversion range. A normal readout operation for A / D conversion between the reset signal level and the pixel signal level is performed.

As shown in FIG. 2, the reading operation when optimizing the A / D conversion range is performed by incrementing the frame index i and repeating the operations from step S04 to step S08 for the subsequent frames. This is shown in FIG. FIG. 6 is a diagram illustrating a state of a normal read operation including a reset signal level distribution acquisition operation. Thereby, it is possible to follow changes in the optimum range due to changes in temperature and voltage.

However, in the solid-state imaging device 100, the A / D conversion range is optimized when the imaging mode is changed, such as when the moving image acquisition mode is changed to the still image acquisition mode or the angle of view is changed even in the same moving image mode. It is desirable to operate from the beginning (step S01), that is, from the all-pixel reset signal level distribution acquisition mode.

Also, since exposure control is not performed when the reset signal level is acquired, the exposure time is not relevant. However, in a low-illuminance shooting mode with an exposure time of about 1 second or more, it is normal to set a large gain and there is no restriction on the frame rate. For this reason, it is desirable to operate the A / D conversion range from the beginning (step S01).

Here, exposure control is control performed to obtain appropriate exposure for various illuminance conditions of the subject. This exposure control includes a method of increasing / decreasing the exposure time to increase / decrease the pixel signal itself, and a method of changing the amplification degree of the subsequent circuit, and is usually realized by combining these two methods. An example of the amplifying means for changing the amplification degree of the circuit in the subsequent stage is a case where the solid-state device 100 includes a column amplifier, and in another example, the solid-state imaging device 100 includes the column A / This is a case where the D conversion circuit 106 is provided. When the solid-state imaging device 100 includes the column A / D conversion circuit 106, the amplification degree can be changed by changing the slope of the lamp reference potential.

In addition, the gain of the amplifier circuit in the previous stage of the column A / D conversion circuit 106 including the slope of the lamp reference potential directly amplifies the variation in the reset signal level. Therefore, it is desirable to match the gain in step S02 with the gain in step S04.

Further, as a margin for the range setting error by the above linear approximation, for example, the upper limit value and the lower limit value may be increased by 16 LSBs, respectively. In that case, (Expression 4) and (Expression 5) used when optimizing the A / D conversion range of the reset signal level in step S06 may be changed to (Expression 8) and (Expression 9) shown below.

MMAX (i) = [(PMAX (i) ÷ 16) +2] × 16 (Equation 8)
MMIN (i) = [(PMIN (i) ÷ 16) −1] × 16 (Equation 9)

Next, the effect of A / D conversion range optimization will be described below with reference to FIG.

7 and 8 are diagrams for explaining the effect of A / D conversion range optimization. FIG. 7A shows a timing diagram when the A / D conversion range optimization is not performed. FIGS. 7B, 8C, and 8D are examples of timing diagrams after A / D conversion range optimization. In FIGS. 7A, 7B, 8C, and 8D, the horizontal axis is time in the upper and lower graphs, whereas the vertical axis in the upper graph. Indicates the count value of the UD counter 117, and the vertical axis of the lower graph indicates the analog potential of the lamp reference potential. Further, in FIGS. 7B, 8C, and 8D, the waveform when the optimization is not performed (the waveform in FIG. 7A) is indicated by a dotted line for reference.

FIG. 7B shows a timing diagram when the A / D conversion range of the reset signal level is 16 mV to 64 mV and the maximum value of the corresponding column count is 48 in steps S01 to S06 in FIG. ing. As shown in FIG. 7B, it can be seen that the A / D conversion range of the reset signal level can be reduced from the default 128 gradations to 48 gradations by steps S01 to S06. Thereby, the “second D range reduction” can be suppressed, and the effective output D range (Reff in the figure) can be expanded from 767 gradations to 847 gradations. Further, along with the reduction of the A / D conversion range of the reset signal level, the A / D conversion period, which is an obstacle to increasing the frame rate, can be realized. This is because the reset signal comparison range ts is shortened by reducing the reset signal level range Rres, and the A / D conversion of the pixel signal level can be performed ahead of schedule.

As described above, since the effective output D range can be expanded by optimizing the reset signal level in steps S01 to S06, the bit accuracy of the pixel signal level can be increased. In addition, the A / D conversion period can be shortened, and there is an effect that it can be driven at a higher speed.

FIG. 8C shows a timing diagram when the pixel signal level A / D conversion range is expanded by changing the digital value code assignment in step S07. As shown in FIG. 8 (c), in step S07, by changing the code assignment corresponding to the reset signal level conversion range reduction, the “first D range reduction” and the “second D range reduction” are performed. And the effective output D range can be expanded from 767 gradations to 927 gradations. However, since the A / D conversion range of the pixel signal level is expanded, the time (signal level comparison period ts) for performing the A / D conversion of the pixel signal level becomes longer, so the A / D conversion range of the reset signal level Almost offsets the reduction in time. Therefore, even if pixel signal level conversion start is advanced, the entire A / D conversion period does not change before and after range optimization.

Thus, by optimizing the reset signal level in steps S01 to S07, the effective output D range can be further expanded, so that the bit accuracy of the pixel signal level can be further increased.

In FIG. 8D, the above steps S01 to S06 are performed, but when the range optimization of the pixel signal level in step S07 is performed, the effective output D range is not expanded from the default, but the default In order to keep the same, a timing diagram is shown when the pixel signal level range is changed so as to be rather reduced. As shown in FIG. 8D, the length of the signal level comparison period ts is obtained by optimizing the A / D conversion range in which priority is given to speeding up the A / D conversion of the reset signal level and the pixel signal level. This is shorter than the case of FIG. That is, there is an effect of further shortening the A / D conversion period. In this way, it can be seen that the pixel signal level conversion period can also be shortened by the same period as the reset signal level conversion period, which is effective in increasing the frame rate.

As described above, according to the first embodiment, the distribution of the reset signal level is determined during operation, and the A / D conversion range assigned to the reset signal level and the pixel signal level can be optimized. The solid-state imaging device 100 having high pixel signal level bit speed and high speed can be realized without changing the hardware configuration.

In addition, the solid-state imaging device 100 changes the count direction of the UD counter 117 for each pixel 101 in each row, so that the column A / D conversion circuit 106 receives the difference value between the pixel signal level and the reset signal level as A / It has a pixel signal output mode in which it is output after being D-converted (that is, digital CDS). In addition, the solid-state imaging device 100 has a pixel reset output mode in which only the pixel reset signal level is A / D converted by the column A / D conversion unit and output for each pixel in each row.

(Modification 1)
Next, as a modification of the solid-state imaging device according to the first embodiment, a case where an average value and a standard deviation are used when acquiring a reset signal level distribution of a reference pixel will be described.

FIG. 9 is a flowchart for explaining the operation of optimizing the A / D conversion range of the solid-state imaging device 100 according to this modification. Elements similar to those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted.

First, Step S01 is the same as the flow of FIG.

Next, initial state data RAVG (0) and RSTD (0), and PAVG (0) and PSTD (0) indicating the reset level distribution of the reference pixels and all the pixels are acquired (step S12).

Next, an all-pixel reset distribution model formula is set based on the initial state data acquired in step S12 (step S13).

Specifically, based on the initial state data acquired in step S01 and step S12, for example, as shown in FIG. 10, a linear relationship is approximated between the reset signal level of the reference pixel and the reset signal level of all pixels. . Accordingly, the following (Equation 10) for calculating the reset signal level distribution of all the pixels can be derived from the reset signal level distribution of the reference pixels. FIG. 10 is a graph showing a reset signal level distribution calculation model in this modification.

Y = (PSTD (0)) / (RSTD (0)) × (X-RAVG (0)) + PAVG (0) (Equation 10)

Here, RAVG (0) is an average value of the initial state of the pixel 101 in the reference pixel region 112, and RSTD (0) is a standard deviation of the initial state of the pixel 101 in the reference pixel region 112. Similarly, PAVG (0) is an average value of the initial state of all the pixels in the pixel array 102, and PSTD (0) is a standard deviation of the initial state of all the pixels in the pixel array 102.

Next, the operation mode of the solid-state imaging device 100 is set to “reference pixel reset signal level distribution acquisition mode” (step S14). In this operation mode, that is, the reference pixel reset signal level distribution acquisition mode, the A / D range is set to a default value as in step S01. Further, the reset signal level distribution acquisition circuit 119 acquires the average value RAVG (i) and standard deviation RSTD (i) of the pixels 101 in the reference pixel region 112.

Next, the average and standard deviation of all pixels are calculated using the data indicating the reference pixel reset level distribution acquired in step S14 and the all pixel reset signal level distribution model formula (step S15).

Specifically, the average RAVG (1) and standard deviation RSTD (1) of the reference pixels acquired in step S14 are input to X in (Equation 10), which is the all-pixel reset signal level distribution model expression derived in step S13. By doing this, the following (formula 11) and (formula 12) are obtained. Then, the average PAVG (i) and the standard deviation PSTD (i) of all the pixels are calculated from these (Equation 11) and (Equation 12).

PAVG (i) = (PSTD (0) / (RSTD (0)) × (RAVG (i) −RAVG (0)) + PAVG (0) (Equation 11)
PSTD (i) = (PSTD (0) / (RSTD (0)) × RSTD (i) (Equation 12)

As described above, the solid-state imaging device 100 according to the present modification performs the reset level distribution acquisition step.

In the A / D conversion range switching step, the maximum value and the minimum value of the distribution of the reset signal level are required to determine the A / D conversion range. In that case, for example, the average value ± 3σ may be used, and calculation may be performed using the following (Expression 13) and (Expression 14). From this calculation, PMAX (1) and PMIN (1) can be calculated.

PMAX (i) = PAVG (i) + 3 × PSTD (i) (Equation 13)
PMIN (i) = PAVG (i) -3 × PSTD (i) (Equation 14)

(Embodiment 2)
In the second embodiment, a camera system will be described as an example of an imaging system including a solid-state imaging device.

FIG. 11 is a block diagram showing the configuration of the camera system according to Embodiment 2 of the present invention. Elements similar to those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

The camera system shown in FIG. 11 includes an optical system 200, a camera signal processing LSI 300, and a solid-state imaging device 400.

The difference from the first embodiment is that the reset signal level distribution is acquired by the camera signal processing LSI 300 outside the solid-state imaging device 400, and the reset signal range is set by register writing. Specifically, unlike the solid-state imaging device 100 according to the first embodiment, the solid-state imaging device 400 does not include the reset signal level distribution acquisition circuit 119, and the camera signal processing LSI 300 includes the reset signal level distribution acquisition circuit 119. I have.

The camera signal processing LSI 300 includes an image signal processing unit 301, a reset signal level distribution acquisition circuit, and a solid-state imaging device control unit 303.

The image signal processing unit 301 performs image signal processing for a camera such as color interpolation and gamma correction as a circuit block that reads a digital image signal from the solid-state imaging device 400.

The reset signal level distribution acquisition circuit 119 is for acquiring the reset signal level distribution as described in the first embodiment.

The solid-state imaging device control unit 303 analyzes the image information obtained by the image signal processing unit 301 and performs automatic exposure control for adjusting the exposure time and gain of the solid-state imaging device 400, and imaging input via a user interface. Parameters related to the mode change are written to the register of the solid-state imaging device 400 via an I / F such as a 3-wire serial or I2C. At this time, the solid-state imaging device control unit 303 also writes an index (for example, maximum value or minimum value) related to the distribution of the reset signal level acquired by the reset signal level distribution acquisition circuit 119.

As described above, the camera system according to the second embodiment is configured. Note that the A / D conversion range optimization operation is the same as that of the first embodiment, and thus the description thereof is omitted.

As described above, according to the present invention, it is possible to realize a high-speed solid-state imaging device and imaging system with high pixel signal level bit accuracy without changing the hardware configuration of the column A / D conversion circuit.

As mentioned above, although the solid-state imaging device and imaging system of this invention were demonstrated based on embodiment, this invention is not limited to this embodiment. Unless it deviates from the meaning of this invention, the form which carried out the various deformation | transformation which those skilled in the art can think to this embodiment, and the structure constructed | assembled combining the component in different embodiment is also contained in the scope of the present invention. .

For example, the following cases are also included in the scope of the present invention.

For example, when trying to change the A / D conversion range for normal pixel readout in the same frame where the reset signal level distribution of the reference pixel is acquired, there is a case where it is not in time for a normal 3-line serial or register writing means such as I2C. is there. In that case, what is necessary is just to comprise so that it may reflect in the following flame | frame.

Also, it is not always necessary to acquire the distribution information of the reference pixels and change the range of the ramp generation circuit 108 based on the distribution information every frame.

In particular, when changing the range at a high frequency, if the difference between the current parameter and the parameter obtained by the calculation is 100% and the parameter is changed by 100% in one setting, the image blinks brightly or darkly. Therefore, it is desirable to devise a sequence specific to the feedback control, such as a change of 30% in one setting.

In addition, here, all the pixels are read only once when the all-pixel reset signal level is acquired. However, the accuracy of the reset signal level initial value may be increased by reading a plurality of frames instead of one frame. . Thereby, the accuracy of the calculation model can be further increased.

Further, for example, the following FD pixel mixing and vertical line pixel mixing may be applied.

In other words, when the solid-state imaging device and imaging system of the present invention includes a column amplifier, when the readout circuit system of the column circuit determines the signal offset level by the auto-zero operation instead of the pixel, all rows of the pixel are read. Thus, it is not always necessary to acquire the reset signal level distribution. By repeatedly reading out pixels in the same row, the number of samples of the reset signal level distribution can be increased and the statistical accuracy can be improved. At this time, since it is not necessary to read out the pixel signal level in the drive for acquiring the reset signal level distribution, it is not necessary to ensure the exposure time that is normally required. Will contribute.

When the solid-state imaging device and the imaging system of the present invention include a column amplifier, the reset level output determined by the auto-zero operation of the column amplifier does not depend on the pixel signal level. Even if the amplification factor of the column amplifier is changed, the output of the reset signal level is only the zero point of the output, so that the variation is not affected and the distribution of the reset signal level does not spread. That is, there is no need to change the reset signal level range.

On the other hand, when the solid-state imaging device and the imaging system of the present invention include the column A / D conversion circuit 106, the reset signal level range is changed by changing the slope of the lamp reference potential to change the amplification degree in the column A / D conversion circuit 106. Also need to be changed. This is because, for example, if the slope is halved and the amplification degree is doubled, the voltage distribution itself of the reset variation does not change, but the distribution range of the converted digital value is doubled.

Therefore, in the solid-state imaging device and imaging system of the present invention, it is necessary to change the reset signal level range when the amplification degree is changed by the gradient of the lamp reference potential regardless of whether or not the column amplifier is provided.

Further, the reference pixel used for acquiring the reset signal level distribution may be a pixel located in the peripheral portion of the normal readout pixel, and the readout of the normal pixel and the readout of the reference pixel must be continuous in readout of one frame. No, you may mix.

In addition, an example in which the ramp generation circuit 108 includes a binary counter 104 and a D / A conversion circuit (DAC circuit 105) is shown, but the binary counter 104 is not necessarily provided, and the ramp signal is synchronized with the clock. It is not always necessary to control. For example, a triangular wave potential may be generated by supplying electric charges to the fixed capacitor with a constant current. In this case, it is also possible to use an initial potential setting method similar to the conventional one by inserting a capacitor in series with a node that directly generates a potential and disconnecting the lamp supply destination circuit in a DC manner.

For simplicity, the UD counter 117 of the column A / D conversion circuit 106 and the output signal bus 126 are described as being directly connected, but the present invention is not limited to this. Since a configuration including a column digital memory between the UD counter 117 and the output signal bus 126 is normal, it does not matter. This is because the effectiveness of the present invention is not impaired by the presence or absence.

In the above description, an example has been shown in which only the maximum value and the minimum value are used as distribution indexes. However, the normal distribution can be obtained by monitoring the average value and standard deviation and using the distribution as a reference index. It may be monitored that there is no significant fluctuation.

Further, the case where the reference pixel area 112 exists only in the upper part of the entire pixel area (pixel array 102) has been described, but the reference pixel area 112 may be arranged in both the upper part and the lower part. Thereby, in the case of scanning by switching the image reading direction (vertical scanning direction) in the reverse order, especially when the scanning circuit is configured by a shift register, by using the lower reference pixel area instead of the upper part, The effects of the invention described in this embodiment can be obtained. However, even when the vertical scanning direction is used in the reverse order, when using a decoder type scanning circuit, it is not always necessary to arrange the reference pixel regions on both the upper and lower sides.

Further, in the reset signal level distribution acquisition circuit 119, the configuration in which the MAX operation circuit and the MIN operation circuit are commonly used for all the pixels and the reference pixels has been shown. However, although the area of the logic circuit that can be configured with fine elements slightly increases, when the distribution of all the pixels and the reference pixel is acquired simultaneously, the operation frequency of the circuit can be halved.

INDUSTRIAL APPLICABILITY The present invention can be used for a solid-state imaging device and an imaging system having a column A / D conversion circuit that receives output signals from photoelectric conversion elements arranged in a matrix. For example, a digital still camera, a mobile phone with a camera, and a surveillance camera It can be used for an image pickup apparatus and an image pickup system for detecting various physical quantity distributions such as light and radiation, which are used for a camera built in a notebook computer, a camera unit connected to an information processing device, and the like. Furthermore, the present invention can also be used for a solid-state imaging device for detecting an amount of an object such as electromagnetic waves including visible light and X-rays, or particle radiation such as alpha rays and beta rays.

100, 400, 920 Solid- state imaging device 101, 930 Pixel 102 Pixel array 103 Read signal line 104 Binary counter 105, 960 DAC circuit 106, 940 Column A / D conversion circuit 107 Comparator 108 Lamp generation circuit 109 Output buffer 112 Reference pixel Area 113 Digital preprocessing circuit 114 Clock generation circuit 115 Mode terminal 116 Control unit 117 UD counter 119 Reset signal level distribution acquisition circuit 120 Timing generation circuit 126 Output signal bus 191 All pixel MIN register 192 All pixel MAX register 193 Reference pixel MIN register 194 Reference pixel MAX register 195 MIN calculator 196 MAX calculator 200 Optical system 201 Lens 202 Shutter 300 Camera signal processing LSI
301 Image Signal Processing Unit 303 Solid-State Imaging Device Control Unit 914 Row Scanning Means 942 Comparison Circuit 944 Up / Down Counter 946 Column Scanning Means 950 Up Counter

Claims (7)

1. A solid-state imaging device including a plurality of pixels arranged in a matrix,
   The plurality of pixels are provided corresponding to each column or every plurality of columns, and have an up / down counter for counting in the up-count direction and the down-count direction, and output from the corresponding pixel by causing the up / down counter to count. A column A / D converter for A / D converting an analog signal to be converted into a digital signal;
   A distribution information acquisition unit that acquires distribution information indicating a distribution of pixel reset signal levels of a plurality of pixels that have been A / D converted by the column A / D conversion unit;
   Based on the distribution information acquired by the distribution information acquisition unit, respective count ranges allocated to count the pixel reset signal level and the pixel signal level in a predetermined counter bit width of the up / down counter A solid-state imaging device.
2. The solid-state imaging device
   By changing the count direction of the up / down counter for each pixel in each row, the column A / D converter causes the difference value between the pixel signal level and the pixel reset signal level to be A / D converted and output. Signal output mode,
   The solid-state imaging device according to claim 1, further comprising: a pixel reset output mode in which only the pixel reset signal level is A / D converted by the column A / D conversion unit and output for each pixel in each row.
3. The distribution information acquisition unit
   Based on the count range, a pixel reset signal level of the plurality of pixels A / D converted by the column A / D conversion unit and a reset signal level of a reference pixel that is a part of the plurality of pixels are obtained. To obtain first distribution information indicating a distribution of pixel reset signal levels of a plurality of pixels A / D converted by the column A / D converter,
   Based on the count range, by further acquiring a reset signal level of only the reference pixel that has been A / D converted by the column A / D converter, the column A / D converter has performed A / D conversion. Obtaining second distribution information indicating a distribution of a reset signal level of only the reference pixel;
   The control unit changes the count range from the first distribution information and the second distribution information,
   The solid-state imaging device
   3. The solid-state imaging according to claim 1, wherein the column A / D conversion unit performs A / D conversion of a pixel reset signal level and a pixel signal level of a plurality of pixels based on the count range changed by the control unit. apparatus.
4. The distribution information acquisition unit includes a maximum value and a minimum value of reset signal levels of the plurality of pixels that have been A / D converted by the column A / D conversion unit, and an A / D conversion by the column A / D conversion unit. The pixels of the plurality of pixels that have been A / D converted by the column A / D conversion unit by acquiring the maximum value and the minimum value of the reset signal level of the reference pixel that is a partial pixel of the plurality of pixels The solid-state imaging device according to any one of claims 1 to 3, wherein distribution information indicating a distribution of a reset signal level is acquired.
5. The distribution information acquisition unit includes an average value and a standard deviation of reset signal levels of the plurality of pixels A / D converted by the column A / D conversion unit, and an A / D conversion by the column A / D conversion unit. Pixels of the plurality of pixels that have been A / D converted by the column A / D conversion unit by obtaining an average value and a standard deviation of a reset signal level of a reference pixel that is a partial pixel of the plurality of pixels The solid-state imaging device according to any one of claims 1 to 3, wherein distribution information indicating a distribution of a reset signal level is acquired.
6. A solid-state imaging device according to any one of claims 1 to 5,
   An imaging system comprising: an optical system that condenses light from a subject to form an image in an imaging region of the solid-state imaging device and controls the amount of light.
7. An optical system that collects light from a subject to form an image in an imaging region of the solid-state imaging device and controls the amount of light;
   A plurality of pixels arranged in a matrix and an up / down counter that is provided corresponding to each column or each plurality of columns of the plurality of pixels and counts in the up-count direction and the down-count direction. By counting, a column A / D converter that converts an analog signal output from the corresponding pixel into a digital signal, and a pixel reset signal level and a pixel signal level in a predetermined counter bit width of the up / down counter A solid-state imaging device having a control unit for changing each count range allocated for counting;
   A distribution indicating the distribution of pixel reset signal levels of a plurality of pixels that are digitally processed for signals input from the solid-state imaging device and A / D converted by the column A / D conversion unit in the solid-state imaging device A signal processing device having a distribution information acquisition unit for acquiring information,
   The control unit switches the count range based on the distribution information acquired by the distribution information acquisition unit.

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