WO2020177125A1

WO2020177125A1 - Method for multiple analog-to-digital conversion

Info

Publication number: WO2020177125A1
Application number: PCT/CN2019/077342
Authority: WO
Inventors: Takamasa Sakuragi
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2019-03-07
Filing date: 2019-03-07
Publication date: 2020-09-10
Also published as: CN113508532A; JP7264332B2; JP2022522269A

Abstract

A method for multiple analog-to-digital conversion, includes: receiving, by an ADC among a plurality of analog-to-digital converters (ADCs), a ramp reference signal from a ramp generator; generating, by a control circuitry in the ADC, a local ramp signal based on the received ramp reference signal; comparing, by a comparator in the ADC, an analog signal input to the ADC with the local ramp signal; and generating, by the ADC, a digital signal based on an output of the comparator. The local ramp signal is generated by resetting a signal level of the received ramp reference signal to a predetermined initial level based on the output of the comparator. During a predetermined period after the resetting in at least one of the plurality of ADCs, the signal level of the ramp reference signal output from the ramp generator is retained, and a process for generating a digital signal by the ADC is suspended.

Description

METHOD FOR MULTIPLE ANALOG-TO-DIGITAL CONVERSION

Technical Field

The present disclosure relates to an analog-to-digital convertor (ADC) , and specifically, to multiple conversion ADCs. In more detail, the disclosure relates to single-slope ADCs (SS ADCs) with a multi-conversion function. The disclosure also relates to an image sensor for generating a digital image such as a static image (still picture) , or a moving image (video image) . Furthermore, the disclosure relates to an apparatus having the image sensor, such as a mobile device, a digital camera, or the like.

Background Art

A digital still camera, a digital video camera, and devices equipped with a camera capability (e.g., a mobile phone, a smart phone, a wireless communication terminal, a tablet device, a personal computer, and the like) each include an image sensor of a CMOS (Complementary Metal-Oxide-Semiconductor) or CCD (Charge Coupled Device) type or the like.

The image sensor includes a plurality of pixel cells that output analog signals of signal levels corresponding to the intensity of incident light, and a plurality of ADCs for converting those analog signals outputs from the pixel cells into digital signals.

A single slope ADC (SS ADC) is known as one type of ADC. The SS ADC causes a comparator to compare a reference signal having a ramp waveform (ramp reference signal) with an analog signal output from a pixel cell, and outputs a digital signal based on the output of the comparator. The SS ADC may reduce temporal noises such as quantization and input noises, and has advantageous characteristics of low power and a small silicon area.

Regarding the SS ADC, the specification of U.S. Patent No. 8,816,893 proposes an SS ADC having a multiple conversion capability (multiple conversion ADC) . The multiple conversion ADC performs conversion from an analog signal to a digital signal multiple times and outputs an average of the conversion results in each period of the ramp reference signal. Averaging the conversion results reduces quantization noise and the noise in the analog signal and the ramp reference signal.

The following further describes the multiple conversion ADC (ADC 90) with reference to Figs. 6 and 7. Fig. 6 is a schematic circuit diagram describing an AD convertor according to related art. Fig. 7 is a timing diagram describing modification of a ramp reference signal according to the related art.

As shown in Fig. 6, in an ADC 90, an analog signal is input to a minus (-) input of a comparator via a capacitor C0. A ramp reference signal is input to a plus (+) input of the comparator via capacitors C1 and C2. The signal level of the ramp reference signal is reset by ON/OFF switching of a switch SW1. In Fig. 6, the ramp reference signal after resetting is denoted as "modified ramp reference signal. "

The ON/OFF switching of the switch SW1 is controlled by a ramp control signal output from a control circuitry. The control circuitry performs ON/OFF switching of the switch SW1 based on the output of the comparator. For example, the control circuitry performs the ON/OFF switching in response to Hi-level signal output from the comparator when the reset ramp reference signal is equal to or lower than an input pixel signal.

For example, as shown in Fig. 7, the signal level of the ramp reference signal is reset once in a LARGE SIGNAL SAMPLING part, and its waveform is modified to a waveform including two tooth waves. In this part, one AD conversion is performed. In a SMALL SIGNAL SAMPLING part, the signal level of the ramp reference signal is reset five times, and its waveform is modified to a waveform including six tooth waves. In this part, six AD conversions are performed.

A conversion counter counts the number of AD conversions in each period of the ramp reference signal based on the output of the comparator. A summation counter counts the number of pulses of a master clock while the output of the comparator is in HI level. An arithmetic operator divides the result of counting performed by the summation counter by the result of the counting by the conversion counter to calculate an average value. This averaging reduces quantization noise and the input noise. An image sensor includes a plurality of ADCs each having the same structure of ADC 90, which are electrically connected with each other via a common ramp reference line for transmitting the ramp reference signal.

In the aforementioned ADC 90, the ON/OFF switching of the switch SW1 generates a transient current, so that a switching noise voltage can arise in the common ramp reference line due to its parasitic resistance. The switching noise voltage causes the disturbance of the waveform of the ramp reference signal, and the disturbance causes the other comparators to output an erroneous comparison result. In addition, the error in the comparator output generates noise (switching noise) in the digital signal. The disturbance of the waveform of the ramp reference signal propagates to other ADCs via the common ramp reference line. As a result, the switching noise propagating via the common reference line (that is, crosstalk noise) causes deterioration in a digital image finally output from the image sensor.

Summary of Invention

Embodiments provide an AD convertor, an image sensor, an apparatus such as a mobile device or a digital camera, a method for converting an analog signal to a digital signal, and a method for generating a digital image. For example, the mobile device may be a mobile phone, a smart phone, a wireless communication terminal, a tablet device, a personal computer, or the like, which may capture a picture and/or a video.

To achieve the foregoing objective, the following technical solutions are used in the embodiments.

A first aspect of an embodiment provides a method of doing multiple analog-to-digital conversion. The method according to the first aspect includes:

receiving, by an ADC among a plurality of analog-to-digital converters (ADCs) , a ramp reference signal from a ramp generator;

generating, by a control circuitry in the ADC, a local ramp signal based on the received ramp reference signal;

comparing, by a comparator in the ADC, an analog signal input to the ADC with the local ramp signal; and

generating, by the ADC, a digital signal based on an output of the comparator,

wherein the local ramp signal is generated by resetting a signal level of the received ramp reference signal to a predetermined initial level based on the output of the comparator, and

during a predetermined period after the resetting in at least one of the plurality of ADCs, the signal level of the ramp reference signal output from the ramp generator is retained, and a process for generating a digital signal by the ADC is suspended.

According to the first aspect, during a predetermined period after the resetting in at least one of the plurality of ADCs, a process for generating a digital signal by the ADC is suspended, making it possible to avoid disturbance caused by noise originated from the resetting in at least one of the plurality of ADCs on the digital signal.

In particular, even if the noise generated in a certain ADC propagates through the common ramp reference line to other ADCs, disturbance caused by the noise does not occur on the digital signal in any one of those ADCs, so that disturbance caused by crosstalk noise on the digital signal may also be avoided. During the period in which the process for generating the digital signal is suspended, AD conversion is not performed, which makes it possible to reduce the number of AD conversions, so that power consumption of the ADCs can be reduced. In addition, the multiple AD conversion can reduce temporal noises such as quantization noise and input noise.

In a first possible implementation form of the method according to the first aspect, the generating a digital signal includes:

counting a number of conversions in each period of the ramp reference signal;

counting a number of pulses of a master clock while the output of the comparator is in a predetermined level; and

generating the digital signal based on the counted number of conversions and the counted number of the pulses of the master clock, and

the counting a number of conversions and the counting a number of pulses of a master clock are suspended during the predetermined period after the resetting in at least one of the plurality of ADCs.

According to the first possible implementation form of the first aspect, during a predetermined period after the resetting in at least one of the plurality of ADCs, the counting the number of conversions in each period of the ramp reference signal, and the counting the number of pulses of the master clock are suspended. This makes it possible to avoid the influence of noise originated from the resetting of the received ramp reference signal on the counting result, so that even if the noise causes the comparator to output an erroneous comparison result, it is possible to avoid disturbance caused by the noise on the digital signal. In addition, the counting process stops during the period in which the counting the number of conversions and the counting the number of pulses of the master clock are suspended, so that the processing load can be reduced, thus reducing the power consumption of the ADCs.

In a second possible implementation form of the method according to the first aspect or the first possible implementation form of the first aspect, the method further includes:

receiving, by the ADC, a pulse train having a shorter period than a period of the ramp reference signal to reset the signal level of the received ramp reference signal, wherein a width of each pulse in the pulse train corresponds to the predetermined period after the resetting,

wherein the resetting a signal level of the received ramp reference signal to a predetermined initial level is performed at a rising edge of a pulse in the pulse train.

According to the second possible implementation form of the first aspect, AD conversion is performed multiple times in each period of the ramp reference signal by resetting the signal level of the received ramp reference signal based on a pulse train having a shorter period than the period of the ramp reference signal. Further, the width of each pulse in the pulse train corresponds to the predetermined period after the resetting, and the signal level of the received ramp reference signal is reset to the predetermined initial level at the rising edge of the pulse in the pulse train, making it possible to avoid disturbance caused by the noise on the digital signal, by using the pulse train. Especially, the supply of the pulse train to each ADC allows each ADC to easily implement the aforementioned control.

In a third possible implementation form of the method according to the first aspect, or the first possible implementation form or the second possible implementation form of the first aspect,

the resetting a signal level of the received ramp reference signal to a predetermined initial level is performed via switching by a switching circuitry, and

the predetermined period after the resetting is set to a period longer than a settling time of transient phenomena originated from the switching of the switching circuitry.

According to the third possible implementation form of the first aspect, the predetermined period after the resetting is set to a period longer than the settling time of transient phenomena originated from the switching of the switching circuitry, which makes it possible to avoid disturbance caused by the switching noise originated from the switching of the switching circuitry on the digital signal.

In a fourth possible implementation form of the method according to the first aspect or the second possible implementation form of the first aspect, the pulse train is set in such a way that one pulse in the pulse train appears every N pulses (N≥2) of a master clock. For example, when the resolution of AD conversion is 10 bits, N is set to 16, 32 or 64.

According to the fourth possible implementation form of the first aspect, the individual pulses in a pulse train are defined at equal intervals based on the pulses of the master clock, so that the pulse train can be easily set based on the resolution of AD conversion and the maximum number of AD conversions which can be performed in each period of the ramp reference signal.

In a fifth possible implementation form of the method according to the first aspect or the second possible implementation form or the fourth possible implementation form of the first aspect, the ramp reference signal is generated based on a pulse set extracted from a master clock during LO level duration of the pulse train.

According to the fifth possible implementation form of the first aspect, each ADC can easily perform control to stop ramping down of the ramp reference signal based on the pulse train during a period in which the process for generating the digital signal is suspended.

A second aspect of an embodiment provides multiple analog-to-digital conversion circuitry. The circuity according to the second aspect includes:

a ramp generator configured to generate a ramp reference signal; and

a plurality of analog-to-digital converters (ADCs) configured to receive the ramp reference signal from the ramp generator, an ADC among the plurality of ADCs including:

a controller configured to receive the ramp reference signal from the ramp generator, and generate a local ramp signal based on the received ramp reference signal; and

a comparator configured to compare an analog signal input to the ADC with the local ramp signal,

wherein

the controller generates a digital signal with which resets a signal level of the received ramp reference signal to a predetermined initial level based on an output of the comparator,

during a predetermined period after the resetting in at least one of the plurality of ADCs, the ramp generator keeps the signal level of the ramp reference signal constant, and

the ADC generates a digital signal based on the output of the comparator, and suspends a process for generating the digital signal during the predetermined period after the resetting.

According to the second aspect,

during a predetermined period after the resetting in at least one of the plurality of ADCs, a process for generating a digital signal by the ADC is suspended, making it possible to avoid disturbance caused by noise originated from the resetting in at least one of the plurality of ADCs on the digital signal.

In a first possible implementation form of the circuitry according to the second aspect,

the ADC performs:

counting a number of conversions in each period of the ramp reference signal;

generation of the digital signal based on the counted number of conversions and the counted number of the pulses of the master clock,

wherein the counting the number of conversions and the counting the number of pulses of a master clock are suspended during the predetermined period after the resetting in at least one of the plurality of ADCs.

According to the first possible implementation form of the second aspect,

during a predetermined period after the resetting in at least one of the plurality of ADCs, the counting the number of conversions in each period of the ramp reference signal, and the counting the number of pulses of the master clock are suspended. This makes it possible to avoid the influence of noise originated from the resetting of the received ramp reference signal on the counting result, so that even if the noise causes the comparator to output an erroneous comparison result, it is possible to avoid disturbance caused by the noise on the digital signal. In addition, the counting process stops during the period in which the counting the number of conversions and the counting the number of pulses of the master clock are suspended, so that the processing load can be reduced, thus reducing the power consumption of the ADCs.

In a second possible implementation form of the circuitry according to the second aspect or the first possible implementation form of the second aspect,

the ADC further performs receiving a pulse train having a shorter period than a period of the ramp reference signal to reset the signal level of the received ramp reference signal, wherein a width of each pulse in the pulse train corresponds to the predetermined period after the resetting,

the resetting of a signal level of the received ramp reference signal to a predetermined initial level is performed at a rising edge of a pulse in the pulse train.

According to the second possible implementation form of the second aspect, AD conversion is performed multiple times in each period of the ramp reference signal by resetting the signal level of the received ramp reference signal based on a pulse train having a shorter period than the period of the ramp reference signal. Further, the width of each pulse in the pulse train corresponds to the predetermined period after the resetting, and the signal level of the received ramp reference signal is reset to the predetermined initial level at the rising edge of the pulse in the pulse train, making it possible to avoid disturbance caused by the noise on the digital signal by using the pulse train. Especially, the supply of the pulse train to each ADC allows each ADC to easily implement the aforementioned control.

In a third possible implementation form of the circuitry according to the second aspect, or the first possible implementation form or the second possible implementation form of the second aspect,

the controller performs the resetting of a signal level of the received ramp reference signal to a predetermined initial level via switching by a switching circuitry, and

According to the third possible implementation form of the second aspect, the predetermined period after the resetting is set to a period longer than the settling time of transient phenomena originated from the switching of the switching circuitry, which makes it possible to avoid disturbance caused by the switching noise originated from the switching of the switching circuitry on the digital signal.

In a fourth possible implementation form of the circuitry according to the second aspect or the second possible implementation form of the second aspect, the pulse train is set in such a way that one pulse in the pulse train appears every N pulses (N≥2) of a master clock. For example, when the resolution of AD conversion is 10 bits, N is set to 16, 32 or 64.

According to the fourth possible implementation form of the second aspect, the individual pulses in a pulse train are defined at equal intervals based on the pulses of the master clock, so that the pulse train can be easily set based on the resolution of AD conversion and the maximum number of AD conversions which can be performed in each period of the ramp reference signal.

In a fifth possible implementation form of the method according to the second aspect, or the second possible implementation form or the fourth possible implementation form of the second aspect, the ramp generator generates the ramp reference signal based on a pulse set extracted from a master clock during LO level duration of the pulse train.

According to the fifth possible implementation form of the second aspect, each ADC can easily perform control to stop ramping down of the ramp reference signal based on the pulse train during a period in which the process for generating the digital signal is suspended.

A third aspect of an embodiment provides an image sensor. The image sensor according to the third aspect, includes:

a plurality of pixel cells configured to generate an analog signal of a level corresponding to an amount of received light through photoelectric conversion; and

a multiple analog-to-digital conversion circuitry configured to receive the analog signal output from at least one of the plurality of pixel cells as an analog signal,

the circuitry including a ramp generator configured to generate a ramp reference signal, and a plurality of analog-to-digital converters (ADCs) configured to receive the ramp reference signal from the ramp generator, an ADC among the plurality of ADCs including:

wherein

the controller generates a digital signal by resetting a signal level of the received ramp reference signal to a predetermined initial level based on an output of the comparator,

the ADC generates a digital signal based on the output of the comparator, and suspends a process of generating a digital signal during the predetermined period after the resetting.

According to the third aspect,

during a predetermined period after the resetting in at least one of the plurality of ADCs, a process of generating a digital signal by the ADC is suspended, making it possible to avoid disturbance caused by noise originated from the resetting in at least one of the plurality of ADCs on the digital signal. As a result, noise of the digital signal output from the image sensor is reduced, thus improving the quality of an output image.

In particular, even if the noise generated in a certain ADC propagates through the common ramp reference line to other ADCs, disturbance caused by the noise does not occur on the digital signal in any one of those ADCs, so that disturbance caused by crosstalk noise on the digital signal may also be avoided. Although the generation of crosstalk noise may reduce the overall quality of the image output from the image sensor, the application of the aforementioned configuration leads to avoidance of the crosstalk noise, which may notably improve the overall quality of the image output from the image sensor equipped with a vast amount of pixels.

During the period in which the process for generating the digital signal is suspended, AD conversion is not performed, which makes it possible to reduce the number of AD conversions, so that power consumption of the ADCs can be reduced. In addition, the multiple AD conversion can reduce temporal noises such as quantization noise and input noise, which contributes to further improvement of the quality of an output image.

In the first possible implementation form of the image sensor according to the third aspect, the image sensor may include the circuit according to any one of the first to fifth possible implementation forms of the second aspect.

A fourth aspect of an embodiment provides an apparatus having camera a function (s) . The apparatus according to the fourth aspect may be preferably the digital camera or the mobile device which may capture a digital image, such as a static image (astill picture) , or a moving image (avideo image) . For example, the mobile device may be a mobile phone, a smart phone, a wireless communication terminal, a tablet device, a personal computer, or the like, which may capture a picture and/or a video.

The apparatus according to the fourth aspect includes:

an image sensor including a plurality of pixel cells configured to generate an analog signal of a level corresponding to an amount of received light through photoelectric conversion, and a multiple analog-to-digital conversion circuitry configured to receive the analog signal output from at least one of the plurality of pixel cells as an analog signal,

wherein

the ADC generates a digital signal based on the output of the comparator, and suspends a process for generating a digital signal during the predetermined period after the resetting.

According to the fourth aspect, during a predetermined period after the resetting in at least one of the plurality of ADCs, a process for generating a digital signal by the ADC is suspended, making it possible to avoid disturbance caused by noise originated from the resetting in at least one of the plurality of ADCs on the digital signal. As a result, noise of the digital signal output from the image sensor is reduced, thus improving the quality of an output image.

In particular, even if the noise generated in a certain ADC propagates through the common ramp reference line to other ADCs, disturbance caused by the noise does not occur on the digital signal in any one of those ADCs, so that disturbance caused by crosstalk noise on the digital signal may also be avoided. Although the generation of crosstalk noise may reduce the overall quality of the image output from the image sensor, the application of the aforementioned configuration leads to avoidance of the crosstalk noise, which may notably improve the overall quality of the image output from the image sensor equipped with a vast amount of pixel cells.

During the period in which the process of generating the digital signal is suspended, AD conversion is not performed, which makes it possible to reduce the number of AD conversions, so that power consumption of the ADCs can be reduced. The reduction in power consumption extends the battery-based operational time in small devices such as digital cameras or mobile devices, which contributes to improvement on the usability. In addition, the multiple AD conversion can reduce temporal noises such as quantization noise and input noise, which contributes to further improvement of the quality of an output image.

In a first possible implementation form of the apparatus according to the fourth aspect, the image sensor in the apparatus may include the circuit according to any one of the first to fifth possible implementation forms of the second aspect.

Brief Description of Drawings

Fig. 1 is a schematic block diagram for describing an apparatus according to an embodiment of the present disclosure,

Fig. 2 is a schematic diagram for describing an image sensor according to the embodiment of the present disclosure,

Fig. 3 is a schematic circuit diagram for describing multiple AD conversion circuitry according to the embodiment of the present disclosure,

Fig. 4 is a schematic circuit diagram for describing a controller in the multiple AD conversion circuitry according to the embodiment of the present disclosure,

Fig. 5 is a timing diagram for describing signals and clocks in the readout circuitry according to the embodiment of the present disclosure,

Fig. 6 is a schematic circuit diagram for des cribing an AD convertor according to related art, and

Fig. 7 is a timing diagram for describing modification of a RAMP reference signal according to the related art.

Description of Embodiments

The following describes technical solutions of the embodiments, referring to the accompanying drawings. It will be understood that the embodiments described below are not all but just some of embodiments relating to the present disclosure. It is to be noted that all other embodiments which may be derived by a person skilled in the art based on the embodiments described below without creative efforts shall fall within the protection scope of the present disclosure.

With reference to Fig. 1, an apparatus 10 equipped with a camera capability will be described below. Fig. 1 is a schematic block diagram for describing an apparatus according to an embodiment of the present disclosure.

The apparatus 10 may be, for example, a mobile device, a digital camera or the like. For example, the mobile device may be a mobile phone, a smart phone, a wireless communication terminal, a tablet device, a personal computer, and the like, which may capture a picture and/or a video.

As shown in Fig. Fig. 1, an apparatus 10 includes a lens 10a, an image sensor 10b, a processing circuitry 10c, and a storage 10d. Hereinafter, the set of the lens 10a and the image sensor 10b may be referred to as "imaging unit. " The apparatus 10 may be equipped with a plurality of imaging units.

The lens 10a is an optical system that guides incident light to the image sensor 10b. The image sensor 10b convers light input via the lens 10a to an electrical signal (analog signal) through photoelectric conversion. The image sensor 10b also convers an analog signal to a digital signal. A digital signal output from the image sensor 10b is input to the processing circuitry 10c.

The processing circuitry 10c processes the digital signal output from the image sensor 10b to generate image data, and stores the generated image data into the storage 10d. For example, the processing circuitry 10c compresses/encodes a digital signal according to a compression/encoding method standardized by a standardization group, such as JPEG (Joint Photographic Experts Group) , and generates image data from the digital signal. The processing circuitry 10c may store a digital signal as RAW data into the storage 10d.

Next, the image sensor 10b will be further described with reference to Fig. 2. Fig. 2 is a schematic diagram for describing an image sensor according to the embodiment of the present disclosure.

As shown in Fig. 2, the image sensor 10b includes a control circuitry 11, a pixel array 12, and a multiple AD conversion circuitry 13.

For simplicity of illustration, the pixel array 12 is regularly shaped in Fig. 2, but in other embodiments, the pixel array 12 may have a regular or irregular arrangement and include more or less pixels, rows, and columns. Moreover, the pixel array 12 may include red, green, and blue pixels designed to capture images in the visible portion of the spectrum, or may include pixels for capturing images in the invisible portion of the spectrum, such as infra-red or ultraviolet.

For simplicity of illustration, Fig. 2 only shows two

columns

12a and 12b, each having four pixel cells. However, actual image sensors may include from hundreds to thousands of columns, and each column may include from hundreds to thousands of pixels.

Each pixel cell of the pixel array 12 outputs an analog signal having a signal level corresponding to the intensity of received light. The analog signal output from each pixel cell is input to the multiple AD conversion circuitry 13. The multiple AD conversion circuitry 13 includes a plurality of ADCs for converting analog signals to digital signals. Analog signals output from a plurality of pixel cells of a column corresponding to each ADC, for example, are input to each ADC. The control circuitry 11 controls the foregoing operations.

For example, analog signals (first pixel signals) output from the individual pixel cells of the column 12a are input to an ADC 13a in the multiple AD conversion circuitry 13. Analog signals (second pixel signals) output from the individual pixel cells of the column 12b are input to an ADC 13b in the multiple AD conversion circuitry 13.

The ADC 13a performs AD conversion on the first pixel signals to generate first digital signals. The first digital signals output from the ADC 13a are input to the processing circuitry 10c. The ADC 13b performs AD conversion on the second pixel signals to generate second digital signals. The second digital signals output from the ADC 13b are input to the processing circuitry 10c.

Next, the multiple AD conversion circuitry 13 will be further described with reference to Fig. 2. Fig. 3 is a schematic circuit diagram for describing multiple AD conversion circuitry according to the embodiment of the present disclosure.

As shown in Fig. 3, the multiple AD conversion circuitry 13 includes elements such as a ramp generator 13c, AND circuitries 13d, ADC 13a, ADC 13b, and so forth. While the multiple AD conversion circuitry 13 actually includes three or more ADCs, only the

ADCs

13a and 13b are shown in Fig. 3 for the sake of description. The multiple AD conversion circuitry 13 may also include elements for providing a master clock and elements for providing a control clock to be described later.

The ADC 13a includes a controller 131, a comparator 132, a DFF (D-Flip Flop) circuitry 133, a NOR circuitry 134, AND

circuitries

135, 136, a conversion counter 137, a counter 138, and an average calculator 139.

The ADC 13b includes a controller 141, a comparator 142, a DFF circuitry 143, a NOR circuitry 144, AND

circuitries

145, 146, a conversion counter 147, a counter 148, and an average calculator 149. The other ADCs included in the multiple AD conversion circuitry 13 have the same circuit configuration.

The master clock is input to the AND

circuitries

13d, 136, 136, 146, and so forth. An output (GATED CLOCK B) of the AND circuitry 13d is input to the ramp generator 13c. The ramp generator 13c generates a ramp reference signal synchronizing with the GATED CLOCK B. The ramp reference signal output from the ramp generator 13c is input to IN terminals of the

controllers

131, 141. The

controllers

131, 141 generate local ramp signals based on the ramp reference signal.

With reference to Fig. 4, a specific circuit configuration of the controller 131 will be described. Fig. 4 is a schematic circuit diagram for describing the controller in the multiple AD conversion circuitry according to the embodiment of the present disclosure.

As shown in Fig. 4, the controller 131 includes an IN terminal, an OUT terminal, switches SW1 and a capacitor C1. Hereinafter, for the sake of description, the switch SW1 may be referred to as switch 131a.

The switch 131a carries out ON/OFF switching according to the signal level of the signal (GATED CLOCK A1) input to the CNT terminal of the controller 131.

Specifically, when the GATED CLOCK A1 is at a HI level, the switch 131a is turned ON, when the GATED CLOCK A1 is at a LO level, on the other hand, the switch 131a is turned OFF.

The IN terminal of the controller 131 is connected to one end of the capacitor C1. The other end of the capacitor C1 is connected to one end of the switch 131a and the OUT terminal of the controller 131. A reset voltage V_RESET is supplied to the other end of the switch 131a. The controller 131 operates as a clamp circuit.

Through the above operation, when the GATED CLOCK A1 becomes a HI level, the controller 131 resets the signal level of the ramp reference signal input to the IN terminal to an initial level corresponding to the reset voltage V_RESET. During the HI level duration of the GATED CLOCK A1, the controller 131 retains the signal level at the OUT terminal at the initial level. During the LO level duration of the GATED CLOCK A1, the controller 131 supplies the ramp reference signal after the resetting to the OUT terminal.

The controller 131 generates the local ramp signal through the aforementioned method. The circuit configuration shown in Fig. 4 may be applied to the controller 141 and the controllers included in the other ADCs. In a case where the configuration is applied to the controller 141, for example, the controller 141 performs ON/OFF switching of the switch SW1 according to the signal level of the signal (GATED CLOCK A2) input to the CNT terminal of the controller 141.

With reference to Fig. 3 again, the local ramp signal (RAMP_1) output from the controller 131 is input to a minus (-) terminal of the comparator 132. The first pixel signal output from the column 12a is input to a plus (+) terminal of the comparator 132. The comparator 132 compares the RAMP_1 with the first pixel signal, and outputs an enable signal of a signal level corresponding to the result of the comparison.

For example, the comparator 132 retains the HI level during a period in which the signal level of the RAMP_1 is equal to or lower than the signal level of the first pixel signal, and outputs an enable signal (HI level signal) retaining the LO level during the other period. Specifically, the comparator 132 outputs the HI level during the RAMP_1 signal level is equal to or lower than the first pixel signal, and changes the output to the LO level synchronizing with rising time of CLK_A which causes reset of the local ramp signal. The enable signal output from the comparator 132 is input to a CLK terminal of the DFF circuitry 133 and an EN terminal, which is lo active, of the counter 138.

A HI-level (fixed) signal is input to a D (input) terminal of the DFF circuitry 133. An inverted output of the NOR circuitry 134 is input to an R (RESET) terminal of the DFF circuitry 133. The output of the comparator 132 and a control clock (CLK_A) generated from the master clock are input to the NOR circuitry 134. The CLK_A is a pulse signal such that one pulse appears every N pulses of the master clock.

When the resolution of AD conversion that is performed by the ADC 13a is 10 bits, the CLK_A is set such that one pulse appears every 64 pulses of the master clock provided that the maximum number of multiple AD conversions is set to "16. " That is, N is set to 64 (64=1024/16) . The NOR circuitry 134 performs a NOR operation of the CLK_A and the output of the comparator 132. The result of the operation performed by the NOR circuitry 134 is input to the R terminal of the DFF circuitry 133 after being inverted.

A signal output from a Q (output) terminal of the DFF circuitry 133 is input to the AND circuitry 135. The output of the DFF circuitry 133 and the CLK_A are input to the AND circuitry 135. The AND circuitry 135 performs an AND operation of the output of the DFF circuitry 133 and the CLK_A. The result of the operation performed by the AND circuitry 135 is input as GATED CLOCK A1 to the CNT terminal of the controller 131 and the conversion counter 137.

The conversion counter 137 counts the number of pulses of the GATED CLOCK A1. As described above, when the GATED CLOCK A1 is at the HI level, the controller 131 resets the signal level of the ramp reference signal, and outputs the ramp reference signal after the resetting as RAMP_1. Since the number of times resetting is performed by the conversion counter 137 corresponds to the number of pulses of the RAMP_1, the number of pulses of the GATED CLOCK A1 corresponds to the number of AD conversions performed by the ADC 13a.

The output of the conversion counter 137 is input to the average calculator 139. The output of the counter 138 is also input to the average calculator 139. The counter 138 counts the number of pulses of the signal input to the clock terminal during the HI level duration of the signal input to the EN terminal. As described above, the output of the comparator 132 is input to the EN terminal, which is lo active, of the counter 138. A signal (GATED CLOCK B) output from the AND circuitry 136 is input to the clock terminal of the counter 138.

The master clock and the inverted CLK_A are input to the AND circuitry 136. The AND circuitry 136 performs an AND operation of the master clock and the inverted CLK_A, and outputs the result of the operation as GATED CLOCK B. In other words, the GATED CLOCK B is a set of pulses in the master clock which is extracted during the LO level duration of the CLK_A.

The GATED CLOCK B is also generated by the AND circuitry 13d, and is also supplied to the ramp generator 13c. The ramp generator 13c generates the ramp reference signal based on the GATED CLOCK B. Accordingly, during a period in which no pulse of the GATED CLOCK B is present, the signal level of the ramp reference signal is retained at the signal level at the start time of that period. That is, during the HI level duration of the CLK_A, the signal level of the ramp reference signal becomes constant. During this period, the number of counts in the counter 138 will not be increased.

Attention is paid to the GATED CLOCK A1 output from the AND circuitry 135. As described above, the GATED CLOCK A1 is the signal obtained by gating the output of the DFF circuitry 133 with the pulse of the CLK_A. The GATED CLOCK A1 is then input to the CNT terminal of the controller 131, and is used for ON/OFF control over the switches 131a. In other words, ON/OFF control over the switches 131a is executed at the rising edge of a pulse of the CLK_A.

As described above, during the HI level duration of the CLK_A, the ramp generator 13c keeps the level of the ramp reference signal constant, and the counter 138 suspends its counting. That is, during the HI level duration of the CLK_A, AD conversion in the ADC 13a is suspended. During the HI level duration of the CLK_A, AD conversion in the ADC 13b is also suspended. Therefore, switching noise if generated by the ON/OFF control over the switch 131a does not affect AD conversion in the

ADCs

13a, 13b. Namely, the crosstalk noise does not affect AD conversion in each ADC of the image sensor.

As described above, the outputs of the conversion counter 137 and the counter 138 are input to the average calculator 139. The average calculator 139 divides the output of the counter 138 by the output of the conversion counter 137 to calculate an average number of pulses of the master clock in a single AD conversion. The average calculator 139 then outputs a sequence of bit values corresponding to the calculated average number of pulses as a first digital signal.

The ADC 13b and the other ADCs included in the multiple AD conversion circuitry 13 have the same configuration as the configuration of the ADC 13a.

For example, the controller 141 corresponds to the aforementioned controller 131. The comparator 142 corresponds to the aforementioned comparator 132. The DFF circuitry 143 corresponds to the aforementioned DFF circuitry 133. The NOR circuitry 144 corresponds to the aforementioned NOR circuitry 134. The AND

circuitries

145 and 146 respectively correspond to the aforementioned AND

circuitries

135 and 136. The conversion counter 147 corresponds to the aforementioned conversion counter 137. The counter 148 corresponds to the aforementioned counter 138. The average calculator 149 corresponds to the aforementioned average calculator 139.

It should be noted however that a second pixel signal output from the column 12b is input to the + terminal of the comparator 142. As a result, the local ramp signal (RAMP_2) output from the controller 141 differs from the RAMP_1 output from the controller 131. In addition, a signal (GATED CLOCK A2) output from the AND circuitry 145 and input to the CNT terminal of the controller 141 as well as to the conversion counter 147 differs from the GATED CLOCK A1 output from the AND circuitry 135. Further, a second digital signal is output from the average calculator 149.

As described above, the

ADCs

13a and 13b as well as the other ADCs operate based on the same master clock, ramp reference signal and CLK_A. When the ramp reference signal is reset in any one of the ADCs, therefore, switching noise is transferred through the common line for the ramp reference signal. As described above, however, during the HI level duration of the CLK_A, each ADC suspends AD conversion to avoid the influence of the switching noise. As a result, crosstalk noise is also avoided in the multiple AD conversion circuitry 13.

Next, specific operations of the

ADCs

13a and 13b will be further described with reference to Fig. 5. Fig. 5 is a timing diagram for describing signals and clocks in the readout circuitry according to the embodiment of the present disclosure.

In the example of Fig. 5, it is assumed that the signal level of the first pixel signal is higher than the signal level of the second pixel signal.

At timing T0, the ramp generator 13c starts ramping down its output in synchronization with the GATED CLOCK B. The

counter

138, 148 starts an operation of counting the pulses of the GATED CLOCK B.

At timing T1, the signal level of the ramp reference signal reaches the signal level of the first pixel signal. At this time, the output of the comparator 132 becomes a HI level, and the output of the DFF circuitry 133 becomes a HI level. Then, the counting by the counter 138 is suspended. Meanwhile, the counter 148 continues the counting operation for the AD conversion for the second pixel signal.

At timing T2, the CLK_A becomes a HI level. The GATED CLOCK A1 becomes a HI level, causing the conversion counter 137 to perform counting. That is, the counter indicating the number of AD conversions is incremented by "1. " The GATED CLOCK B becomes a LO level. That is, the supply of the master clock to the

counter

138, 148 is suspended. The controller 131 resets the signal level of the RAMP_1 to the initial level. The ramp generator 13c suspends ramping down of its output.

As described above, at timing T2, the RAMP_1 is reset for the next AD conversion. Then, the charge/discharge current is generated on the common ramp reference line due to the ON/OFF switching of the switch 131a, so that transient phenomena may appear on the ramp reference signal (see the part denoted by reference symbol "FL" ) . When the disturbance of the ramp reference signal becomes large, for example, the disturbance causes the RAMP_2 to cross the second pixel signal, so that a signal based on an erroneous comparison result may be output from the comparator 142.

As described above, however, in the multiple AD conversion circuitry 13 according to the present embodiment, the supply of the master clock to the

counter

138, 148 is suspended. Therefore, even if a signal based on an erroneous comparison result is output from the comparator 142, the counter 148 does not perform counting, so that the result of AD conversion is hardly affected. To obtain such an effect, it is preferable to set the pulse width of the CLK_A substantially longer than the settling time of the transient phenomena.

At timing T3, the CLK_A becomes a LO level. The ramp generator 13c restarts ramping down its output. Accordingly, the RAMP_1 is ramped down from the initial level for the next AD conversion. The RAMP_2 is ramped down from the signal level of the ramp reference signal at timing T2. The DFF circuitry 133 resets the output, so that the GATED CLOCK A1 becomes a LO level. The

counter

138, 148 restarts counting the pulses to be supplied as the GATED CLOCK B.

At timing T4, the level of the RAMP_2 reaches the signal level of the second pixel signal. At this time, the output of the comparator 142 becomes a HI level. The output of the DFF circuitry 143 becomes a HI level, so that the counter 148 suspends the counting operation. At timing T4, the CLK_A is at a LO level, and a pulse of the master clock is supplied as GATED CLOCK B to the ramp generator 13c. As a result, the ramp generator 13c keeps generating the ramp reference signal.

At timing T5, the level of the RAMP_1 reaches the signal level of the first pixel signal again. At this time, the output of the comparator 132 becomes a HI level. The output of the DFF circuitry 133 becomes a HI level, so that the counter 138 suspends the counting operation.

At timing T6, the CLK_A becomes a HI level. The GATED CLOCKs A1 and A2 become a HI level, so that the number of counts in each of the conversion counters 137 and 147 is incremented by "1. " The signal levels of the RAMP_1 and RAMP_2 are reset to the initial levels.

At timing T7, the CLK_A becomes a LO level. The GATED CLOCKs A1 and A2 become a LO level, so that the next AD conversion for the first pixel signal and the second pixel signal starts, and the

counters

138 and 148 restarts the counting operation.

At timing T8, the signal level of the RAMP_1 reaches the signal level of the first pixel signal. At this time, the output of the comparator 132 becomes a HI level, and the counter 138 suspends the counting. Meanwhile, as the signal level of the RAMP_2 does not reach the signal level of the second pixel signal, the counter 148 continues the counting operation.

At timing T9, the CLK_A becomes a HI level. Then, the counter 148 suspends the counting operation, and the ramp generator 13c suspends outputting of the ramp reference signal. The conversion counter 137 increments the number of counts indicating the number of AD conversions for the first pixel signal by "1" according to the GATED CLOCK A1. The conversion counter 147 increments the number of counts indicating the number of AD conversions for the first pixel signal by "1" according to the GATED CLOCK A2.

The operation of repeating the aforementioned AD conversion continues until the number of pulses of the CLK_A reaches a predetermined number N (e.g., N=16) . After this operation is finished, the

average calculators

139 and 149 average the count numbers in the

counters

138 and 148 based on the count numbers in the conversion counters 137 and 147 (the numbers of AD conversions in one period of the ramp reference signal) to each calculate the averaged number of pulses of the master clock in a single AD conversion. This averaging calculation reduces temporal noises such as quantization noise and input noise.

It is to be noted that the circuit configuration and the operation of the multiple AD conversion circuitry 13 described so far are merely illustrative for description, and this example may be modified in the form of various other embodiments. For example, the resolution of AD conversion may be set to other values than 10 bits, and the number of pulses N of the CLK_A may be set to other numbers than "16. " Although, with regard to the arrangement of pulses of the CLK_A, the foregoing description illustrates as a preferable example a pulse train including pulses arranged at equal intervals, the pulses of the CLK_A may be arranged at unequal intervals. Those modifications are also encompassed within the technical scope of the present disclosure.

As described above, the embodiments of the present disclosure makes it possible to avoid the influence of switching noise on the result of AD conversion in each ADC. In particular, it is possible to avoid the influence of switching noise generated in a certain ADC on the results of AD conversions in the other ADCs, thus effectively suppressing generation of crosstalk noise in a vast amount of ADCs equipped in an image sensor. In addition, the multiple AD conversion reduces temporal noises. Those advantages enhance the quality of digital signals output from the image sensor. Such an enhancement of the image quality contributes to an enhancement of the quality of output images captured by the apparatus 10.

The foregoing disclosure merely discloses exemplary embodiments, and is not intended to limit the protection scope of the present invention. It will be appreciated by those skilled in the art that the foregoing embodiments and all or some of other embodiments and modifications which may be derived based on the scope of claims of the present invention will of course fall within the scope of the present invention.

Claims

A method for multiple analog-to-digital conversion, comprising:

receiving, by an ADC among a plurality of analog-to-digital converters (ADCs) , a ramp reference signal from a ramp generator;

generating, by a control circuitry in the ADC, a local ramp signal based on the received ramp reference signal;

comparing, by a comparator in the ADC, an analog signal input to the ADC with the local ramp signal; and

generating, by the ADC, a digital signal based on an output of the comparator,

wherein the local ramp signal is generated by resetting a signal level of the received ramp reference signal to a predetermined initial level based on the output of the comparator, and

during a predetermined period after the resetting in at least one of the plurality of ADCs, the signal level of the ramp reference signal output from the ramp generator is retained, and a process for generating a digital signal by the ADC is suspended.
The method according to claim 1, wherein the generating a digital signal includes:

counting a number of conversions in each period of the ramp reference signal;

counting a number of pulses of a master clock while the output of the comparator is in a predetermined level; and

generating the digital signal based on the counted number of conversions and the counted number of the pulses of the master clock, and

the counting a number of conversions and the counting a number of pulses of a master clock are suspended during the predetermined period after the resetting in at least one of the plurality of ADCs.
The method according to claim 1 or 2, further comprising:

receiving, by the ADC, a pulse train having a shorter period than a period of the ramp reference signal to reset the signal level of the received ramp reference signal, wherein a width of each pulse in the pulse train corresponds to the predetermined period after the resetting,

wherein the resetting a signal level of the received ramp reference signal to a predetermined initial level is performed at a rising edge of a pulse in the pulse train.
The method according to any one of claims 1 to 3, wherein

the resetting a signal level of the received ramp reference signal to a predetermined initial level is performed via switching by a switching circuitry, and

the predetermined period after the resetting is set to a period longer than a settling time of transient phenomena originated from the switching of the switching circuitry.
The method according to claim 3, wherein

the pulse train is set in such a way that one pulse in the pulse train appears every N pulses (N≥2) of a master clock.
The method according to claim 3 or 5, wherein

the ramp reference signal is generated based on a pulse set extracted from a master clock during LO level duration of the pulse train.
The method according to claim 5, wherein

the N is set to 16, 32 or 64.
A multiple analog-to-digital conversion circuitry, comprising:

a ramp generator configured to generate a ramp reference signal; and

a plurality of analog-to-digital converters (ADCs) configured to receive the ramp reference signal from the ramp generator, an ADC among the plurality of ADCs including:

a controller configured to receive the ramp reference signal from the ramp generator, and generate a local ramp signal based on the received ramp reference signal; and

a comparator configured to compare an analog signal input to the ADC with the local ramp signal, wherein

the controller generates a digital signal with which resets a signal level of the received ramp reference signal to a predetermined initial level based on an output of the comparator,

during a predetermined period after the resetting in at least one of the plurality of ADCs, the ramp generator keeps the signal level of the ramp reference signal constant, and

the ADC generates a digital signal based on the output of the comparator, and suspends a process of generating a digital signal during the predetermined period after the resetting.
The circuitry according to claim 8, wherein the ADC performs:

counting a number of conversions in each period of the ramp reference signal;

counting a number of pulses of a master clock while the output of the comparator is in a predetermined level; and

generation of the digital signal based on the counted number of conversions and the counted number of the pulses of the master clock,

wherein the counting a number of conversions and the counting a number of pulses of a master clock are suspended during the predetermined period after the resetting in at least one of the plurality of ADCs.
The circuitry according to claim 8 or 9, wherein

the ADC further performs receiving a pulse train having a shorter period than a period of the ramp reference signal to reset the signal level of the received ramp reference signal, wherein a width of each pulse in the pulse train corresponds to the predetermined period after the resetting,

the resetting a signal level of the received ramp reference signal to a predetermined initial level is performed at a rising edge of a pulse in the pulse train.
The circuitry according to any one of claims 8 to 10, wherein

the controller performs the resetting of a signal level of the received ramp reference signal to a predetermined initial level via switching by a switching circuitry, and

the predetermined period after the resetting is set to a period longer than a settling time of transient phenomena originated from the switching of the switching circuitry.
The circuitry according to claim 10, wherein

the pulse train is set in such a way that one pulse in the pulse train appears every N pulses (N≥2) of a master clock.
The circuitry according to claim 10 or 12, wherein

the ramp generator generates the ramp reference signal based on a pulse set extracted from a master clock during LO level duration of the pulse train.
The circuitry according to claim 12, wherein

the N is set to 16, 32 or 64.
An image sensor comprising:

a plurality of pixel cells configured to generate an analog signal of a level corresponding to an amount of received light through photoelectric conversion; and

a multiple analog-to-digital conversion circuitry configured to receive the analog signal output from at least one of the plurality of pixel cells as an analog signal,

the circuitry including a ramp generator configured to generate a ramp reference signal, and a plurality of analog-to-digital converters (ADCs) configured to receive the ramp reference signal from the ramp generator, an ADC among the plurality of ADCs including:

a controller configured to receive the ramp reference signal from the ramp generator, and generate a local ramp signal based on the received ramp reference signal; and

a comparator configured to compare an analog signal input to the ADC with the local ramp signal, wherein

the controller generates a digital signal by resetting a signal level of the received ramp reference signal to a predetermined initial level based on an output of the comparator,

during a predetermined period after the resetting in at least one of the plurality of ADCs, the ramp generator keeps the signal level of the ramp reference signal constant, and

the ADC generates a digital signal based on the output of the comparator, and suspends a process for generating a digital signal during the predetermined period after the resetting.
The image sensor according to claim 15, wherein the ADC performs:

counting a number of conversions in each period of the ramp reference signal;

counting a number of pulses of a master clock while the output of the comparator is in a predetermined level; and

generation of the digital signal based on the counted number of conversions and the counted number of the pulses of the master clock,

wherein the counting a number of conversions and the counting a number of pulses of a master clock are suspended during the predetermined period after the resetting in at least one of the plurality of ADCs.
The image sensor according to claim 15 or 16, wherein

the ADC further performs receiving a pulse train having a shorter period than a period of the ramp reference signal to reset the signal level of the received ramp reference signal, wherein a width of each pulse in the pulse train corresponds to the predetermined period after the resetting,

the resetting a signal level of the received ramp reference signal to a predetermined initial level is performed at a rising time of a pulse in the pulse train.
The image sensor according to any one of claims 15 to 17, wherein

the controller performs the resetting of a signal level of the received ramp reference signal to a predetermined initial level via switching by a switching circuitry, and

the predetermined period after the resetting is set to a period longer than a settling time of transient phenomena originated from the switching of the switching circuitry.
The image sensor according to claim 17, wherein

the pulse train is set in such a way that one pulse in the pulse train appears every N pulses (N≥2) of a master clock.
The image sensor according to claim 17 or 19, wherein

the ramp generator generates the ramp reference signal based on a pulse set extracted from a master clock during LO level duration of the pulse train.
The image sensor according to claim 19, wherein

the N is set to 16, 32 or 64.
An apparatus equipped with a camera capability, the apparatus comprising:

an image sensor including a plurality of pixel cells configured to generate an analog signal of a level corresponding to an amount of received light through photoelectric conversion, and a multiple analog-to-digital conversion circuitry configured to receive the analog signal output from at least one of the plurality of pixel cells as an analog signal,

the circuitry including a ramp generator configured to generate a ramp reference signal, and a plurality of analog-to-digital converters (ADCs) configured to receive the ramp reference signal from the ramp generator, an ADC among the plurality of ADCs including:

a controller configured to receive the ramp reference signal from the ramp generator, and generate a local ramp signal based on the received ramp reference signal; and

a comparator configured to compare an analog signal input to the ADC with the local ramp signal, wherein

the controller generates a digital signal by resetting a signal level of the received ramp reference signal to a predetermined initial level based on an output of the comparator,

during a predetermined period after the resetting in at least one of the plurality of ADCs, the ramp generator keeps the signal level of the ramp reference signal constant, and

the ADC generates a digital signal based on the output of the comparator, and suspends a process for generating a digital signal during the predetermined period after the resetting.
The apparatus according to claim 22, wherein the ADC performs:

counting of a number of conversions in each period of the ramp reference signal;

counting of a number of pulses of a master clock while the output of the comparator is in a predetermined level; and

generation of the digital signal based on the counted number of conversions and the counted number of the pulses of the master clock,

wherein the counting of a number of conversions and the counting of a number of pulses of a master clock are suspended during the predetermined period after the resetting in at least one of the plurality of ADCs.
The apparatus according to claim 22 or 23, wherein

the ADC further performs receiving a pulse train having a shorter period than a period of the ramp reference signal to reset the signal level of the received ramp reference signal, wherein a width of each pulse in the pulse train corresponds to the predetermined period after the resetting,

the resetting of a signal level of the received ramp reference signal to a predetermined initial level is performed at a rising time of a pulse in the pulse train.
The apparatus according to any one of claims 22 to 24, wherein

the controller performs the resetting of a signal level of the received ramp reference signal to a predetermined initial level via switching by a switching circuitry, and

the predetermined period after the resetting is set to a period longer than a settling time of transient phenomena originated from the switching of the switching circuitry.
The apparatus according to claim 24, wherein

the pulse train is set in such a way that one pulse in the pulse train appears every N pulses (N≥2) of a master clock.
The apparatus according to claim 24 or 26, wherein

the ramp generator generates the ramp reference signal based on a pulse set extracted from a master clock during LO level duration of the pulse train.
The apparatus according to claim 26, wherein

the N is set to 16, 32 or 64.