WO2021007843A1

WO2021007843A1 - Method for multiple analog-to-digital conversion

Info

Publication number: WO2021007843A1
Application number: PCT/CN2019/096508
Authority: WO
Inventors: Takamasa Sakuragi
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2019-07-18
Filing date: 2019-07-18
Publication date: 2021-01-21
Also published as: CN114128150A

Abstract

Provided is a method for multiple analog-to-digital conversion by an analog-to-digital convertor (ADC), comprising: receiving a first ramp reference signal whose level changes along a slope from an initial level during each period of the first ramp reference signal, and a second ramp reference signal whose level tracks the first ramp reference signal with a given offset from the level of the first ramp reference signal; comparing the second ramp reference signal with an input analog signal; sampling a level of the first ramp reference signal when the second ramp reference signal reaches the analog input signal, and resetting a level of the second ramp reference signal to the level sampled from the first ramp reference signal after the sampling; and generating a digital signal based on results of the comparing, where the comparing, the sampling and the resetting are performed multiple times in said each period of the first ramp reference signal, and the comparing after the resetting is performed by using the reset second ramp reference signal.

Description

METHOD FOR MULTIPLE ANALOG-TO-DIGITAL CONVERSION

TECHNICAL FIELD

The present disclosure relates to an analog-to-digital convertor (ADC) , specifically, to multiple conversion ADCs. The disclosure also relates to an image sensor for generating a digital image such as a static image (still picture) , or a moving image (video image) , and an apparatus having the image sensor such as mobile equipment or a digital camera.

BACKGROUND

In recent, mobile equipment such as a mobile phone, a smart phone, a wireless communication terminal, a tablet device or a personal computer has a camera function. The mobile equipment or a digital camera is equipped with an image sensor such as a CMOS (Complementary Metal-Oxide-Semiconductor) image sensor or CCD (Charge Coupled Device) image sensor.

The image sensor includes a plurality of pixels that output analog signals with signal levels each corresponding to intensity of incident light, and a plurality of ADCs for converting those output analog signals into digital signals.

A single slope ADC (SS ADC) is known as one type of ADC. The SS ADC causes a comparator to compare a ramp reference signal having a ramp waveform with an analog signal output from a pixel , and outputs a digital signal based on an output signal from the comparator. In the SS ADC, temporal noises such as quantization and input noises may be reduced, and lower power consumption and a smaller silicon area may be achieved.

With regard to the SS ADC, U.S. Patent No. 8,816,893 proposes multiple conversion ADCs which performs conversion from an analog signal to a digital signal multiple times and outputs an average of the conversion results in each period of the ramp reference signal. With the use of the multiple conversion procedure, quantization noise and the noise in the analog signal may be effectively reduced.

The following further describes the multiple conversion ADC with reference to Figs. 10 and 11. Fig. 10 is a schematic circuit diagram for describing an ADC according to related art. Fig. 11 is a timing diagram for describing the multiple conversion procedure according to the related art. ADC 90 shown in Fig. 10 is an example of the multiple conversion ADC according to the related art.

As shown in Fig. 10, an analog signal is fed to a minus (-) input terminal of a comparator via a capacitor C0. A ramp reference signal is fed to a plus (+) input terminal of the comparator via capacitors C1 and C2. The ramp reference signal is modified by resetting the level of the ramp reference signal responding to ON/OFF switching of a switch SW1. In Fig. 10, the ramp reference signal after the resetting is denoted as "modified ramp reference signal. "

The ON/OFF switching of the switch SW1 is controlled by a ramp control signal output from control circuitry according to the output of the comparator. For example, the control circuitry performs the ON/OFF switching in response to Hi-level signal output from the comparator when the modified ramp reference signal is equal to or lower than an input pixel signal.

In an example shown in Fig. 11, the level of the ramp reference signal is reset once in a part labelled as "LARGE SIGNAL SAMPLING" , and a waveform of the ramp reference signal is modified to a waveform with two tooth waves. In this part, the AD conversion is performed once. In a part labelled as "SMALL SIGNAL SAMPLING" , the level of the ramp reference signal is reset five times, and the waveform of the ramp reference signal is modified to a waveform with six tooth waves. In this part, the AD conversion is performed six times.

A conversion counter counts the number of times of the performed AD conversion in each period of the ramp reference signal based on the output of the comparator. A summation counter counts the number of pulses of a master clock while the output of the comparator is in LO level. An arithmetic operator calculates average values based on counted values by the summation counter and counted values by the conversion counter. By doing averaging, quantization noise and the input noise may be reduced. However, a conversion rate of the ADC 90 is lower than that of the conventional SS ADC performing a single AD conversion during each period of the ramp reference signal.

SUMMARY

Embodiments provide an ADC, an image sensor, an apparatus such as mobile equipment or a digital camera, and a method for multiple analog-to-digital conversion. The mobile equipment may be a mobile phone, a smart phone, a wireless communication terminal, a tablet device, a personal computer, or the like, and the mobile equipment and the digital camera may generate digital image data such as picture data or video data.

A first aspect of the embodiments provides the method for multiple analog-to-digital conversion by an ADC. In a first possible implementation form of the first aspect, the method includes:

receiving a first ramp reference signal whose level changes along a slope from an initial level during each period of the first ramp reference signal, and a second ramp reference signal whose level tracks the first ramp reference signal with a given offset from the level of the first ramp reference signal;

comparing the second ramp reference signal with an input analog signal;

sampling a level of the first ramp reference signal just when the second ramp reference signal reaches the analog input signal, and resetting a level of the second ramp reference signal to the level sampled from the first ramp reference signal after the sampling; and

generating a digital signal based on results of the comparing, wherein the comparing, the sampling and the resetting are performed multiple times in said each period of the first ramp reference signal, and the comparing after the resetting is performed by using the reset second ramp reference signal.

In the first possible implementation form of the first aspect, AD conversion is performed multiple times during a single period of the first ramp reference signal, the level sampled from the first ramp reference signal in former AD conversion is used as a starting point of the reset second ramp reference signal. For example, if the level of the ramp reference signal monotonically decreases along the slope, the reset second ramp reference signal slopes down from the level sampled from the first ramp reference signal. On the other hand, if the level of the ramp reference signal monotonically increases along the slope, the reset second ramp reference signal slopes up from the level sampled from the first ramp reference signal. According to this configuration, an amplitude of the second ramp reference signal is reduced by the resetting, so that the reset second ramp reference signal may reach the input analog signal in a short time. This configuration reduces a time necessary for the AD conversion, so that the number of times of the AD conversion can be increased effectively without sacrificing the AD conversion speed. Increasing the number of times of the AD conversion makes it possible to improve signal-to-noise ratio of the digital signals and quality of output images based on the digital signals.

A second possible implementation form of the first aspect provides: the method according to the first possible implementation form of the first aspect, wherein the given offset is determined based on temporal noises in the input analog signal and the first and second reference signals, and an input-referred noise of a comparator performing the comparing. According to the second possible implementation form of the first aspect, the resetting can be surely performed even when the temporal noises and the input-referred noise exist.

A third possible implementation form of the first aspect provides; the method according to the second possible implementation form of the first aspect, wherein the given offset is set to be a larger value than a total of the temporal noises in peak-to-peak magnitude. According to the third possible implementation form of the first aspect, the resetting can be surely performed under the situation where the temporal noises in the input analog signal and the first and second reference signals exist.

A fourth possible implementation form of the first aspect provides: the method according to the second or third possible implementation form of the first aspect, wherein the first reference signal is fed to the comparator through a capacitive member, and the second reference signal is used as a clamp voltage of the capacitive member. According to the fourth possible implementation form of the first aspect, the level sampled from the first ramp reference signal may be held in the capacitive member just when the second ramp reference signal reaches the analog input signal.

A fifth possible implementation form of the first aspect provides: the method according to any one of the first to fourth possible implementation forms of the first aspect, wherein the level of the first ramp reference signal slopes down from the initial level during said each period of the first ramp reference signal, and polarity of the given offset is set to be negative. In case of using a slope-down type signal as the first and second ramp reference signal, the fifth possible implementation form of the first aspect may be preferably applied.

A sixth possible implementation form of the first aspect provides: the method according to any one of the first to fourth possible implementation forms of the first aspect, wherein the level of the first ramp reference signal slopes up from the initial level during said each period of the first ramp reference signal, and polarity of the given offset is set to be positive. In case of using a slope-up type signal as the first and second ramp reference signal, the sixth possible implementation form of the first aspect may be preferably applied.

A seventh possible implementation form of the first aspect provides: the method according to any one of the first to sixth possible implementation forms of the first aspect, wherein the ADC is connected to other ADCs via common reference lines for distributing the first and second reference signals to the ADC and the other ADCs, and the generating by the ADC is suspended during a predetermined period after the resetting in at least one of the ADC and the other ADCs.

In general, an image sensor includes a plurality of ADCs which are electrically connected with each other via a common ramp reference line for transmitting a ramp reference signal. If ON/OFF switching for resetting the ramp reference signal is performed, the ON/OFF switching may generate a transient current which causes a switching noise arising in the common ramp reference line due to its parasitic resistance. The switching noise causes disturbance of the ramp reference signal that propagates to other ADCs via the common ramp reference line and acts as a crosstalk noise. The crosstalk noise may cause comparison errors in comparators of the other ADCs and decrease quality of a digital image finally output from the image sensor.

According to the seventh possible implementation form of the first aspect, the generating by the ADC is suspended during the predetermined period after the resetting, thus making it possible to avoid comparison errors in the comparing and realize a high quality digital image that is finally output from the image sensor.

An eighth possible implementation form of the first aspect provides: the method according to any one of the first to seventh possible implementation forms of the first aspect, wherein the receiving includes: receiving the second ramp reference signal from a ramp generator, and generating the first ramp reference signal based on the received second ramp reference signal. According to the eighth possible implementation form of the first aspect, the first and second ramp reference signals may be generated by the single ramp generator.

A ninth possible implementation form of the first aspect provides: the method according to any one of the first to seventh possible implementation forms of the first aspect, wherein the receiving includes: receiving the first ramp reference signal from a ramp generator, and generating the second ramp reference signal based on the received first ramp reference signal. According to the eighth possible implementation form of the first aspect, the first and second ramp reference signals may be generated by the single ramp generator.

A tenth possible implementation form of the first aspect provides: the method according to any one of the first to ninth possible implementation forms of the first aspect, wherein the generating includes: retaining a result of the comparing in each AD conversion, averaging retained results of the comparing during said each period of the first ramp reference signal, and determining the digital signal based on the averaged result. According to the tenth possible implementation form of the first aspect, quantization and input noises can be reduced by averaging the retained results of the comparing.

A second aspect of the embodiments provides the analog-to-digital convertor (ADC) performing multiple analog-to-digital conversion. In a first possible implementation form of the second aspect, the ADC comprising:

a receiving unit configured to perform receiving a first ramp reference signal whose level changes along a slope from an initial level during each period of the first ramp reference signal, and a second ramp reference signal whose level tracks the first ramp reference signal with a given offset from the level of the first ramp reference signal;

a comparing unit configured to perform comparing the second ramp reference signal with an input analog signal;

a resetting unit configured to perform sampling a level of the first ramp reference signal just when the second ramp reference signal reaches the analog input signal, and perform resetting a level of the second ramp reference signal to the level sampled from the first ramp reference signal after the sampling; and

a generating unit configured to perform generating a digital signal based on the results of the comparing, wherein the comparing, the sampling and the resetting are performed multiple times in said each period of the first ramp reference signal, and the comparing after the resetting is performed by using the reset second ramp reference signal.

In the first possible implementation form of the second aspect, AD conversion is performed multiple times during a single period of the first ramp reference signal, the level sampled from the first ramp reference signal in former AD conversion is used as a starting point of the reset second ramp reference signal. For example, if the level of the ramp reference signal monotonically decreases along the slope, the reset second ramp reference signal slopes down from the level sampled from the first ramp reference signal. On the other hand, if the level of the ramp reference signal monotonically increases along the slope, the reset second ramp reference signal slopes up from the level sampled from the first ramp reference signal. According to this configuration, an amplitude of the second ramp reference signal is reduced by the resetting, so that the reset second ramp reference signal may reach the input analog signal in a short time. This configuration reduces a time necessary for the AD conversion, so that the number of times of the AD conversion can be increased effectively without sacrificing the AD conversion speed. Increasing the number of times of the AD conversion makes it possible to improve signal-to-noise ratio of the digital signals and quality of output images based on the digital signals.

A second possible implementation form of the second aspect provides: the ADC according to first possible implementation form of the second aspect, wherein the given offset is determined based on temporal noises in the input analog signal and the first and second reference signals, and an input-referred noise of a comparator performing the comparing. According to the second possible implementation form of the second aspect, the resetting can be surely performed even when the temporal noises and the input-referred noise exist.

A third possible implementation form of the second aspect provides; the ADC according to the second possible implementation form of the second aspect, wherein the given offset is set to be a larger value than a total of the temporal noises in peak-to-peak magnitude. According to the third possible implementation form of the second aspect, the resetting can be surely performed under the situation where the temporal noises in the input analog signal and the first and second reference signals exist.

A fourth possible implementation form of the second aspect provides; the ADC according to the second or third possible implementation form of the second aspect, wherein the first reference signal is fed to the comparing unit through a capacitive member, and the second reference signal is used as a clamp voltage of the capacitive member. According to the fourth possible implementation form of the second aspect, the level sampled from the first ramp reference signal may be held in the capacitive member just when the second ramp reference signal reaches the analog input signal.

A fifth possible implementation form of the second aspect provides; the ADC according to any one of the first to fourth possible implementation forms of the second aspect, wherein the level of the first ramp reference signal slopes down from the initial level during said each period of the first ramp reference signal, and polarity of the given offset is set to be negative. In case of using a slope-down type signal as the first and second ramp reference signal, the fifth possible implementation form of the second aspect may be preferably applied.

A sixth possible implementation form of the second aspect provides; the ADC according to any one of the first to fourth possible implementation forms of the second aspect, wherein the level of the first ramp reference signal slopes up from the initial level during said each period of the first ramp reference signal, and polarity of the given offset is set to be positive. In case of using a slope-up type signal as the first and second ramp reference signal, the sixth possible implementation form of the second aspect may be preferably applied.

A seventh possible implementation form of the second aspect provides; the ADC according to any one of the first to sixth possible implementation forms of the second aspect, wherein the ADC is connected to other ADCs via common reference lines for distributing the first and second reference signals to the ADC and the other ADCs, and the generating by the ADC is suspended during a predetermined period after the resetting in at least one of the ADC and the other ADCs. According to the seventh possible implementation form of the second aspect, the generating by the ADC is suspended during the predetermined period the resetting, thus making it possible to avoid comparison errors in the comparing and realize a high quality digital image finally output from the image sensor.

An eighth possible implementation form of the second aspect provides; the ADC according to any one of the first to seventh possible implementation forms of the second aspect, wherein in the receiving, the receiving unit performs: receiving the second ramp reference signal from a ramp generator, and generating the first ramp reference signal based on the received second ramp reference signal. According to the eighth possible implementation form of the second aspect, the first and second ramp reference signals may be generated by the single ramp generator.

A ninth possible implementation form of the second aspect provides; the ADC according to any one of the first to seventh possible implementation forms of the second aspect, wherein in the receiving, the receiving unit performs: receiving the first ramp reference signal from a ramp generator, and generating the second ramp reference signal based on the received first ramp reference signal. According to the eighth possible implementation form of the second aspect, the first and second ramp reference signals may be generated by the single ramp generator.

A tenth possible implementation form of the second aspect provides; the ADC according to any one of the first to ninth possible implementation forms of the second aspect, wherein in the generating, the generating unit performs: retaining a result of the comparing in each AD conversion, averaging retained results of the comparing during said each period of the first ramp reference signal, and determining the digital signal based on the averaged result. According to the tenth possible implementation form of the second aspect, quantization and input noises can be reduced by averaging the retained results of the comparing.

A third aspect of the embodiments provides an image sensor comprising: a plurality of pixels for generating analog signals based on intensity of incident light, and analog-to-digital convertors (ADCs) each being identical with the ADC according to any one of the first to tenth possible implementation forms of the second aspect, wherein the ADCs convert analog signals output from the plurality of pixels into digital signals.

According to the third aspect, a time necessary for the AD conversion is reduced and the number of times of the AD conversion can be increased effectively without sacrificing the AD conversion speed. Increasing the number of times of the AD conversion makes it possible to improve signal-to-noise ratio of the digital signals and quality of output images based on the digital signals.

A fourth aspect of the embodiments provides an apparatus equipped with a camera function, the apparatus comprising: an optical system; an image sensor including a plurality of pixels for generating analog signals based on intensity of incident light through the optical system, and analog-to-digital convertors (ADCs) each being identical with the ADC according to any one of the first to tenth possible implementation forms of the second aspect, wherein the ADCs convert analog signals output from the plurality of pixels into digital signals; and signal processing circuitry generating image data based on the digital signals.

According to the fourth aspect, a time necessary for the AD conversion is reduced and the number of times of the AD conversion can be increased effectively without sacrificing the AD conversion speed. Increasing the number of times of the AD conversion makes it possible to improve signal-to-noise ratio of the digital signals and quality of output images based on the digital signals.

BRIEF DESCRIPTION OF DRAWINGS

Fig. 1 is a schematic block diagram for describing an apparatus according to an embodiment of the present disclosure,

Fig. 2 is a schematic diagram for describing an image sensor according to the embodiment of the present disclosure,

Fig. 3 is a schematic block diagram for describing functions of ADCs in the multiple AD conversion circuitry according to an embodiment of the present disclosure,

Fig. 4 is a schematic circuit diagram for describing structure of the multiple AD conversion circuitry according to the embodiment of the present disclosure,

Fig. 5 is a timing diagram for describing operation of the multiple AD conversion circuitry according to the embodiment of the present disclosure,

Fig. 6 is a schematic circuit diagram for describing structure of the ADC in the image sensor according to a first variation of the embodiment of the present disclosure,

Fig. 7 is a timing diagram for describing operation of the multiple AD conversion circuitry according to the first variation of the embodiment of the present disclosure,

Fig. 8 is a schematic circuit diagram for describing structure of the ADC in the image sensor according to a second variation of the embodiment of the present disclosure,

Fig. 9 is a schematic circuit diagram for further describing the structure of the ADC in the image sensor according to a second variation of the embodiment of the present disclosure,

Fig. 10 is a schematic circuit diagram for describing an AD convertor according to related art, and

Fig. 11 is a timing diagram for describing modification of a RAMP reference signal according to the related art.

DESCRIPTION OF EMBODIMENTS

The following describes technical solutions of the embodiments, referring to the accompanying drawings. It will be understood that the embodiments described below are not all but just some of embodiments relating to the present disclosure. It is to be noted that all other embodiments which may be derived by a person skilled in the art based on the embodiments described below without creative efforts shall fall within the protection scope of the present disclosure.

Fig. 1 is a schematic block diagram for describing an apparatus according to an embodiment of the present disclosure. An apparatus 10 shown in Fig. 1 is an example of the apparatus according to the embodiment of the present disclosure.

The apparatus 10 may be mobile equipment with a camera function, a digital camera, or the like. The mobile equipment may be a mobile phone, a smart phone, a wireless communication terminal, a tablet device, a personal computer, or the like.

As shown in Fig. 1, the apparatus 10 includes a lens 10a, an image sensor 10b, processing circuitry 10c, and a storage 10d.

The lens 10a is an optical system that guides incident light to the image sensor 10b. The optical system may include a plurality of optical lenses, and at least one of the plurality of optical lenses may be used for automatic focusing and/or optical image stabilization. The image sensor 10b performs photoelectric conversion to convert light passed through the lens 10a to an electrical signal, and an analog-to-digital conversion to convert the electrical signal to a digital signal. The digital signal output from the image sensor 10b is fed to the processing circuitry 10c.

The processing circuitry 10c may be at least one processing unit such as an application-specific integrated circuit (ASIC) , a graphics processing unit (GPU) , a field-programmable gate array (FPGA) , or a general purpose processor. In some examples, the processing circuitry 10c may be implemented via hardware, imaging dedicated hardware, or the like.

The processing circuitry 10c generates image data based on the digital signal and stores the image data into the storage 10d. When generating the image data, the processing circuitry 10c may compress and/or encode the digital signal according to any compression and/or encoding techniques standardized by a working group such as JPEG (Joint Photographic Experts Group) , Moving Picture Experts Group (MPEG) , or the like. The processing circuitry 10c may store the digital signal as RAW data into the storage 10d.

The following describes an image sensor according to the embodiment of the present disclosure. Fig. 2 is a schematic diagram for describing the image sensor according to the embodiment of the present disclosure. The image sensor 10b shown in Fig. 2 is one possible implementation form of the image sensor according to the embodiment of the present disclosure.

As shown in Fig. 2, the image sensor 10b includes control circuitry 11, a pixel array 12, and multiple AD conversion circuitry 13. The control circuitry 11 controls the pixel array 12 and the multiple AD conversion circuitry 13.

The pixel array 12 includes a plurality of columns each having a plurality of pixels. Fig. 2 shows only two

columns

12a and 12b for simplicity but the pixel array 12 may include hundreds or thousands of columns. In Fig. 2, each of

columns

12a and 12b has only four pixels for simplicity but each column of the pixel array 12 may include hundreds or thousands of pixels. Each pixel outputs an analog signal according to intensity of the incident light. The output analog signals from each pixel are fed to the multiple AD conversion circuitry 13.

The multiple AD conversion circuitry 13 includes

ADCs

13a and 13b which correspond to the

columns

12a and 12b, respectively. Fig. 2 shows only two ADCs (

ADCs

13a and 13b) but the multiple AD conversion circuitry 13 may include hundreds or thousands of ADCs. Hereinafter, analog signals output from the column 12a may be referred to as "first pixel signals" , and analog signals output from the column 12b may be referred to as "second pixel signals" .

The first pixel signals are fed to the ADC 13a, and the second pixel signals are fed to the ADC 13b. The ADC 13a performs AD conversion for the first pixel signals to generate first digital signals, and the ADC 13b performs AD conversion for the second pixel signals to generate second digital signals. The first and second digital signals are fed to the processing circuitry 10c.

The following describes functions of the ADCs in the multiple AD conversion circuitry 13. Fig. 3 is a schematic block diagram for describing the functions of the ADCs in the multiple AD conversion circuitry according to an embodiment of the present disclosure. The ADCs in the multiple AD conversion circuitry 13 may have the substantially same structure and functions, thus the following describes only the ADC 13a as one example of the ADCs in the multiple AD conversion circuitry 13.

As shown in Fig. 3, the ADC 13a includes a ramp generator 301, a receiving unit 302, a resetting unit 303, a comparing unit 304 and a generating unit 305. In Fig. 3, the ramp generator 301 is disposed in the ADC 13a, but the ramp generator 301 may be disposed outside the ADC 13a in the multiple AD conversion circuitry 13.

The ramp generator 301 may generate a first ramp reference signal whose level changes along a slope from a given initial level during each period of the first ramp reference signal. Also, the ramp generator 301 may generate a second ramp reference signal whose level tracks the first ramp reference signal with a given offset from the level of the first ramp reference signal.

The given offset may be determined based on temporal noises in the first pixel signals, temporal noises of the first and second reference signals, and an input-referred noise of a comparator in ADC 13a. For example, the given offset may be a larger value than the total temporal noises in peak-to-peak magnitude.

If the level of the first ramp reference signal slopes down from the initial level during each period of the first ramp reference signal, then polarity of the given offset is set to be negative. In that case, the level of the first ramp reference signal is larger than the level of the second ramp reference signal.

Alternatively, if the level of the first ramp reference signal slopes up from the initial level during each period of the first ramp reference signal, then polarity of the given offset is set to be positive. In that case, the level of the first ramp reference signal is smaller than the level of the second ramp reference signal.

The receiving unit 302 receives the first and second ramp reference signals from the ramp generator 301. In one possible variation, the receiving unit 302 may receive only the second ramp reference signal from the ramp generator 301, and generate the first ramp reference signal based on the received second ramp reference signal. Alternatively, the receiving unit 302 may receive only the first ramp reference signal from the ramp generator 301, and generate the second ramp reference signal based on the received first ramp reference signal.

The resetting unit 303 receives the first and second ramp reference signals from the receiving unit 302. In the first AD conversion, the resetting unit 303 may input the received second ramp reference signal into the comparing unit 304. The comparing unit 304 compares the second ramp reference signal with the first pixel signals which are output from the column 12a.

When a result of comparison by the comparing unit 304 indicates that the second ramp reference signal reaches the analog input signal, the resetting unit 303 samples the level of the first ramp reference signal. After sampling the level of the first ramp reference signal, the resetting unit 303 resets the level of the second ramp reference signal to the level sampled from the first ramp reference signal. The reset second ramp reference signal is fed to the comparing unit 304 and is used in the following AD conversion.

In the ADC 13a, the comparing procedure by the comparing unit 304, and the sampling and resetting procedures by the resetting unit 303 are performed multiple times in each period of the first ramp reference signal.

In the first AD conversion, the second ramp reference signal received from the receiving unit 302 is used for the comparing procedure. The first reference signal is used for determining a reset level which indicates a starting point of the reset second ramp reference signal in the following AD conversion. In the following AD conversion, the reset second ramp reference signal is used in the comparing procedure. In each period of the first ramp reference signal, the comparing, the sampling and the resetting are repeatedly performed.

The generating unit 305 generates the digital signal based on comparison results output from the comparing unit 304. For example, the generating unit 305 may retain a comparison result output from the comparing unit 304 in each AD conversion, average retained comparison results output from the comparing unit 304 during a single period of the first ramp reference signal, and determine the digital signal based on the averaged result.

According to the above-mentioned configuration of the ADC 13a, an amplitude of the second ramp reference signal is reduced by the reset, so that the reset second ramp reference signal may reach the first pixel signal in a short time. This makes it possible to reduce the time necessary for the AD conversion, and increase the number of times of the AD conversion without sacrificing the AD conversion speed. Increasing the number of times of the AD conversion may improve signal-to-noise ratio of the digital signal and quality of the image data.

The ADC 13a is connected to the ADC 13b and other ADCs in the multiple AD conversion circuitry 13 via common reference lines for distributing the first and second reference signals. In order to avoiding comparison errors caused from the crosstalk noise on the common reference lines, the ADC 13a may suspend to generate the digital signal during a predetermined period after resetting the second ramp reference signal by at least one of the ADCs. This makes it possible to improve quality of the image data.

The following describes one specific example of structure of the multiple AD conversion circuitry according to the embodiment of the present disclosure.

Fig. 4 is a schematic circuit diagram for describing the structure of the multiple AD conversion circuitry according to the embodiment of the present disclosure. For simplicity, the following describes only the

ADCs

13a and 13b in the multiple AD conversion circuitry 13, with an assumption that a level of the first pixel signal is set to be larger than that of the second pixel signal.

As shown in Fig. 4, the multiple AD conversion circuitry 13 includes

switches

101, 102, 103, 104, 201, 202, 203 and 204,

buffer amplifiers

105 and 205,

capacitors

106, 107, 108, 206, 207 and 208,

comparators

109 and 209, conversion counters 110 and 210, counters 111 and 211, and

average calculators

112 and 212.

A first portion including the

switches

101, 102, 103 and 104, the buffer amplifier 105, the

capacitors

106, 107 and 108, the comparator 109, the conversion counter 110, the counter 111, and the average calculator 112 corresponds to the ADC 13a. A second portion including the

switches

201, 202, 203 and 204, the buffer amplifier 205, the

capacitors

206, 207 and 208, the comparator 209, the conversion counter 210, the counter 211, and the average calculator 212 corresponds to the ADC 13b.

In Fig. 4, "V1" and "V2" indicate voltage levels of the first and second pixel signals, respectively. "Vramp1" and "Vramp2" indicate voltage levels of the first and second reference signals, respectively. "Vmod1" and "Vmod2" indicate modified voltage levels of the second reference signals by the

ADCs

13a and 13b, respectively. "COMP1" and "COMP2" are output signals indicating comparison results by the

comparators

109 and 209, respectively.

In this example, the Vramp2 slopes down from a given initial level, and the Vramp1 is set to have a higher voltage level than the Vramp2. Further, the Vramp1 ramps down at the exactly same rate with the Vramp2. Voltage difference (dV) between the Vramp1 and Vramp2 is designed to be large enough for temporal noises in input pixel signals and input-referred noises of comparators in the multiple AD conversion circuitry 13. For example, the dV may be set to be 1.7 mV. Hereinafter, the dV may be referred to as a "offset voltage" .

The first pixel signal (V1) is fed to a minus (-) input terminal of the comparator 109, the Vmod1 is fed to a plus (+) input terminal of the comparator 109 via the capacitor 108, and the comparator 109 compares the V1 with the Vmod1. Since the Vramp2 is not modified in the first AD conversion, the comparator 109 compares the V1 with the Vramp2 in the first AD conversion. In the following AD conversion, the Vramp2 is modified and the comparator 109 compares the V1 with the Vmod1 corresponding to the modified Vramp2 in the ADC 13a. The Vramp1 is used to decide the reset level of the Vmod1.

The comparator 109 outputs the COMP1 whose level is HI (ahigh level) when the V1 is equal to or lower than the Vmod1, or LO (alow level) when the V1 is higher than the Vmod1. The COMP1 is fed to the

switches

101 and 104, the conversion counter 110, and the counter 111.

The conversion counter 110 counts the number of pulses of the COMP1 in one period of the ramp reference signals, and outputs data which represent a first value (N1a) indicating a result of the counting to the average calculator 112. The counter 111 counts the number of pulses of a master clock (CLK) fed to the counter 111 while the level of the COMP1 is LO, and outputs data which represent a second value (N2a) indicating a result of the counting to the average calculator 112. The average calculator 112 divides the N2a by the N1a to calculate an averaged value corresponding to the first digital signal.

In the similar way, the second pixel signal (V2) is fed to a minus (-) input terminal of the comparator 209, the Vmod2 is fed to a plus (+) input terminal of the comparator 209 via the capacitor 208, and the comparator 209 compares the V2 with the Vmod2. Since the Vramp2 is not modified in the first AD conversion, the comparator 209 compares the V2 with the Vramp2 in the first AD conversion. In the following AD conversion, the Vramp2 is modified and the comparator 209 compares the V2 with the Vmod2 corresponding to the modified Vramp2 in the ADC 13b. The Vramp1 is used to decide the reset level of the Vmod2.

The comparator 209 outputs the COMP2 whose level is HI (ahigh level) while the V2 is equal to or lower than the Vmod2, or LO (alow level) while the V2 is higher than the Vmod2. The COMP2 is fed to the

switches

201 and 204, the conversion counter 210, and the counter 211.

The conversion counter 210 counts the number of pulses of the COMP2 in one period of the ramp reference signals, and outputs data which represent a first value (N1 b) indicating a result of the counting to the average calculator 212. The counter 211 counts the number of pulses of the CLK fed to the counter 211 while the level of the COMP2 is LO, and outputs data which represent a second value (N2b) indicating a result of the counting to the average calculator 212. The average calculator 212 divides the N2b by the N1 b to calculate an averaged value corresponding to the second digital signal.

The following further describes operation of the multiple AD conversion circuitry 13 along with the timing diagram shown in Fig. 5. Fig. 5 is the timing diagram for describing operation of the multiple AD conversion circuitry according to the embodiment of the present disclosure.

In an example of Fig. 5, pixel reset duration for resetting the image sensor 10b starts at timing T1, and image output duration for generating image data starts at timing T6. At timing T1, a pixel reset pulse (PIX_RESET) goes high, and pixels are reset according to the PIX_RESET. In the pixel reset duration, a given pixel reset level (Vreset) appears on each input signal line (IN) . Information indicating the Vreset may be stored in the storage 10d.

At the timing T1, the control circuitry 11 controls the

switches

102, 104, 201 and 204 to turn ON and then OFF for initiating the first AD conversion. According to this ON/OFF operation, the offset voltage is sampled and held in the

capacitors

108 and 208, so that the

capacitors

108 and 208 are reset. After the resetting the

capacitors

108 and 208, the first AD conversion starts by sloping down the Vramp2.

At timing T2, the Vramp2 reaches the Vreset, and each of the

comparators

109 and 209 turns its output HI. Each of the conversion counters 110 and 210 counts one, and the

counters

111 and 211 suspend to count the number of pulses of the CLK. At the timing T2, the control circuitry 11 controls the

switches

101 and 201 to turn OFF. After the

switches

101 and 201 turn OFF, the Vmod1 equivalent to (Vramp_init + dV) is held in each of the

capacitors

106 and 206, where the Vramp_init represents an input signal level (Vreset) sampled just when the Vramp2 reaches the Vreset.

At timing T3, the control circuitry 11 controls the

switches

103 and 203 to turn ON for resetting each of the Vmod1 and Vmod2 to (Vramp_init + dV) which is held in the

capacitors

106 and 206. In response to the resetting, each of the

comparators

109 and 209 turns its output LO.

At timing T4, the control circuitry 11 controls the

switches

103 and 203 to turn OFF for initiating the second AD conversion. After the

switches

103 and 203 turn OFF, nodes with the Vmod1 and Vmod2 are AC coupled to the Vramp2, so that the Vmod1 and Vmod2 track the Vramp2.

At timing T5, the Vmod1 and Vmod2 reach the Vreset, and each of the

comparators

109 and 209 turn its output HI. Each of the conversion counters 110 and 210 counts two, and the

counters

111 and 211 suspend to count the number of pulses of the CLK. In the following AD conversion, operation of the AD conversion is performed in the same manner with the second AD conversion.

If resolution of the AD conversion is 10 bit, the AD conversion is performed four times in the first period of the ramp reference signals, and the dV equals to n LSB (LSB = n *Vramp1 /2 ¹⁰) , each of the

average calculators

112 and 212 generates averaged digital data (Dav) given by the following equation:

Dav = {D1 + (D1 -n + D2) + (D1 -n + D3) + (D1 -n + D4) } /4,

where Dk (k = 1, 2, 3, 4) indicates the number of pulses of the CLK counted by each of the

counters

111 and 211 during the k-th AD conversion. The pixel reset level is set to be the Dav output from each of the

average calculators

112 and 212 in the pixel reset duration and is used in the image output duration.

At timing T6, a pixel transfer pulse (PIX_TRANS) goes high for initiating the first AD conversion in the image output duration, the V1 appears on the input signal line (IN) of the ADC 13a, and the V2 appears on the input signal line (IN) of the ADC 13b. At timing T7, the Vmod1 and Vmod2 start ramping down from the (Vramp_init + dV) which is held in each of the

capacitors

106 and 206.

At timing T10, the Vramp2 reaches the V1, the comparator 109 turns its output HI. The counter 111 stops counting the number of pulses of the CLK, and the conversion counter 110 counts one. At the timing T10, the switch 101 turns OFF, so that the Vramp1 equivalent to (Vramp_init_pix1 + dV) is held in capacitor 106, where the Vramp_init_pix1 represents an input signal level (V1) sampled just when the Vramp2 reaches the V1.

At timing T11, the control circuitry 11 controls the switch 103 to turn ON for resetting the Vmod1 to (Vramp_init_pix1 + dV) which is held in the capacitor 106. In response to the resetting, the comparator 109 turns its output LO.

At timing T12, the control circuitry 11 controls the switch 103 to turn OFF for initiating the second AD conversion for the V1. After the switch 103 turn OFF, the node with the Vmod1 is AC coupled to the Vramp2, so that the Vmod1 tracks the Vramp2.

At timing T13, the Vmod1 reaches the V1, and the comparator 109 turns its output HI. The conversion counter 110 counts two, and the counter 111 suspends to count the number of pulses of the CLK.

At timing T14, the control circuitry 11 controls the switch 103 to turn ON for resetting the Vmod1 to (Vramp_init_pix1 + dV) again. In response to the resetting, the comparator 109 turns its output LO. At timing T15, the control circuitry 11 controls the switch 103 to turn OFF for initiating the third AD conversion for the V1. In the following AD conversion for the V1, operation of the AD conversion is performed in the same manner with the second AD conversion.

At timing T20, the Vramp2 reaches the V2, the comparator 209 turns its output HI. The counter 211 stops counting the number of pulses of the CLK, and the conversion counter 210 counts one. At the timing T20, the switch 201 turns OFF, so that the Vramp1 equivalent to (Vramp_init_pix2 + dV) is held in capacitor 206, where the Vramp_init_pix2 represents an input signal level (V2) sampled just when the Vramp2 reaches the V2.

At timing T21, the control circuitry 11 controls the switch 203 to turn ON for resetting the Vmod2 to (Vramp_init_pix2 + dV) which is held in the capacitor 206. In response to the resetting, the comparator 209 turns its output LO.

At timing T22, the control circuitry 11 controls the switch 203 to turn OFF for initiating the second AD conversion for the V2. After the switch 203 turn OFF, the node with the Vmod2 is AC coupled to the Vramp2, so that the Vmod2 tracks the Vramp2.

At timing T23, the Vmod2 reaches the V2, and the comparator 209 turns its output HI. The conversion counter 210 counts two, and the counter 211 suspends to count the number of pulses of the CLK.

At timing T24, the control circuitry 11 controls the switch 203 to turn ON for resetting the Vmod2 to (Vramp_init_pix2 + dV) again. In response to the resetting, the comparator 209 turns its output LO. At timing T25, the control circuitry 11 controls the switch 203 to turn OFF for initiating the third AD conversion for the V2. In the following AD conversion for the V2, operation of the AD conversion is performed in the same manner with the second AD conversion.

In the example of Fig. 5, the AD conversion for the V1 is performed four times in the second period of the ramp reference signals. In this case, the average calculator 112 generates averaged digital data (Dav_pix1) given by the following equation:

Dav_pix1 = {D1_pix1 + (D1_pix1 -n + D2_pix1) + (D1_pix1 -n + D3_pix1) + (D1_pix1 -n + D4_pix1) } /4,

where Dk_pix1 (k = 1, 2, 3, 4) indicates the number of pulses of the CLK counted by the counter 111 during the k-th AD conversion.

Similarly, in the example of Fig. 5, the AD conversion for the V2 is performed three times in the second period of the ramp reference signals. In this case, the average calculator 212 generates averaged digital data (Dav_pix2) given by the following equation:

Dav_pix2 = {D1_pix2 + (D1_pix2 -n + D2_pix2) + (D1_pix2 -n + D3_pix2) } /3,

where Dk_pix2 (k = 1, 2, 3) indicates the number of pulses of the CLK counted by the counter 211 during the k-th AD conversion.

The Dav_pix1 and the Dav_pix2 are subtracted by the Dav in order to suppress noises and fluctuations which come from offset voltages of the

buffer amplifiers

105 and 205. The offset voltages may be referred to as "hold step voltage" that may arise in the

capacitors

106, 206 holding the Vramp1, and may cause delay time of

comparators

109 and 209.

The first digital signal (D_pix1) is provided by the following equation:

D_pix1 = Dav_pix1 -Dav,

and the second digital signal (D_pix2) is provided by the following equation:

D_pix2 = Dav_pix2 -Dav.

The above-mentioned averaging and subtracting operations make it possible to reduce the noises in the first and second digital signals output from the

ADCs

13a and 13b, respectively.

As mentioned above, in the ADC 13a, the Vmod2 is reset to the reset level held in the capacitor 106. In the similar way, the ADC 13b performs the resetting operation based on the reset level held in the capacitor 206. These resetting operations make it possible to effectively reduce necessary time for the multiple AD conversion, so that the number of times of the AD conversion can be increased effectively without sacrificing the AD conversion speed. Increasing the number of times of the AD conversion enables to improve signal-to-noise ratio of the digital signals and quality of output images.

(First variation) The following describes one specific example of structure of the multiple AD conversion circuitry according to a first variation of the embodiment of the present disclosure.

Fig. 6 is a schematic circuit diagram for describing structure of the ADC in the image sensor according to the first variation of the embodiment of the present disclosure. For simplicity, the following describes only the

ADCs

As shown in Fig. 6, the multiple AD conversion circuitry 13 includes

switches

101, 102, 103, 104, 121, 201, 202, 203, 204 and 221,

buffer amplifiers

105, 122, 205 and 222,

capacitors

106, 107, 108, 123, 206, 207, 208 and 223,

comparators

109 and 209, conversion counters 110 and 210, counters 111 and 211,

average calculators

112 and 212, and a voltage supply 120. Namely, in the first variation, the voltage supply 120, the

switches

121 and 221, the

buffer amplifiers

122 and 222, and the

capacitors

123 and 223 are added to the multiple AD conversion circuitry 13 as shown in Fig. 6.

In the first variation, a first portion including the

switches

101, 102, 103, 104 and 121, the

buffer amplifiers

105 and 122, the

capacitors

106, 107, 108 and 123, the comparator 109, the conversion counter 110, the counter 111, and the average calculator 112 corresponds to the ADC 13a. Further, a second portion including the

switches

201, 202, 203, 204 and 221, the

buffer amplifiers

205 and 222, the

capacitors

206, 207, 208 and 223, the comparator 209, the conversion counter 210, the counter 211, and the average calculator 212 corresponds to the ADC 13b.

In this example, an input offset level "Voffset" is fed to a first input terminal (IN1) as shown in Fig. 6. The voltage supply 120 supplies the offset voltage (dV) which lifts the Voffset up to the Vramp1 which is larger than the Vramp2 by the dV.

In this example, the Vramp2 slopes down from the given initial level, and the Vramp1 is set to have a higher voltage level than the Vramp2. Further, the Vrmap1 ramps down at the exactly same rate with the Vramp2. The dV is designed to be large enough for temporal noises in input pixel signals and input-referred noises of comparators in the multiple AD conversion circuitry 13. The Vramp1 is fed to the

switches

121 and 221.

switches

101 and 104, the conversion counter 110, and the counter 111.

The conversion counter 110 counts the number of pulses of the COMP1 in one period of the ramp reference signals, and outputs data which represent a first value (N1a) indicating a result of the counting to the average calculator 112. The counter 111 counts the number of pulses of the master clock (CLK) fed to the counter 111 while the level of the COMP1 is LO, and outputs data which represent a second value (N2a) indicating a result of the counting to the average calculator 112. The average calculator 112 divides the N2a by the N1a to calculate an averaged value corresponding to the first digital signal.

In the similar way, the second pixel signal (V2) is fed to a minus (-) input terminal of the comparator 209, the Vmod2 is fed to a plus (+) input terminal of the comparator 209 via the capacitor 208, and the comparator 209 compares the V2 with the Vmod2. Since the Vramp2 is not modified in the first AD conversion, the comparator 209 substantially compares the V2 with the Vramp2 in the first AD conversion. In the following AD conversion, the Vramp2 is modified and the comparator 209 compares the V2 with the Vmod2 corresponding to the modified Vramp2 in the ADC 13b. The Vramp1 is used to decide the reset level of the Vmod2.

The comparator 209 outputs the COMP2 whose level is HI (ahigh level) while the V2 is equal to or lower than the Vmod2 or LO (alow level) while the V2 is higher than the Vmod2. The COMP2 is fed to the

switches

201 and 204, the conversion counter 210, and the counter 211.

The following further describes operation of the multiple AD conversion circuitry 13 along with the timing diagram shown in Fig. 7. Fig. 7 is a timing diagram for describing operation of the multiple AD conversion circuitry according to the first variation of the embodiment of the present disclosure.

In an example of Fig. 7, pixel reset duration for resetting the image sensor 10b starts at timing T1, and image output duration for generating image data starts at timing T6. At timing T1, a pixel reset pulse (PIX_RESET) goes high, and pixels are reset according to the PIX_RESET. In the pixel reset duration, a given reset level (Vreset) appears on each input signal line (IN) . Information indicating the Vreset may be stored in the storage 10d.

At the timing T1, the control circuitry 11 controls the

switches

capacitors

108 and 208, so that the

capacitors

108 and 208 are reset. Further, the control circuitry 11 controls the

switches

121 and 221 to turn OFF, so that voltage difference between terminals of the

capacitors

123 and 223 is set to have the dV. After setting the voltage difference, the multiple AD conversion initiates and input levels of the

buffer amplifiers

122 and 222 starts to ramp down exactly the same rate with the Vramp2.

At timing T2, the Vramp2 reaches the Vreset, and each of the

comparators

counters

switches

101 and 201 to turn OFF. After the

switches

101 and 201 turn OFF, output levels of the

buffer amplifiers

122 and 222 equivalent to (Vramp_init + dV) is held in each of the

capacitors

At timing T3, the control circuitry 11 controls the

switches

capacitors

106 and 206. In response to the resetting, each of the

comparators

109 and 209 turns its output LO.

At timing T4, the control circuitry 11 controls the

switches

103 and 203 to turn OFF for initiating the second AD conversion. After the

switches

At timing T5, the Vmod1 and Vmod2 reach the Vreset, and each of the

comparators

counters

average calculators

Dav = {D1 + (D1 -n + D2) + (D1 -n + D3) + (D1 -n + D4) } /4,

counters

average calculators

capacitors

106 and 206.

At timing T20, the Vramp2 reaches the V2, the comparator 209 turns its output HI. The counter 211 stops counting the number of pulses of the CLK, and the conversion counter 210 counts one. At the timing T20, the switch 201 turns OFF, so that the Vramp1 equivalent to (Vramp_init_pix2 + dV) is held in capacitor 206, where the Vramp_init_pix2 represents an input signal level (the V2) sampled just when the Vramp2 reaches the V2.

In the example of Fig. 7, the AD conversion for the V1 is performed four times in the second period of the ramp reference signals. In this case, the average calculator 112 generates averaged digital data (Dav_pix1) given by the following equation:

Similarly, in the example of Fig. 7, the AD conversion for the V2 is performed three times in the second period of the ramp reference signals. In this case, the average calculator 212 generates averaged digital data (Dav_pix2) given by the following equation:

Dav_pix2 = {D1_pix2 + (D1_pix2 -n + D2_pix2) + (D1_pix2 -n + D3_pix2) } /3,

buffer amplifiers

capacitors

106, 206 holding the Vramp1, and may cause delay time of

comparators

109 and 209.

The first digital signal (D_pix1) is provided by the following equation:

D_pix1 = Dav_pix1 -Dav,

and the second digital signal (D_pix2) is provided by the following equation:

D_pix2 = Dav_pix2 -Dav.

ADCs

13a and 13b, respectively. Further, necessary time for the multiple AD conversion may be effectively reduced.

(Second variation) The following describes one specific example of structure of the multiple AD conversion circuitry according to a second variation of the embodiment of the present disclosure.

Fig. 8 is a schematic circuit diagram for describing structure of the ADC in the multiple AD conversion circuitry according to a second variation of the embodiment of the present disclosure. For simplicity, the following describes only the ADCs 13a in the multiple AD conversion circuitry 13.

As shown in Fig. 8, the ADC 13a includes

switches

101, 102, 103 and 104, a buffer amplifier 105,

capacitors

106, 107, 108 and 131, a comparator 109, a conversion counter 110, a counter 111, and an average calculator 112. The ADC 13a further includes a DFF (D-Flip Flop) circuit 132, a NOR circuit 133 and AND

circuits

134 and 135. Namely, in the second variation, a portion including the capacitor 131, the DFF circuit 132, the NOR circuit 133 and the AND

circuits

134 and 135 is added to the ADC 13a shown in Fig. 4. Although the V1 is fed to the minus (-) input terminal of the comparator 109 via the capacitor 131, the added portion operates in the similar manner of the ADC 13a in Fig. 4. Thus, the following mainly describes the DFF (D-Flip Flop) circuit 132, the NOR circuit 133 and the AND

circuits

134 and 135.

In Fig. 8, "GATE_A" and "GATE_B" indicate gated clocks, and "CLK_A" indicates a control clock which is fed to each of the ADCs in the multiple AD conversion circuitry 13. The CLK_A is a pulse signal such that one pulse appears every M pulses of the CLK, where the M is predetermined value. If resolution of the AD conversion by the ADC 13a is 10 bits, the M may be set to 64 (64=1024/16) . In this case, the maximum number of times of the AD conversion in a single period of the ramp reference signal is set to "16" .

As shown in Fig. 8, the CLK is fed to an input terminal of the AND circuit 135, and the CLK_A is fed to an input terminal of the NOR circuit 133 and an input terminal of the AND circuit 134. Further, an inversed signal of the CLK_A is fed to another input terminal of the AND circuit 135.

The GATE_A is a signal obtained by gating output of the DFF circuit 132 with the CLK_A. The GATE_A output from the AND circuit 134 is fed to the switch 103 and the conversion counter 110. The GATE_B is output from the AND circuit 135 and is fed to a clock terminal of the counter 111. The COMP1 is output from the comparator 109 and is fed to the switch 101, an enable terminal of the counter 111, a clock terminal of the DFF circuit 132 and another input terminal of the NOR circuit 133.

A signal fed to a D-input terminal of the DFF circuit 132 is consistently HI, and an inverted signal output from the NOR circuit 133 is fed to a R-input terminal of the DFF circuit 132. A signal output from a Q-output terminal of the DFF circuit 132 is fed to another input terminal of the AND circuit 134.

In the second variation, the Vramp1 and Vramp2 supplied to the ADCs in the multiple AD conversion circuitry 13 are controlled based on the GATE_B generated by the CLK and the CLK_A. For example, a ramp generating unit shown in Fig. 4 may supply the Vramp1 and Vramp2 to the ADCs in the multiple AD conversion circuitry 13. Fig. 9 is a schematic circuit diagram for further describing the structure of the ADC in the image sensor according to a second variation of the embodiment of the present disclosure.

As shown in Fig. 9, the ramp generating unit includes

ramp generators

141 and 142, and AND

circuits

143 and 144. The CLK is fed to an input terminal of each of the AND

circuits

143 and 144. An inversed signal of the CLK_A is fed to another input terminal of each of the AND

circuits

143 and 144. The AND

circuits

143 and 144 perform AND operation for the CLK and CLK_A, and outputs the GATE_B to the

ramp generators

141 and 142, respectively. The GATE_B is a series of pulses in the CLK which is extracted while the level of the CLK_A is LO level.

The ramp generator 141 generates the Vramp1 which ramps down from a given initial level, and controls the Vramp1 based on the GATE_B so that the level of the Vramp1 is retained at the given initial level during a period in which no pulse of the GATE_B is present. Similarly, the ramp generator 142 generates and controls the Vramp2 whose level is retained at a given initial level of the Vramp2 during the period in which no pulse of the GATE_B is present.

According to the above-mentioned configuration, the comparator 109 changes its output to LO synchronizing with rising time of the CLK_A, and the counter 111 suspends to count the number of pulses of the CLK while the level of the CLK_A is HI. That is, the AD conversion by the ADC 13a is suspended during a predetermined period corresponding to a pulse width of the CLK_A after resetting the ramp reference signals. Therefore, switching noises arising when resetting the ramp reference signals do not affect the AD conversion by the ADCs in the multiple AD conversion circuitry 13.

As described above, the ADCs in the multiple AD conversion circuitry 13 operate based on the common ramp reference signals (Vramp1, Vramp2) . When the ramp reference signal is reset by any one of the ADCs, switching noise may be transferred through the common reference lines. However, according to the second variation, each ADC suspends the AD conversion during the HI level duration of the CLK_A, thus avoiding comparator errors caused from the switching noise. This makes it possible to improve quality of output images from the image sensor 10b.

As described above, the embodiments and its variations make it possible to reduce a time necessary for the AD conversion, so that the number of times of the AD conversion can be increased effectively without sacrificing the AD conversion speed. Increasing the number of times of the AD conversion makes it possible to improve signal-to-noise ratio of the digital signals and quality of output images based on the digital signals.

The foregoing disclosure merely discloses exemplary embodiments, and is not intended to limit the protection scope of the present invention. It will be appreciated by those skilled in the art that the foregoing embodiments and all or some of other embodiments and modifications which may be derived based on the scope of claims of the present invention will of course fall within the scope of the present invention.

Claims

A method for multiple analog-to-digital conversion by an analog-to-digital convertor (ADC) , comprising:

receiving a first ramp reference signal whose level changes along a slope from an initial level during each period of the first ramp reference signal, and a second ramp reference signal whose level tracks the first ramp reference signal with a given offset from the level of the first ramp reference signal;

comparing the second ramp reference signal with an input analog signal;

sampling a level of the first ramp reference signal just when the second ramp reference signal reaches the analog input signal, and resetting a level of the second ramp reference signal to the level sampled from the first ramp reference signal after the sampling; and

generating a digital signal based on results of the comparing, wherein the comparing, the sampling and the resetting are performed multiple times in said each period of the first ramp reference signal, and the comparing after the resetting is performed by using the reset second ramp reference signal.
The method according to claim 1, wherein the given offset is determined based on temporal noises in the input analog signal and the first and second reference signals, and an input-referred noise of a comparator performing the comparing.
The method according to claim 2, wherein the given offset is set to be a larger value than a total of the temporal noises in peak-to-peak magnitude.
The method according to claim 2 or 3, wherein the first reference signal is fed to the comparator through a capacitive member, and the second reference signal is used as a clamp voltage of the capacitive member.
The method according to any one of claims 1 to 4, wherein the level of the first ramp reference signal slopes down from the initial level during said each period of the first ramp reference signal, and polarity of the given offset is set to be negative.
The method according to any one of claims 1 to 4, wherein the level of the first ramp reference signal slopes up from the initial level during said each period of the first ramp reference signal, and polarity of the given offset is set to be positive.
The method according to any one of claims 1 to 6, wherein the ADC is connected to other ADCs via common reference lines for distributing the first and second reference signals to the ADC and the other ADCs, and the generating by the ADC is suspended during a predetermined period after the resetting in at least one of the ADC and the other ADCs.
The method according to any one of claims 1 to 7, wherein the receiving includes: receiving the second ramp reference signal from a ramp generator, and generating the first ramp reference signal based on the received second ramp reference signal.
The method according to any one of claims 1 to 7, wherein the receiving includes: receiving the first ramp reference signal from a ramp generator, and generating the second ramp reference signal based on the received first ramp reference signal.
The method according to any one of claims 1 to 9, wherein the generating includes: retaining a result of the comparing in each AD conversion, averaging retained results of the comparing during said each period of the first ramp reference signal, and determining the digital signal based on the averaged result.
Analog-to-digital convertor (ADC) performing multiple analog-to-digital conversion, the ADC comprising:

a receiving unit configured to perform receiving a first ramp reference signal whose level changes along a slope from an initial level during each period of the first ramp reference signal, and a second ramp reference signal whose level tracks the first ramp reference signal with a given offset from the level of the first ramp reference signal;

a comparing unit configured to perform comparing the second ramp reference signal with an input analog signal;

a resetting unit configured to perform sampling a level of the first ramp reference signal just when the second ramp reference signal reaches the analog input signal, and perform resetting a level of the second ramp reference signal to the level sampled from the first ramp reference signal after the sampling; and

a generating unit configured to perform generating a digital signal based on results of the comparing, wherein the comparing, the sampling and the resetting are performed multiple times in said each period of the first ramp reference signal, and the comparing after the resetting is performed by using the reset second ramp reference signal.
The ADC according to claim 11, wherein the given offset is determined based on temporal noises in the input analog signal and the first and second reference signals, and an input-referred noise of a comparator performing the comparing.
The ADC according to claim 12, wherein the given offset is set to be a larger value than a total of the temporal noises in peak-to-peak magnitude.
The ADC according to claim 12 or 13, wherein the first reference signal is fed to the comparing unit through a capacitive member, and the second reference signal is used as a clamp voltage of the capacitive member.
The ADC according to any one of claims 11 to 14, wherein the level of the first ramp reference signal slopes down from the initial level during said each period of the first ramp reference signal, and polarity of the given offset is set to be negative.
The ADC according to any one of claims 11 to 14, wherein the level of the first ramp reference signal slopes up from the initial level during said each period of the first ramp reference signal, and polarity of the given offset is set to be positive.
The ADC according to any one of claims 11 to 16, wherein the ADC is connected to other ADCs via common reference lines for distributing the first and second reference signals to the ADC and the other ADCs, and the generating by the ADC is suspended during a predetermined period after the resetting in at least one of the ADC and the other ADCs.
The ADC according to any one of claims 11 to 17, wherein in the receiving, the receiving unit performs: receiving the second ramp reference signal from a ramp generator, and generating the first ramp reference signal based on the received second ramp reference signal.
The method according to any one of claims 11 to 17, wherein in the receiving, the receiving unit performs: receiving the first ramp reference signal from a ramp generator, and generating the second ramp reference signal based on the received first ramp reference signal.
The ADC according to any one of claims 11 to 19, wherein in the generating, the generating unit performs: retaining a result of the comparing in each AD conversion, averaging retained results of the comparing during said each period of the first ramp reference signal, and determining the digital signal based on the averaged result.
An image sensor comprising:

a plurality of pixels for generating analog signals based on intensity of incident light, and analog-to-digital convertors (ADCs) each being identical with the ADC according to any one of claims 11 to 20, wherein the ADCs convert analog signals output from the plurality of pixels into digital signals.
An apparatus equipped with a camera function, the apparatus comprising:

an optical system; an image sensor including a plurality of pixels for generating analog signals based on intensity of incident light through the optical system, and analog-to-digital convertors (ADCs) each being identical with the ADC according to any one of claims 11 to 20, wherein the ADCs convert analog signals output from the plurality of pixels into digital signals; and signal processing circuitry generating image data based on the digital signals.