JP4631255B2 - Active matrix substrate, display device, and electronic device - Google Patents

Description

  The present invention relates to an active matrix substrate, a display device, and an electronic device.

  As a display device such as a liquid crystal device or an EL (electroluminescence) device, an active matrix type display device is conventionally known. An active matrix substrate used in this type of display device has an image display region composed of a large number of pixels arranged in a matrix in plan view, and switching elements such as TFTs (thin film transistors) are provided corresponding to the pixels. ing. In addition, there is a configuration in which peripheral circuits such as a drive circuit and an inspection circuit that supply an image signal and a scanning signal to the switching elements in the image display area are provided on the outer periphery of the image display area.

Polycrystalline silicon is widely used as the TFT used for the pixel and the peripheral circuit. Recently, a low temperature process for forming a semiconductor layer at a relatively low temperature has attracted attention as a manufacturing process thereof.
In the semiconductor layer (low-temperature p-Si) manufactured using such a low-temperature process, the heating at the time of manufacture is higher than that of a semiconductor layer (high-temperature p-Si) manufactured by polycrystallizing a silicon thin film at a high temperature. There are many process restrictions such as temperature and surface roughness of the semiconductor layer, and TFTs using such low-temperature p-Si are often applied to relatively inexpensive display devices, thus simplifying the manufacturing process. Efficiency is becoming essential. Further, even in this type of display device, there is a strong general demand for high-quality display, and high definition (narrow pitch of pixels) is required without impairing the aperture ratio and retention characteristics of the pixels. Yes.

Therefore, in the electro-optical device described in Patent Document 1, the light leakage of the TFT is increased in order to increase the storage capacity of the pixel without increasing the number of steps and enlarging the non-opening region of the pixel, and to cope with higher definition. A configuration in which a light-shielding layer provided to prevent this and an electrode portion constituting the storage capacitor of the pixel are formed in the same layer below the semiconductor layer (substrate side) is employed.
JP 2000-267131 A

  The technique described in Patent Document 1 is an effective technique for increasing the definition of a pixel because the storage capacity can be increased without reducing the aperture ratio of the pixel. However, in the case of high-definition pixels, not only the efficiency of the storage capacitor is required, but also the switching elements of the pixels are downsized and the degree of integration in peripheral circuits provided outside the display area of the display device is required. However, if wirings and gate electrodes connected to switching elements such as TFTs are simply reduced in size and pitch, their workability reaches the limit, which may affect the stability and reliability of operation.

  The present invention has been made in view of the above-described problems of the prior art, and can achieve high definition of pixels and high quality of a display image, and can be manufactured by a simple manufacturing process. And a display device including the same.

In order to solve the above-described problem, the present invention includes a base material and a plurality of pixel regions arranged on the base material. The pixel region includes a thin film transistor and a storage capacitor connected to the thin film transistor. Wherein the thin film transistor includes a channel region formed in a semiconductor layer in the pixel region, and a gate electrode portion facing the channel region via an insulating film, A light shielding member layer having a plurality of light shielding members arranged on the opposite side of the gate electrode portion across the semiconductor layer is provided, and the light shielding member layer is made of the light shielding member at a position facing the channel region. A back gate wiring having a back gate electrode portion and a capacitor electrode portion made of the light shielding member and forming an electrode of the storage capacitor are provided, and the back gate wiring is In a region excluding the back gate line and the peripheral area, the scanning line that is a signal line extending along the back gate line is separated in plan view, and the thin film transistor includes the plurality of gate electrode parts and the plurality of gate electrode parts. A plurality of channel regions facing the gate electrode part, and a capacitor line forming an electrode of the storage capacitor is provided on a layer opposite to the capacitor electrode part across the semiconductor layer, and the capacitor line The capacitor electrode portion is electrically connected, and an intermediate electrode layer electrically connected to the semiconductor layer is provided on a layer opposite to the semiconductor layer across the capacitor line, The electrode layer and the capacitor line are arranged so as to overlap in a plane, and the planar regions of the capacitor electrode part, the semiconductor layer, the capacitor line, and the intermediate electrode layer constituting the storage capacitor have a layer thickness. direction The light shielding member layer is formed so as to be narrowed sequentially from the substrate side, and is arranged on the light shielding member layer so as to overlap the data line connected to the thin film transistor in a planar manner, and forms a part of the capacitive electrode portion. An active matrix substrate , wherein a member is formed, and the semiconductor layer is provided up to a position facing a capacitive electrode portion arranged in a plane overlapping with the data line in a layer thickness direction. provide.
According to this configuration, the light-shielding film formed using the same light-shielding material on the same light-shielding member layer, the back gate electrode portion, and the capacitor electrode portion can prevent light leakage of the thin film transistor due to the light-shielding film. In addition, it is possible to reduce the off-current of the thin film transistor by the back gate electrode portion, stabilize the operation, and increase the storage capacitance by the capacitor electrode portion, thereby realizing high definition of the pixel. In other words, it is possible to reduce the storage capacity by reducing the leakage current and off-current of the thin film transistor, thereby reducing the storage capacity, and reducing the storage capacitor's flat area by increasing the capacity of the storage capacity itself. Can do. Thereby, the non-opening region in the pixel region can be reduced, and the aperture ratio of the pixel can be increased.
In addition, since the light shielding member is formed in the same light shielding member layer and can be formed in the same process, the performance of the active matrix substrate can be improved without increasing the number of processes.

The active matrix substrate of the present invention includes a signal wiring extended to a side edge of the pixel region so as to supply an electric signal to the thin film transistor, and overlaps the signal wiring in a plan view with the light shielding member layer. It is also possible to adopt a configuration in which a light shielding member arranged in this manner is provided.
Accordingly, a configuration including a light shielding member for partitioning the pixel region can be provided. For example, when the active matrix substrate is applied to a liquid crystal device, the light shielding for partitioning the pixel region on the oppositely arranged substrate side is possible. There is no need to provide means (black matrix). When the black matrix is provided on the counter substrate side, it is necessary to form the black matrix thicker than the boundary between the pixel regions on the active matrix substrate side in consideration of the misalignment between the substrates. Therefore, the light shielding member functioning as a black matrix does not become thicker than necessary. Therefore, the aperture ratio of the pixel region can be increased and a bright display can be obtained.

In the active matrix substrate of the present invention, the light shielding member arranged to overlap the signal wiring in a plane forms part of the capacitor electrode portion, and the semiconductor layer overlaps the signal wiring in a plane. It is possible to adopt a configuration in which the capacitor electrode portions are arranged along the layer thickness direction so as to face each other.
According to this configuration, since the capacitor composed of the semiconductor layer and the light shielding member can be formed at a position overlapping with the signal wiring, the storage capacitor can be increased without decreasing the aperture ratio of the pixel, and high definition can be achieved. It is possible to provide an active matrix substrate having a suitable structure.

In the active matrix substrate of the present invention, a back gate wiring electrically connected to the back gate electrode portion is provided in the light shielding member layer, and the back gate wiring includes the back gate electrode portion and its peripheral region. In the region excluding, the signal wiring extending along the back gate wiring may be separated from the signal wiring in a plan view.
According to this configuration, crosstalk between the back gate wiring and the signal wiring can be prevented, and the film thickness of the insulating film between the back gate wiring and the signal wiring can be reduced. The gate electrode portion can effectively function with respect to the thin film transistor, and the capacitance using the capacitor electrode portion provided in the light shielding member layer as an electrode can be increased.

In the active matrix substrate of the present invention, a capacitor line that forms an electrode of the storage capacitor is provided on a layer opposite to the capacitor electrode portion across the semiconductor layer, and the capacitor line, the capacitor electrode portion, Can be configured to be electrically connected.
According to this configuration, since the capacitor electrode part and the capacitor line are arranged on both sides of the semiconductor layer, a capacitor is formed between the capacitor electrode part and the semiconductor layer, and between the semiconductor layer and the capacitor line, The storage capacity of the pixel area can be increased. Thereby, the planar area of the storage capacitor can be reduced and the aperture ratio of the pixel can be increased.

In the active matrix substrate of the present invention, an intermediate electrode layer electrically connected to the semiconductor layer is provided on a layer opposite to the semiconductor layer across the capacitor line, and the intermediate electrode layer, the capacitor line, However, it can be set as the structure arrange | positioned by overlapping in a plane.
According to this configuration, the capacity formed by the intermediate electrode layer and the capacity line can be added to the storage capacity. Therefore, the planar area can be reduced by increasing the storage capacity, and the aperture ratio can be further increased. Improvements can be realized.

The active matrix substrate of the present invention is formed such that the planar regions of the capacitor electrode part, the semiconductor layer, the capacitor line, and / or the intermediate electrode layer constituting the storage capacitor are sequentially narrowed from the substrate side in the layer thickness direction. It is preferable to adopt a configuration as described above.
According to this configuration, when forming a storage capacitor having a structure in which a plurality of conductive films (the capacitor electrode portion, the semiconductor layer, etc.) are stacked, the step portion of the insulating film formed so as to cover one conductive film is formed. Avoiding this, the upper layer can be formed. As a result, a storage capacitor that hardly causes a capacitance leak between the conductive films can be formed. In the stepped portion, the insulating film tends to have insufficient coverage, and if the conductive film is opposed to the stepped portion through the stepped portion, electric charges may pass through the stepped portion, resulting in capacitance leakage. . This configuration is a configuration that can prevent a capacity leak due to the stepped portion.

  The active matrix substrate of the present invention may be configured such that the thin film transistor includes a plurality of the gate electrode portions and a plurality of channel regions facing the plurality of gate electrode portions. That is, a structure including a thin film transistor with a multi-gate structure can be provided, so that off current of the pixel thin film transistor can be reduced and the retention characteristics of the pixel can be improved.

  In the active matrix substrate of the present invention, in the multi-gate structure, the gate electrode portion is provided at a scanning line branching portion that branches from a scanning line extending on the substrate and extends in a direction intersecting the scanning line. It can be set as a structure. The semiconductor layer may have a meandering shape in plan view and intersect the scanning line at a plurality of locations, and the gate electrode portion may be provided at the intersecting portion.

  The active matrix substrate of the present invention may be configured such that the back gate electrode portion is disposed to face the channel region. According to this configuration, in addition to the operation stability of the thin film transistor by the back gate electrode portion and the effect of reducing off-leakage current, there is an advantage that the channel region can be shielded by the back gate electrode portion which is a light shielding member. In addition, since the gate electrode portion and the back gate electrode portion can be driven so as to apply an electric field to the channel region, on-state current can be secured even if the thin film transistor is downsized.

The active matrix substrate of the present invention further includes a peripheral circuit that supplies an electric signal to the thin film transistor in the pixel region, and a thin film transistor for circuit provided in the peripheral circuit is formed on the light shielding member layer. It can also be set as the structure provided with the part.
By providing the back gate electrode portion in the circuit thin film transistor in this manner, the density and size reduction of the thin film transistor in the peripheral circuit can be realized in combination with the gate electrode portion of the circuit thin film transistor. As a result, a highly integrated peripheral circuit that can easily cope with high definition of pixels can be obtained.
According to this configuration, when the light shielding member layer is formed, the back gate electrode portion of the circuit thin film transistor can be formed at the same time, and the back gate electrode portion can be provided without increasing the number of steps.

  The active matrix substrate of the present invention may be configured such that a light shielding film formed on the light shielding member layer is provided at a position facing the channel region of the circuit thin film transistor. According to this configuration, the light shielding film of the thin film transistor in the peripheral circuit can also be an active matrix substrate that can be formed simultaneously with the formation of the light shielding member layer.

The active matrix substrate of the present invention may have a configuration in which a gate electrode portion and a back gate electrode portion are formed on both sides in a layer thickness direction of a semiconductor layer constituting the circuit thin film transistor.
According to this configuration, it is possible to obtain an effect of reducing the off-current due to the back gate electrode portion, and it is also possible to form a multi-gate circuit thin film transistor by causing the back gate electrode to function as a gate.

In the active matrix substrate of the present invention, among the circuit thin film transistors arranged adjacent to each other in the peripheral circuit, one circuit thin film transistor includes a gate electrode portion arranged to face the channel region, and the other circuit. The thin film transistor can also be configured to include the back gate electrode portion disposed to face the channel region.
According to this configuration, since the gates of the circuit thin film transistors arranged adjacent to each other are formed in different layers, the circuit thin film transistors can be formed without being limited by the processing limit of the gate electrode portion and the back gate electrode portion. A highly integrated peripheral circuit which can be arranged at high density and can easily cope with an increase in the number of drive pixels due to high definition can be configured.

In the active matrix substrate of the present invention, a plurality of gate electrode portions and back gate electrode portions of the circuit thin film transistor are provided, and the gate electrode portion and the back gate electrode portion are arranged in the operation direction of the circuit thin film transistor. Can be arranged alternately.
In this configuration, in a circuit thin film transistor including a plurality of gates, electrode portions that configure the plurality of gates are alternately formed in different layers along the operation direction of the transistor. By adopting such a configuration, even when the interval between the gates is narrowed, the interval between the gate electrode portions or the back gate electrode portions formed in the same layer is more than twice the interval between the gates. The gate interval can be narrowed beyond the processing limit of these electrode portions, so that the circuit thin film transistor can be miniaturized and the peripheral circuit can be highly integrated.

The active matrix substrate of the present invention may be configured such that the gate electrode portion and the back gate electrode portion provided in the circuit thin film transistor are formed at substantially the same position in plan view.
According to this configuration, the back gate electrode portion and the gate electrode portion can cooperate to apply an electric field to one channel region, and thus an on-current can be secured even if the thin film transistor is downsized. It becomes like this.

  The active matrix substrate of the present invention has a configuration in which different voltages can be applied to the back gate electrode portion provided in the pixel thin film transistor and the back gate electrode portion provided in the circuit thin film transistor. Is preferred. According to this configuration, for example, the use form of the back gate electrode part can be applied such that the pixel thin film transistor is used for stabilizing the operation and reducing the off-current, while the peripheral circuit is used as the gate of the circuit thin film transistor. become.

  Next, a display device of the present invention includes the active matrix substrate of the present invention described above. According to such a display device, a high-luminance and high-definition display can be obtained by using the active matrix substrate of the present invention.

  Next, an electronic apparatus according to the present invention includes the display device according to the present invention described above. According to this configuration, an electronic apparatus including a high-luminance and high-definition display unit is provided.

(First embodiment)
DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, a first embodiment of the invention will be described with reference to the drawings.
FIG. 1A is a plan view of a liquid crystal device, which is an example of a display device including an active matrix substrate according to the present invention, as viewed from the counter substrate side together with each component, and FIG. 1B is a plan view of FIG. FIG. 2 is a block diagram showing an electrical configuration of various wirings and peripheral circuits provided on the active matrix substrate constituting the liquid crystal device.

[Overall configuration of liquid crystal device]
As shown in FIGS. 1A and 1B, the liquid crystal device according to this embodiment includes a sealing material 52 in which a TFT array substrate (active matrix substrate) 10 and a counter substrate 20 have a substantially rectangular frame shape in plan view. And the liquid crystal layer 50 is sealed in a region surrounded by the sealing material 52. A peripheral parting part 53 having a rectangular frame shape in plan view is formed along the inner peripheral side of the sealing material 52, and an area inside the parting part is set as an image display area 51. A data line driving circuit 201 and an external circuit mounting terminal 202 are formed along one side (the lower side in the drawing) of the TFT array substrate 10 in the region outside the sealing material 52, and the two sides adjacent to this one side are formed. Scanning line driving circuits 204 and 204 are formed along the lines to form peripheral circuits. On the remaining one side (illustrated upper side) of the TFT array substrate 10, a plurality of wirings 205 are provided for connecting the scanning line drive circuits 204 on both sides of the image display area 51. Further, an inter-substrate conductive material 206 for providing electrical continuity between the TFT array substrate 10 and the counter substrate 20 is disposed at each corner of the counter substrate 20. The liquid crystal device of this embodiment is configured as a transmissive liquid crystal device, and modulates light from a light source (not shown) arranged on the TFT array substrate 10 side and emits it from the counter substrate 20 side. .

  Instead of forming the data line driving circuit 201 or the scanning line driving circuits 204 and 204 on the TFT array substrate 10, for example, a COF (Chip On Film) substrate on which a driving LSI is mounted and a TFT array substrate 10 are mounted. You may make it electrically and mechanically connect with the terminal group formed in the periphery part via an anisotropic conductive film. In the liquid crystal device, the type of liquid crystal to be used, that is, an operation mode such as a TN (Twisted Nematic) mode, an STN (Super Twisted Nematic) mode, a vertical alignment mode, or a normally white mode / normally black mode is used. Accordingly, a retardation plate, a polarizing plate, and the like are arranged in a predetermined direction, but the illustration is omitted here.

  In the image display area 51 of the liquid crystal device having such a structure, as shown in FIG. 3, a plurality of scanning lines 3a and data lines 6a are formed in the X direction and the Y direction, respectively. Pixel regions 41 each including a TFT (thin film transistor) 30, a pixel electrode 9, and a storage capacitor 70 are arranged in a matrix at the intersection of the data lines 6 a. The gate and source of the TFT 30 are connected to the scanning line 3 a and the data line 6 a, respectively, and the drain is connected to the pixel electrode 9. In addition, the storage capacitor 70 provided to improve the retention characteristic of the pixel is connected in parallel with the pixel electrode 9.

The scanning line driving circuit 204 is mainly composed of a vertical shift register, and outputs pulsed scanning signals G1, G2,... Gm based on a reference clock input from an external control device via a clock signal line (not shown). Within one vertical scanning period, the scanning line 3a is applied line-sequentially. In addition, a predetermined voltage or a pulsed electric signal can be applied to the capacitor line 3b as necessary.
The data line driving circuit 201 sequentially supplies sampling driving signals S1, S2,... Sn to each sampling driving signal line 111 based on a reference clock input from an external control device via a clock signal line (not shown). A horizontal shift register 201a and a sample hold circuit 201b that samples the image signals VID1 to VID6 supplied via the image signal line 112 are provided.

  The sample hold circuit 201b includes a sampling switch (circuit thin film transistor) 131 provided for each data line, and each sampling switch 131 receives sampling drive signals S1, S2,... Sn from the horizontal shift register 110. The image signals VID1 to VID6 sampled for each of the six image signal lines 112 are sequentially applied to each group of six adjacent data lines 6a. Thereby, the sampled image signal is supplied to each data line 6a in one horizontal scanning period (a period in which the scanning signal is supplied to one scanning line 3a by the scanning line driving circuit 204). It has become.

[Detailed pixel configuration]
3 is a plan configuration diagram showing one pixel region on the TFT array substrate 10 constituting the liquid crystal device of the present embodiment. FIG. 4 is a cross-sectional configuration diagram taken along the line AA ′ in FIG. These are the cross-section block diagrams which follow the BB 'line | wire.
As shown in FIG. 3, on the TFT array substrate, a data line 6a and a scanning line 3a are provided so as to intersect with each other, and a substantially rectangular pixel partitioned by the data line 6a and the scanning line 3a. In the region 41, a substantially planar bowl-shaped semiconductor layer 42 is provided. The scanning line 3a includes a scanning line main line portion 31 extending in a direction intersecting with the data line 6a, and a plurality of (two in FIG. 3) gate electrode portions (two in FIG. 3) extending from the main line portion 31 to the center side of the pixel region 41. Scanning line branching portions) 32 and 33, and these gate electrode portions 32 and 33 are arranged so as to intersect with a portion extending in parallel with the scanning line main line portion 31 of the semiconductor layer 42. A TFT having a dual gate (double gate) structure is formed.

One end of the substantially L-shaped semiconductor layer 42 in plan view is electrically connected to the data line 6a through the source contact hole 55 provided at the intersection with the data line 6a, while the other end of the pixel region 41 is connected. An inwardly extending L-shaped semiconductor capacitor electrode 42a is formed.
The semiconductor capacitor electrode 42 a is disposed so as to overlap with the capacitor line 3 b extending in parallel with the scanning line main line portion 31 in a plane. A portion of the L-shaped semiconductor capacitor electrode 42 a extending in the vertical direction in the figure overlaps with the data line 6 a in the plan view and extends to the side edge of the pixel region 41.

  The pixel electrode 9 formed in a planar region substantially overlapping with the pixel region 41 is made of a transparent conductive material such as ITO, and is electrically connected to the semiconductor layer 42 via the intermediate electrode layer 58. That is, the pixel electrode 9 and the intermediate electrode layer 58 are electrically connected through the pixel contact hole 57, and the intermediate electrode layer 58 and the semiconductor layer 42 of the TFT 30 are electrically connected through the drain contact hole 56. Thus, the pixel electrode 9 and the TFT 30 are electrically connected. The intermediate electrode layer 58 is disposed at a position overlapping the capacitor line 3b in plan view.

The pixel region 41 has substantially the same shape as the L-shaped semiconductor capacitor electrode 42a in plan view, and is disposed along the scanning line 3a with a capacitor electrode portion 15a disposed at substantially the same position as the semiconductor capacitor electrode 42a in plan view. In addition, a back gate wiring 15b is provided so as to overlap with a portion of the semiconductor layer 42 extending in the horizontal direction in the figure. The capacitor electrode portion 15a and the back gate wiring 15b are formed in the same layer below the semiconductor layer 42 by using the same light shielding material, and the light shielding member formed in the light shielding member layer according to the present invention. 15 is constituted. The back gate wiring 15 b functions as a back gate electrode portion of the TFT 30 at a position facing the semiconductor layer 42.
The capacitor electrode portion 15 a is disposed so as to substantially overlap the semiconductor capacitor electrode 42 a in plan view, and is electrically connected to the above-described capacitor line 3 b via the contact hole 59. As described above, by providing the conductive connection portion between the capacitor line 3b and the capacitor electrode portion 15a in the pixel region 41, it is not necessary to route the capacitor electrode portion 15a to the outside of the image display region. The disconnection of the data line 6a) and the crosstalk between the wirings can be effectively prevented.

4 and FIG. 5, the TFT array substrate 10 has a base insulating film 11 and a base insulating film 11 on one side of a substrate body (base material) 10a made of, for example, quartz, glass, plastic, or the like. A light shielding member 15 (capacitance electrode portion 15a, back gate wiring 15b) is partially formed on the base insulating film 11. A first interlayer insulating film 12 is formed so as to cover the light shielding member 15 and the substrate body 10 a, and a TFT 30 is provided on the first interlayer insulating film 12. That is, the layer between the base insulating film 11 and the first interlayer insulating film 12 is a light shielding member layer according to the present invention.
The base insulating film 11 functions as a buffer layer against over-etching in the patterning process of the light shielding member 15, and the first interlayer insulating film 12 insulates the light shielding member 15 from the TFT 30. In addition, the base insulating film 11 and the first interlayer insulating film 12 have an effect of suppressing deterioration of the characteristics of the TFT 30 due to surface roughness or contamination of the substrate body 10a.

As described above, the TFT 30 has a dual gate structure and an LDD structure. More specifically, the TFT 30 includes gate electrode portions 32 and 33, two channel regions 1 a formed in regions facing the gate electrode portions 32 and 33 of the semiconductor layer 42, and gate electrode portions 32 and 33. The insulating thin film 2 constituting a gate insulating film that insulates the semiconductor layer 42 is mainly used. Then, a low concentration source region 1b and a low concentration drain region 1c formed on both sides of the two channel regions 1a to form an LDD portion, and a high concentration source region 1d and a high concentration source region formed on both sides of these LDD portions, respectively. A concentration drain region 1e and a high concentration source / drain region 1f formed between the channel regions 1a are provided.
The semiconductor layer 42 according to this embodiment is formed of polycrystalline silicon, and amorphous silicon formed on a substrate is crystallized by a low-temperature process such as laser annealing or Ni-assisted solid phase growth. It is preferable to use it.

A second interlayer insulating film 13 is formed so as to cover the scanning line 3a, the capacitor line 3b, and the insulating thin film 2, and the data line 6a and the intermediate electrode layer 58 are formed in the same layer on the second interlayer insulating film 13. Has been. The data line 6a and the intermediate electrode layer 58 are formed using a low resistance metal such as Al.
A source contact hole 55 penetrating the second interlayer insulating film 13 is formed, and the data line 6 a and the high concentration source region 1 d of the semiconductor layer 42 are electrically connected through the source contact hole 55. On the other hand, a drain contact hole 56 penetrating the second interlayer insulating film 13 is formed, and the intermediate electrode layer 58 and the high concentration drain region 1e of the semiconductor layer 42 are electrically connected through the drain contact hole 56. .

A third interlayer insulating film 14 is formed so as to cover the data line 6 a and the intermediate electrode layer 58, and a pixel electrode 9 is formed on the third interlayer insulating film 14. A pixel contact hole 57 that penetrates the third interlayer insulating film 14 is formed in the planar region of the intermediate electrode layer 58, and the pixel electrode 9 and the intermediate electrode layer 58 are electrically connected via the pixel contact hole 57. It is connected to the. With the above configuration, the high concentration drain region 1 e of the semiconductor layer 42 and the pixel electrode 9 are electrically connected via the intermediate electrode layer 58.
Further, an alignment film 17 made of a polyimide film or the like subjected to an alignment process such as a rubbing process is provided on the pixel electrode 9 and the third interlayer insulating film 14.

As shown in FIGS. 3 to 5, in the liquid crystal device of the present embodiment, the plane of the semiconductor capacitor electrode 42 a formed by extending the high concentration drain region 1 e of the semiconductor layer 42 toward the center of the pixel region 41. In the region, a storage capacitor 70 is configured by laminating members made of a plurality of conductive materials via the insulating thin film 2 and the interlayer insulating films 12 to 14.
More specifically, in the formation region of the storage capacitor 70, the capacitor electrode portion 15a of the light shielding member layer is disposed opposite to the lower layer side of the semiconductor capacitor electrode 42a via the first interlayer insulating film 12, and the semiconductor capacitor electrode A part of 42a and a part of the capacitor electrode portion 15a are extended to the data line 6a side and face each other at a position overlapping the data line 6a in a plan view. On the upper side of the semiconductor capacitor electrode 42 a, the capacitor line 3 b is disposed so as to face the insulating thin film 2. Further, the capacitor line 3 b and the intermediate electrode layer 58 are disposed to face each other with the second interlayer insulating film 13 interposed therebetween.
As shown in FIG. 5, the capacitor electrode portion 15a sandwiching the semiconductor capacitor electrode 42a and the capacitor line 3b are electrically connected via the contact hole 59, and as shown in FIG. 4, the semiconductor capacitor electrode 42a The intermediate electrode layer 58 is electrically connected through the drain contact hole 57.

  As described above, the storage capacitor 70 includes the first storage capacitor portion including the capacitor electrode portion 15a and the semiconductor capacitor electrode 42a, the second storage capacitor portion including the semiconductor capacitor electrode 42a and the capacitor line 3b, and the capacitance. It has a laminated structure in which the third storage capacitor portion composed of the line 3b and the intermediate electrode layer 58 is overlapped in the layer thickness direction. With this configuration, in the storage capacitor 70, a large capacity can be obtained while saving the plane area occupied in the pixel region 41. As a result, the aperture ratio of the pixel region 41 can be increased, and the pixel pitch can be increased. A bright display can be obtained even when the size is narrowed to increase the definition.

In the liquid crystal device of the present embodiment, as shown in FIGS. 3 and 5, the storage capacitor 70 is formed in the planar regions of the capacitor electrode portion 15 a , the semiconductor capacitor electrode 42 a, the capacitor line 3 b, and the intermediate electrode layer 58. The formed region is formed so as to become smaller (narrower) sequentially from the substrate body 10a side. Thereby, the formation region of the member laminated on one member can be prevented from covering the step portion of the insulating film, and the capacity leak due to the step portion can be prevented.

  On the other hand, the counter substrate 20 includes a common electrode 21 formed in a solid shape on the liquid crystal layer 50 side of the substrate body 20 a and an alignment film 22 formed so as to cover the common electrode 21. The common electrode 21 can be formed of a transparent conductive material such as ITO, and the alignment film 22 can have the same configuration as the alignment film 17 of the TFT array substrate 10 described above. Further, when performing color display, a color filter including, for example, R (red), G (green), and B (blue) color material layers corresponding to each pixel region 41 is provided on the substrate body 10a or 20a. What is necessary is just to form.

In the liquid crystal device of this embodiment includes an image display area of the above structure, the light shielding member layer between the semiconductor layer 42 and the substrate main body 10a, and a back gate wiring 15b made of a light shielding material, and the capacitor electrode portion 15 a The main feature is that the The back gate wiring 15b is formed so as to cover the channel region of the TFT 30 from the substrate body 10a side, and also functions as a light shielding film that blocks light incident on the TFT 30 from the substrate body 10a side.
Further, the back gate wiring 15b can function as a back gate electrode portion of the TFT 30 in a region overlapping with the semiconductor layer 42 in a plane, and by applying a negative potential to the back gate electrode portion, The off-leakage current of the TFT 30 can be suppressed. Even when the back gate electrode portion is not set to a negative potential, the operation of the TFT 30 can be stabilized by maintaining the back gate electrode portion at a constant potential.
Furthermore, in the liquid crystal device of this embodiment, the TFT 30 has a multi-gate structure, thereby reducing the voltage on both sides of one channel region 1a and reducing off-leakage current. Since the LDD structure in which the low concentration source region 1b and the low concentration drain region 1c are formed is employed, the off-current can be reduced.

  In the high-definition liquid crystal device, since the sum of the liquid crystal capacitance and the storage capacitance of the pixel is small, if the leakage current of the TFT 30 as a switching element is large, the display quality cannot be maintained due to the charge leakage. In a polycrystalline silicon TFT, an on-current is large but an off-current is also large. Therefore, it is particularly important to suppress a leakage current. In the liquid crystal device of the present embodiment, the leakage current can be suppressed to a low level by the above-described actions. In addition, the leakage current can be effectively reduced in this way, and the storage area 70 having the above-described stacked structure can reduce the plane area of the storage capacity 70 and increase the aperture ratio of the pixel. It is like that.

In the present embodiment, as shown in FIG. 3, a back gate line 15b, the scanning line 3 a are arranged spaced apart in a plane. With this configuration, the crosstalk between the back gate line 15b that is capable inputting an electric signal to the scanning line 3 a can be prevented. In the structure in this way to separate the two in a plane, it is possible to thin the insulating film (first interlayer insulating film 12 and the insulating film 2) between the back gate line 15b and the scanning lines 3 a The capacitance formed by the capacitor electrode portion 15a formed in the same layer as the back gate wiring 15b and the semiconductor capacitor electrode 42a can be increased, which contributes to the reduction of the storage capacitor area.

  Furthermore, the reduction in the plane area of the storage capacitor 70 effectively works to improve the manufacturing yield when using a low temperature process. If the film forming temperature when forming the insulating film of each layer is low, the covering property of the insulating film is likely to deteriorate, and pinholes are likely to occur particularly in the thin insulating film (gate insulating film) 2. In the capacitor formed between the capacitor line 3b, leakage is likely to occur. Therefore, if the plane area of the storage capacitor 70 can be reduced, it is difficult to place the pinhole between the capacitor line 3b and the semiconductor capacitor electrode 42a. As a result, the operation failure due to the capacitor leak is reduced, and the high manufacturing yield. It becomes possible to manufacture a liquid crystal device.

Since the capacitor electrode portion 15a and the back gate wiring 15b are formed in the same layer on the lower layer side of the TFT 30 by using the same light-shielding material, the capacitor capacitance is formed on the substrate body 10a before the TFT 30 is formed. The electrode portion 15a and the back gate wiring 15b can be easily formed by patterning using a metal material such as WSi, for example, thereby enabling a configuration effective for high definition of the liquid crystal device. It can be realized.
As described in Patent Document 1, in a conventional liquid crystal device, a light shielding film is formed on the TFT substrate side, and this light shielding film is usually patterned after a metal thin film is formed on the entire surface of the substrate. Formed with. Therefore, if the capacitor electrode portion 15a and the back gate wiring 15b are formed in a pattern in the light shielding film forming step, the light shielding film can be manufactured without increasing the number of steps as compared with the conventional case. As described above, the liquid crystal device of the present embodiment is a liquid crystal device that is excellent in manufacturability.

  Further, as shown in FIG. 3, a part of the capacitor electrode portion 15a extends so as to overlap the data line 6a in plan view, and the capacitor electrode portion 15a is made of a light shielding material. Therefore, the capacitor electrode portion 15 a also functions as a BM (black matrix) that partitions the pixel region 41 in the TFT array substrate 10. With such a configuration, it is not necessary to provide the BM in the direction along the data line 6a on the counter substrate 20, and the aperture ratio of the pixel region 41 can be improved. This is because the BM provided on the counter substrate 20 side is formed wider than the width of the data line 6a in consideration of the misalignment between the TFT array substrate 10 and the counter substrate 20, but the BM is provided on the TFT array substrate 10 side. This is because it is not necessary to take the above-mentioned margin of misalignment, and as shown in FIG. 3, it can be narrowed to a width equal to or less than that of the data line 6a.

[Peripheral circuit]
Next, circuit thin film transistors mounted on peripheral circuits (the data line driving circuit 201 and the scanning line driving circuit 204) in the liquid crystal device of this embodiment will be described. 6 to 8 are diagrams respectively showing first to third configuration examples of circuit TFTs that can be mounted on the peripheral circuit shown in FIGS. 1 and 2.

<First configuration example>
6A is a plan configuration diagram of the circuit TFT of the first configuration example, and FIG. 6B is a cross-sectional configuration diagram taken along line FF ′ shown in FIG. As shown in FIG. 6A, this example is a configuration that can be suitably used when two circuit TFTs 80 and 81 are arranged adjacent to each other.
The circuit TFT 80 includes a semiconductor layer 800 having a rectangular shape in plan view, a gate electrode portion 810 disposed at the center of the semiconductor layer 800, a channel region 800a, and source regions provided on both sides of the channel region 800a. 800b and a drain region 800c. Then, as shown in FIG. 6B, the source region 800b and the source wiring 820 are electrically connected via two contact holes 830 provided through the insulating thin film 2 and the second interlayer insulating film 13. The drain region 800c and the drain wiring 840 are electrically connected through two contact holes 850.

  The circuit TFT 81 is disposed substantially parallel to the circuit TFT 81, and has a rectangular semiconductor layer 801 in plan view, a back gate electrode portion 811 disposed in the center of the semiconductor layer 801, a channel region 801a, and the like. , And a source region 801b and a drain region 801c formed on both sides thereof. As shown in FIG. 6B, the source region 801b and the source wiring 821 are electrically connected via two contact holes 831 provided through the insulating thin film 2 and the second interlayer insulating film 13. The drain region 801c and the drain wiring 841 are electrically connected through two contact holes 851.

  When two circuit TFTs are arranged adjacent to each other in this way, the gate of one circuit TFT 80 is constituted by the gate electrode portion 810 provided on the upper layer side of the semiconductor layer 800, and the other circuit TFT is used. Even if the distance between the semiconductor layers 80 and 81 is shortened by configuring the gate of the TFT 81 with the back gate electrode 811 provided on the lower layer side of the semiconductor layer 800, the gate electrode portion 810 and the back gate electrode portion 811 Are formed in different layers, the gate electrode portion can be arranged without being limited by the limit of workability. Therefore, if the circuit TFT having this configuration is employed, a peripheral circuit suitable for a high-definition liquid crystal device in which circuit TFTs are arranged at high density can be realized.

  Further, as shown in FIG. 6B, the back gate electrode portion 811 of the circuit TFT 81 is formed in a layer between the base insulating film 11 and the first interlayer insulating film 12 on the substrate body 10a. In the same layer as the back gate wiring 15b provided in the pixel region 41, the same light shielding material is used. Therefore, when the circuit TFTs 80 and 81 having this configuration are manufactured, the back gate electrode 811 can be formed simultaneously with the light shielding member 15 in the pixel region 41, and without increasing the number of steps, the peripheral area with high integration can be obtained. A circuit can be formed.

<Second configuration example>
FIG. 7A is a plan configuration diagram of the circuit TFT of the second configuration example, and FIG. 7B is a cross-sectional configuration diagram along the line GG ′ shown in FIG.
The circuit TFT 90 of this example is disposed between a semiconductor layer 900 having a rectangular shape in plan view, two gate electrode portions 910 and 920 intersecting with the semiconductor layer 900, and these gate electrode portions 910 and 920. A back gate electrode portion 930 intersecting with the semiconductor layer 900 is provided.
Three channel regions 900a are formed in a region of the semiconductor layer 900 facing the gate electrode portions 910 and 920 and the back gate electrode portion 930. A source region 900b and a drain region are respectively formed at both ends of the semiconductor layer 900. 900c, and a source / drain region 900d is formed between the channel regions 900a and 900a. The source region 900b and the source wiring 950 are electrically connected to each other through a contact hole 950 provided through the insulating thin film 2 and the second interlayer insulating film 13, and a contact hole 970 is also provided therethrough. The drain region 900c and the drain wiring 960 are electrically connected through the via.
The back gate electrode portion 930 is formed in a layer between the base insulating film 11 and the first interlayer insulating film 12 on the substrate body 10a as shown in FIG. In the same layer as the back gate wiring 15b provided in 41, the same light shielding material is used. The back gate electrode portion 930 functions as the gate of the circuit TFT 90 independently of the two gate electrode portions 910 and 920.

In the circuit TFT 90 of this configuration example having the above configuration, as shown in FIG. 7, the gate electrode portions 910 and 920 and the back gate electrode portion 930 are arranged in the operating direction of the TFT 90 (in FIG. 7, the extension of the semiconductor layer 900). (Direction) are alternately arranged in plan view. With this configuration, when the circuit TFT 90 is downsized, the back gate electrode portion 930 on the opposite side across the semiconductor layer 900 is disposed between the gate electrode portions 910 and 920, so that the gate interval is reduced. However, the distance between the gate electrode portions 910 and 920 in the same layer is secured. Therefore, the TFT 90 can be reduced in size beyond the processing limit, and high integration of peripheral circuits can be realized.
Further, as in the previous configuration example, the back gate electrode 930 can be formed in the same process as the light shielding member 15 in the pixel region 41 and has an advantage that it can be formed without increasing the number of processes.

<Third configuration example>
FIG. 8A is a plan configuration diagram of the circuit TFT of the third configuration example, and FIG. 8B is a cross-sectional configuration diagram along the line GG ′ shown in FIG.
The circuit TFT 100 of this example includes a semiconductor layer 1000 having a rectangular shape in plan view, a gate electrode portion 1010 extending from the upper side of FIG. 8A with respect to the semiconductor layer 1000 and intersecting the semiconductor layer 1000, and FIG. (A) A back gate electrode portion 1020 extending from the lower side and intersecting the semiconductor layer 1000 is configured, and the gate electrode portion 1010 and the back gate electrode portion 1020 are substantially at the same position in plan view. Crosses the semiconductor layer 1000. A channel region 1000a of the semiconductor layer 1000 is formed in a region sandwiched between the gate electrode portion 1010 and the back gate electrode portion 1020. A source region 1000b and a drain region 1000c are respectively formed on both sides of the channel region 1000a. As shown in FIG. 8B, contacts provided through the insulating thin film 2 and the second interlayer insulating film 13 are formed. Through the holes 1050 and 1070, the source region 1000b and the source wiring 1040 are electrically connected, and the drain region 1000c and the drain wiring 1060 are electrically connected, respectively.

  The back gate electrode portion 1020 is formed in a layer between the base insulating film 11 and the first interlayer insulating film 12 on the substrate body 10a as shown in FIG. It is formed in the same layer as the provided back gate wiring 15b using the same light shielding material. Therefore, it can be formed in the same process as the light shielding member 15 in the pixel region, as in the previous configuration example.

  In the circuit TFT 100 having the above-described structure, a gate electrode portion 1010 and a back gate electrode portion 1020 are disposed with one channel region interposed therebetween, and these electrode portions 1010 and 1020 cooperate to apply an electric field to the channel region. It can be applied. Thereby, even when the TFT 100 is downsized, a sufficient electric field can be applied to the channel region, and an on-current can be secured. Accordingly, the TFT 100 can be reduced in size without reducing the driving capability, and the peripheral circuit can be highly integrated.

  The circuit TFTs of the first to third configuration examples include, for example, the sampling switch 131 of the sample hold circuit 201b shown in FIG. 2, the inverter of the latch circuit applied to the horizontal shift register 201a, and the scanning line driving circuit 204 (complementary). Type TFT), transmission gates, and the like. By using the circuit TFT according to this embodiment, the TFT can be reduced in size and density, and the peripheral circuit can be highly integrated corresponding to the increase in the number of drive pixels due to the higher definition of the pixel. .

  As described above in detail, the liquid crystal device according to the present embodiment is provided with the capacitor electrode portion 15a and the back gate electrode 15b made of a light shielding material on the lower layer side of the semiconductor layer 42 in the image display region. Thus, it is possible to reduce the leakage current of the TFT 30 and reduce the plane area of the storage capacitor 70, and thus the pixel area 41 can have a high aperture ratio. Also, in the peripheral circuit, the back gate electrode portion is provided in the circuit TFT, so that the circuit TFT can be reduced in size and increased in density, thereby increasing the number of drive pixels accompanying higher definition. Peripheral circuits that can be fully supported can be realized. Therefore, according to the liquid crystal device of this embodiment provided with the image display area and the peripheral circuit, it is possible to obtain a high-quality display even if the pixels are made high definition.

(Second Embodiment)
FIG. 9 is a plan view showing a pixel region of the liquid crystal device according to the second embodiment of the present invention. The present embodiment is a modification of the liquid crystal device according to the present invention, and has the same configuration as the liquid crystal device of the first embodiment except that the configuration of the pixel region is different. 9 having the same reference numerals as those in FIGS. 1 to 5 have substantially the same functions as the components shown in these drawings. Hereinafter, the configuration of the pixel region will be described in detail with reference to FIGS. 1 to 5 as necessary.

  Further, the cross-sectional structure of the pixel region of the present embodiment is almost the same as that of the liquid crystal device of the first embodiment, and the cross-sectional structure along the line DD ′ in FIG. 9 is the same as the cross-sectional structure shown in FIG. Approximate agreement. Further, the cross-sectional structure taken along the line E-E ′ of FIG. 9 substantially matches the cross-sectional structure shown in FIG. 5 (however, in this embodiment, the contact hole 59 is not formed).

  The pixel region shown in FIG. 9 is a region partitioned by the data line 6a and the scanning line 3a provided so as to intersect with each other, and the semiconductor layer 42 intersects with the scanning line 3a extending in the horizontal direction in the drawing. Are arranged to constitute a TFT 30 having a dual gate structure. Specifically, a substantially U-shaped (meandering) TFT forming portion 42b of the semiconductor layer 42 arranged on the lower left side of the pixel region 41 in the drawing intersects the scanning line 3a at two locations, and these intersections. The scanning lines 3 a of the portions are the gate electrode portions 32 and 33 of the TFT 30.

  One end of the TFT forming portion 42b is electrically connected to the data line 6a through a source contact hole 55 provided at the intersection with the data line 6a, and the other end is extended to the inside of the pixel region to be a plane. The semiconductor capacitor electrode 42a has a substantially rectangular shape. The semiconductor capacitor electrode 42a is disposed so as to substantially overlap with the capacitor line 3b extending substantially parallel to the scanning line 3a in plan view. An intermediate electrode layer 58 is provided above the capacitor line 3b so as to overlap the capacitor line 3b in plan view, and the intermediate electrode layer 58 is connected to the TFT forming portion 42b (semiconductor layer 42) via the drain contact hole 56. And the pixel electrode 9 through the pixel contact hole 57.

A substantially U-shaped capacitor electrode portion 15b having a region partially overlapping with the semiconductor capacitor electrode 42a is provided. The capacitor electrode portion 15a forms a capacitor at a position overlapping the semiconductor capacitor electrode 42a in plan view, and a portion extending along the data line 6a with the position as a base end is used as a BM (black matrix) of the TFT array substrate 10. It is supposed to function.
The capacitance electrode portion 15a is U-shaped in a plan view when one pixel region is viewed, but is formed so as to extend in the extending direction of the scanning line 3a and has a comb-like shape in a plan view extending in the left-right direction in FIG. It is a member and is configured to be connectable to a peripheral circuit outside the image display area.

  The storage capacitor 70 in the pixel region shown in FIG. 9 is formed by the capacitor electrode portion 15b, the semiconductor capacitor electrode 42a, the capacitor line 3b, and the intermediate electrode layer 58 which are stacked with an insulating film interposed therebetween. Similarly, a large storage capacity is realized by a structure in which three capacitor electrode portions are stacked in the layer thickness direction. As a result, the area occupied by the storage capacitor 70 can be reduced without impairing the retention characteristics of the pixels, and as a result, a high aperture ratio can be obtained.

  Between the semiconductor capacitor electrode 42a and the scanning line 3a, a back gate wiring 15b having a region partially overlapping with the scanning line 3a is provided. As shown in FIG. 9, the back gate wiring 15b meanders in the pixel region, and is disposed so as to overlap the scanning line 3b and the TFT forming portion 42b in the region where the TFT 30 is formed, and in other regions, the scanning is performed. This is a wiring that is spaced apart from the line 3a in plan view. That is, the back gate wiring 15b functions as a back gate electrode portion of the TFT 30 and a light shielding film at a position overlapping with the TFT forming portion 42b. In other regions, the back gate wiring 15b crosses the scanning line 3a. They are spaced apart in a plane to prevent talk.

  The capacitor electrode portion 15a and the back gate wiring 15b are formed in the same layer below the semiconductor layer 42 by using the same light shielding material, as in the first embodiment. It is. Therefore, the capacitor electrode portion 15a and the binding gate wiring 15b can be formed at the same time in a process which has been conventionally formed as a light shielding film.

According to the liquid crystal device of the present embodiment having the above-described configuration, the leakage current of the TFT 30 can be suppressed to a low level as in the liquid crystal device of the first embodiment, and the plane area of the storage capacitor 70 is reduced. As a result, the aperture ratio of the pixel region can be improved, and the structure is suitable for a high-definition liquid crystal device.
In the present embodiment, since no contact hole is provided in the pixel region for conductive connection between the capacitor line 3b and the capacitor electrode portion 15a, the storage capacitor 70 is provided as compared with the pixel region according to the first embodiment. It is possible to enlarge the area. In addition, since the portion functioning as the BM of the capacitor electrode portion 15a is disposed in most of the extension region of the data line 6a, a step is formed in the formation region of the data line 6a on the surface of the third interlayer insulating film 13. Is suppressed. As a result, disconnection is unlikely to occur in the data line 6a, which can contribute to improving the reliability of the liquid crystal device.

(Electronics)
FIG. 10 is a perspective view showing an example of an electronic apparatus according to the invention. A cellular phone 1300 shown in this figure includes the liquid crystal device of the above embodiment as a small-sized display portion 1301, and includes a plurality of operation buttons 1302, an earpiece 1303, and a mouthpiece 1304.

  The display device of each of the above embodiments is not limited to the mobile phone, but is an electronic book, a personal computer, a digital still camera, a liquid crystal television, a viewfinder type or a monitor direct view type video tape recorder, a car navigation device, a pager, and an electronic notebook. , Calculators, word processors, workstations, videophones, POS terminals, devices equipped with touch panels, etc., can be suitably used as image display means, and any electronic device can display bright and high-definition. Yes.

FIG. 1A is a plan configuration diagram of the liquid crystal device according to the first embodiment, and FIG. 1B is a cross-sectional configuration diagram taken along line HH in FIG. FIG. 2 is a circuit configuration diagram of the liquid crystal device. FIG. 3 is a plan configuration diagram showing one pixel region. 4 is a cross-sectional configuration diagram taken along the line A-A ′ of FIG. 3. FIG. 5 is a cross-sectional configuration diagram taken along line B-B ′ of FIG. 3. FIG. 6A is a plan configuration diagram of the circuit TFT of the first configuration example, and FIG. 6B is a cross-sectional configuration diagram taken along the line F-F ′ of FIG. FIG. 7A is a plan configuration diagram of the circuit TFT of the second configuration example, and FIG. 7B is a cross-sectional configuration diagram taken along the line G-G ′ shown in FIG. FIG. 8A is a plan configuration diagram of a circuit TFT according to a third configuration example, and FIG. 8B is a cross-sectional configuration diagram along line J-J ′ shown in FIG. FIG. 9 is a plan configuration diagram illustrating one pixel region of the liquid crystal device according to the second embodiment. FIG. 10 is a perspective configuration diagram illustrating an example of an electronic apparatus.

Explanation of symbols

  10 TFT array substrate (active matrix substrate), 20 counter substrate, 10a, 20a substrate body, 1a channel region, 3a scanning line, 3b capacitance line, 6a data line, 9 pixel electrode, 15 light shielding member, 15a capacitance electrode portion, 15b Back gate wiring (back gate electrode portion, light shielding film), 30 (for pixel) TFT, 41 pixel area, 50 liquid crystal layer, 58 intermediate electrode layer, 70 storage capacitor, 201 data line driving circuit (peripheral circuit), 204 scanning line Driving circuit (peripheral circuit), 80, 81, 90, 100 TFT for circuit, 811, 930, 1020 Back gate electrode part

Claims (5)

An active matrix substrate comprising a base material and a plurality of pixel regions arrayed on the base material, wherein the pixel region is provided with a thin film transistor and a storage capacitor connected to the thin film transistor;
The thin film transistor includes a channel region formed in a semiconductor layer in the pixel region, and a gate electrode portion facing the channel region via an insulating film,
A light shielding member layer formed by arranging a plurality of light shielding members on the opposite side of the gate electrode portion across the semiconductor layer is provided,
The light shielding member layer is provided with a back gate wiring made of the light shielding member and having a back gate electrode portion at a position facing the channel region, and a capacitor electrode portion made of the light shielding member and forming an electrode of the storage capacitor ,
The back gate wiring is separated in a plan view from a scanning line which is a signal wiring extending along the back gate wiring in a region excluding the back gate electrode portion and its peripheral region ,
The thin film transistor includes a plurality of the gate electrode portions and a plurality of channel regions facing the plurality of gate electrode portions,
A capacitor line forming an electrode of the storage capacitor is provided on a layer opposite to the capacitor electrode part across the semiconductor layer, and the capacitor line and the capacitor electrode part are electrically connected,
An intermediate electrode layer electrically connected to the semiconductor layer is provided on a layer opposite to the semiconductor layer with the capacitance line interposed therebetween, and the intermediate electrode layer and the capacitance line are arranged so as to overlap in a plane. Has been
Planar regions of the capacitor electrode part, the semiconductor layer, the capacitor line, and the intermediate electrode layer constituting the storage capacitor are formed so as to be sequentially narrowed from the substrate side in the layer thickness direction,
The light shielding member layer is disposed to overlap the data line connected to the thin film transistor in a planar manner, and a light shielding member that forms a part of the capacitor electrode portion is formed.
An active matrix substrate , wherein the semiconductor layer is provided to a position facing a capacitor electrode portion disposed so as to overlap the data line in a layer thickness direction . 2. The active matrix according to claim 1 , wherein the gate electrode portion is provided at a scanning line branching portion that branches from a scanning line extending on the substrate and extends in a direction intersecting the scanning line. substrate. 2. The active according to claim 1 , wherein the semiconductor layer has a meandering shape in plan view and intersects the scanning line at a plurality of locations, and the gate electrode portion is provided at the intersecting portion. Matrix substrate. A display device comprising the active matrix substrate according to claim 1 . An electronic apparatus comprising the display device according to claim 4 .

Images