JP2003158270A - Electro-optic device and its manufacturing method, projection indicator, and electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electro-optic device together with its manufacturing method wherein an etching liquid does not penetrate a bonded boundary between a semiconductor substrate and a supporting substrate, when a contact hole is formed for controlling the potential of a light shielding layer by wet-etching. SOLUTION: This electro-optic device is provided with a first insulator layer 206b formed beneath a semiconductor layer 1a, a second insulator layer 12 formed under the first insulator layer 206b, a light shading layer 11a formed between the first insulator layer 206b and second insulator layer 12, and a contact hole 13 that penetrates at least the first insulator layer 206b to the light shading layer 11a. The light shading layer 11a is located above a bonded boundary between a supporting substrate 10A and a semiconductor substrate.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to Silicon On Insu
Abbreviated as lator (hereinafter, "SOI"). ) An electro-optical device to which the technology is applied, a method for manufacturing the electro-optical device, a projection-type display device, and an electronic apparatus, and in particular, an electro-optical device and an electro-optical device that can be manufactured with high yield and have high reliability. The present invention relates to a manufacturing method, and a highly reliable projection display device and electronic equipment including the electro-optical device.

[0002]

2. Description of the Related Art The SOI technique of forming a semiconductor thin film made of silicon or the like on an insulating substrate and forming the semiconductor thin film on a semiconductor device can achieve high speed operation, low power consumption and high integration of elements. Since it has advantages such as
For example, the technique is preferably applied to an electro-optical device.

In order to manufacture an electro-optical device to which the SOI technique is applied, a thin film single crystal semiconductor layer is formed by a method of laminating a semiconductor substrate having a single crystal semiconductor layer made of single crystal silicon or the like on a supporting substrate and polishing the same. Then, the thin film single crystal semiconductor layer is formed into a transistor element such as a thin film transistor (hereinafter referred to as “TFT”) for driving a liquid crystal.

Further, an electro-optical device using the SOI technique has been conventionally applied to a liquid crystal light valve of a projection type display device such as a liquid crystal projector. In such a liquid crystal light valve, when the supporting substrate is light transmissive, the light incident from the display surface side is reflected at the interface on the rear surface side of the supporting substrate and returns to the channel region of the transistor element such as TFT. May be incident as. For this reason,
A liquid crystal light valve has been proposed in which a light blocking layer for blocking return light is formed at a position corresponding to a transistor element region on the surface side of a supporting substrate. In a liquid crystal light valve in which a light-shielding layer is formed on the surface of such a supporting substrate, the light-shielding layer and the constant potential source are electrically connected to fix the potential of the light-shielding layer to the constant potential. Therefore, the potential fluctuation of 1 does not adversely affect the transistor element.

In order to manufacture an electro-optical device having a light-shielding layer on the surface of such a supporting substrate, a light-shielding layer is patterned on the surface of the supporting substrate, covered with an insulating layer and planarized by polishing. A semiconductor substrate is attached to the obtained flat surface. Then, a thin film single crystal semiconductor layer is formed by a method of polishing the single crystal semiconductor layer forming the semiconductor substrate, and the thin film single crystal semiconductor layer is formed into, for example, TF for driving a liquid crystal.
It is formed in a transistor element such as T. In addition, in a place where the thin film single crystal semiconductor layer of the semiconductor substrate attached to the supporting substrate does not exist, a contact hole which penetrates the insulating layer provided on the supporting substrate and reaches the light shielding layer is wet-etched. The light shielding layer and the constant potential source are electrically connected through the contact hole.

[0006]

However, in the above-mentioned electro-optical device, the contact hole used for controlling the potential of the light-shielding layer is formed by wet etching the insulator layer provided on the supporting substrate. Since it is obtained by penetrating, the etching solution permeates from the bonding interface between the supporting substrate and the semiconductor substrate when forming the contact hole, and even the layers forming the bonding interface are etched. There is a problem. And
When the layer forming the bonding interface is etched, a defect such as separation between the supporting substrate and the semiconductor substrate is likely to occur, which results in reduction in product yield.

The present invention has been made to solve the above problems, and in an electro-optical device to which the SOI technique is applied and a light shielding layer is formed on the surface of a supporting substrate, the potential of the light shielding layer is determined. When forming a contact hole for fixing to the potential using wet etching, since the disadvantage that the etching solution permeates from the bonding interface between the semiconductor substrate and the supporting substrate does not occur, it can be manufactured with high yield, It is an object of the present invention to provide an electro-optical device with high reliability. Another object of the present invention is to provide a method for manufacturing the above electro-optical device, and a highly reliable projection display device and electronic equipment including the above electro-optical device.

[0008]

In order to achieve the above object, the electro-optical device of the present invention is an electro-optical device using a composite substrate obtained by laminating a semiconductor substrate having a semiconductor layer on a supporting substrate. A device, comprising: a first insulator layer provided below the semiconductor layer; a second insulator layer provided below the first insulator layer; and a first insulator layer. A light-shielding layer provided between the second insulator layer and a contact hole penetrating at least the first insulator layer to reach the light-shielding layer, the light-shielding layer including the support substrate and the semiconductor. It is characterized in that it is located above the bonding interface with the substrate.

That is, in the electro-optical device of the present invention, the supporting substrate, the second insulating layer, the light shielding layer, the first insulating layer, and the semiconductor layer are provided in this order from the lower side, and the bonding interface is provided. The contact hole that penetrates the first insulating layer located above the light shielding layer located above the light shielding layer and reaches the light shielding layer does not penetrate the bonding interface between the semiconductor substrate and the support substrate. Become. Therefore, when the contact hole is formed by wet etching, the disadvantage that the etching liquid permeates from the bonding interface between the semiconductor substrate and the supporting substrate does not occur unlike the conventional electro-optical device. Therefore, the electro-optical device can be manufactured with high yield and has high reliability.

Further, in the electro-optical device of the present invention, as described above, the light shielding layer is located above the bonding interface between the supporting substrate and the semiconductor substrate. Therefore, as shown below, the thickness of the first insulator layer can be reduced to shorten the distance between the semiconductor layer and the light shielding layer.

For example, when the light-shielding layer is located below the bonding interface, there is a bonding interface between the semiconductor layer and the light-shielding layer, so that the semiconductor layer and the light-shielding layer are separated from each other. The distance between cannot be shortened. If there is a bonding interface between the semiconductor layer and the light shielding layer,
Regarding the distance between the semiconductor layer and the light shielding layer, when performing the chemical mechanical polishing method, the distance of the remaining film thickness such that the light shielding layer is not exposed due to variations in polishing, or the distance between the supporting substrate and the semiconductor substrate is set. A distance corresponding to the thickness required for bonding will be included. Therefore, usually, the distance between the semiconductor layer and the light shielding layer is a dimension obtained as a result after the supporting substrate and the semiconductor substrate are bonded together, and the thickness required to insulate the semiconductor layer and the light shielding layer. Much thicker than 800
It is about nm to 1000 nm. Further, if the distance between the semiconductor layer and the light shielding layer is 200 nm or less,
Since the chemical mechanical polishing method before bonding becomes difficult, when the light-shielding layer is located below the bonding interface, the distance between the semiconductor layer and the light-shielding layer is set to 2 mm.
It cannot be less than 00 nm.

On the other hand, according to the electro-optical device of the present invention, as described above, the light-shielding layer is located above the bonding interface between the supporting substrate and the semiconductor substrate. Since there is no bonding interface between the light-shielding layer and the light-shielding layer, the light-shielding layer is not exposed at the distance between the semiconductor layer and the light-shielding layer due to variations in polishing by the chemical mechanical polishing method. It does not include the distance of the film thickness or the distance corresponding to the thickness required when the supporting substrate and the semiconductor substrate are bonded together. Therefore, the distance between the semiconductor layer and the light shielding layer can be shortened within a range in which the semiconductor layer and the light shielding layer can be insulated. That is, in the electro-optical device of the present invention, it is possible to reduce the thickness of the first insulator layer corresponding to the distance between the semiconductor layer and the light shielding layer. When the thickness of the first insulator layer is reduced, the semiconductor layer and the light shielding layer come close to each other, so that the light shielding layer can be positively used as a back gate of a TFT, for example, and the potential of the light shielding layer can be controlled. Thus, the off-leakage current can be reduced and the on-current can be increased.

Specifically, in the above electro-optical device, the thickness of the first insulator layer is 30 nm to 200 nm.
It is desirable that the range is. With such an electro-optical device, the semiconductor layer and the light-shielding layer can be reliably insulated, and the off-leakage current can be reduced or the on-current can be increased by controlling the potential of the light-shielding layer. Therefore, the electro-optical device can be made even more excellent.

Further, in the above electro-optical device, the thickness of the first insulator layer is more preferably in the range of 50 nm to 100 nm. With such an electro-optical device, the semiconductor layer and the light-shielding layer can be more reliably insulated, and the off-leakage current can be more effectively reduced and the on-current can be increased more effectively. Becomes

Further, in order to achieve the above object, the electro-optical device of the present invention uses an electro-optical device that uses a composite substrate in which a semiconductor substrate having a semiconductor layer and a light-shielding layer is laminated on a supporting substrate. The device is characterized in that the light-shielding layer is located above the bonding interface between the support substrate and the semiconductor substrate. In such an electro-optical device, the light-shielding layer is located above the bonding interface between the support substrate and the semiconductor substrate, and therefore penetrates the member formed above the light-shielding layer. When a contact hole reaching the light shielding layer is provided, the contact hole does not penetrate the bonding interface between the semiconductor substrate and the supporting substrate. Therefore, when this contact hole is formed by wet etching, there is no inconvenience that the etching solution permeates from the bonding interface between the semiconductor substrate and the supporting substrate, unlike the conventional electro-optical device. The light shielding layer is located above the bonding interface between the support substrate and the semiconductor substrate. Therefore, there is no bonding interface between the semiconductor layer and the light shielding layer, and the distance between the semiconductor layer and the light shielding layer is shortened within a range in which the semiconductor layer and the light shielding layer can be insulated. be able to.

In order to achieve the above-mentioned object, a projection display device of the present invention is a projection display device including the above electro-optical device, comprising a light source and light emitted from the light source. The electro-optical device for modulation and the magnifying projection optical system for magnifying and projecting the light modulated by the electro-optical device onto a projection surface are characterized by being provided. Since such a projection display device includes the electro-optical device described above, it can be a highly reliable projection display device.

In order to achieve the above object, an electronic apparatus of the present invention is characterized by including the above electro-optical device. With such an electronic device, an electronic device including a highly reliable display portion can be provided.

In order to achieve the above object, the method of manufacturing an electro-optical device according to the present invention is an electro-optical device using a composite substrate obtained by bonding a semiconductor substrate having a semiconductor layer on a supporting substrate. A method of manufacturing the semiconductor substrate, wherein a step of sequentially forming a first insulating layer, a light-shielding layer, and a second insulating layer on a surface of the semiconductor substrate on a side to be bonded to the supporting substrate; A step of forming the composite substrate by bonding the semiconductor substrates, a step of patterning the semiconductor layer, and a contact hole penetrating the first insulator layer and reaching the light shielding layer are formed by wet etching. And a process.

In such a method of manufacturing an electro-optical device, a step of sequentially forming a first insulating layer, a light shielding layer and a second insulating layer on the surface of the semiconductor substrate on which the supporting substrate is bonded. And a step of bonding the semiconductor substrate on the supporting substrate to form the composite substrate, so that the light shielding layer is positioned above the bonding interface between the supporting substrate and the semiconductor substrate. You are doing
In the step of forming a contact hole that penetrates the first insulating layer and reaches the light shielding layer by wet etching, it is not necessary to penetrate the bonding interface between the semiconductor substrate and the supporting substrate. Therefore, when the contact hole is formed by wet etching, the disadvantage that the etching solution permeates from the bonding interface between the semiconductor substrate and the supporting substrate does not occur. Therefore, it is possible to manufacture the electro-optical device with high yield and with high reliability.

Further, a step of sequentially forming a first insulator layer, a light-shielding layer, and a second insulator layer on a surface of the semiconductor substrate which is to be attached to the support substrate, and the semiconductor on the support substrate. A semiconductor substrate and a support substrate are bonded together after a light-shielding layer is formed on a semiconductor substrate, so that the semiconductor layer and the light-shielding layer are bonded together. There is no bonding interface between them. Therefore, the thickness of the first insulator layer, which corresponds to the distance between the semiconductor layer and the light shielding layer, can be reduced within a range in which the semiconductor layer and the light shielding layer can be insulated.

In the method of manufacturing the electro-optical device, the first insulator layer has a thickness of 30 nm to 200 nm.
It is desirable to form it in the range of nm. By using such a method for manufacturing an electro-optical device, the semiconductor layer and the light-shielding layer can be reliably insulated, and the potential of the light-shielding layer can be controlled to reduce off-leakage current and reduce on-current. A superior electro-optical device that can be increased is obtained.

In the method of manufacturing the electro-optical device described above, chemical mechanical polishing (CM) is performed on the second insulator layer.
It is desirable to flatten using the P) method. With such a method of manufacturing an electro-optical device, the second insulator layer can be easily and accurately planarized, and the second insulator layer forms the bonding interface between the supporting substrate and the semiconductor substrate. In this case, the adhesiveness between the support substrate and the semiconductor substrate can be increased, and the substrates can be easily and accurately bonded together. Therefore, an electro-optical device having high reliability can be easily formed.

(First Embodiment) (Structure of Electro-Optical Device) Hereinafter, embodiments of the present invention will be described in detail. In the present embodiment, an active matrix type liquid crystal device using a TFT (transistor element) as a switching element will be described as an example of an electro-optical device.

FIG. 1 is an equivalent circuit of various elements, wirings, etc. in a plurality of pixels formed in a matrix which constitutes a pixel portion (display area) of a liquid crystal device. Further, FIG. 2 shows a TF in which a data line, a scanning line, a pixel electrode, a light shielding layer, etc. are formed.
FIG. 3 is an enlarged plan view showing a plurality of pixel groups adjacent to each other on a T array substrate. 3 is a sectional view taken along the line AA ′ of FIG. 1 to 3, the scales are different for each layer and each member in order to make each layer and each member recognizable in the drawings.

In FIG. 1, a plurality of pixels formed in a matrix form a pixel portion of a liquid crystal device, a plurality of pixel electrodes 9a formed in a matrix and a pixel switching TFT (for controlling the pixel electrode 9a). And a data line 6 to which an image signal is supplied.
a is electrically connected to the source of the pixel switching TFT 30. The image signals S1, S2, ..., Sn to be written to the data line 6a may be line-sequentially supplied in this order, and may be supplied to a plurality of adjacent data lines 6a.
It may be supplied for each group. Further, the scanning line 3a is electrically connected to the gate of the pixel switching TFT 30, and the scanning signals G1, G2, ..., Gm are pulse-wise applied in this order to the scanning line 3a in a pulsed manner at a predetermined timing. Is configured to.

The pixel electrode 9a is a pixel switching TF.
The pixel line switching TFT 30, which is electrically connected to the drain of T30, is closed for a certain period of time to close the data line 6a.
, Sn are supplied at predetermined timing. Image signals S1, S2, ..., Sn of a predetermined level written in the liquid crystal through the pixel electrode 9a.
Are held for a certain period of time with a counter electrode described later formed on a counter substrate.

Further, in order to prevent a display defect such as a decrease in contrast ratio and flicker called flicker due to leakage of the held image signal, a liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode is formed. A storage capacitor 70 is added in parallel. For example, the voltage of the pixel electrode 9a is held by the storage capacitor 70 for a time that is three orders of magnitude longer than the time when the voltage is applied to the data line. This allows
The holding characteristics are further improved, and an electro-optical device having a high contrast ratio can be realized. In the present embodiment, in particular, in order to form such a storage capacitor 70, the capacitance line 3b having a low resistance is provided by using the same layer as the scanning line or a conductive light shielding layer as described later.

Next, with reference to FIG. 2, the planar structure in the transistor element formation region (pixel portion) of the TFT array substrate will be described in detail. As shown in FIG. 2, a plurality of transparent pixel electrodes 9a (indicated by dotted line portions 9a ') are arranged in a matrix form in a transistor element formation region (pixel portion) on the TFT array substrate of the electro-optical device. Are provided, and the data line 6a, the scanning line 3a, and the capacitance line 3b are provided along the vertical and horizontal boundaries of the pixel electrode 9a. The data line 6a is electrically connected to the later-described source region of the semiconductor layer 1a through the contact hole 5, and the pixel electrode 9a is electrically connected to the later-described drain region of the semiconductor layer 1a through the contact hole 8. It is electrically connected. In addition, the scanning line 3 is arranged so as to face the channel region (the hatched region in the upper right of the figure) of the semiconductor layer 1a.
a is arranged, and the scanning line 3a functions as a gate electrode.

In FIG. 2, a plurality of light-shielding layers 11a are provided in the area shown by the diagonal lines rising to the right. More specifically, each of the light shielding layers 11a is a pixel switching TFT including the channel region of the semiconductor layer 1a in the pixel portion.
The TFT array substrate is provided at a position that covers the TFT array substrate when viewed from the side of the substrate body, which will be described later. Further, a main line portion that extends linearly along the scanning line 3a facing the main line portion of the capacitance line 3b and a data line. 6a, and a protruding portion that protrudes from the position intersecting with 6a to the adjacent step side (that is, downward in the drawing) along the data line 6a. The tip of the downward projecting portion in each step (pixel row) of the light shielding layer 11a is overlapped with the tip of the upward projecting section of the capacitance line 3b in the next step below the data line 6a. A contact hole 13 for electrically connecting the light-shielding layer 11a and the capacitance line 3b to each other is provided at this overlapping portion.
Is provided. That is, in the present embodiment, the light shielding layer 11
A is electrically connected to the capacitance line 3b at the front stage or the rear stage by the contact hole 13.

In the present embodiment, the pixel electrode 9
a, the pixel switching TFT 30, and the light shielding layer 11a
Are provided only in the pixel portion.

Next, referring to FIG. 3, the cross-sectional structure in the pixel portion of the liquid crystal device will be described. TFT array substrate 10
Is a support substrate 10A made of quartz, a pixel electrode 9a formed on the surface of the support substrate 10A on the liquid crystal layer 50 side, and a pixel switching T.
The counter substrate 20 is mainly composed of an FT (transistor element) 30 and an alignment film 16, and the counter substrate 20 is formed on the substrate body 20A made of a transparent substrate such as transparent glass or quartz and on the liquid crystal layer 50 side surface thereof. Counter electrode (common electrode) 21
And the alignment film 22 as main components.

A pixel electrode 9a is provided on the surface of the support substrate 10A of the TFT array substrate 10 on the liquid crystal layer 50 side, and the liquid crystal layer 50 side is subjected to a predetermined alignment treatment such as rubbing treatment. An alignment film 16 is provided. The pixel electrode 9a is made of a transparent conductive thin film such as ITO (indium tin oxide), and the alignment film 16 is
For example, it is made of an organic thin film such as polyimide.

Further, as shown in FIG. 3, on the surface of the supporting substrate 10A on the liquid crystal layer 50 side, a pixel switching TFT 30 for switching control of each pixel electrode 9a is provided at a position adjacent to each pixel electrode 9a. ing.

On the other hand, a counter electrode (common electrode) 21 is provided on the entire surface of the substrate body 20A of the counter substrate 20 on the liquid crystal layer 50 side, and the liquid crystal layer 50 side is rubbed. An alignment film 22 that has been subjected to a predetermined alignment treatment such as is provided. The counter electrode 21 is, for example, ITO.
The alignment film 22 is made of an organic thin film such as polyimide.

Further, on the surface of the substrate body 20A on the liquid crystal layer 50 side, as shown in FIG. 3, a counter substrate light shielding layer 23 is provided in a region other than the opening region of each pixel portion. By providing the counter substrate light-shielding layer 23 on the counter substrate 20 side as described above, incident light from the counter substrate 20 side is incident on the channel region 1a ′ of the semiconductor layer 1a of the pixel switching TFT 30 and the LDD (Lightly Doped Drain) regions 1b and 1c. It is possible to prevent the invasion into the area and improve the contrast.

Between the TFT array substrate 10 and the counter substrate 20 which are arranged as described above and are arranged so that the pixel electrode 9a and the counter electrode 21 face each other, a seal formed between the peripheral portions of both substrates. Liquid crystal is enclosed in a space surrounded by a material (not shown) to form a liquid crystal layer 50.

The liquid crystal layer 50 is made of, for example, a liquid crystal in which one kind or several kinds of nematic liquid crystals are mixed, and the alignment film 16 is formed in a state where the electric field from the pixel electrode 9a is not applied.
A predetermined orientation state is adopted by the elements 22 and 22.

The TFT array substrate 10 uses a composite substrate obtained by laminating a single crystal silicon substrate on the supporting substrate 10A, and the liquid crystal layer 5 of the supporting substrate 10A.
The lower bonding film 10B provided on the 0-side surface and the upper bonding film 12 provided on the lower bonding film 10B (corresponding to the "second insulating layer" in the claims). Is a bonding interface between the support substrate 10A and the semiconductor substrate.

On the surface of the upper bonding film 12,
At the position corresponding to each pixel switching TFT 30,
The light shielding layer 11a is embedded. As will be described later, the light shielding layer 11a is formed on the surface of the single crystal silicon substrate on the side to be bonded to the support substrate 10A, and then the support substrate 1 is formed.
Since it is formed on the supporting substrate 10A by bonding the single crystal silicon substrate 208 on the substrate 0A,
The upper bonding film 12 formed on the single crystal silicon substrate provided with the light shielding layer 11a so as to cover the light shielding layer 11a.
It is in a state of being embedded by.

The light shielding layer 11a is preferably an opaque refractory metal such as Ti, Cr, W, Ta, Mo and P.
It is composed of a simple metal, an alloy, a metal silicide, or the like containing at least one of d. By forming the light shielding layer 11a from such a material, the TFT array substrate 1
On the surface of the support substrate 10A of 0, the pixel switching TFT 30 performed after the step of forming the light shielding layer 11a.
By the high temperature treatment in the forming step, it is possible to prevent the light shielding layer 11a from being broken or melted.

In this embodiment, the TFT is
Since the light-shielding layer 11a is formed on the array substrate 10,
The return light or the like from the TFT array substrate 10 side is the channel region 1a ′ of the pixel switching TFT 30 and the LDD region 1
It is possible to prevent the incident light from entering b and 1c, and prevent the characteristics of the pixel switching TFT 30 as a transistor element from being deteriorated due to the generation of photocurrent.

A first interlayer insulating film 206b (corresponding to the "first insulator layer" in the claims) is provided on the upper bonding film 12 and the light shielding layer 11a. The first interlayer insulating film 206b is provided to electrically insulate the semiconductor layer 1a forming the pixel switching TFT 30 from the light shielding layer 11a, and is formed on the entire surface of the support substrate 10A. Further, by providing the first interlayer insulating film 206b on the surface of the TFT array substrate 10 as described above, it is possible to prevent the light shielding layer 11a from contaminating the pixel switching TFT 30 and the like.

The thickness of the first interlayer insulating film 206b is 30 n.
The range of m to 200 nm is more preferable, and the range of 50 nm to 100 nm is more preferable. First interlayer insulating film 206b
If the thickness is less than 30 nm, the semiconductor layer and the light-shielding layer may not be reliably insulated, which is not preferable. In addition, the thickness of the first interlayer insulating film 206b is 20
When the thickness is within 0 nm, the light shielding layer can be positively used as a back gate.

Further, in this embodiment, the light shielding layer 11a (and the capacitor line 3b electrically connected thereto) penetrates the first interlayer insulating film 206b and reaches the light shielding layer 11a through the contact hole 13. A constant potential is established by being electrically connected to the constant potential source. Therefore, the light shielding layer 1
The potential fluctuation of the light-shielding layer 11a does not adversely affect the pixel switching TFT 30 that is arranged to face 1a. Further, the capacitance line 3b can function well as the second storage capacitance electrode of the storage capacitance 70. As the constant potential source, a constant potential source such as a negative power source or a positive power source supplied to a peripheral circuit (for example, a scanning line driving circuit, a data line driving circuit, etc.) for driving the electro-optical device of this embodiment, a ground Power supply, counter electrode 2
1 may be a constant potential source or the like. As described above, by using the power source for the peripheral circuit or the like, the light shielding layer 11a and the capacitance line 3b can be set to a constant potential without the need to provide a dedicated potential wiring or an external input terminal.

Further, when the variable voltage is applied to the light shielding layer 11a, the off leak current can be reduced and the on current can be increased by controlling the potential of the light shielding layer 11a.

Further, in this embodiment, the gate insulating film 2 is extended from the position facing the scanning line 3a to be used as a dielectric film, and the semiconductor film 1a is extended to be the first storage capacitor electrode 1f. The storage capacitor 70 is configured by using a part of the capacitance line 3b facing these as the second storage capacitor electrode.

More specifically, the high-concentration drain region 1e of the semiconductor layer 1a is extended below the data line 6a and the scanning line 3a, and the portion of the capacitance line 3b also extending along the data line 6a and the scanning line 3a. Are opposed to each other via the insulating film 2 and serve as a first storage capacitor electrode (semiconductor layer) 1f.
In particular, since the insulating film 2 as the dielectric of the storage capacitor 70 is nothing but the gate insulating film 2 of the pixel switching TFT 30 formed on the single crystal semiconductor layer by high temperature oxidation, it should be a thin and high breakdown voltage insulating film. The storage capacity is 70
Can be configured as a large-capacity storage capacitor with a relatively small area.

Further, in the storage capacitor 70, as can be seen from FIGS. 2 and 3, the light shielding layer 11a is provided on the first storage capacitor electrode 1f on the side opposite to the capacitance line 3b as the second storage capacitor electrode. By arranging them as the third storage capacitor electrodes so as to face each other via the insulating film 206b (see the storage capacitor 70 on the right side of FIG. 3), the storage capacitor is further provided. That is, in the present embodiment, the double storage capacitor structure in which the storage capacitors are provided on both sides of the first storage capacitor electrode 1f is constructed, and the storage capacitance is further increased. With such a structure, it is possible to improve the function of the electro-optical device according to the present embodiment to prevent flicker and burn-in in a display image.

As a result, the space outside the opening region, that is, the region below the data line 6a and the region where the liquid crystal disclination occurs along the scanning line 3a (that is, the region where the capacitance line 3b is formed) is effective. Can be used to increase the storage capacity of the pixel electrode 9a.

Next, in FIG. 3, the pixel switching TFT 30 is a fully depleted N-type transistor.
The semiconductor layer 1a has a constant film thickness in the range of 30 nm to 100 nm, preferably in the range of 40 nm to 60 nm. When the film thickness of the semiconductor layer 1a is 100 nm or less, the depletion layer controlled by the gate electrode spreads larger than that of the semiconductor layer 1a regardless of the impurity concentration of the channel portion, so that the pixel switching TFT 30 becomes a complete depletion type.

Further, the pixel switching TFT 30 is
The scanning line 3a has a LDD (Lightly Doped Drain) structure, the channel region 1a 'of the semiconductor layer 1a in which a channel is formed by an electric field from the scanning line 3a, and the scanning line 3
a, the gate insulating film 2 for insulating the semiconductor layer 1a from the semiconductor layer 1a, the data line 6a, and the low-concentration source region (source side L
DD region) 1b and low-concentration drain region (drain side L)
DD region) 1c, high-concentration source region 1d of the semiconductor layer 1a
In addition, the high concentration drain region 1e is provided.

Since the semiconductor layer 1a has a thickness of 30 nm or more, preferably 40 nm or more, the channel region 1a '
It is possible to reduce variations in transistor characteristics such as the threshold voltage due to the film thickness of. Further, since the semiconductor layer 1a has a thickness of 100 nm, preferably 60 nm or less, even if the semiconductor layer 1a is irradiated with stray light that cannot be prevented by the light shielding layer 11a, the amount of photoexcited electron-hole pairs can be suppressed to be small. it can. Therefore, the light leak current can be reduced, and the pixel switching TFT 3 which is a pixel switching element.
It is valid as 0.

The data line 6a is composed of a light-shielding metal thin film such as a metal film such as Al or an alloy film such as metal silicide. In addition, a contact hole 5 leading to the high-concentration source region 1d and a contact hole 8 leading to the high-concentration drain region 1e are formed on the scanning line 3a, the gate insulating film 2, and the first interlayer insulating film 206b, respectively. The interlayer insulating film 4 is formed. The data line 6a is electrically connected to the high-concentration source region 1d through the contact hole 5 to the source region 1b. Furthermore, the data line 6a
And the high-concentration drain region 1 on the second interlayer insulating film 4.
A third interlayer insulating film 7 in which a contact hole 8 to e is formed is formed. The pixel electrode 9a is electrically connected to the high concentration drain region 1e through the contact hole 8 to the high concentration drain region 1e. The above-mentioned pixel electrode 9a is provided on the upper surface of the third interlayer insulating film 7 thus configured. The pixel electrode 9a and the high-concentration drain region 1e may be electrically connected by relaying the same Al film as the data line 6a or the same poly semiconductor film as the scanning line 3b.

Although the pixel switching TFT 30 preferably has the LDD structure as described above, it may have an offset structure in which the low concentration source region 1b and the low concentration drain region 1c are not implanted with impurity ions, respectively. A self-aligned TFT may be used in which high-concentration source and drain regions are formed in a self-aligned manner by implanting impurity ions at a high concentration using the electrode 3a as a mask.

Further, although the single gate structure in which only one gate electrode (scanning line) 3a of the pixel switching TFT 30 is arranged between the source-drain regions 1b and 1e is used, two or more gate electrodes are provided between them. You may arrange. At this time, the same signal is applied to each gate electrode. If the TFT is configured with a double gate or a triple gate or more as described above, it is possible to prevent a leak current at the junction between the channel and the source-drain region, and to reduce the off-state current. If at least one of these gate electrodes has an LDD structure or an offset structure, the off current can be further reduced, and a stable switching element can be obtained.

Here, in general, the single crystal semiconductor layers such as the channel region 1a ', the low-concentration source region 1b, and the low-concentration drain region 1c of the semiconductor layer 1a are photocurrent due to the photoelectric conversion effect of the semiconductor when light enters. However, in this embodiment, the data line 6a is formed of a light-shielding metal thin film such as Al so as to cover the scanning line 3a from the upper side. Light can be effectively prevented from entering at least the channel region 1a ′ and the LDD regions 1b and 1c of the semiconductor layer 1a.

Further, as described above, since the light shielding layer 11a is provided below the pixel switching TFT 30, at least the channel region 1a 'of the semiconductor layer 1a, the low concentration source region 1b, and the low concentration drain region are formed. It is also possible to effectively prevent the returning light to 1c from entering. Furthermore, even if there is incident light that leaks from the above structure, the semiconductor layer 1 of the pixel switching TFT 30
Since a is thin, light leakage can be sufficiently suppressed.

In the present embodiment, the semiconductor layer 1
It is needless to say that a is not limited to the case of a single crystal semiconductor, and the same structure can be applied to the case where the semiconductor layer 1a is a polycrystalline semiconductor.

(Method for Manufacturing Electro-Optical Device) Next, a method for manufacturing the electro-optical device having the above structure will be described with reference to FIGS. First, a method of manufacturing the TFT array substrate 10 will be described with reference to FIGS. 4 to 8 and 9 to 13 are shown at different scales.

First, as shown in FIG. 4A, for example,
A single crystal silicon substrate 208 (corresponding to the "semiconductor substrate" in the claims) including a single crystal silicon layer (corresponding to the "semiconductor layer" in the claims) having a thickness of about 600 µm is prepared. . A first interlayer insulating film 206 made of a silicon oxide film is formed on the surface of the single crystal silicon substrate 208 on the side to be bonded to the supporting substrate 10A.
b (corresponding to the "first insulator layer" in the claims) is formed in advance. First interlayer insulating film 2
06b is formed by oxidizing the surface of the single crystal silicon substrate 208, and the thickness of the first interlayer insulating film 206b is in the range of 30 nm to 200 nm, and more preferably in the range of 50 nm to 100 nm.

Further, on the surface of the single crystal silicon substrate 208 on the side where it is bonded to the supporting substrate 10A, hydrogen ions (H ⁺ ) are, for example, accelerating voltage 100 keV and dose 10.
× being injected at 10 ^{1 6} / cm ^2.

Next, as shown in FIG. 4B, T is formed on the first interlayer insulating film 206b of the single crystal silicon substrate 208.
A film of, for example, 150 to 200 nm formed by using a metal simple substance, an alloy, a metal silicide, or the like containing at least one of i, Cr, W, Ta, Mo, and Pd by a sputtering method, a CVD method, an electron beam heating evaporation method, or the like. The light shielding layer 11 is formed by thickly depositing.

Next, a photoresist is formed on the entire surface of the single crystal silicon substrate 208, and the photoresist is exposed using a photomask having a pattern (see FIG. 2) of the light shielding layer 11a to be finally formed. . Then, the photoresist is developed to form a photoresist 207 having a pattern of the light shielding layer 11a to be finally formed, as shown in FIG.

Next, the light shielding layer 11 is etched by using the photoresist 207 as a mask, and then the photoresist 207 is peeled off, so that the surface of the single crystal silicon substrate 208 is formed as shown in FIG. 4D. The light shielding layer 11a having a predetermined pattern is formed. Light-shielding layer 11
The film thickness of a is, for example, 150 to 200 nm.

Next, as shown in FIG. 5A, the light shielding layer 1
On the surface of the single crystal silicon substrate 208 on which 1a is formed, the upper bonding film 12 made of SiO ₂ is formed by the CVD method or the like (the “second insulator layer” in the claims).
Corresponding to the above) is formed. The film thickness of the insulator layer 12A is set to be thicker than at least the film thickness of the light shielding layer 11a, and is preferably about 400 to 1200 nm, more preferably 1000 to 1200 nm.
The degree.

Next, as shown in FIG. 5B, the light shielding layer 1
CMP the surface of the insulator layer 12A located on the 1a.
The upper bonding film 12 that forms the bonding interface with the support substrate 10A is formed by polishing and planarizing using the (chemical mechanical polishing) method. The film thickness of the upper bonding film 12 is, for example, 400 to 600 nm. As described above, the first interlayer insulating film 206b and the light shielding layer 11a
The single crystal silicon substrate 208 including the upper bonding film 12 and the upper bonding film 12 is formed.

Next, as shown in FIG. 5C, the supporting substrate 10A and the single crystal silicon substrate 208 are bonded to each other to form a composite substrate. A lower bonding film 10B forming a bonding interface 221 with the single crystal silicon substrate 208 is previously formed on the surface of the supporting substrate 10A used here that is bonded to the single crystal silicon substrate 208. . Like the upper bonding film 12, the lower bonding film 10B is made of SiO ₂ and is formed by the CVD method or the like. The support substrate 10A and the single crystal silicon substrate 208 are the support substrate 1
0A lower bonding film 10B and single crystal silicon substrate 2
No. 08 of the upper bonding film 12 faces each other, and the lower bonding film 10B and the upper bonding film 12 serve as a bonding interface 221.

The bonding of the support substrate 10A and the single crystal silicon substrate 208 here is performed by heat treatment at 300 ° C. for 2 hours, for example. In order to further increase the bonding strength between the supporting substrate 10A and the single crystal silicon substrate 208, it is necessary to raise the heat treatment temperature to about 450 ° C., but the supporting substrate 10A made of quartz or the like and the single crystal silicon substrate 208 are required. Since the difference in the thermal expansion coefficient between the single crystal silicon substrate 208 and the single crystal silicon substrate 208 is further heated, defects such as cracks are generated in the single crystal silicon layer of the single crystal silicon substrate 208. The quality of the manufactured TFT array substrate 10 may deteriorate.

In order to suppress the occurrence of defects such as cracks, the single crystal silicon substrate 208 which has been once subjected to the heat treatment for bonding at 300 ° C. is wet-etched or CMP to have a thickness of about 100 to 150 μm. It is desirable to increase the bonding strength by a method of reducing the thickness and then performing a heat treatment at a higher temperature. Specifically, for example, the single crystal silicon substrate 208 and the supporting substrate 10A are heat-treated at 300 ° C. to be bonded to each other, and the single crystal silicon substrate 208 is etched with a KOH aqueous solution at 80 ° C. to a thickness of 150 μm. After that, it is desirable to increase the bonding strength by performing heat treatment again at 450 ° C.

Next, part of the single crystal silicon layer of the single crystal silicon substrate 208 is peeled off by heat-treating the single crystal silicon substrate 208, and as shown in FIG.
A thin film single crystal silicon layer 206a is formed on the support substrate 10A. The peeling phenomenon of the single crystal silicon layer here occurs because hydrogen ions introduced into the single crystal silicon substrate 208 in advance break the semiconductor bond in a layer near the surface of the single crystal silicon substrate 208. It is a thing.

The heat treatment for peeling off the single crystal silicon layer can be carried out, for example, by heating to 600 ° C. at a heating rate of 20 ° C./min. By this heat treatment, part of the single crystal silicon layer of the single crystal silicon substrate 208 is separated. Note that the thin film single crystal silicon layer 206a
By changing the acceleration voltage of hydrogen ion implantation performed on the single crystal silicon substrate 208,
It can be formed with an arbitrary film thickness of up to 3000 nm.

The thin film single crystal silicon layer 206a is
In addition to the method described above, the surface of the single crystal silicon substrate 208 is polished to a film thickness of 3 to 5 μm, and then PAC is further added.
E (Plasma Assisted Chemical)
(1 Etching) method for finishing by etching, or ELTRAN (Epitax) for transferring an epitaxial semiconductor layer formed on a porous semiconductor onto a bonded substrate by selective etching of the porous semiconductor layer.
It can also be obtained by the ial Layer Transfer method.

Next, the process of forming the oxide film 206c by thermally oxidizing the thin film single crystal silicon layer 206a and removing the oxide film 206c by wet etching will be described with reference to FIGS. This step is a step for controlling the film thickness of the thin film single crystal silicon layer 206a forming the pixel switching TFT 30.

First, as shown in FIG. 6A, a low pressure chemical vapor deposition method (LPC) is formed on the entire surface of the support substrate 10A.
The silicon nitride film 209 is formed to a thickness of 100 nm to 300 nm by the reaction of dichlorosilane and ammonia using the VD method).
Form a degree.

Next, as shown in FIG. 6B, a photoresist 205 is formed on the silicon nitride film 209. After that, the photoresist 205 located on the end surface of the support substrate 10A is removed so that the photoresist 205 provided on the end surface of the support substrate 10A is not peeled off during transportation. The removal of the photoresist 205 here is
It may be carried out by exposing the end surface of the supporting substrate 10A to light and exposing it, or by peeling it with an alkaline solution such as an aqueous potassium hydroxide solution.

Next, as shown in FIG. 6C, the photoresist 205 is exposed to light using a photomask and developed to form a pattern covering a region other than a region where a fully depleted transistor is desired to be formed. A photoresist 205a having the same is formed.

Next, the silicon nitride film 209 is wet-etched by using the photoresist 205a as a mask.
By etching, and then removing the photoresist 205a, as shown in FIG. 6D, selective oxidation covering a region other than a region where a fully depleted transistor is to be formed on the thin film single crystal silicon layer 206a. Forming a mask pattern 209a.

Next, as shown in FIG. 7A, the thin film single crystal silicon layer 206a provided in the region not covered by the selective oxidation mask pattern 209a is locally grown by thermal oxidation. Then, the oxide film 206c is formed. The film thickness of the oxide film 206c is, for example, when the film thickness of the thin film single crystal silicon layer 206a is about 400 nm,
It is desirable to set it to about 700 nm.

Next, as shown in FIG. 7B, the oxide film 2
06c is removed by wet etching, and then, FIG.
As shown in (c), the mask pattern 209 for selective oxidation is used.
a is removed by a method using hot phosphoric acid, a dry etching method such as a reactive etching method or a reactive ion beam etching method, and the thin film single crystal silicon layer 206a in a region where a fully depleted transistor is to be formed is formed. It was formed to have a constant film thickness in the range of 30 nm to 100 nm.

Next, as shown in FIG. 8A, a semiconductor layer 1a having a predetermined pattern is formed by a photolithography process, an etching process and the like. That is, the data line 6a
In the region where the capacitance line 3b is formed below and the region where the capacitance line 3b is formed along the scanning line 3a, the first storage capacitance electrode 1f extended from the semiconductor layer 1a forming the pixel switching TFT 30 is formed. To form. In addition, in FIG.
The first storage capacitor electrode 1f is not shown.

Next, as shown in FIG. 8B, the semiconductor layer 1a is heated to a temperature of about 850 to 1300 ° C., preferably about 10 ° C.
The gate insulating film 2 is formed by performing thermal oxidation for about 72 minutes at a temperature of 00 ° C. to form a thermal oxide semiconductor film having a relatively thin thickness of about 60 nm. As a result, the semiconductor layer 1a has a thickness of about 30 to 170 nm, and the gate insulating film 2 has a thickness of about 60 nm.

Next, a method of manufacturing the TFT array substrate 10 from the support substrate 10A on which the gate insulating film 2 is formed will be described with reference to FIGS. Note that FIG.
FIG. 13 is a process diagram showing a part of the TFT array substrate in each process corresponding to the sectional view shown in FIG. Further, FIGS. 9 to 13 are shown at a different scale from FIGS. 4 to 8.

As shown in FIG. 9A, the gate insulating film 2
A resist film 301 is formed at a position corresponding to the N-channel semiconductor layer 1a on the support substrate 10A in which P is formed, and a V-group dopant 302 such as P is added to the P-channel semiconductor layer 1a at a low concentration (for example, 70k P ion
eV acceleration voltage, 2 × 10 ¹¹ / cm ² dose)
Dope.

Next, as shown in FIG. 9B, a resist film is formed at a position corresponding to the P-channel semiconductor layer 1a (not shown), and B or the like is formed on the N-channel semiconductor layer 1a.
Group III element dopant 303 at a low concentration (for example, B
The ions are doped with an accelerating voltage of 35 keV and a dose of 1 × 10 ¹² / cm ² .

Next, as shown in FIG. 9C, the channel region 1 of the semiconductor layer 1a is formed for each P channel and N channel.
The resist film 3 is formed on the surface of the supporting substrate 10A except the end portion of a '.
No. 05 is formed, and the P channel is doped with a dopant 306 of a group V element such as P at a dose amount about 1 to 10 times that of the step shown in FIG. b)
III such as B at a dose amount about 1 to 10 times that of the process shown in
A group element dopant 306 is doped.

Next, as shown in FIG. 9D, in order to reduce the resistance of the first storage capacitor electrode 1f formed by extending the semiconductor layer 1a, the scanning line 3a (gate electrode) on the surface of the support substrate 10A is reduced. A resist film 307 (wider than the scanning line 3a) is formed in a portion corresponding to (4), and using this as a mask, a dopant 308 of a group V element such as P is formed at a low concentration (for example, P ion is 70 keV). Acceleration voltage of 3 × 10 ¹⁴ /
Doping (with a dose of cm ² ).

Next, as shown in FIG. 10A, by dry etching such as reactive etching or reactive ion beam etching, or wet etching, the first interlayer insulating film 206b is penetrated to reach the light shielding layer 11a. The contact hole 13 is formed. Contact hole 1
As shown in FIG. 10 (a), the first hole
Since the light shielding layer 11a is reached only by penetrating the interlayer insulating film 206b, the bonding interface 221 between the single crystal silicon substrate 208 and the supporting substrate 10A located between the lower bonding film 10B and the upper bonding film 12 is formed. No need to penetrate.

The contact hole 13 is preferably formed by dry etching having anisotropy such as reactive etching or reactive ion beam etching.
There is an advantage that the aperture shape can be made almost the same as the mask shape. However, if dry etching and wet etching having anisotropy are combined to open the holes, the contact hole 13 can have a tapered shape, which has an advantage of preventing disconnection during wiring connection.

Next, as shown in FIG. 10B, the reduced pressure C
After depositing the poly semiconductor layer 3 to a thickness of about 350 nm by VD or the like, phosphorus (P) is thermally diffused to form the poly semiconductor film 3
Is made conductive. Alternatively, a doped semiconductor film in which P ions are introduced simultaneously with the formation of the poly semiconductor film 3 may be used. As a result, the conductivity of the poly semiconductor layer 3 can be increased.

Next, as shown in FIG. 10C, the capacitance line 3b is formed together with the scanning line 3a having a predetermined pattern by a photolithography process using a resist mask, an etching process, and the like. After this, the poly semiconductor film remaining on the back surface of the support substrate 10A is removed by etching while covering the surface of the support substrate 10A with a resist film.

Next, as shown in FIG. 10D, N is formed in order to form a P-channel LDD region in the semiconductor layer 1a.
The resist film 3 is formed at a position corresponding to the semiconductor layer 1a of the channel.
09, and using the scanning line 3a (gate electrode) as a diffusion mask, first, a dopant 310 of a group III element such as B is used at a low concentration (for example, BF ₂ ions are accelerated at an acceleration voltage of 90 keV, 3 × 10 ¹³ / cm ² Dope, P
A low concentration source region 1b and a low concentration drain region 1c of the channel are formed.

Then, as shown in FIG. 10E, in order to form the P-channel high-concentration source region 1d and the high-concentration drain region 1e in the semiconductor layer 1a, a position corresponding to the N-channel semiconductor layer 1a is formed. Of the scanning line 3 corresponding to the P channel with the mask covered with the resist film 309 and using a mask (not shown) wider than the scanning line 3a.
After being formed on a, the dopant 311 of a group III element such as B is highly concentrated (for example, BF ² ions are added at 90 ke
Doping (with an accelerating voltage of V and a dose of 2 × 10 ¹⁵ / cm ² ).

Next, as shown in FIG. 11A, in order to form an N-channel LDD region in the semiconductor layer 1a, P
A position corresponding to the semiconductor layer 1a of the channel is covered with a resist film (not shown), the scan line 3a (gate electrode) is used as a diffusion mask, and the dopant 60 of the group V element such as P is used at a low concentration (for example, P ion). Acceleration voltage of 70 keV, 6
(Dose amount of × 10 ¹² / cm ² ), doping, N-channel low-concentration source region 1b and low-concentration drain region 1c
To form.

Subsequently, as shown in FIG. 11B, in order to form the N-channel high-concentration source region 1d and the high-concentration drain region 1e in the semiconductor layer 1a, a mask wider than the scanning line 3a is used. After forming a resist 62 on the scanning line 3a corresponding to the N channel, a dopant 61 of a V group element such as P is highly concentrated (for example, P ions are 70 keV).
Accelerating voltage of 4 × 10 ¹⁵ / cm ² ).

Next, as shown in FIG. 11C, for example, a normal pressure or low pressure CVD method or TEOS gas is used so as to cover the scanning lines 3a as well as the capacitance lines 3b and the scanning lines 3a in the pixel switching TFT 30. Using NSG, PS
A second interlayer insulating film 4 made of a silicate glass film such as G, BSG, BPSG, a nitride semiconductor film, an oxide semiconductor film, or the like is formed. The thickness of the second interlayer insulating film 4 is about 500 to 15
00 nm is preferable, and further 800 nm is more preferable.

Thereafter, an annealing treatment at about 850 ° C. is performed for about 20 minutes to activate the high concentration source region 1d and the high concentration drain region 1e.

Next, as shown in FIG. 11D, the contact hole 5 for the data line 31 is formed by dry etching such as reactive etching or reactive ion beam etching, or by wet etching. Further, contact holes for connecting the scanning lines 3a and the capacitance lines 3b to wirings not shown are also formed in the second interlayer insulating film 4 by the same process as the contact holes 5.

Next, as shown in FIG. 12A, a light-shielding A film is formed on the second interlayer insulating film 4 by sputtering or the like.
The metal film 6 is made of a low resistance metal such as 1 or metal silicide, and has a thickness of about 100 to 700 nm, preferably about 350.
After being deposited to a thickness of nm, a data line 6a is formed by a photolithography process, an etching process, etc., as shown in FIG.

Next, as shown in FIG. 12C, NSG, PSG, BSG, etc. are formed so as to cover the data lines 6a by using, for example, a normal pressure or low pressure CVD method or TEOS gas.
A third interlayer insulating film 7 made of a silicate glass film such as BPSG, a nitride semiconductor film or an oxide semiconductor film is formed. The thickness of the third interlayer insulating film 7 is preferably about 500 to 1500 nm, more preferably 800 nm.

Next, as shown in FIG. 13A, in the pixel switching TFT 30, the contact hole 8 for electrically connecting the pixel electrode 9a and the high concentration drain region 1e is subjected to reactive etching and reaction. It is formed by dry etching such as reactive ion beam etching.

Next, as shown in FIG. 13B, a transparent conductive thin film 9 such as ITO is deposited on the third interlayer insulating film 7 by sputtering or the like to a thickness of about 50 to 200 nm. After that, as shown in FIG. 13C, a pixel electrode 9a is formed by a photolithography process, an etching process, or the like. When the electro-optical device of this embodiment is a reflective electro-optical device, the pixel electrode 9a may be formed of an opaque material having a high reflectance such as Al.

Subsequently, a coating liquid of a polyimide-based alignment film is applied on the pixel electrode 9a, and then a rubbing process is performed so as to have a predetermined pretilt angle and in a predetermined direction. Is formed. As described above, the TFT array substrate 10 shown in FIG. 3 is manufactured.

Next, the method of manufacturing the counter substrate 20 and the TFT
A method of manufacturing a liquid crystal device from the array substrate 10 and the counter substrate 20 will be described. To manufacture the counter substrate 20 shown in FIG. 3, a light transmissive substrate such as a glass substrate is prepared as the substrate body 20A, and the counter substrate light shielding layer 23 is formed on the surface of the substrate body 20A. The counter substrate light shielding layer 23 is formed through a photolithography process and an etching process after sputtering a metal material such as Cr, Ni and Al. Note that the counter substrate light-shielding layer 23 may be formed of a material such as resin black in which carbon, Ti, or the like is dispersed in a photoresist, in addition to the above metal materials.

Then, a transparent conductive thin film such as ITO is deposited on the entire surface of the substrate body 20A by a sputtering method or the like to a thickness of about 50 to 200 nm.
The counter electrode 21 is formed. Further, after the application liquid of the alignment film such as polyimide is applied on the entire surface of the counter electrode 21, the alignment film 22 is formed by performing a rubbing treatment so as to have a predetermined pretilt angle and in a predetermined direction. To do. As described above, the counter substrate 20 shown in FIG. 1 is manufactured.

Finally, the TFT array substrate 10 and the counter substrate 20 manufactured as described above are attached by a sealing material so that the alignment film 16 and the alignment film 22 face each other, and a method such as a vacuum suction method is used. Allows the space between both boards to
For example, a liquid crystal device having the above-described structure is manufactured by sucking a liquid crystal formed by mixing a plurality of types of nematic liquid crystals to form a liquid crystal layer 50 having a predetermined thickness.

In the method of manufacturing a liquid crystal device of this embodiment, the first interlayer insulating film 206b and the light shielding layer 11a are formed on the surface of the single crystal silicon substrate 208 on the side to be bonded to the supporting substrate 10A.
And the upper bonding film 12 are sequentially formed, and then the single crystal silicon substrate 208 is bonded to the supporting substrate 10A to form a composite substrate. Therefore, the light shielding layer 11a includes the single crystal silicon substrate 208 and the supporting substrate 10A. Will be formed above the bonding interface 221 and the contact interface 221 is formed in the step of forming the contact hole 13 penetrating the first interlayer insulating film 206b and reaching the light shielding layer 11a by wet etching. No need to penetrate. Therefore, when the contact hole 13 is formed by wet etching, the bonding interface 221
Therefore, the inconvenience that the etching solution permeates does not occur. Therefore, a liquid crystal device which can be manufactured with high yield and has high reliability can be obtained.

Further, in the method of manufacturing the liquid crystal device of the present embodiment, the upper bonding film 12 is planarized by using CMP, so that the upper bonding film 12 can be planarized easily and accurately. The adhesion between the single crystal silicon substrate 208 and the support substrate 10A can be improved, and the single crystal silicon substrate 208 and the support substrate 10A can be easily and accurately bonded together.

Further, in the liquid crystal device of this embodiment, the light shielding layer 11a is located above the bonding interface 221 between the single crystal silicon substrate 208 and the supporting substrate 10A, and the light shielding layer 1a
Semiconductor layer 1a and light-shielding layer 11a located above 1a
Since there is no bonding interface 221 between the semiconductor layer 1a and the light-shielding layer 11a, the distance corresponding to the thickness required for bonding the single crystal silicon substrate 208 and the support substrate 10A to the distance between the semiconductor layer 1a and the light-shielding layer 11a. Is never included.

Therefore, the semiconductor layer 1a and the light shielding layer 11a are
The distance between the first interlayer insulating film 206b and the first interlayer insulating film 206b can be reduced within a range in which the semiconductor layer 1a and the light shielding layer 11a can be insulated. As a result, the distance between the semiconductor layer 1a and the light shielding layer 11a can be reduced, and the light shielding layer 11a can be positively used as a back gate.

In the liquid crystal device of the present embodiment, the thickness of the first interlayer insulating film 206b is set in the range of 30 nm to 200 nm, so that the semiconductor layer 1a and the light shielding layer 11a can be reliably insulated and the light shielding is performed. By controlling the potential of the layer 11a, the off-leakage current can be reduced and the on-current can be increased, so that a more excellent liquid crystal device can be obtained.

In the present invention, as in the example shown in this embodiment, in order to enhance the adhesion between the single crystal silicon substrate 208 and the support substrate 10A, the single crystal silicon substrate 208 of the support substrate 10A is bonded. It is desirable that a lower bonding film 10B made of the same material as the upper bonding film 12 is formed on the surfaces to be bonded together,
The lower bonding film 10B may not be formed.

Further, in the present embodiment, the selective oxidation mask pattern 209a is made of silicon nitride, but it may be another inorganic film or an organic film such as a photoresist.

(Overall Configuration of Electro-Optical Device) The overall configuration of the liquid crystal device of the present embodiment configured as described above will be described below with reference to FIGS. 14 and 15. In addition, FIG.
FIG. 15 is a plan view of the TFT array substrate 10 viewed from the counter substrate 20 side, and FIG. 15 is a cross-sectional view taken along line HH ′ of FIG. 13 including the counter substrate 20.

In FIG. 14, a sealing material 52 is provided on the surface of the TFT array substrate 10 along the edge thereof, and as shown in FIG. 15, the sealing material 5 shown in FIG.
The counter substrate 20 having substantially the same contour as 2 is the sealing material 5
It is fixed to the TFT array substrate 10 by 2. As shown in FIG. 15, on the surface of the counter substrate 20, a counter substrate light shielding layer 53, which is made of the same material as or different from the counter substrate light shielding layer 23 and serves as a peripheral partition, is provided in parallel with the inside of the sealing material 52. Has been.

In the TFT array substrate 10, the data line driving circuit 101 is provided in the area outside the sealing material 52.
The mounting terminals 102 are provided along one side of the TFT array substrate 10, and the scanning line driving circuit 104 is provided along two sides adjacent to the one side. Scanning line 3a
If the delay of the scanning signal supplied to
It goes without saying that the scanning line driving circuit 104 may be provided on only one side.

Further, the data line driving circuits 101 may be arranged on both sides along the sides of the display area (pixel portion). For example, the odd-numbered data lines 6a supply an image signal from the data-line driving circuit arranged along one side of the display area, and the even-numbered data lines 6a are arranged along the opposite side of the display area. The image signal may be supplied from the provided data line driving circuit. By thus driving the data lines 6a in a comb shape, the occupied area of the data line driving circuit can be expanded, and a complicated circuit can be configured.

Further, on the remaining one side of the TFT array substrate 10, the scanning line driving circuits 104 provided on both sides of the display area.
A plurality of wirings 105 for connecting the spaces are provided.
Further, a precharge circuit may be provided hidden under the counter substrate light shielding layer 53 as a peripheral parting. In addition, at least one position of the corner between the TFT array substrate 10 and the counter substrate 20 is provided with a conductive material 106 for electrically connecting the TFT array substrate 10 and the counter substrate 20.

Further, on the surface of the TFT array substrate 10, an inspection circuit or the like for inspecting quality, defects, etc. of the electro-optical device during manufacturing or shipping may be further formed. Also,
The data line driving circuit 101 and the scanning line driving circuit 104 are set to T
Instead of being provided on the surface of the FT array substrate 10, for example, a driving LSI mounted on a TAB (tape automated bonding substrate) is provided with an anisotropic conductive film provided in the peripheral region of the TFT array substrate 10 interposed therebetween. You may make it connect electrically and mechanically.

Further, for example, a TN (twisted nematic) mode, STN is provided on the light incident side of the counter substrate 20 and on the light emitting side of the TFT array substrate 10, respectively.
Depending on the operation mode such as (super TN) mode, D-STN (dual scan-STN) mode, or normally white mode / normally black mode,
A polarizing film, a retardation film, a polarizing means, etc. are arranged in a predetermined direction.

When the liquid crystal device of the present embodiment is applied to a color liquid crystal projector (projection type display device), 3
Each of the electro-optical devices is used as a light valve for RGB, and light of each color decomposed through a dichroic mirror for RGB color separation enters each panel as projection light. Therefore, in that case, as shown in the above-described embodiment, the counter substrate 20 is not provided with a color filter.

However, the substrate body 2 of the counter substrate 20
On the surface of the liquid crystal layer 50 side of 0A, the counter substrate light shielding layer 2
An RGB color filter may be formed together with its protective film in a predetermined region facing the pixel electrode 9a where 3 is not formed. With such a configuration, the electro-optical device according to the above-described embodiment can be applied to a color electro-optical device such as a direct-view type or reflective type color liquid crystal television other than the liquid crystal projector.

Further, microlenses may be formed on the surface of the counter substrate 20 so as to correspond to one pixel.
By doing so, a bright electro-optical device can be realized by improving the efficiency of collecting incident light. Furthermore, a dichroic filter that produces RGB colors may be formed by utilizing interference of light by depositing a number of interference layers having different refractive indexes on the surface of the counter substrate 20. With this counter substrate with a dichroic filter, a brighter color electro-optical device can be realized.

Incidentally, in the liquid crystal device of this embodiment,
Although the incident light is made to enter from the counter substrate 20 side as in the conventional case, since the TFT array substrate 10 is provided with the light shielding layer 11a, the incident light is made to enter from the TFT array substrate 10 side and the counter substrate 20 side. You may make it emit from. That is, even if the liquid crystal device is attached to the liquid crystal projector as described above, the channel region 1 of the semiconductor layer 1a is
It is possible to prevent light from entering the a ′ and the LDD regions 1b and 1c, and it is possible to display a high quality image.

Conventionally, in order to prevent reflection on the back surface side of the TFT array substrate 10, AR (Anti) for antireflection is used.
-Reflection) It was necessary to dispose a polarizing means coated with the film separately or to attach an AR film. However, in this embodiment, the surface of the TFT array substrate 10 and at least the channel region 1a ′ of the semiconductor layer 1a and the LD.
Since the light-shielding layer 11a is formed between the D regions 1b and 1c, such a polarizing means or AR film coated with AR is used, or the TFT array substrate 10 itself is AR.
Eliminates the need to use treated substrates.

Therefore, according to this embodiment, the material cost can be reduced, and the yield is not lowered due to dust, scratches, etc. when the polarizing means is attached, which is very advantageous.
Further, since the light resistance is excellent, even if the light utilization efficiency is improved by using a bright light source or polarization conversion by the polarization beam splitter, image deterioration such as crosstalk due to light does not occur.

(Electronic Device) A projection type display device will be described below as an example of an electronic device using the liquid crystal device of the above embodiment. FIG. 16 is a schematic configuration diagram showing an example of a projection type display device including the liquid crystal device of the first embodiment. This projection display device is a so-called three-plate projection liquid crystal display device using three liquid crystal panels. Here, the liquid crystal device of the above embodiment is used as a liquid crystal panel that constitutes a liquid crystal light valve. In FIG. 16, reference numeral 510 is a light source, 513, 514 are dichroic mirrors, 515, 516, 517 are reflection mirrors, 51.
8, 519 and 520 are relay lenses, 522, 523 and
524 is a liquid crystal light valve, 525 is a cross dichroic prism, and 526 is a projection lens system.

The light source 510 is a lamp 5 such as an ultra-high pressure mercury lamp.
11 and a reflector 512 that reflects the light of the lamp 511. The dichroic mirror 513 that reflects blue light and green light transmits red light of the white light from the light source 510 and reflects blue light and green light. The transmitted red light is reflected by the reflection mirror 517,
The light enters the liquid crystal light valve 522 for red light.

On the other hand, of the color light reflected by the dichroic mirror 513, the green light is reflected by the green light reflecting dichroic mirror 514 and is incident on the green liquid crystal light valve 523. On the other hand, the blue light also passes through the second dichroic mirror 514. For blue light, in order to compensate for the fact that the optical path length is different from that of green light and red light, a light guide means 521 including a relay lens system including an entrance lens 518, a relay lens 519, and an exit lens 520.
Is provided, and the blue light is incident on the blue light liquid crystal light valve 524 via the.

The three color lights modulated by the respective light valves enter the cross dichroic prism 525. In this prism, four right-angled prisms are bonded together, and a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are formed in a cross shape on the inner surface thereof. Three color lights are combined by these dielectric multilayer films to form light representing a color image. The combined light is projected on the screen 527 by the projection lens system 526 which is a projection optical system, and the image is enlarged and displayed.

Since such a projection type liquid crystal display device is equipped with the above liquid crystal device, it can be provided as a highly reliable and excellent projection type display device.

Other examples of electronic equipment using the liquid crystal device of the first embodiment will be described below. FIG. 17 is a perspective view showing an example of a mobile phone. In FIG. 17, reference numeral 1
Reference numeral 1001 indicates a mobile phone main body, and reference numeral 1001 indicates a liquid crystal display unit using the above liquid crystal device.

FIG. 18 is a perspective view showing an example of a wrist watch type electronic device. In FIG. 18, reference numeral 1100 indicates a watch body, and reference numeral 1101 indicates a liquid crystal display unit using the above liquid crystal device.

FIG. 19 is a perspective view showing an example of a portable information processing device such as a word processor and a personal computer. In FIG. 19, reference numeral 1200 is an information processing apparatus, reference numeral 1202 is an input unit such as a keyboard, reference numeral 1204 is an information processing apparatus main body, and reference numeral 1206 is a liquid crystal display unit using the above liquid crystal device.

Since the electronic equipment shown in FIGS. 17 to 19 is equipped with the liquid crystal device of the first embodiment, it can be an electronic equipment equipped with a highly reliable and excellent display section. .

The technical scope of the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, the specific configuration of the liquid crystal device described with reference to FIGS. 1 to 15 is merely an example, and the present invention can be applied to liquid crystal devices having various other configurations. Also,
For example, the present invention relates to electroluminescence (E
L), a digital micromirror device (DMD), or an electro-optical device using various electro-optical elements using plasma light emission or fluorescence due to electron emission, and electronic devices equipped with the electro-optical device. It goes without saying that it is possible.

[0136]

As described above, according to the electro-optical device and the method for manufacturing the electro-optical device of the present invention, the light-shielding layer is located above the bonding interface between the supporting substrate and the semiconductor substrate. When the contact hole that penetrates the member formed above the light shielding layer and reaches the light shielding layer is provided, the contact hole does not penetrate the bonding interface between the semiconductor substrate and the support substrate. Therefore, when this contact hole is formed by wet etching, there is no inconvenience that the etching solution permeates from the bonding interface between the semiconductor substrate and the supporting substrate, unlike the conventional electro-optical device.

Further, since the light-shielding layer is located above the bonding interface between the supporting substrate and the semiconductor substrate, there is no bonding interface between the semiconductor layer and the light-shielding layer. The distance between the layer and the light-blocking layer can be shortened within a range in which the semiconductor layer and the light-blocking layer can be insulated.

Therefore, the semiconductor layer and the light-shielding layer can be brought close to each other, and the light-shielding layer can be positively used as a back gate, and the off-leak current can be reduced by controlling the potential of the light-shielding layer. And the on-current can be increased.

Furthermore, the thickness of the first insulator layer is set to 30 nm.
Or 200 nm, the semiconductor layer and the light-shielding layer can be reliably insulated from each other, and the off-leakage current can be reduced or the on-current can be increased by controlling the potential of the light-shielding layer. The electro-optical device is even more excellent.

[Brief description of drawings]

FIG. 1 is an equivalent circuit of various elements, wirings, and the like in a plurality of pixels that are formed in a matrix and form a pixel portion (display region) of a liquid crystal device that is an example of an electro-optical device of the present invention.

FIG. 2 is an enlarged plan view showing a plurality of pixel groups adjacent to each other on a TFT array substrate on which a data line, a scanning line, a pixel electrode, a light shielding layer, etc. are formed.

FIG. 3 is a sectional view taken along the line AA ′ of FIG.

FIG. 4 is a process diagram (1) sequentially showing the manufacturing process of the embodiment of the liquid crystal device.

FIG. 5 is a process chart (1) sequentially showing the manufacturing process of the embodiment of the liquid crystal device.

FIG. 6 is a process diagram (1) sequentially showing the manufacturing process of the embodiment of the liquid crystal device.

FIG. 7 is a process chart (1) sequentially showing the manufacturing process of the embodiment of the liquid crystal device.

FIG. 8 is a process chart (1) sequentially showing the manufacturing process of the embodiment of the liquid crystal device.

FIG. 9 is a process chart (1) sequentially showing the manufacturing process of the embodiment of the liquid crystal device.

FIG. 10 is a process chart (1) sequentially showing the manufacturing process of the embodiment of the liquid crystal device.

FIG. 11 is a process chart (1) sequentially showing the manufacturing process of the embodiment of the liquid crystal device.

FIG. 12 is a process chart (1) sequentially showing the manufacturing process of the embodiment of the liquid crystal device.

FIG. 13 is a process diagram (1) sequentially showing the manufacturing process of the embodiment of the liquid crystal device.

FIG. 14 is a plan view of the TFT array substrate according to the first embodiment together with the respective constituent elements formed thereon as viewed from the counter substrate side.

15 is a cross-sectional view taken along the line HH 'of FIG.

FIG. 16 is a configuration diagram of a projection display device which is an example of an electronic apparatus using a liquid crystal device.

FIG. 17 is a diagram for explaining another example of the electronic device using the liquid crystal device of the first embodiment.

FIG. 18 is a diagram for explaining another example of an electronic device using the liquid crystal device of the first embodiment.

FIG. 19 is a diagram for explaining another example of an electronic device using the liquid crystal device of the first embodiment.

[Explanation of symbols]

1a semiconductor layer 1a 'channel region 1b Low-concentration source region (source-side LDD region) 1c Low-concentration drain region (drain side LDD region) 1d high concentration source region 1e high concentration drain region 10 TFT array substrate 10A support substrate 11a light shielding layer 12 Upper bonding film (second insulator layer) 13 contact holes 206b First interlayer insulating film (first insulator layer) 208 Single crystal silicon substrate (semiconductor substrate) 221 Bonding interface

Front page continuation (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09F 9/30 349 H01L 27/12 B 5C094 H01L 21/336 H05B 33/14 A 5F110 27/12 H01L 29/78 619B / / H05B 33/14 627D F-term (reference) 2H088 EA14 EA15 HA06 HA08 HA14 2H090 HA04 HA05 HA07 HB03X HC12 JB04 JC11 LA04 LA05 2H091 FA34Y FB08 GA07 GA11 GA13 LA12 2H092 JB52 JB53 JB57 JB58 NA16 3K007 AB11 BA06 BB06 DB03 EA00 5C094 AA13 AA16 AA25 AA42 AA43 AA48 AA53 BA03 BA16 BA43 CA19 DA13 DB04 EA04 EB02 ED15 FA01 FA02 FB12 FB14 FB15 5F110 AA06 AA15 AA30 AA30 BB01 BB04 CC02 DD03 DD11 DD13 DD17 HL15 HL03 HL09 HL23 HL14 HL23 HL14 NN03 NN04 NN22 NN23 NN24 NN25 NN26 NN44 NN46 NN47 NN72 QQ17

Claims (9)

[Claims] 1. An electro-optical device using a composite substrate obtained by laminating a semiconductor substrate having a semiconductor layer on a supporting substrate, comprising: a first insulator layer provided below the semiconductor layer. A second insulator layer provided below the first insulator layer, a light shielding layer provided between the first insulator layer and the second insulator layer, and at least the first insulator layer A contact hole penetrating an insulating layer and reaching the light-shielding layer, wherein the light-shielding layer is positioned above a bonding interface between the supporting substrate and the semiconductor substrate. apparatus. 2. The thickness of the first insulator layer is in the range of 30 nm to 200 nm.
The electro-optical device according to. 3. The thickness of the first insulator layer is in the range of 50 nm to 100 nm.
Alternatively, the electro-optical device according to claim 2. 4. An electro-optical device using a composite substrate in which a semiconductor substrate having a semiconductor layer and a light-shielding layer is laminated on a support substrate, wherein the light-shielding layer is the support substrate and the semiconductor substrate. An electro-optical device characterized in that it is located above the bonding interface with. 5. A projection display device comprising the electro-optical device according to claim 1, wherein the electro-optical device modulates light emitted from the light source. A projection type display device, comprising: a device; and a magnifying projection optical system that magnifies and projects light modulated by the electro-optical device onto a projection surface. 6. An electronic apparatus comprising the electro-optical device according to claim 1. Description: 7. A method of manufacturing an electro-optical device using a composite substrate comprising a supporting substrate and a semiconductor substrate having a semiconductor layer attached to the supporting substrate, wherein the semiconductor substrate is bonded to the supporting substrate. A first insulating layer, a light shielding layer, and a second insulating layer are sequentially formed on the surface, a step of adhering the semiconductor substrate on the supporting substrate to form the composite substrate, and the semiconductor layer A method of manufacturing an electro-optical device comprising: a step of patterning; and a step of forming a contact hole penetrating the first insulator layer and reaching the light shielding layer by wet etching. 8. The method of manufacturing an electro-optical device according to claim 7, wherein the first insulator layer is formed to have a thickness in the range of 30 nm to 200 nm. 9. The method according to claim 7, wherein the second insulating layer is planarized by a chemical mechanical polishing method, and then the semiconductor substrate is attached to the supporting substrate. A method for manufacturing the electro-optical device described.