JP4611275B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine that allows a player to play a predetermined game using a game medium.

  As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a prize area such as a prize opening provided in the game area, a predetermined number of prize balls are paid out to the player. There is something to be done. Further, a variable display device capable of variably displaying the identification information (also referred to as “variation”) is provided on the game board, and the player when the display result of the variable display of the identification information in the variable display device becomes the specific display result. Some are configured to be controllable to a specific gaming state advantageous to the user.

  The specific game state means a state advantageous for a player who is given a predetermined game value. Specifically, the specific gaming state is, for example, a state in which a special variable winning device is advantageous for a player who is likely to win a ball (a big hit gaming state), or a state in which a right to become advantageous for a player has occurred. In this state, a predetermined game value such as a state where conditions for paying out premium game media are easily established is given.

  In such a gaming machine, the fact that the display result of the variable display device that displays the symbol as identification information is a combination of specific display modes (specific display result) determined in advance is generally referred to as “big hit”. When the big hit occurs, for example, the big winning opening is opened a predetermined number of times, and the game shifts to a big hit gaming state where the hit ball is easy to win. And in each open period, if there is a prize for a predetermined number (for example, 10) of the big prize opening, the big prize opening is closed. And the number of times of opening the special winning opening is fixed to a predetermined number (for example, 15 rounds). An opening time (for example, 29.5 seconds) is determined for each opening, and even if the number of winnings does not reach a predetermined number, the big winning opening is closed when the opening time elapses. Further, when a predetermined condition (for example, winning in the V zone provided in the big prize opening) is not established at the time when the big prize opening is closed, the big hit gaming state is ended. Some are also available.

  In addition, the gaming machine is provided with light emitters such as a large number of lamps and LEDs. Among these light emitters, the gaming state at that time (for example, reach state, big hit game state, big hit occurs). To the player (high probability state in which the probability of being improved) is informed to the player, the result of variable display of identification information (design variation result) and reach state to the player There is a illuminant for notice. By making these light emitters emit light or blink, it is possible to realize a game effect in which a game state is notified or a notice is given.

  However, there is a problem that the game effect by causing the light emitter to emit light or blinking is monotonous and easily bored by the player. In other words, it is monotonous to notify the change of the gaming state by changing the light emitter from the unlit state to the lit state, and even if it is changed from the unlit state to the blinking state, it will perform an effective game effect. It ’s hard to say.

  Therefore, it is provided with brightness change control means for performing brightness change control for changing the brightness of the light emitter in a plurality of stages by changing the on period and the off period of the drive signal output to the light emitter, and the brightness change control means includes a plurality of brightness change control means Proposed gaming machines configured to perform brightness change control with reference to a drive signal pattern table in which data corresponding to the ON period or OFF period of the drive signal output corresponding to the brightness of each stage is stored (For example, refer to Patent Document 1).

JP 2003-825 A (paragraphs 0200-0208, FIG. 37)

  The gaming machine is provided with a large number of light emitters. When it is configured to perform brightness change control with reference to a drive signal pattern table in which data corresponding to the ON period or OFF period of the drive signal output corresponding to the brightness of each of the plurality of stages is stored Increases the size of the drive signal pattern table. In general, each data in the drive signal pattern table is stored in a ROM. Then, as the size of the drive signal pattern table increases, the required ROM capacity increases. In order to make the production more effective, it is preferable to increase the number of lightness levels or the number of types of lightness change patterns, but when increasing the number of lightness levels or the number of types of lightness change patterns, Furthermore, the required ROM capacity increases.

  Therefore, an object of the present invention is to provide a gaming machine that can enhance the effect of the game effect by the light emitting means and can prevent the data storage capacity in the control means for controlling the light emitting means from being increased. To do.

A gaming machine according to the present invention is a gaming machine in which a player can perform a predetermined game using a game medium (for example, a game ball), and emits light in response to a drive signal (as a ceiling lamp). LED 281a to 281l, LEDs 282a to 282f as left frame lamps, LEDs 283a to 283f as right frame lamps, LEDs 126a to 126f as stage lamps, LEDs 127a, 127b, and 127c), and a driving signal to the light emitting means Light emission control means (for example, the production control microcomputer 100 and serial-parallel conversion ICs 611 to 615, 618, 619, etc.), and the light emission control means has a predetermined unit time (for example, 15 ms). ) To control the length of the drive signal output ON period (see FIG. 45). Brightness change control means for controlling the lightness level of the light emitting means (for example, in the production control microcomputer 100, the switching time / switching number calculation process in steps S861 to S865 and the brightness control process in steps S981 to S996 (particularly in steps) And a control table in which a plurality of combinations of a predetermined time and a target lightness level after the elapse of the predetermined time are set, and the lightness change control means changes the lightness level of the light emitting means. The current brightness level at the time of starting control (for example, the value (specifically, the value of the immediately preceding period) indicated as data in the periods (1) to (11) shown in FIG. 46) and the control table It has been set a predetermined time (e.g., period (1 shown in FIG. 46) to (11 each time)) and, the predetermined time after Based on the later target lightness level (for example, the values shown as data in the periods (1) to (11) shown in FIG. 46), the number of lightness level switchings in a predetermined time and the next lightness level are set. Lightness level calculation means for determining the time until switching and the lightness level at each time by calculation (for example, the part for executing the switching time / switching number calculation processing of steps S861 to S865 in the production control microcomputer 100) Brightness value execution means for controlling the length of the ON period of the drive signal output in accordance with each brightness level obtained by the calculation by the brightness level calculation means (for example, the processing of step S984 is executed in the production control microcomputer 100) Part).

  The brightness change control means is a non-calculated brightness level determination means (for example, the processing in steps S861 and S865 in the production control microcomputer 100) that determines the brightness level for each predetermined unit time in the predetermined time as a target brightness level without calculation. In the case where information of “constant brightness” is stored in the RAM, a value corresponding to the constant brightness (set in the lamp control table) in the process of step S984 (see FIG. 58). The control for setting the drive signal to the LED according to the value) is performed).

  A game board (for example, a game frame) including a game frame (for example, the game frame 11) installed to be openable and closable with respect to the outer frame, and a predetermined plate-like body and various parts attached to the plate-like body. And a game control means for executing a game control process for controlling the progress of the game (for example, a game control microcomputer 560). And an effect control means (for example, an effect control microcomputer) for controlling the light emitting means based on the command transmitted by the game control means, the brightness change control means is included in the effect control means, Based on a command transmitted by the game control means (for example, an effect control command), a signal output means for outputting a control signal for controlling the light emitting means in a serial signal system ( For example, the production control microcomputer 100 includes a part that executes step S708), converts the control signal output by the signal output means into a parallel signal system, and outputs it to the light emitting means provided in the game board. A parallel conversion circuit (for example, serial-parallel conversion ICs 616 to 619) and a frame side serial-parallel conversion that converts the control signal output from the signal output means into a parallel signal system and outputs it to the light emitting means provided in the game frame Circuit (for example, serial-parallel conversion ICs 611 to 615), and the board-side serial-parallel conversion circuit and the frame-side serial-parallel conversion circuit are connected via one line of wiring (for example, relay board 606, 607 is connected in a bus type, and is connected via one system wiring. The real conversion ICs 611 to 619 are connected in one system by being connected in a bus form or daisy chain type), and different address information is assigned in advance (for example, addresses “01” to “01” shown in FIG. 12 and FIG. 13). “09” is assigned), and only the control signal with its own address information added is converted into a parallel signal system and output (for example, when the header / address detection unit 653 matches the address stored in the address storage unit 654) If it is determined, the input buffer signal is output to the data buffer 655 and latched.) When the signal output means outputs a control signal for controlling the light emitting means provided in the game board, the board side serial-parallel conversion is performed. A control signal with address information that can identify the circuit is output in a serial signal system (for example, In step S953, the production control microcomputer 100 uses the serial output circuit 353 to transmit serial data to which any of the addresses “06” to “09” shown in FIG. When outputting a control signal for controlling the provided light emitting means, a control signal to which address information that can identify the frame side serial-parallel conversion circuit is added is output in a serial signal system (for example, an effect control microcomputer 100 may be configured to transmit serial data to which any of the addresses “01” to “05” illustrated in FIG. 12 is added using the serial output circuit 353 in step S953).

  A game board (for example, a game frame) including a game frame (for example, the game frame 11) installed to be openable and closable with respect to the outer frame, and a predetermined plate-like body and various parts attached to the plate-like body. And a game control means for executing a game control process for controlling the progress of the game (for example, a game control microcomputer 560). And an effect control means (for example, an effect control microcomputer) for controlling the light emitting means based on the command transmitted by the game control means, the brightness change control means is included in the effect control means, Based on a command transmitted by the game control means (for example, an effect control command), a signal output means for outputting a control signal for controlling the light emitting means in a serial signal system ( For example, the production control microcomputer 100 includes a part that executes step S708), converts the control signal output by the signal output means into a parallel signal system, and outputs it to the light emitting means provided in the game board. A parallel conversion circuit (for example, serial-parallel conversion ICs 616 to 619) and a frame side serial-parallel conversion that converts the control signal output from the signal output means into a parallel signal system and outputs it to the light emitting means provided in the game frame Circuit (for example, serial-parallel conversion ICs 611 to 615), and at least a part of the panel-side serial-parallel conversion circuit or the frame-side serial-parallel conversion circuit is connected in series (for example, as shown in FIG. 72, Each serial-parallel conversion IC 611-614 is connected in series by the same system wiring. The serial-parallel conversion ICs 616 to 619 are connected in series with the same system wiring), and the signal output means controls all of the panel-side serial-parallel conversion circuit or the frame-side serial-parallel conversion circuit connected in series. The fixed-length data including signal information is output in units of unit data (for example, 1 bit) at a predetermined cycle (for example, the cycle of the clock signal) in a serial signal system (for example, the production control microcomputer 100 performs stepping). In S972A, the serial output circuit 375 is used to output a control signal sequence including a lamp control signal), and the serially connected panel side serial-parallel conversion circuit or frame side serial-parallel conversion circuit is connected to the lower side. To the board side serial-parallel conversion circuit or the frame side serial-parallel conversion circuit. The unit data output for each period is sequentially transferred as it is (for example, as shown in FIG. 73, in each of the serial-parallel conversion ICs 611 to 614 and 616 to 619, the last bit of the shift register 682 is the lower-order data as it is. A control signal is output based on the unit data at a predetermined timing (for example, as shown in FIG. 73, in each of the serial-parallel conversion ICs 611 to 614 and 616 to 619, the data buffer 683 is input to the latch unit 681). May be configured to latch and output the data stored in the shift register 682 at the timing when the latch signal from the production control microcomputer 100 is input).

  A relay board (for example, relay boards 606 and 607) between the board side serial-parallel conversion circuit and the frame side serial-parallel conversion circuit, or a relay board between the frame side serial-parallel conversion circuit and the effect control means ( For example, a relay board 607) may be provided.

  An assembly board on which a plurality of frame-side serial-parallel conversion circuits or board-side serial-parallel conversion circuits are mounted (for example, a board-side IC board 601 on which a plurality of serial-parallel conversion ICs 616 to 619 are mounted, a plurality of serial-parallel conversion ICs 611, A frame side IC substrate 602 on which 612 is mounted may be provided.

According to the first aspect of the present invention, the brightness change control means starts the control to change the brightness of the light emitting means, the current brightness level, a predetermined time set in the control table , and after the predetermined time has elapsed. based on the target brightness level, in Jo Tokoro time, the number of times of switching brightness level, time before switching to the next brightness level, the brightness level at each time, the brightness level calculating means for determining by calculation, the brightness Since the level calculation means includes brightness change execution means for controlling the length of the ON period of the drive signal output according to each brightness level obtained by the calculation, the brightness level is increased and the types of brightness change patterns are increased. However, the data storage capacity in the control means for controlling the light emitting means can be prevented from increasing. Further, it is easy to divert the lightness change control means to other models having different lightness level numbers and lightness change pattern types.

  In the invention described in claim 2, since the brightness change control means includes non-calculated brightness level determination means for determining the brightness level for each predetermined unit time in the predetermined time as the target brightness level without calculating, variation in brightness change is provided. When increasing, there is an effect that the control burden of the brightness change control means does not increase.

  According to a third aspect of the present invention, when the signal output means outputs a control signal for controlling the light emitting means provided in the game board, the control is added with address information that can identify the board-side serial-parallel conversion circuit. When outputting a signal in the serial signal system and outputting a control signal for controlling the light emitting means provided in the game frame, the control signal added with address information that can identify the frame side serial-parallel conversion circuit is a serial signal. Since it is configured to output in a system, the number of wires between the game board and the game frame can be reduced. Therefore, in the gaming machine in which the game frame and the game board are detachable, it is possible to easily attach and detach the game frame and the game board.

  According to a fourth aspect of the present invention, the signal output means outputs unit data of fixed length data including control signal information for all of the panel side serial-parallel conversion circuits or the frame side serial-parallel conversion circuits connected in series. Since it is configured to output in a serial signal system at predetermined intervals, it is possible to eliminate the need to assign different address information to the panel side serial-parallel conversion circuit and the frame side serial-parallel conversion circuit in advance. The format of the signal output by the signal output means can be simplified.

  In the invention of claim 5, a relay board is provided between the board side serial-parallel conversion circuit and the frame side serial-parallel conversion circuit, or a relay board is provided between the frame side serial-parallel conversion circuit and the effect control means. Therefore, even when a plurality of light emitting means are provided on the frame side, the game frame can be easily attached to and detached from the game board simply by performing the connection work and the removal work to the relay board.

  In the invention described in claim 6, since the collective board on which a plurality of frame side serial-parallel conversion circuits or board side serial-parallel conversion circuits are mounted is provided, the number of components such as circuits and boards in the gaming machine is reduced. be able to.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, the overall configuration of a pachinko gaming machine that is an example of a gaming machine will be described. FIG. 1 is a front view of a pachinko gaming machine as viewed from the front. FIG. 2 is a front view showing the front of the game frame 11. FIG. 3 is a front view showing the front of the game board. In the following embodiments, a pachinko gaming machine will be described as an example. However, the gaming machine according to the present invention is not limited to a pachinko gaming machine, and can be applied to other gaming machines such as a slot machine. FIG. 2 also shows an enlarged view of the hitting ball supply tray (upper plate) 3 portion of the front surface of the game frame 11.

  The pachinko gaming machine 1 includes an outer frame (not shown) formed in a vertically long rectangular shape, and a game frame 11 attached to the inside of the outer frame so as to be opened and closed. Further, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape that is provided in the game frame 11 so as to be opened and closed. The game frame 11 is a front frame (not shown) installed to be openable and closable with respect to the outer frame, a mechanism plate to which mechanism parts and the like are attached, and various parts attached to them (excluding game boards to be described later). ).

  As shown in FIGS. 1 to 3, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2 is a hitting ball supply tray (upper plate) 3. Below the hitting ball supply tray 3, there are provided an extra ball receiving tray 4 for storing game balls that cannot be accommodated in the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing the game balls. On the back surface of the glass door frame 2, as shown in FIG. 3, there is a plastic frame (plastic frame) that constitutes a part of the game frame 11. The plastic frame includes a mechanism plate, and components such as a power supply circuit (not shown) and a speaker 27 are attached to the mechanism plate. In addition, the plastic frame of the game frame 11 is provided with a relay board 607 that relays the wiring between the game frame 11 and the game board 6. Moreover, as shown in FIG. 3, the game board 6 is attached to the front frame of the game frame 11 so that attachment or detachment is possible. The game board 6 is a structure including a plate-like body constituting the game board 6 and various components attached to the plate-like body. A game area 7 is formed on the front surface of the game board 6.

  Near the center of the game area 7, there is provided a variable display device (image display device) 9 including a plurality of variable display portions each variably displaying a decorative pattern for performance. The variable display device 9 has, for example, three variable display portions (symbol display areas) of “left”, “middle”, and “right”. The variable display device 9 performs variable display of a decorative symbol as a symbol for decoration (production) during the variable symbol display period of the special symbol by the special symbol indicator 8. The variable display device 9 that performs variable display of decorative symbols is controlled by an effect control microcomputer mounted on the effect control board.

  Below the variable display device 9, there is provided a special symbol display (special symbol display device) 8 for variably displaying a special symbol as identification information. In this embodiment, the special symbol display 8 is realized by a simple and small display (for example, 7 segment LED) capable of variably displaying a number of, for example, 00 to 99. Note that the special symbol display 8 is not limited to displaying a two-digit number, and may be configured to variably display a number of other digits such as 0 to 9. In addition, the variable display device 9 performs variable display of a decorative symbol as a symbol for decoration (for production) during the variable symbol display period of the special symbol by the special symbol indicator 8.

  On the right side of the special symbol display 8 is a special symbol hold composed of four indicators for displaying the number of effective winning balls that have entered the start winning openings 13, 14, that is, the number of hold memories (also referred to as start memory or start prize memory). A storage indicator 18 is provided. Every time there is an effective start prize, the display color of one display is changed. Each time the variable display on the special symbol display 8 is started, the display color of one display is restored. In the display area of the variable display device 9, a special symbol reserved storage display area including four display areas for displaying the number of reserved memories may be provided. Further, in this embodiment, the upper limit value of the number of reserved memories is 4, but the upper limit value may be a larger value. Further, the upper limit value may be changed according to the gaming state.

  A first start winning opening 13 is provided below the variable display device 9. The game ball won in the first start winning opening 13 is guided to the back of the game board 6 and detected by the first start opening switch 13a. In addition, on the left side of the variable display device 9, a variable winning device 15 that forms a second start winning port 14 is provided. The winning ball that has entered the second start winning opening 14 is guided to the back of the game board 6 and detected by the start opening switch 14a. The variable winning ball device 15 is opened by a solenoid 16.

  On the right side of the variable display device 9, a trolley 151 as a movable member used for a game effect is provided. In the game effect, the truck 151 can produce an effect of jumping from the right side of the variable display device 9 to the left side as shown in FIG. 4 according to the control of the effect control means.

  Further, on the upper and right sides of the variable display device 9, a beam 152 is provided as a movable member used for a game effect. As shown in FIG. 5, the beam 152 can perform an effect that collapses from the upper part and the right side of the variable display device 9 according to the control of the effect control means in the game effect.

  Furthermore, a skeleton 153 as a movable member used for a game effect is provided below the variable display device 9. In the game effect, the skeleton 153 can perform an effect such that the mouth part opens and closes as shown in FIG. 6 according to the control of the effect control means. Further, the skeleton 153 includes a special variable winning ball apparatus 20 and forms a big winning opening. In this embodiment, in the skeleton 153, in the specific game state (big hit state), the special variable winning ball device 20 is controlled to be opened by the solenoid 21, so that the big winning opening serving as a winning area is opened. The winning ball that has won the big winning opening is detected by the count switch 23.

  The pachinko gaming machine 1 also includes operation buttons 81a to 81e that can be operated by the player while the game is in progress. For example, when the operation buttons 81a to 81e are operated (pressed), the trolley 151, the beam 152, and the skeleton 153 as movable members are operated.

  When the game ball passes through the gate 32 and is detected by the gate switch 32a, variable display of the normal symbol display 10 is started. In this embodiment, variable display is performed by alternately lighting left and right lamps (designs can be visually recognized when lit). For example, if the right lamp is lit at the end of variable display, it is a win. And when the stop symbol in the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball apparatus 15 is opened for a predetermined number of times. Below the normal symbol display 10 is provided a normal symbol start memory display 41 having a display unit with four LEDs for displaying the number of winning balls that have entered the gate 32. Each time there is a prize at the gate 32, the normal symbol start memory display 41 increases the number of LEDs to be turned on by one. Each time variable display on the normal symbol display 10 is started, the number of LEDs to be lit is reduced by one.

  The game board 6 is provided with a plurality of winning ports (ordinary winning ports) 29, 30, 33, and 39. The winning holes 29, 30, 33, and 39 for the game balls are awarded to the winning port switches 29a and 30a, respectively. , 33a, 39a. Each winning opening 29, 30, 33, 39 constitutes a winning area provided in the game board 6 as an area for accepting game media and allowing winning. The start winning openings 13, 14 and the big winning opening also constitute a winning area that accepts game media and allows winning. In addition, the game balls won in the respective winning openings 29, 30, 33, 39 may be detected by one switch.

  A decoration member 154 is attached to the center of the game area 7 so as to surround the variable display device 9, and a decoration lamp (center decoration lamp) that is lit or flashed during the game is placed above the decoration member 154. ) Is provided. In this embodiment, six LEDs 125a to 125f are provided as center decoration lamps. In addition, the decoration member 154 is provided with a decoration lamp (stage lamp) that is lit or flashed during the game so as to surround the variable display device 9. In this embodiment, six LEDs 126a to 126f are provided as stage lamps.

  Further, at the lower part of the game area 7, there is an out port 26 for absorbing game balls that have not won a prize. Two speakers 27 that emit sound effects are provided on the left and right upper portions outside the game area 7. A top frame lamp, a left frame lamp, and a right frame lamp are provided on the outer periphery of the game area 7. Further, a decoration LED is installed around each structure in the game area 7. The top frame lamp, the left frame lamp, the right frame lamp, and the decoration LED are examples of a decorative light emitter provided in the gaming machine. In this embodiment, twelve LEDs 281a to 281l are provided as ceiling lamps. In addition, six LEDs 282a to 282f are provided as left frame lamps. In addition, six LEDs 283a to 283f are provided as right frame lamps. As decoration LEDs around the structure, one LED 127a is provided for the skeleton 153, two LEDs 127b and 127c are provided for the special variable winning ball apparatus 20, and one LED 83 is provided for the operation buttons 81a to 81e. 3 includes four LEDs 82a to 82d. In this embodiment, the decorative “lamp” is constituted by a decorative “LED”, but a light emitter (light emitting means) other than the LED may be used as each lamp. Good.

  The game balls launched from the hit ball launching device enter the game area 7 through the hit ball rail, and then descend the game area 7. When a game ball enters the first start winning opening 13 and is detected by the first start opening switch 13a, or when a game ball enters the second start winning opening 14 and is detected by the second start winning opening switch 14a, If the variable display can be started, the special symbol on the special symbol display unit 8 starts variable display (variation), and the variable display device 9 starts variable display (variation). If it is not in a state where the variable display of symbols can be started, the start winning memory number is increased by one.

  The variable display of the special symbol on the special symbol display 8 and the variable display of the decorative symbol on the variable display device 9 are stopped when a certain time has passed. If the special symbol (stop symbol) at the time of stoppage is a jackpot symbol (specific display result), the game shifts to a jackpot gaming state. That is, the special winning opening is opened until a predetermined time elapses or a predetermined number (for example, 10) of game balls wins.

  When the game ball passes through the gate 32, the normal symbol display unit 10 enters a state in which the normal symbol is variably displayed. When the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the probability variation state, the probability that the stop symbol in the normal symbol display 10 becomes a winning symbol is increased, and the opening time and the number of times of opening of the variable winning ball device 15 are increased. Further, in the short time state (the game state in which the variable symbol display time for special symbols is shortened), the opening time and the number of opening times of the variable winning ball device 15 may be increased.

  As described above, the pachinko gaming machine 1 of this embodiment is provided with lamps and LEDs as light emitters in various places. Further, a prepaid card unit (hereinafter also simply referred to as a “card unit”) that enables ball lending by inserting a prepaid card is installed adjacent to the pachinko gaming machine 1 (not shown).

  FIG. 7 is an explanatory diagram showing a state in which the game frame 11 is opened. As shown in FIG. 7, four substrates (frame side IC substrates) 602 to 605 for mounting ICs and the like are attached to the back surface on the game frame 11 side. A frame-side IC board 602 attached to the upper part of the game frame 11 is mounted with serial-parallel conversion ICs 611 and 612 for converting serial data into parallel data. A control signal is supplied to the LEDs 281a to 281l. Further, the frame side IC substrate 603 attached to the right side (left side when viewed from the back side) of the game frame 11 is mounted with the serial-parallel conversion IC 613, and the serial-parallel conversion IC 613 passes the LEDs 283 a to 283 f of the right frame lamp. A control signal is supplied. The frame side IC substrate 604 attached to the left side of the game frame 11 (the right side when viewed from the back) is equipped with a serial-parallel conversion IC 614, and the serial-parallel conversion IC 614 passes the LEDs 282a to 282f of the left frame lamp. A control signal is supplied.

  The frame side IC substrate 605 attached to the lower part of the game frame 11 is equipped with a serial-parallel conversion IC 615 and an input IC 620 for converting parallel data into serial data. From the serial-parallel conversion IC 615, operation buttons 81a to Control signals are supplied to the LEDs (operation button lamps) 83 provided at 81e and the LEDs 82a to 82d of the dish lamps provided on the hitting ball supply tray (upper plate) 3. In addition, detection signals from the operation buttons 81a to 81e are input to the input IC 620 in parallel. In addition, the figure which looked at the frame side IC board | substrate 605 from the side is also shown by FIG.

  As shown in FIG. 7, in this embodiment, the frame side IC substrate 602 attached to the upper part of the game frame 11 among the frame side IC substrates 602 to 605 is equipped with two serial-parallel conversion ICs. Configured as a collective substrate. With such a configuration, it is possible to consolidate boards on which serial-parallel conversion ICs are mounted, and it is possible to reduce the number of parts in the gaming machine.

  As shown in FIG. 7, a relay board 607 is attached to the game frame 11 side, and wiring from the relay board 607 is connected to the frame side IC board 604, and the frame side IC board 604 to the frame side IC board 602. The frame side IC substrate 602 is further connected to the frame side IC substrate 603. Further, the wiring from the relay substrate 607 is connected to the frame side substrate 605. Further, the wiring between the frame side IC substrates 602 to 604 and the wiring between the frame side IC substrates 604 and 605 and the relay substrate 607 are performed using connectors 156a to 156h on each substrate as shown in FIG. Connected. FIG. 7 shows a case where the wiring connection is performed using a connector of a type that is connected to the board in the vertical direction. You may make it perform.

  As shown in FIG. 7, the wiring from the connector 156 a of the relay board 607 is connected to the connector 156 b of the frame side IC board 604. The wiring pattern of the frame side IC substrate 604 is further branched from the connector 156b, one is connected to the serial-parallel conversion IC 614, and the other is connected to the connector 156c. Further, in the frame side IC substrate 604, the connector 156c is arranged at an end portion on the frame side IC substrate 602 side. The wiring from the connector 156c of the frame side IC substrate 604 is connected to the connector 156d of the frame side IC substrate 602. The wiring pattern of the frame side IC substrate 602 is further branched into three from the connector 156d and connected to the serial-parallel conversion IC 611, the serial-parallel conversion IC 612, and the connector 156e. Further, in the frame side IC substrate 602, the connector 156e is disposed at an end portion on the frame side IC substrate 603 side. The wiring from the connector 156e of the frame side IC substrate 602 is connected to the connector 156f of the frame side IC substrate 603. The wiring pattern of the frame side IC substrate 603 is connected to the serial-parallel conversion IC 613.

  Further, the wiring from the connector 156g of the relay substrate 607 is connected to the connector 156h of the frame side IC substrate 605. The wiring pattern of the frame side IC substrate 605 is further branched from the connector 156h, one is connected to the serial-parallel conversion IC 615, and the other is connected to the input IC 620.

  Further, as shown in FIG. 7, a door opening sensor 155 for detecting the opening of the game frame 11 is attached.

  FIG. 8 is an explanatory view showing the back surface of the game board 6. As shown in FIG. 8, a base (board side IC substrate) 601 for mounting an IC or the like is attached to the back surface of the game board 6. The board side IC substrate 601 is equipped with four serial-parallel conversion ICs 616 to 619 for converting serial data into parallel data, and motors 151 a for driving the movable members 151 to 153 from the serial-parallel conversion IC 616. Control signals are supplied to 152a and 153a. Further, a control signal is supplied from the serial-parallel conversion IC 617 to the LEDs 125a to 125f of the center decoration lamp. Further, a control signal is supplied from the serial-parallel conversion IC 618 to each LED 126a to 126f of the stage lamp. In addition, a control signal is supplied from the serial-parallel conversion IC 619 to the skeleton 153 that is a movable member and the LEDs 127 a to 127 b of each lamp provided in the special variable winning ball apparatus 20.

  As shown in FIG. 8, in this embodiment, the board side IC substrate 601 is configured as a collective substrate on which four serial-parallel conversion ICs are mounted. With such a configuration, it is possible to consolidate boards on which serial-parallel conversion ICs are mounted, and it is possible to reduce the number of parts in the gaming machine.

  The board-side IC board 601 is equipped with an input IC 621 for converting parallel data into serial data, and detection signals from the position sensors 151b, 152b, 153b for detecting the positions of the movable members 151 to 153 are input ICs 621. Are input in parallel.

  As shown in FIG. 8, a relay board 606 is attached on the game board 6 side, and a relay board 607 is provided on the game frame 11 side. The wiring from the effect control means is first connected to the relay board 606 and further connected to the relay board 607. The wiring from the relay board 606 is connected to the board side IC board 601. Also, the wiring between the board side IC substrate 601 and the relay substrate 606, the wiring between the relay substrates 606 and 607, and the wiring between the relay substrate 606 and the effect control means are shown in FIG. Are connected using connectors 157a to 157e. The connection method of the connectors 157a to 157e is the same as the connection method of the connectors 156a to 156h shown in FIG.

  Further, a relay board is provided to relay the serial-parallel conversion ICs 611 to 615 mounted on the frame side IC boards 602 to 605 and the serial-parallel conversion ICs 616 to 619 mounted on the panel side IC board 601. Also good. In this case, the relay board may be arranged on either the game frame 11 side or the game board 6 side.

  Further, a relay board may be provided to relay the effect control board 80 and the serial-parallel conversion ICs 611 to 615 mounted on the frame side IC boards 602 to 605. In this case, the relay board may be arranged on either the game frame 11 side or the game board 6 side.

  An opening is formed in the upper plate of the plastic frame above the hole for paying out the game ball, and a relay board 607 is provided in the opening. The relay board 607 is a board that relays through the front and back connectors. The connector 157b is disposed on the front side of the plastic frame, and the connectors 156a and 156g are disposed on the back side. Further, the relay board 607 is disposed at the end of the opening to which the game board 6 is attached. As shown in FIG. 7, the relay board 607 is formed in a shape that follows the shape of the end of the opening to which the game board 6 is attached. The relay board 607 is in a state of being shifted so that the positions of the connector 157b arranged on the front side and the connectors 156a and 156g arranged on the back side do not overlap.

  A relay board 606 is provided on the back side of the game board 6. As shown in FIG. 8, the relay board 606 is provided at the end of the game board 6 so as to be positioned in the vicinity of the relay board 607 of the plastic frame. The relay board 606 is a board that relays via a connector, and connectors 157b to 157d are arranged. The connector 157b is connected to the production control microcomputer 100 mounted on the game board 6.

  FIG. 9 is a block diagram illustrating an example of a circuit configuration in the main board (game control board) 31. 9 also shows a payout control board 37 and an effect control board 80 on which a payout control microcomputer for controlling the ball payout device 97 is mounted. A game control microcomputer (corresponding to game control means) 560 for controlling the pachinko gaming machine 1 according to a program is mounted on the main board 31. The game control microcomputer 560 includes a ROM 54 for storing a game control (game progress control) program and the like, a RAM 55 as storage means used as a work memory, a CPU 56 for performing control operations in accordance with the program, and an I / O port unit 57. And a serial output circuit for converting parallel data into serial data and outputting the serial data. In this embodiment, the ROM 54 and the RAM 55 are built in the game control microcomputer 560. That is, the game control microcomputer 560 is a one-chip microcomputer. The one-chip microcomputer only needs to incorporate at least the CPU 56 and the RAM 55, and the ROM 54 may be external or built-in. The I / O port unit 57 may be externally attached.

  The game control microcomputer 560 further includes a random number circuit 503 for generating hardware random numbers.

  In the game control microcomputer 560, the CPU 56 executes control in accordance with the program stored in the ROM 54, so that the game control microcomputer 560 (or CPU 56) executes (or performs processing) hereinafter. Specifically, the CPU 56 executes control according to a program. The same applies to microcomputers mounted on substrates other than the main substrate 31.

  Also, an input driver circuit for supplying detection signals from the gate switch 32a, the first start port switch 13a, the second start port switch 14a, the count switch 23, and the winning port switches 29a, 30a, 33a and 39a to the game control microcomputer 560. 58 is also mounted on the main board 31. The main board also includes an output circuit 59 for driving the solenoid 16 for opening and closing the variable winning ball device 15 and the solenoid 21 for opening and closing the special variable winning ball device 20 that forms a large winning opening in accordance with a command from the game control microcomputer 560. 31.

  Further, the game control microcomputer 560 receives a power-off signal from a power supply board (not shown) and a clear switch detection signal (clear signal). The power-off signal is a signal that is output when a power supply monitoring circuit mounted on the power supply board detects a decrease in a predetermined voltage. The clear switch is a switch that can be operated by a game clerk or the like, and is a switch that is operated when the RAM 55 is to be initialized.

  In addition, the game control microcomputer 560 includes a special symbol display 8 that variably displays special symbols, a normal symbol display 10 that variably displays normal symbols, a special symbol hold memory display 18, and a normal symbol hold memory display 41. Perform display control.

  The serial output circuit 78 mounted on the game control microcomputer 560 is constituted by a shift register or the like. The serial control circuit 78 converts the presentation control command output from the CPU 56 into serial data, and sends it to the presentation control board 80 via the relay board 77. Send. The serial output circuit 78 converts the control signal output from the CPU 56 into serial data, and via the relay board 77, the special symbol display 8, the special symbol hold storage display 18, the normal symbol display 10, and the normal symbol. Output to the on-hold storage display 41. The special symbol display 8, the special symbol hold storage display 18, the normal symbol display 10 and the normal symbol hold storage display 41 are provided with serial-parallel conversion ICs for converting serial data into parallel data, respectively. The control signal from the relay board 77 is converted into parallel data and supplied to the special symbol display 8, the special symbol hold storage display 18, the normal symbol display 10, and the normal symbol hold storage display 41.

  An information output circuit (not shown) that outputs an information output signal such as jackpot information indicating the occurrence of a jackpot gaming state to an external device such as a hall computer is also mounted on the main board 31.

  In this embodiment, when the payout control microcomputer mounted on the payout control board 37 receives a ball lending request signal from the card unit 50 via the interface board 66, the ball payout device 97 is driven. Pay out game balls for lending balls.

  In addition, the effect control means (comprising an effect control microcomputer) mounted on the effect control board 80 sends an effect control command from the game control microcomputer 560 via the relay board 77 to the serial signal system ( Serial communication system: a system in which data is transmitted by one signal line), and display control of the variable display device 9 for variably displaying decorative symbols is performed.

  Further, the effect control means mounted on the effect control board 80 controls the display of the LED 125a to 125f of the center decoration lamp and the LEDs 126a to 126f of the stage lamp provided on the game board 6, and is provided on the frame side. The display control of the LED 281a to 281l of the ceiling frame lamp, the LEDs 282a to 282f of the left frame lamp, and the LEDs 283a to 283f of the right frame lamp is performed, and the sound output from the speaker 27 is controlled.

  Further, the effect control microcomputer 100 of the effect control board 80 has a control for display control of the lamps 125a to 125f, 126a to 126f, 281a to 281l, 282a to 282f, and 283a to 283f output by the effect control means. A serial output circuit 353 for converting a signal from parallel data to serial data is mounted. In addition, the effect control microcomputer 100 of the effect control board 80 is equipped with a serial input circuit 354 that converts the input serial data into parallel data and outputs the parallel data to the effect control means. Therefore, the effect control means outputs the control signal in the serial signal system via the serial output circuit 353, thereby controlling the display of each of the lamps 125a to 125f, 126a to 126f, 281a to 281l, 282a to 282f, 283a to 283f. I do.

  On the game board side, a board-side IC board 601 on which a serial-parallel conversion IC for converting serial data into parallel data is mounted. The board side IC substrate 601 is connected to the effect control substrate 80 via the relay substrate 606. On the game frame 11 side, frame-side IC substrates 602, 603, 604, and 605 on which serial-parallel conversion ICs for converting serial data into parallel data are provided. Each frame side IC substrate 602, 603, 604, 605 is connected to the effect control substrate 80 via the relay substrate 606, 607.

  The effect control board 80, the relay board 606, and the relay board 607 are connected by one bus type wiring route.

  FIG. 10 is a block diagram illustrating a circuit configuration example of the relay board 77 and the effect control board 80. In addition, although the example shown in FIG. 10 shows the case where only the effect control board 80 is provided regarding the effect control, a lamp driver board and an audio output board may be provided. In this case, the lamp driver board and the sound output board are not equipped with a microcomputer, but may be equipped with a microcomputer.

  The effect control board 80 includes an effect control microcomputer 100 including an effect control CPU 101, a RAM (not shown), a serial output circuit 353, a serial input circuit 354, a clock signal output unit 356 and an input capture signal output unit 357. It is installed. The RAM may be externally attached. In the effect control board 80, the effect control CPU 101 operates in accordance with a program stored in a built-in or external ROM (not shown), and receives an effect control command via the serial input circuit 102 and the input port 103. In this case, the serial input circuit 102 converts the effect control command received by the serial signal method into parallel data and outputs the parallel data. Further, the effect control CPU 101 causes the VDP (video display processor) 109 to perform display control of the variable display device 9 based on the effect control command.

  In this embodiment, a VDP 109 that performs display control of the variable display device 9 in cooperation with the effect control microcomputer 100 is mounted on the effect control board 80. The VDP 109 has an address space independent of the production control microcomputer 100 and maps the VRAM therein. VRAM is a buffer memory for developing image data. The VDP 109 outputs the image data in the VRAM to the variable display device 9 via the frame memory.

  The effect control CPU 101 outputs to the VDP 109 a command for reading out necessary data from a CGROM (not shown) in accordance with the received effect control command. The CGROM stores character image data and moving image data displayed on the variable display device 9, specifically, a person, characters, figures, symbols, etc. (including decorative designs), and background image data in advance. ROM. The VDP 109 reads image data from the CGROM in response to the instruction from the effect control CPU 101. The VDP 109 executes display control based on the read image data.

  As a signal direction regulating means, the signal inputted from the main board 31 is allowed to pass through the relay board 77 only in the direction toward the effect control board 80 (the signal is not passed in the direction from the effect control board 80 to the relay board 77). The unidirectional circuit 74 is mounted. For example, a diode or a transistor is used as the unidirectional circuit. FIG. 10 illustrates a diode.

  Further, the effect control CPU 101 outputs a signal for driving the lamp via the serial output circuit 353. The serial output circuit converts the input signal (parallel data) for driving the LED of the lamp into serial data and outputs the serial data to the relay board 606. Further, the production control CPU 101 outputs the sound number data to the speech synthesis IC 173.

  Further, the clock signal output unit 356 outputs a clock signal to the relay board 606. The clock signal from the clock signal output unit 356 is supplied to the serial-parallel conversion ICs 611 to 615 and the input IC 620 mounted on the frame side IC substrates 602 to 605 via the relay substrates 606 and 607. The clock signal from the clock signal output unit 356 is supplied to the serial-parallel conversion ICs 616 to 619 and the input IC 621 mounted on the board side IC substrate 601 via the relay substrate 606. Therefore, in this embodiment, a common clock signal is supplied to the serial-parallel conversion ICs 611 to 619 and the input ICs 620 and 621.

  Further, the input capture signal output unit 357 inputs the input capture signal (latch signal) to the board side IC board 601 or the frame side IC boards 602 to 605 via the relay boards 606 and 607 in accordance with the instruction of the effect control CPU 101. Is output. The input IC 620 mounted on the frame side IC board 605 latches the detection signals of the operation buttons 81a to 81e when an input input signal from the production control microcomputer 100 is input, and relay boards 606 and 607 in a serial signal system. To the production control microcomputer 100. The input IC 621 mounted on the board-side IC board 601 latches the detection signals of the position sensors 151b, 152b, and 153b when the input capture signal from the production control microcomputer 100 is input, and uses a serial signal method. This is output to the production control microcomputer 100 via the relay board 606.

  When the sound number IC 173 receives the sound number data, the sound synthesizing IC 173 generates a sound or a sound effect corresponding to the sound number data and outputs it to the amplifier circuit 175. The amplifier circuit 175 outputs an audio signal obtained by amplifying the output level of the speech synthesis IC 173 to a level corresponding to the volume set by the volume 176 to the speaker 27. The voice data ROM 174 stores control data corresponding to the sound number data. The control data corresponding to the sound number data is a collection of data indicating the sound effect or sound output mode in a time series in a predetermined period (for example, a decorative symbol variation period).

  FIG. 11 is a block diagram illustrating a configuration example of the effect control board 80, the relay boards 606 and 607, the board-side IC board 601, and the frame-side IC boards 602, 603, 604, and 605. The effect control microcomputer 100 of the effect control board 80 outputs a clock signal to the relay board 607 together with serial data as a control signal. In addition, an input capture signal for causing the input ICs 620 and 621 to latch the input signal is output to the relay board 606.

  The relay board 606 supplies the serial data and the clock signal input from the effect control microcomputer 100 to the serial-parallel conversion ICs 616 to 619 mounted on the board side IC board 601. And each serial-parallel conversion IC616-619 converts the input serial data into parallel data, LED125a-125f of each lamp provided in the game board 6, 126a-126f, 127a-127c, and each movable member To the motors 151a to 151c. The serial-parallel conversion ICs 616 to 619 are also drive circuits for driving the LEDs 125a to 125f, 126a to 126f, 127a to 127c and the motors 151a to 151c. In other words, the LED 125a to 125f, 126a to 126f, 127a to 127c and the motors 151a to 151c have a capability of supplying a current necessary for driving (LEDs are lit).

  Further, the relay board 607 is connected to the relay board 606 through one bus-type wiring route, and the serial data line 300 and the clock signal line 301 connected to the serial-parallel conversion ICs 616 to 619 are the board side IC board. 601 is connected in a bus format. In addition, being connected by one wiring route means that a plurality of serial-parallel conversion ICs or relay boards are connected to one wiring route.

  Each serial-parallel conversion IC 616 to 619 mounted on the board side IC substrate 601 is assigned a unique ID. In this embodiment, as shown in FIG. 11, the ID of IC 616 is 06, the ID of IC 617 is 07, the ID of IC 618 is 08, and the ID of IC 619 is 09.

  In addition, an input IC 621 for inputting a detection signal of a position sensor of each movable member provided on the game board 6 is mounted on the board side IC board 601. In this embodiment, the input IC 621 and the production control microcomputer 100 mounted on the board-side IC board 601 include an input signal line 302, a clock signal line 301, and an input capture signal line 303 via a relay board 606. The connected production control microcomputer 100 outputs an input capture signal to the input IC 621 via the relay board 606 at a predetermined timing. Then, the input IC 621 latches the detection signal of each position sensor based on the input fetch signal (latch signal) and outputs it to the effect control microcomputer 100 via the relay board 606. In this case, the input IC 621 converts the detection signal input in parallel from each position sensor into serial data and outputs it. In this embodiment, the unique ID of the input IC 621 is 11, as shown in FIG.

  As shown in FIG. 11, the serial data and the clock signal input to the relay board 607 are supplied to the serial-parallel conversion ICs 611 to 615 mounted on the frame side IC boards 602 to 605, respectively. And each serial-parallel conversion IC611-615 converts the input serial data into parallel data, LED281a-281l of each lamp provided in the game frame 11, 282a-282f, 283a-283f, 82a-82d, 83. The serial-parallel conversion ICs 611 to 615 are also drive circuits for driving the LEDs 281a to 281l, 282a to 282f, 283a to 283f, 82a to 82d, 83. That is, the LED 281a to 281l, 282a to 282f, 283a to 283f, 82a to 82d, and 83c have a capability of supplying a current necessary for driving (lighting).

  The serial data lines and clock signal lines connected to the serial-parallel conversion ICs 611 to 614 are connected in a bus format on the frame side IC substrates 602 to 604. In this embodiment, as shown in FIG. 11, first, the serial-parallel conversion IC 614 of the frame side IC substrate 604 is input, and the serial-parallel conversion IC 614 and the serial-parallel conversion IC 611 of the frame side IC substrate 602 are serially converted. The signals are input in the order of the parallel conversion IC 612, and further input from the serial-parallel conversion IC 612 to the serial-parallel conversion IC 613 of the frame side IC substrate 603. The serial data line and the clock signal line connected to the serial-parallel conversion IC 615 are directly connected from the relay board 607.

  Each serial-parallel conversion IC 611 to 615 mounted on each frame side IC substrate 602 to 605 has a unique ID. In this embodiment, as shown in FIG. 11, the ID of IC 611 is 01, the ID of IC 612 is 02, the ID of IC 613 is 03, the ID of IC 614 is 04, and the ID of IC 615 is 05 It is.

  In addition, an input IC 620 for inputting detection signals of the operation buttons 81 a to 81 e provided on the game frame 11 is mounted on the frame side IC board 605. In this embodiment, an input signal line, a clock signal line, and an input capture signal line are connected to the input IC 620 mounted on the frame side IC board 605 and the production control microcomputer 100 via the relay boards 606 and 607. Then, the production control microcomputer 100 outputs an input capture signal to the input IC 620 via the relay boards 606 and 607 at a predetermined timing. In this case, the production control microcomputer 100 outputs the input capture signal to the input IC 620 at a timing different from the timing of outputting the input capture signal to the input IC 621. Then, the input IC 620 latches the detection signals from the operation buttons 81a to 81e based on the input capture signal (latch signal), and outputs it to the effect control microcomputer 100 via the relay boards 606 and 607. In this case, the input IC 620 converts detection signals input in parallel from the operation buttons 81a to 81e into serial data and outputs the serial data. In this embodiment, the unique ID of the input IC 620 is 10 as shown in FIG.

  The serial-parallel conversion ICs 616 to 619 mounted on the panel-side IC substrate 601 and the serial-parallel conversion ICs 611 to 615 mounted on the frame-side IC substrates 602 to 605 are connected via one line of wiring. . Specifically, the connection through one system wiring means that the relay boards 606 and 607 are connected in a bus type, and the serial-parallel conversion ICs 611 to 619 are connected in a bus type or a daisy chain type. It is that. In this embodiment, as shown in FIG. 11, the serial-parallel conversion ICs 611 to 619 are connected in a bus type. As described above, in this embodiment, the serial-parallel conversion ICs 616 to 619 mounted on the board side IC substrate 601 and the serial-parallel ICs 611 to 615 mounted on the frame side IC substrates 602 to 605 are provided. The connectors 156a to 156h and 157a to 157e are connected via the relay boards 606 and 607 via one line of wiring. Therefore, the wiring work between the game frame 11 and the game board 6 can be performed simply by attaching and detaching the connector, and the game frame 11 and the game board 6 can be attached and detached more easily.

  In addition, according to this embodiment, the serial-parallel conversion ICs 616 to 619 mounted on the board side IC substrate 601, the serial-parallel conversion ICs 611 to 615 mounted on the frame side IC substrates 602 to 605, and the input ICs 620 and 621. The common clock signal is input from the production control microcomputer 100. Therefore, the wiring of the clock signal to the serial-parallel conversion ICs 611 to 619 and the wiring of the clock signal to the input ICs 620 and 621 can be shared, and communication between the effect control means and the board-side IC 601 board, Communication between the effect control means and the frame side IC substrates 602 to 605 can be realized using one channel, respectively, and the number of wirings can be reduced. Also, the serial-parallel conversion ICs 616 to 619 mounted on the board side IC substrate 601, the serial-parallel conversion ICs 611 to 615 mounted on the frame side IC substrates 602 to 605, and the input ICs 620 and 621 can be easily synchronized. The number of clock signal wirings can also be reduced.

  In this embodiment, addresses are assigned in advance to the serial-parallel conversion ICs 611 to 619, and the production control microcomputer 100 adds addresses to the serial data when outputting the control signal converted into serial data. And output. When each serial-parallel conversion IC 611-619 inputs serial data, it checks whether the address added to the input serial data matches its own address, and if it matches, converts it to parallel data. Are supplied (ie, output) to the LEDs of each lamp. If the addresses do not match, the LED of each lamp is not supplied.

  As shown in FIG. 11, the production control microcomputer 100 performs bidirectional communication with the board-side IC board 601 and the frame-side IC boards 602 to 605 (specifically, serial data is converted into each serial-parallel converter). IC 611 to 619 and input signals are input from the input ICs 620 and 621). Therefore, a data input terminal and a data output terminal are provided, and data input and data output can be performed in one channel. In this embodiment, as shown in FIG. 11, a data input terminal and a data output terminal of one channel are respectively connected to different output target devices (in this embodiment, serial-parallel conversion ICs 611 to 619) and input targets. It is connected to a device (in this embodiment, input ICs 620 and 621). With such a configuration, when the output target device and the input target device are originally different devices, the communication should be performed using different channels in both directions. Communication is enabled to reduce the number of channels between the production control microcomputer 100 and the board-side IC board 601 and the frame-side IC boards 602 to 605.

  In this embodiment, the channel is a terminal for a data line (output data line), a clock signal line, an input signal line (input data line), and an input take-in signal line (signal line for input data read request). Is a set. One channel may include a ground wire or a terminal dedicated to the power source. Further, in this embodiment, a case where both data input and data output are performed using one channel is shown, but an output-dedicated channel in which only a terminal for a data line (output data line) and a clock signal line is set. May be used. Alternatively, an input-only channel in which only terminals for input signal lines (input data lines) and input take-in signal lines (input data read request signal lines) are set may be used.

  12 and 13 are explanatory diagrams showing examples of addresses given to the serial-parallel conversion ICs 611 to 619. FIG. In this embodiment, the production control microcomputer 100 stores the addresses of the serial-parallel conversion ICs 611 to 619 shown in FIGS. 12 and 13 in a predetermined address storage area previously provided in the RAM.

  In this embodiment, as shown in FIGS. 12 and 13, in the serial-parallel conversion ICs 611 to 615 mounted on the frame side IC substrates 602 to 605, an address 01 is assigned to the IC 611, and an address is assigned to the IC 612. 02 is given, address 03 is given to IC613, address 04 is given to IC614, and address 05 is given to IC615. Further, in the serial-parallel conversion ICs 616 to 619 mounted on the board side IC substrate 601, the address 006 is assigned to the IC 616, the address 07 is given to the IC 617, the address 08 is given to the IC 618, and the IC 619 is given to the IC 619. Address 09 is given.

  The serial-parallel conversion ICs 611 to 619 may be given the same ID as the unique ID of the IC as an address, or may be given an address including numbers, characters, and symbols different from the unique ID of the IC. Good.

  As shown in FIGS. 12 and 13, the serial-parallel conversion IC 611 whose address is 01 converts serial data into parallel data, and the LED of the ceiling lamp of the game frame 11 (in this embodiment, the ceiling frame). Six LEDs (281a to 281f) of the LEDs 281a to 281l of the lamp are supplied. The serial-parallel conversion IC 612 whose address is 02 converts serial data into parallel data, and the LED of the top frame lamp of the game frame 11 (in this embodiment, the other six LEDs of the top frame lamp LEDs 281a to 281l). (281 g to 281 l)). The serial-parallel conversion IC 613 whose address is 03 converts the serial data into parallel data and supplies it to the LED of the right frame lamp of the game frame 11 (six LEDs (283a to 283f in this embodiment)). Further, the serial-parallel conversion IC 614 whose address is 04 converts the serial data into parallel data, and supplies it to the LED of the left frame lamp of the game frame 11 (in this embodiment, six LEDs (282a to 282f)).

  Further, the serial-parallel conversion IC 615 whose address is 05 converts the serial data into parallel data, and provides a dish lamp (four LEDs (82a to 82d) in this embodiment) provided on the hitting ball supply tray 3 of the game frame 11. ) And an LED (operation button lamp) 83 (one lamp in this embodiment) provided on the operation buttons 81a to 81e.

  The serial-parallel conversion IC 616 whose address is 06 converts serial data into parallel data, and each movable member provided in the game board 6 (in this embodiment, imitating the shape of a beam, a truck, and a skeleton) The three motors 151a, 152a, 153a for driving the accessory) are supplied in the opposite direction to the forward direction. The serial-parallel conversion IC 617 whose address is 07 converts the serial data into parallel data, and configures the LEDs constituting each lamp of the decorative structure (center decoration) provided in the center of the game board 6 (this embodiment In a form, it supplies to 6 LED (125a-125f). The serial-parallel conversion IC 618 whose address is 08 converts serial data into parallel data, and configures each stage lamp provided around the variable display device 9 (in this embodiment, six LEDs (126a To 126f)). The serial-parallel conversion IC 619 whose address is 09 converts serial data into parallel data, and configures an LED (in this embodiment, a lamp provided around the movable member (the skeleton 153 in this embodiment)). It supplies to three LED (127a-127c).

  In this embodiment, each input IC 620, 621 is also given an address in advance. FIG. 14 is an explanatory diagram showing an example of addresses given to the input ICs 620 and 621. The production control microcomputer 100 stores the addresses of the input ICs 620 and 621 in a predetermined address storage area provided in advance in the RAM. In this embodiment, as shown in FIG. 14, the address 10 is assigned to the input IC 620 mounted on the frame side IC board 605, and the address 11 is assigned to the input IC 621 mounted on the board side IC board 601. ing.

  Each input IC 620, 621 may be given the same ID as the unique ID of the IC as an address, or may be given an address including numbers, characters, and symbols different from the unique ID of the IC.

  Further, as shown in FIG. 14, the input IC 620 whose address is 10, the detection signal of the operation buttons 81a to 81e provided in the game frame 11 (whether or not the operation buttons 81a to 81e themselves are turned on, the operation button 81a ˜81e) is inputted in parallel, converted into serial data, and outputted. Further, the input IC 621 whose address is 11 inputs the detection signals of the position sensors 151b, 152b, 153b (three in this embodiment) provided on each movable member of the game board 6 in parallel and converts them into serial data. Convert and output.

  FIG. 15 is a block diagram showing the configuration of each serial-parallel conversion IC 611-619. As illustrated in FIG. 15, the serial-parallel conversion ICs 611 to 619 include a data latch unit 651, a shift register 652, a header / address detection unit 653, a data buffer 655, and a sync driver 656.

  The data latch unit 651 includes, for example, a latch circuit. When serial data is input, the data latch unit 651 latches the input data bit by bit at the rising timing of the clock signal pulse and outputs the latched data to the shift register 652. The shift register 652 sequentially stores data input bit by bit from the data latch unit 651. The shift register 652 shifts stored data bit by bit at the rising timing of the pulse of the clock signal. By repeatedly shifting the stored data bit by bit as described above, the data finally input as serial data (that is, in the serial signal system) is stored in the shift register 652.

  FIG. 16 is an explanatory diagram showing an example of the format of serial data output from the production control microcomputer 100. FIG. 16A shows a data format of serial data output as lamp lighting data for individually lighting or extinguishing the LEDs of each lamp provided in the game board 6 or the game frame 11. FIG. 16B shows a serial data format that is output as a reset command for resetting the LEDs of the respective lamps provided on the game board 6 and the game frame 11 to turn them all off.

  As shown in FIG. 16A, the lamp lighting data is composed of 28 bits, and includes 9-bit header data, mark bits (M), 8-bit addresses, 8-bit data, and end bits (E). .

  The header data represents the head of the data, and is 1FF (h) in this embodiment. The mark bit (M) is a bit (logical value 0 in this embodiment) representing a data delimiter, and is inserted between the header data and the address and between the address and the data. The address is the address of the data-output destination serial-parallel conversion IC. An ID that is a unique serial number of each serial-parallel conversion IC 611 to 619 may be used as the address.

  The data (8 bits) is for controlling the lighting state of the LED of each lamp, and includes, for example, a logical value 1 as a bit corresponding to the LED of the lamp to be lit, Corresponding bits contain the logical value 0. The end bit (E) indicates the end of data, and is a logical value 0 in this embodiment.

  As shown in FIG. 16B, the reset command is composed of 19 bits and includes 9-bit header data, mark bits (M), 8-bit reset data, and end bits (E).

  The header data represents the head of the data, and is 1FF (h) in this embodiment. The mark bit (M) is a bit (logical value 0 in this embodiment) representing a data delimiter, and is inserted between the header data and the reset data. The reset data is for resetting the lighting states of the LEDs of the respective lamps so that all the lamps are extinguished. The end bit (E) indicates the end of data, and is a logical value 0 in this embodiment.

  In this embodiment, the lamp lighting data shown in FIG. 16A or the reset command shown in FIG. 16B is input, and the shift register 652 is repeatedly shifted bit by bit at the rising timing of the pulse of the clock signal. Will be stored.

  The header / address detector 653 detects the header and address from the data stored in the shift register 652. First, the header / address detection unit 653 constantly detects data from the shift register 652, and confirms whether or not the content of the detected data matches 1FF (h) corresponding to the header data. If it matches the header data (1FF (h)), it is determined that the position that matches the header data is the head of the data, and it is determined that one set of lamp lighting data or reset command is stored in the shift register 652. Next, the header / address detection unit 653 detects the 11th to 18th bits of data from the head corresponding to the address from the shift register 652, and whether or not it matches the address previously given to the serial-parallel conversion IC. To check. The board-side IC board 601 and the frame-side IC boards 602 to 605 are provided with, for example, an address storage register 654 that stores the address of the serial-parallel conversion IC to be mounted, and the header / address detector 653 is a shift register. It may be confirmed whether the address detected from 652 matches the address stored in the address storage register 654 in advance. If the addresses match, the header / address detection 653 determines that data destined for the serial-parallel conversion IC has been input, and outputs an input capture signal (latch signal) to the data buffer 655. If the addresses do not match, the header / address detection 653 does not output the input capture signal to the data buffer 655. That is, in this case, since the data is not destined for the serial-parallel conversion IC, the data stored in the shift register 652 is discarded without being output to the data buffer 655.

  15 shows a case where the address storage register 654 is provided in advance on the board side IC substrate 601 and each of the frame side IC substrates 602 to 605. However, instead of the address storage register 654, serial-parallel conversion is shown. An address is input from an external hardware circuit (for example, a circuit mounted on the production control board 80) via an address terminal (8 terminals (corresponding to each bit of an 8-bit address)) provided in the IC. You may make it do. Then, an address may be input to the serial-parallel conversion IC by controlling the input of each address terminal to high (high level) or low (low level) from the external hardware circuit side. In this case, for example, the external hardware circuit sets the input to the terminal to high by applying a voltage to the terminal corresponding to any bit of the address, or sets the input to the terminal to low by switching to the ground. Control to do.

  The data buffer 655 is constituted by, for example, a latch register. When an input capture signal is input from the header / address detector 653, the data of the 20th to 27th bits from the head corresponding to the data portion is captured from the shift register 652. Latch with. The data buffer 655 supplies (that is, outputs) the fetched data to the LEDs of each lamp as parallel data (Q0 to Q7).

  If the data stored in the shift register 652 is a reset command, the 11th to 18th bits from the beginning all store data having a logical value of 1. In this case, the data buffer 655 determines that a reset command has been input when all data having a logical value of 1 is fetched, and the LEDs of all the lamps are reset and turned off.

  The sync driver 656 inverts and outputs the logical value of the parallel data output from the data buffer 655 based on a predetermined logic inversion setting signal, or outputs it as it is. For example, when the predetermined logic inversion setting signal is High, the signal is turned on when the bit value of the parallel data output from the data buffer 655 is 1 (that is, the corresponding bit value of the lamp lighting data is 1), An ON signal is output to the LED of each lamp. In this embodiment, the set value of the logic inversion setting signal is set in advance in a register or the like provided on the panel side IC board 601 or each frame side IC board 602 to 605, and the LED of each lamp is set according to the set value set in advance. It is assumed that an ON signal is outputted to the LED of each lamp.

  FIG. 17 is a timing diagram showing an example of the input timing of serial data and clock signals to the serial-parallel conversion IC and the output timing of parallel data. In FIG. 17, a case where lamp lighting data is input by a serial signal method will be described. As shown in FIG. 17, the serial data is input to the shift register 652 of the serial-parallel conversion IC in units of 1 bit in the order of header data, mark bits, addresses, mark bits, data, and end bits. The series of data is set as one set. The header / address detection unit 653 does not detect header data until one set of serial data (in this embodiment, lamp lighting data) is completely input, so the output of the data buffer 655 does not change. Therefore, the lighting pattern based on the serial data received last time is output from the serial-parallel conversion IC as it is by the parallel signal method (parallel communication method: a method of sending data through a plurality of signal lines).

  When all sets of serial data have been input, the data portion from the data stored in the shift register 652 is latched in the data buffer 655, and a lighting pattern based on the newly received serial data is output in a parallel signal system. In this embodiment, as shown in FIG. 17, among the parallel data output from the serial-parallel conversion IC, Q0 and Q4 are the rising timing of the pulse of the next clock signal after completion of the serial data input. Immediately, the data is switched to new lighting pattern data. Q1 and Q5 are switched to new lighting pattern data with a delay of one clock from Q0 and Q4. Q2 and Q6 are switched to new lighting pattern data with a delay of two clocks from Q0 and Q4. Further, Q3 and Q7 are switched to new lighting pattern data with a delay of three clocks from Q0 and Q4.

  FIG. 18 is a block diagram illustrating the configuration of each of the input ICs 620 and 621. As shown in FIG. 18, in this embodiment, each input IC 620, 621 is composed of a plurality (eight in this embodiment) of D flip-flops 661-668. In this embodiment, detection signals from the operation buttons 81a to 81e or the position sensors 151b, 152b, and 153b are input in parallel to the input ICs 620 and 621, and are input to one of the D flip-flops 661 to 668 for each detection signal. Entered. A clock signal is input to each of the D flip-flops 661 to 668, and each D flip-flop 661 to 668 sequentially performs a shift operation at the rising edge of the clock. The detection signal input in parallel is converted into serial data and output.

  An input capture signal (latch signal) is input to each of the D flip-flops 661 to 668 from the effect control microcomputer 100 at a predetermined timing. When an input capture signal is input, detection signals from the operation buttons 81a to 81e or the position sensors 151b, 152b, and 153b are latched by the D flip-flops 661 to 668, respectively. Then, the latched detection signals are sequentially shifted at the rising edge of the clock and output in a serial signal system.

  Next, the operation of the gaming machine will be described. FIG. 19 is a flowchart showing main processing executed by the game control microcomputer 560 on the main board 31. When power is supplied to the gaming machine and power supply is started, the input level of the reset terminal to which the reset signal is input becomes high level, and the gaming control microcomputer 560 (specifically, the CPU 56) After executing a security check process, which is a process for confirming whether the contents of the program are valid, the main process after step S1 is started. In the main process, the CPU 56 first performs necessary initial settings.

  In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, the interrupt mode is set to interrupt mode 2 (step S2), and a stack pointer designation address is set to the stack pointer (step S3). Then, after initialization of the built-in device (such as CTC (counter / timer) and PIO (parallel input / output port) which are built-in devices (built-in peripheral circuits)) is performed (step S4), the RAM can be accessed. (Step S5). In interrupt mode 2, the address synthesized from the value (1 byte) of the specific register (I register) built in the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output from the built-in device is This mode indicates an interrupt address.

  Next, the CPU 56 checks the state of the output signal of the clear switch (for example, mounted on the power supply board) input via the input port (step S6). When the ON is detected in the confirmation, the CPU 56 executes normal initialization processing (steps S10 to S15, including S44 and S45).

  If the clear switch is not in the on state, check whether data protection processing of the backup RAM area (for example, power supply stop processing such as addition of parity data) has been performed when power supply to the gaming machine is stopped (Step S7). When it is confirmed that such protection processing is not performed, the CPU 56 executes initialization processing. Whether there is backup data in the backup RAM area is confirmed, for example, by the state of the backup flag set in the backup RAM area in the power supply stop process.

  After confirming that the power supply stop process has been performed, the CPU 56 performs data check of the backup RAM area (step S8). In this embodiment, a parity check is performed as a data check. Therefore, in step S8, the calculated checksum is compared with the checksum calculated and stored by the same process in the power supply stop process. When the power supply is stopped after an unexpected power outage or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area is different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state when the power supply is stopped, an initialization process that is executed when the power is turned on is not performed when the power supply is stopped.

  If the check result is normal, the CPU 56 restores the game state restoration process (steps S41 to S43) for returning the internal state of the game control means and the control state of the electrical component control means such as the effect control means to the state when the power supply is stopped. Process). Specifically, the start address of the backup setting table stored in the ROM 54 is set as a pointer (step S41), and the contents of the backup setting table are sequentially set in the work area (area in the RAM 55) (step S42). ). The work area is backed up by a backup power source. In the backup setting table, initialization data for an area that may be initialized in the work area is set. As a result of the processing in steps S41 and S42, the saved contents of the work area that should not be initialized remain. The parts that must not be initialized include, for example, data indicating a gaming state before the power supply is stopped (special symbol process flag, etc.), an area where the output state of the output port is saved (output port buffer), and unpaid prize balls This is the part where data indicating the number is set.

  Further, the CPU 56 transmits a power failure recovery designation command as an initialization command at the time of power supply recovery (step S43). Then, the process proceeds to step S14.

  In this embodiment, it is confirmed whether the data in the backup RAM area is stored using both the backup flag and the check data. However, only one of them may be used. That is, either the backup flag or the check data may be used as an opportunity for executing the game state restoration process.

  In the initialization process, the CPU 56 first performs a RAM clear process (step S10). The RAM clear process initializes predetermined data (for example, count value data of a counter for generating a big hit determination random number) to 0, but is initialized to an arbitrary value or a predetermined value. You may make it do. Alternatively, the entire area of the RAM 55 may not be initialized, and predetermined data (for example, count value data of a counter for generating a big hit determination random number) may be left as it is. Further, the start address of the initialization setting table stored in the ROM 54 is set as a pointer (step S11), and the contents of the initialization setting table are sequentially set in the work area (step S12).

  As a result of the processing in steps S11 and S12, for example, a normal symbol determination random number counter, a special symbol buffer, a total prize ball number storage buffer, a special symbol process flag, and other flags for selectively performing processing according to the control state are initialized. Is set.

  Further, the CPU 56 initializes a sub board (a board on which a microcomputer other than the main board 31 is mounted) (a command indicating that the game control microcomputer 560 has executed an initialization process). Is also transmitted to the sub-board (step S13). For example, when the initialization control microcomputer 100 receives the initialization designation command, the variable display device 9 performs screen display for notifying that the control of the gaming machine has been initialized, that is, initialization notification.

  Further, the CPU 56 sets an abnormality notification prohibition flag (step S44) and sets a value corresponding to the prohibition period value in the prohibition period timer (step S45). The prohibition period value is a value indicating a period during which an abnormal winning notification described later is prohibited. The abnormality notification prohibition flag is a flag indicating that notification of an abnormal winning is prohibited, and is maintained in the set state until the prohibition period timer times out. Therefore, the start of the abnormal winning notification is prohibited for a predetermined period after the initialization notification is started in the variable display device 9.

  Further, the CPU 56 executes a random number circuit setting process for initial setting of the random number circuit (step S14). For example, the CPU 56 performs setting according to the random number circuit setting program so as to cause the random number circuit to update the value of the random R. In the random number circuit setting process, the CPU 56 also executes a random number circuit confirmation process for confirming the state of the random number circuit. In the random number circuit confirmation process, the CPU 56 monitors a random number confirmation signal output from the random number circuit for a predetermined time. The random number confirmation signal is ON when the clock signal generation circuit built in the random number circuit normally outputs the internal clock signal, and otherwise (for example, when the level of the internal clock signal decreases) Will be off). If the CPU 56 detects the OFF state of the random number confirmation signal continuously for a predetermined time, the CPU 56 determines that an abnormality has occurred in the random number circuit 503 built in the game control microcomputer 560, and generates a random circuit error of the main board 31. A process of transmitting a random circuit error designation command designating notification to the sub-board is executed. If the OFF state of the random number confirmation signal is not detected continuously for a predetermined time, the CPU 56 determines that the random number circuit 503 is operating normally, and proceeds to step S15 as it is.

  In step S15, the CPU 56 sets a register of the CTC built in the game control microcomputer 560 so that a timer interrupt is periodically taken every predetermined time (for example, 2 ms). That is, a value corresponding to, for example, 2 ms is set in a predetermined register (time constant register) as an initial value. In this embodiment, it is assumed that a timer interrupt is periodically taken every 2 ms.

  When the execution of the initialization process (steps S10 to S15) is completed, the CPU 56 repeatedly executes the display random number update process (step S17) and the initial value random number update process (step S18) in the main process. When executing the display random number update process and the initial value random number update process, the interrupt disabled state is set (step S16). When the display random number update process and the initial value random number update process are finished, the interrupt enabled state is set. Set (step S19). In this embodiment, the display random number is a random number for determining the variation pattern, and the display random number update process is a process for updating the count value of the counter for generating the display random number. The initial value random number update process is a process for updating the count value of the counter for generating the initial value random number. In this embodiment, the initial value random number determines an initial value such as a counter for generating a random number for determining whether or not to win a normal symbol (ordinary random number generation counter for normal symbol determination). It is a random number for. A game control process for controlling the progress of the game, which will be described later (the game control microcomputer 560 controls game devices such as a variable display device, a variable winning ball device, a ball payout device, etc. provided in the game machine itself. In the process of transmitting a command signal to be controlled by another microcomputer, or a game machine control process), the count value of the random number for determination per normal symbol is one round (the random number for determination per normal symbol is taken). When the value is incremented by the number of values between the minimum value and the maximum value), an initial value is set in the counter.

  When the timer interrupt occurs, the CPU 56 executes the timer interrupt process in steps S20 to S36 shown in FIG. In the timer interrupt process, first, a power-off detection process for detecting whether or not a power-off signal is output (whether or not an on-state is turned on) is executed (step S20). The power-off signal is output, for example, when a voltage drop monitoring circuit mounted on the power supply board detects a drop in the voltage of the power supplied to the gaming machine. In the power-off detection process, when detecting that the power-off signal has been output, the CPU 56 executes a power supply stop process for storing necessary data in the backup RAM area. Next, detection signals of the gate switch 32a, the first start port switch 13a, the second start port switch 14a, the count switch 23, and the winning port switches 29a, 30a, 33a, 39a are input via the input driver circuit 58, These state determinations are performed (switch processing: step S21).

  Next, the CPU 56 executes a display control process for performing display control of the special symbol display 8, the normal symbol display 10, the special symbol hold storage display 18, and the normal symbol hold storage display 41 (step S22). For the special symbol display 8 and the normal symbol display 10, control for outputting a drive signal to each display is executed according to the contents of the output buffer set in steps S34 and S35.

  Further, the CPU 56 performs a process for notifying an abnormal winning when it detects that a game ball has won a prize at a time other than the regular time (step S23: abnormal winning notification process).

  Next, processing for updating the count value of each counter for generating random numbers for determination such as random numbers for determining jackpot symbols used for game control is performed (determination random number update processing: step S24). The CPU 56 further performs a process of updating the count value of the counter for generating the initial value random number and the display random number (initial value random number update process, display random number update process: steps S25 and S26).

FIG. 21 is an explanatory diagram showing each random number. Each random number is used as follows.
(1) Random 1: Determine a special symbol off symbol (stop symbol) (for off symbol determination)
(2) Random 2: Determines the special symbol stop symbol when generating a big hit (for big hit symbol determination)
(3) Random 3: Determine the variation pattern (variation time) of special symbols (for variation pattern determination)
(4) Random 4: Determines whether or not to generate a hit based on the normal symbol (for normal symbol hit determination)
(5) Random 5: Random 4 initial value is determined (for determining random 4 initial value)

  In step S24 in the game control process shown in FIG. 20, the game control microcomputer 560 uses a counter for generating the jackpot symbol determination random number (2) and the random number for determination per regular symbol (4). Count up (add 1). That is, they are determination random numbers, and other random numbers are display random numbers or initial value random numbers. In addition, in order to improve a game effect, you may make it use random numbers other than the random number of said (1)-(5). In this embodiment, the big hit determination random number is a random number generated by the hardware (random number circuit 503) built in the game control microcomputer 560, but the big hit determination random number is used as the big hit determination random number 560. Software random numbers generated based on the program may be used.

  Further, the CPU 56 performs special symbol process processing (step S27). In the special symbol process, the corresponding symbol is executed in accordance with a special symbol process flag for controlling the special symbol display 8 and the special winning award in a predetermined order. The CPU 56 updates the value of the special symbol process flag according to the gaming state.

  Next, normal symbol process processing is performed (step S28). In the normal symbol process, the CPU 56 executes the corresponding process according to the normal symbol process flag for controlling the display state of the normal symbol display 10 in a predetermined order. The CPU 56 updates the value of the normal symbol process flag according to the gaming state.

  Further, the CPU 56 performs a process of sending an effect control command to the effect control microcomputer 100 (effect control command control process: step S29). In this embodiment, in step S29, the game control microcomputer 560 causes the MODE data or EXT data (MODE data to which the addresses of the transmission destination serial-parallel conversion ICs 611 to 619 are added) to form the effect control command. Alternatively, transmission control is performed by adding header data, mark bits, and end bits to (EXT data). The effect control command is converted into serial data by the serial output circuit 78 and transmitted to the effect control board 80 via the relay board 77.

  Further, the CPU 56 performs information output processing for outputting data such as jackpot information, starting information, probability variation information supplied to the hall management computer, for example (step S30).

  Further, the CPU 56 performs prize ball processing for setting the number of prize balls based on detection signals from the first start port switch 13a, the second start port switch 14a, the count switch 23, and the winning port switches 29a, 30a, 33a, 39a. Execute (Step S31). Specifically, the payout control is performed in accordance with winning detection based on any one of the first starting port switch 13a, the second starting port switch 14a, the count switch 23, and the winning port switches 29a, 30a, 33a, 39a being turned on. A payout control command (award ball number signal) indicating the number of winning balls is output to a payout control microcomputer mounted on the substrate 37. The payout control microcomputer drives the ball payout device 97 in accordance with a payout control command indicating the number of winning balls. In the prize ball process, a process for determining whether or not a prize ball error has occurred is also performed. For example, when there is a discrepancy between the set value of the number of prize balls and the actual number of payouts, the CPU 56 determines that a prize ball error has occurred, and causes the effect control microcomputer 100 mounted on the effect control board 80 to Control is performed to transmit a prize ball error notification designation command designating notification of occurrence of a prize ball error.

  Further, the CPU 56 executes an error detection process based on the detection signal from the full switch, the ball break switch, and the door opening sensor 155 (step S32). Specifically, a full tank error notification designation command for designating notification to the effect control microcomputer 100 mounted on the effect control board 80 that a full tank error has occurred in response to the detection signal of the full tank switch. Send. In addition, in response to a detection signal from the ball-out switch, a ball-out error notification designation command for designating notification to the effect control microcomputer 100 mounted on the effect control board 80 that a ball-out error has occurred. Send. In response to the detection signal of the door opening sensor 155, a door opening error notification designation command for designating that the door opening error has occurred is transmitted to the effect control microcomputer 100 mounted on the effect control board 80. To do.

  In this embodiment, a RAM area (output port buffer) corresponding to the output state of the output port is provided. However, the CPU 56 relates to on / off of the solenoid in the RAM area corresponding to the output state of the output port. The contents are output to the output port (step S33: output process).

  Further, the CPU 56 performs special symbol display control processing for setting special symbol display control data for effect display of the special symbol in the output buffer for setting the special symbol display control data according to the value of the special symbol process flag ( Step S34). For example, if the variation speed is 1 frame / 0.2 seconds until the end flag is set when the start flag set in the special symbol process is set, the CPU 56, for example, every 0.2 seconds passes. Then, the value of the display control data set in the output buffer is incremented by one. Further, the CPU 56 performs variable display of the special symbol on the special symbol display 8 by outputting a drive signal in step S22 according to the display control data set in the output buffer.

  Further, the CPU 56 performs a normal symbol display control process for setting normal symbol display control data for effect display of the normal symbol in an output buffer for setting the normal symbol display control data according to the value of the normal symbol process flag ( Step S35). For example, when the start flag for normal symbol fluctuation is set, the CPU 56 switches the display state (“◯” and “×”) for the normal symbol fluctuation speed every 0.2 seconds until the end flag is set. With such a speed, the value of the display control data set in the output buffer (for example, 1 indicating “◯” and 0 indicating “x”) is switched every 0.2 seconds. In addition, the CPU 56 executes a normal symbol effect display on the normal symbol display 10 by outputting a drive signal in step S22 in accordance with the display control data set in the output buffer.

  Thereafter, the interrupt permission state is set (step S36), and the process ends.

  With the above control, in this embodiment, the game control process is started every 2 ms. The game control process corresponds to the processes in steps S21 to S35 (excluding step S30) in the timer interrupt process. In this embodiment, the game control process is executed by the timer interrupt process. However, in the timer interrupt process, for example, only a flag indicating that an interrupt has occurred is set, and the game control process is performed by the main process. May be executed.

  FIG. 22 is an explanatory diagram of a jackpot determination table. The jackpot determination table is a table in which a jackpot determination value to be compared with the random R is set. The jackpot determination determination table includes a normal jackpot determination table (see FIG. 22A) used in a normal state (a gaming state that is not a probability change state) and a probability change jackpot determination table (FIG. 22B) used in a probability change state. See). The numerical values described in the left column of FIGS. 22A and 22B are jackpot determination values. When the value of the random R matches any one of the jackpot determination values, the CPU 56 determines that the jackpot is to be made. The CPU 56 extracts the count value of the random number circuit at a predetermined time and uses the extracted value as the jackpot determination random value. If the jackpot determination random value matches the jackpot determination value shown in FIG. Is determined to be a big hit (probable big hit or normal big hit).

  The probability variation jackpot is a jackpot that shifts the gaming state after the jackpot game to a probability variation state in which there is a high probability of being determined to be a jackpot compared to the normal state. The normal big hit is a big hit that shifts the gaming state after the big hit game to a state that is not a probable change state. Note that the number of rounds in the case of a probable big hit and the normal big hit is larger than that in the case of a small hit and a sudden probable big hit, for example, 15 rounds.

  The small hit is a big hit in which the number of times of opening of the big winning opening is allowed up to two in the big hit gaming state. When the small hit game ends, the game state does not shift to the probability change state. Suddenly probable jackpot is a jackpot where the number of times the big prize opening is allowed is 2 in the big hit gaming state, but the opening time of the big prize opening is extremely short, and the gaming state after the big hit game is shifted to the probable state It ’s a big hit. That is, in this embodiment, the number of rounds is the same between the sudden probability big hit and the small hit.

  In addition, in the big hit game of sudden probability change big hit, the number of rounds is smaller than that in the case of normal big hit and probability variable big hit, and the allowance opening allowance time of each round (for example, 29 seconds in the case of normal big hit and probability variable big hit) On the other hand, 0.5 seconds) is shorter than the case of the normal big hit and the probability variation big hit, but only the number of rounds may be reduced, or only the allowance opening allowance time may be shortened.

  FIG. 23 is an explanatory diagram showing an example of a variation pattern used in this embodiment. As will be described later, in this embodiment, the presentation control command has a 2-byte structure, the first byte represents MODE (command classification), and the second byte represents EXT (command type). In FIG. 23, “EXT” indicates EXT data of the second byte in the effect control command having a two-byte structure. “Variation time” indicates the variation time of the special symbol (variable display period of identification information).

  “Normal fluctuation” is a fluctuation pattern without a reach mode. “Normal fluctuation / shortening” is a fluctuation pattern that does not involve a reach mode and has a fluctuation time shorter than “normal fluctuation”. “Normal reach” is a variation pattern that is accompanied by a reach mode, but the display result (stop symbol) does not become a big hit symbol. “Reach A” is a variation pattern having a reach form different from “normal reach”. When the reach mode is different, a change mode (speed, rotation direction, etc.), a character image, or the like of a different mode appears in the variable display device 9 during the reach change time (a period during which the reach effect is performed), or the variable display device 9 The background design is different. For example, in “normal reach”, a reach mode is realized by only one type of change mode, whereas in “reach A”, a reach mode including a plurality of change modes having different speeds and directions of change is realized. Further, “reach A / shortening” is a variation pattern having a reach manner similar to “reach A”, but reach variation time is shorter than “reach A”. “Reach A / Extension” is a variation pattern having a reach manner similar to “Reach A”, but the reach variation time is longer than “Reach A”.

  “Reach B” is a fluctuation pattern having a reach mode different from “Normal reach” and “Reach A”. Further, “reach B / shortening” is a variation pattern having a reach manner similar to “reach B”, but the reach variation time is shorter than “reach B”. “Reach B / extension” is a variation pattern having a reach manner similar to “reach B”, but reach variation time is longer than “reach B”. “Reach C” is a variation pattern having a reach form different from “normal reach”, “reach A”, and “reach B”. “Reach C / shortening” is a variation pattern having a reach manner similar to “reach C”, but reach variation time is shorter than “reach C”.

  “Super reach A” is a variation pattern having a reach mode different from “normal reach”, “reach A”, “reach B”, and “reach C”. is there. “Super reach B” is a variation pattern having a reach form different from “normal reach”, “reach A”, “reach B”, “reach C” and “super reach A”. This is a variation pattern. “Reach A / Accuracy” is a variation pattern having a reach form different from “Normal reach”, “Reach A”, “Reach B”, “Reach C”, “Super reach A” and “Super reach B”. It should be noted that the reach form of “reach A / accuracy” is a reach form similar to “reach A”.

  In this embodiment, in the case of a big hit, the game control microcomputer 560 is “reach A / shortening”, “reach A”, “reach B / shortening”, “reach B”, “reach C / shortening”. ", Reach C", "Super Reach A" or "Super Reach B". Further, in the case of a probable big hit, the game control microcomputer 560 is “reach A / extension”, “reach B / extension”, “reach C / shortening”, “reach C”, “super reach A” or “ Select "Super Reach B". In case of sudden big odds, select “Reach A / Random”.

  Further, as shown in FIG. 23, the fluctuation pattern selected only in the case of the normal big hit, the fluctuation pattern selected only in the case of the probability big hit, and the normal big hit and the probability variable big hit can be selected. There are fluctuation patterns.

  In the short-time state, the fluctuation patterns of “normal fluctuation / shortening”, “reach A / shortening”, “reach B / shortening”, and “reach C / shortening” are selected. In the non-time-short state, other variation patterns are selected. However, the variation pattern of “reach A / accuracy” is used in both the short-time state and the non-short-time state.

  In this embodiment, when a big hit occurs and the big hit game ends, the gaming state becomes a short-time state thereafter until the execution of 100 special symbol changes (variable display) is completed. In addition, when variable display of a special symbol is started when variable display is finished, when it is decided to change to a probable change state when the special symbol variable display is started, the game state is changed into a probable change state when the big hit game is ended. To be migrated. If the gaming state at that time is a probability variation state, the probability variation state is continued.

  After the transition to the probability changing state, the state of the probability changing state is short and the state is short until the execution of the variation (variable display) of 100 special symbols is completed. In addition, in the non-probability change state after the big hit game is over, the game state is changed to the normal state (the game state that is not the probability change state and not the short-time state) when the execution of 100 special symbol changes (variable display) is completed. Transition.

  Next, a method for sending a control command from the game control microcomputer 560 to the effect control microcomputer 100 will be described. In this embodiment, the effect control command is converted from parallel data to serial data by the serial output circuit 78 and transmitted from the main board 31 to the effect control board 80 via the relay board 77.

  In this embodiment, the effect control command has a 2-byte structure, the first byte represents MODE (command classification), and the second byte represents EXT (command type). The first bit (bit 7) of the MODE data is always set to “1”, and the first bit (bit 7) of the EXT data is always set to “0”. Note that such a command form is an example, and other command forms may be used. For example, a control command composed of 1 byte or 3 bytes or more may be used.

  FIG. 24 is an explanatory diagram showing an example of the format of the effect control command transmitted by the serial signal method. As shown in FIG. 24, when transmitting the effect control command, the game control microcomputer 560 (specifically, the CPU 56) first adds header data and mark bits to MODE data (MODE data to which an address is added), Transmission control is performed by adding an end bit. Then, the serial output circuit 78 converts the MODE data to which the header data, the address, the mark bit, and the end bit are added into serial data, and transmits the serial data to the effect control board 80 via the relay board 77. Next, the game control microcomputer 560 performs transmission control by adding header data, mark bits, and end bits to EXT data (EXT data with an address added). Then, the serial output circuit 78 converts the EXT data to which the header data, the address, the mark bit, and the end bit are added into serial data, and transmits the serial data to the effect control board 80 via the relay board 77.

  FIG. 25 is an explanatory diagram showing an example of the contents of the effect control command transmitted by the game control microcomputer 560. In the example shown in FIG. 25, commands 8001 (H) to 800E (H) are effect control commands (variation) for designating a variation pattern of decorative symbols that are variably displayed on the variable display device 9 in response to variable display of special symbols. Pattern command). The effect control command for designating the variation pattern is also a command for designating the variation start. Therefore, when the production control microcomputer 100 receives any of the commands 8001 (H) to 800E (H), the variable display device 9 controls the variable display device 9 to start variable display of decorative symbols. In this embodiment, since the variable display of the special symbol and the variable display of the decorative symbol are synchronized (the variable display start time and the variable display end time are the same), the decorative pattern variation pattern (variation time) Determining also means determining the variation pattern (variation time) of the special symbol.

  The commands 8C01 (H) to 8C05 (H) are effect control commands indicating whether or not to make a big hit and the type of the big hit game. The effect control microcomputer 100 determines the display result of the decorative symbols in response to the reception of the commands 8C01 (H) to 8C05 (H). Therefore, the commands 8C01 (H) to 8C05 (H) are referred to as display result specifying commands.

  Command 8F00 (H) is an effect control command (symbol confirmation designation command) indicating that the variable display (fluctuation) of the decorative symbols is terminated and the display result (stop symbol) is derived and displayed. When receiving the symbol confirmation designation command, the effect control microcomputer 100 ends the variable display (fluctuation) of the decorative symbols and derives and displays the display result. The derived display is to finally stop and display the symbol.

  Command 9000 (H) is an effect control command (initialization designation command: power-on designation command) transmitted when power supply to the gaming machine is started. Command 9200 (H) is an effect control command (power failure recovery designation command) transmitted when power supply to the gaming machine is resumed. When the power supply to the gaming machine is started, the gaming control microcomputer 560 transmits a power failure recovery designation command if data is stored in the backup RAM, and if not, initialization designation is performed. Send a command.

  Command 9F00 (H) is an effect control command (customer waiting demonstration designation command) for designating a customer waiting demonstration. The command 9F55 (H) is an effect control command (random number circuit error designation) for designating notification of a random number circuit error of the main board 31 when the occurrence of an abnormality in the random number circuit is detected in the random number circuit check process in the main process. Command).

  The commands A001 to A004 (H) are effect control commands for displaying the fanfare screen, that is, designating the start of the big hit game (big hit start designation command: fanfare designation command). The jackpot start designation commands include jackpot start 1 designation to jackpot start designation 4 designation commands depending on the type of jackpot. The command A1XX (H) is an effect control command (special command during opening of a big winning opening) indicating a display during the opening of the big winning opening for the number of times (round) indicated by XX. A2XX (H) is an effect control command (designation command after opening the big winning opening) indicating the closing of the big winning opening for the number of times (round) indicated by XX.

  Command A301 (H) displays a jackpot end screen, that is, specifies the end of the jackpot game, and also designates an effect control command (special jackpot end 1 designation command: ending) that specifies that the jackpot has been a non-probable variation jackpot (usually a jackpot) 1 designation command). The command A302 (H) is an effect control command for displaying the jackpot end screen, that is, the end of the jackpot game and specifying that it is a promising big hit (a jackpot end 2 designation command: an ending 2 designation command). is there.

  Command D001 (H) is an effect control command (abnormal winning notification designation command) for instructing notification of abnormal winning.

  The command FF02 (H) notifies that a full tank error has occurred when the lower pan (the surplus ball receiving tray 4) is full (that is, when the full tank switch is turned on). This is an effect control command to be designated (full error notification designation command). The command FF01 (H) is an effect control command for designating cancellation of the full-tan error notification when the full-plate state of the lower pan is released (that is, when the full-tan switch is turned off). (Full tank error release specification command).

  The command FF04 (H) designates that when the game frame 11 is in an open state (that is, when a detection signal from the door open sensor 155 is detected), notification that a door open error has occurred is notified. This is a command (door opening error notification designation command). The command FF03 (H) is an effect control command (door opening error release specifying command) that specifies that the notification of the door opening error is released when the open state of the game frame 11 is released.

  Command FF06 (H) is an effect control command (out of ball) that specifies that a ball out error has occurred when the ball is out of state (that is, when the ball out switch is turned on). Error notification designation command). The command FF05 (H) is an effect control command (ball-out error cancel designation command) that designates cancellation of the ball-out error notification when the ball-out state is released.

  The command FF08 (H) is an effect control command (prize ball error notification designation command) for designating notification that a prize ball error has occurred when a prize ball error has occurred. The command FF07 (H) is an effect control command (prize ball error cancel designation command) that designates canceling the notification of the prize ball error when the prize ball error is canceled.

  The effect control microcomputer 100 (specifically, the effect control CPU 101) mounted on the effect control board 80 receives the above-described effect control command from the game control microcomputer 560 mounted on the main board 31. Then, the display state of the variable display device 9 is changed according to the contents shown in FIG. 25, the display state of the lamp is changed, and the sound number data is output to the audio output board 70.

  FIG. 26 is an explanatory diagram illustrating an example of the transmission timing of the effect control command. As shown in FIG. 26, the game control microcomputer 560 transmits a change pattern command and a display result specifying command at the start of change. When the variable display time has elapsed, a symbol confirmation designation command is transmitted.

  Before transmitting the variation pattern command, a background designation command for designating a background image in the variable display device 9 according to the gaming state (for example, normal state / short time state / probability variation state) may be transmitted. Further, an effect control command indicating the number of reserved memories may be transmitted following the display result specifying command.

  FIG. 27 and FIG. 28 are flowcharts showing an example of a program of special symbol process (step S27) executed by the game control microcomputer 560 (specifically, the CPU 56) mounted on the main board 31. As described above, in the special symbol process, a process for controlling the special symbol display 8 and the special winning opening is executed. In the special symbol process, if the first start port switch 13a or the second start port switch 14a for detecting that a game ball has won the start winning port 13 is turned on, that is, a start winning is generated. If so, start port switch passage processing is executed (steps S311 and S312). Then, any one of steps S300 to S310 is performed.

  The processes in steps S300 to S310 are as follows.

  Special symbol normal processing (step S300): executed when the value of the special symbol process flag is zero. When the game control microcomputer 560 enters a state where variable display of special symbols can be started, the game control microcomputer 560 confirms the number of reserved memories (the number of start winning memories). The reserved memory number can be confirmed by the count value of the reserved memory number counter. If the number of reserved memories is not 0, it is determined whether or not to win. Then, the internal state (special symbol process flag) is updated to a value (1 in this example) corresponding to step S301.

  Fluctuation pattern setting process (step S301): This process is executed when the value of the special symbol process flag is 1. The stop symbol after the variable display of the special symbol is determined. Also, the variation pattern is determined, and the variation time in the variation pattern (variable display time: the time from the start of variable display until the display result is derived and displayed (stop display)) Decide to do. Also, a variable time timer for measuring the special symbol variable time is started. Then, the internal state (special symbol process flag) is updated to a value (2 in this example) corresponding to step S302.

  Display result specifying command transmission process (step S302): This process is executed when the value of the special symbol process flag is 2. Control for transmitting a display result specifying command to the production control microcomputer 100 is performed. Then, the internal state (special symbol process flag) is updated to a value (3 in this example) corresponding to step S303.

  Special symbol changing process (step S303): This process is executed when the value of the special symbol process flag is 3. When the variation time of the variation pattern selected in the variation pattern setting process elapses (the variation time timer set in step S301 times out, that is, the variation time timer value becomes 0), the internal state (special symbol process flag) is stepped. Update to a value corresponding to S304 (4 in this example).

  Special symbol stop process (step S304): executed when the value of the special symbol process flag is 4. The variable display on the special symbol display 8 is stopped and the stop symbol is derived and displayed. In addition, control for transmitting a symbol confirmation designation command to the effect control microcomputer 100 is performed. When the big hit flag is set and the small hit flag is not set, the internal state (special symbol process flag) is updated to a value (5 in this example) corresponding to step S305. If the small hit flag is set, the internal state (special symbol process flag) is updated to a value (8 in this example) corresponding to step S308. If the big hit flag is not set, the internal state (special symbol process flag) is updated to a value corresponding to step S300 (0 in this example). The effect control microcomputer 100 controls the variable display device 9 to stop the decorative symbols when it receives the symbol confirmation designation command transmitted by the game control microcomputer 560.

  Preliminary winning opening process (step S305): This process is executed when the value of the special symbol process flag is 5. In the pre-opening process for the big prize opening, control for opening the big prize opening is performed. Specifically, a counter (for example, a counter that counts the number of game balls that have entered the big prize opening) is initialized and the solenoid 21 is driven to open the big prize opening. Also, the execution time of the special prize opening opening process is set by the timer, and the internal state (special symbol process flag) is updated to a value corresponding to step S306 (6 in this example). Note that the pre-opening process for the big prize opening is executed every round, but when the first round is started, the pre-opening process for the big winning opening is also a process for starting the big hit game.

  Large winning opening opening process (step S306): This process is executed when the value of the special symbol process flag is 6. A control for transmitting an effect control command for round display during the big hit gaming state to the effect control microcomputer 100, a process for confirming the completion of the closing condition of the big prize opening, and the like are performed. If the closing condition for the big prize opening is satisfied and there are still remaining rounds, the internal state (special symbol process flag) is updated to a value corresponding to step S305 (5 in this example). When all the rounds are completed, the internal state (special symbol process flag) is updated to a value corresponding to step S307 (7 in this example).

  Big hit end process (step S307): executed when the value of the special symbol process flag is 7. Control for causing the microcomputer 100 for effect control to perform display control for notifying the player that the big hit gaming state has ended is performed. Further, a process for setting a flag (for example, a probability variation flag) indicating a gaming state is performed. Then, the internal state (special symbol process flag) is updated to a value (0 in this example) corresponding to step S300.

  Small hit release pre-processing (step S308): This process is executed when the value of the special symbol process flag is 8. In the pre-opening process for small hits, control is performed to open the big prize opening. Specifically, a counter (for example, a counter that counts the number of game balls that have entered the big prize opening) is initialized and the solenoid 21 is driven to open the big prize opening. Also, the execution time of the special prize opening opening process is set by the timer, and the internal state (special symbol process flag) is updated to a value corresponding to step S309 (9 in this example). It should be noted that although the pre-opening process for small hits is executed for each round, the pre-opening process for small hits is also a process for starting a small hit game when starting the first round.

  Small hit release processing (step S309): executed when the value of the special symbol process flag is 9. A control for transmitting an effect control command for a round display during the small hit gaming state to the effect control microcomputer 100, a process for confirming that the closing condition for the big prize opening is satisfied, and the like are performed. If the closing condition for the special prize opening is satisfied and there are still remaining rounds, the internal state (special symbol process flag) is updated to a value corresponding to step S308 (8 in this example). When all the rounds are completed, the internal state (special symbol process flag) is updated to a value corresponding to step S310 (in this example, 10 (decimal number)).

  Small hit end processing (step S310): executed when the value of the special symbol process flag is 10. Control is performed to cause the microcomputer 100 for effect control to perform display control for notifying the player that the small hit gaming state has ended. Then, the internal state (special symbol process flag) is updated to a value (0 in this example) corresponding to step S300.

  FIG. 29 is a flowchart showing the start port switch passing process in step S312. In the start port switch passing process, the CPU 56 checks whether or not the reserved storage number is 4 which is the upper limit value (step S211). If the number of reserved memories is 4, the process is terminated.

  If the number of reserved memories is not 4, the value of the reserved memory number counter indicating the number of reserved memories is incremented by 1 (step S212). Further, the CPU 56 extracts software random numbers (counter value for generating a big hit symbol determination random number, etc.) and random R (big hit determination random number), and uses them as an extracted random number value of the reserved memory number counter. A process of storing in the storage area in the storage buffer corresponding to the value is executed (step S213). In step S213, the CPU 56 extracts random values 1 to 3 (see FIG. 21) as software random numbers, and extracts the random R by reading the count value of the random number circuit. In the reserved storage buffer, the same number of storage areas as the upper limit value of the number of reserved memories is secured. Further, a counter for generating a jackpot symbol determination random number and the like and a reserved storage buffer are formed in the RAM 55. “Formed in RAM” means an area in the RAM.

  30 and 31 are flowcharts showing the special symbol normal process (step S300) in the special symbol process. In the special symbol normal process, the CPU 56 checks the value of the number of reserved storage (step S51). Specifically, the count value of the pending storage number counter is confirmed. If the number of reserved memories is 0, the process is terminated.

  If the reserved memory number is not 0, the CPU 56 reads out each random number value stored in the storage area corresponding to the reserved memory number = 1 in the reserved memory number buffer of the RAM 55 and stores it in the random number buffer area of the RAM 55 (step S52). Then, the value of the reserved memory number is decreased by 1 (the count value of the reserved memory number counter is decremented by 1), and the contents of each storage area are shifted (step S53). That is, each random number value stored in the storage area corresponding to the reserved storage number = n (n = 2, 3, 4) in the reserved storage number buffer of the RAM 55 is stored in the storage area corresponding to the reserved storage number = n−1. To store. Therefore, the order in which the random number values stored in the respective storage areas corresponding to the number of reserved memories is extracted always matches the order of the number of reserved memories = 1, 2, 3 and 4. Yes.

  Then, the CPU 56 reads a random R (a jackpot determination random number) from the random number buffer area (step S61), and executes a jackpot determination module (step S62). The big hit judgment module compares the big hit judgment value (see Fig. 22) determined in advance with the big hit judgment random number, and if they match, the big hit (normal big hit, probability variation big hit or sudden probability variation big hit) or small hit This is a program for executing the process to be determined.

  Note that, when the gaming state is in the probability variation state, the CPU 56 uses the jackpot determination value in the table in which the jackpot determination value as shown in FIG. 22B is set, and the gaming state is in the normal state (non-probability variation state). Is, the jackpot determination value in the table in which the jackpot determination value as shown in FIG. 22 (A) is set is used. If it is determined to be a big hit (step S63), the process proceeds to step S81. Note that deciding whether or not to make a big hit means deciding whether or not to shift to the big win gaming state, but deciding whether or not to make the stop symbol in the special symbol display 8 a big hit symbol. It is also a thing.

  If it is decided not to win, the CPU 56 reads out the design symbol random number from the random number buffer area (step S64), and determines the stop symbol based on the design symbol random number (step S65). In this case, an off symbol (for example, any of even symbols) is determined.

  Further, when the time reduction flag indicating the time reduction state is set (step S66), the value of the time reduction counter indicating the number of times the special symbol can be changed in the time reduction state is decremented by 1 (step S67). When the value of the time reduction counter becomes 0, a time reduction end flag is set in order to shift the gaming state to the non-time reduction state when the variable display ends (steps S68 and S69). Then, the process proceeds to step S90.

  In step S81, the CPU 56 sets a big hit flag. Then, the big hit symbol determining random number is read from the random number buffer area (step S82), and the big hit symbol (for example, one of the odd symbols) as the stop symbol is determined based on the big hit symbol determining random number (step S83). Here, the stop symbol is determined without distinguishing between the probable big hit and the normal big hit.

  Next, the CPU 56 sets a probability variation jackpot flag if it is determined to be a probability variation jackpot (steps S84 and S85). If it is determined that the sudden probability change big hit is suddenly set, the sudden probability change big hit flag is set (steps S86 and S87). If it is determined to be a small hit, a small hit flag is set (steps S88 and S89). Then, the value of the special symbol process flag is updated to a value corresponding to the variation pattern setting process (step S301) (step S90). When the probability variation big hit flag or the sudden probability variation big hit flag is set, the gaming state is shifted to the probability changing state when the big hit game is finished.

  In this embodiment, whether or not to make a big hit and the type of jackpot are determined based on the big hit determination random number (see FIG. 22), but the big hit is determined based on the big hit determination random number. When a predetermined jackpot symbol (predetermined probability variation jackpot symbol or sudden probability variation jackpot symbol) is determined based on the random number for determining the jackpot symbol when it is determined to be a jackpot You may make it control to a probability change state.

  FIG. 32 is a flowchart showing the variation pattern setting process (step S301) in the special symbol process. In the variation pattern setting process, the CPU 56 reads the variation pattern determination random number from the random number buffer area (step S100). Then, the variation pattern is determined based on the variation pattern determination random number (step S101).

  Here, when the gaming state is the non-time saving state and it is determined to be out of play, “normal variation” or “normal reach” is selected (see FIG. 23). If the gaming state is a non-time-saving state and it is determined to be a big hit, “reach A”, “reach A / extension”, “reach B”, “reach B / extension”, “reach C” ”,“ Super Reach A ”,“ Super Reach B ”or“ Reach A · Accuracy ”(see FIG. 23) When it is determined to be a promising big hit out of the big hits, “reach A / extension”, “reach B / extension”, “reach C”, “super reach A” or “super reach B” is selected. In addition, when it is determined that the sudden probability change is a big hit, “reach A / accuracy” is selected. If it is determined to be a big hit (including the case where it is determined to be a small hit) among the big hits (including the case where it is determined to be a small hit), “ Select Reach A, Reach B, Reach C, or Super Reach A.

  When the game state is the short time state and it is determined to be out of play, “normal variation / shortening” is selected (see FIG. 23). If the gaming state is a short-time state and it has been decided to win the game, select “Reach A / Shorten”, “Reach B / Short”, “Reach C / Short” or “Reach A / Success” Select (see FIG. 23). When it is determined to be a promising big hit out of the big hits, “reach C / shortening” is selected. When it is decided to suddenly change the probability big hit, select “reach A / accuracy”. When it is determined that the big hit is usually a big hit (including the case where it is decided to be a small hit), “reach A / shortening”, “reach B / shortening” or “reach C”・ Select “Short”.

  In order to facilitate the selection as described above, a variation pattern table is used according to the game state (whether or not it is a short-time state) and the determination result of whether or not to make a big hit (rejected and big hit types, respectively) . The variation pattern table is stored in the ROM 54, but is prepared according to the gaming state and the determination result as to whether or not to win. In each variation pattern table, data indicating a variation pattern that can be selected and a numerical value corresponding to the data are set. Then, the CPU 56 selects a variation pattern table according to the gaming state and the determination result as to whether or not to win, and corresponds to a numerical value that matches the value of the variation pattern determination random number in the selected variation pattern table. Select a variation pattern. Therefore, the game control microcomputer 560 selects the variation pattern depending on whether or not the jackpot has already been determined and whether or not the probability variation jackpot is set.

  Then, the CPU 56 performs control to transmit a variation pattern command (see FIG. 23) corresponding to the variation pattern selected in step S101 to the effect control microcomputer 100 (step S103). Specifically, when the CPU 56 transmits an effect control command to the effect control microcomputer 100, the address of the command transmission table (preliminarily set for each command in the ROM) corresponding to the effect control command is used as a pointer. set. And the address of the command transmission table according to an effect control command is set to a pointer, and an effect control command is transmitted in an effect control command control process (step S29).

  Moreover, the variation of the special symbol is started (step S104). For example, a start flag referred to in the special symbol display control process in step S34 is set. Further, a value corresponding to the variation time (see FIG. 23) corresponding to the selected variation pattern is set in the variation time timer formed in the RAM 55 (step S105). Then, the value of the special symbol process flag is updated to a value corresponding to the display result specifying command transmission process (step S302) (step S106).

  FIG. 33 is a flowchart showing the display result specifying command transmission process (step S302). In the display result specifying command transmission processing, the CPU 56 performs any one of the display control 1 designation to the display result 5 designation according to the determined big hit type (including the small win) (see FIG. 25). Control to send. Specifically, the CPU 56 first checks whether or not the big hit flag (which is also set when the small hit is determined) is set (step S110). If not set, control is performed to transmit a display result 1 designation command (step S111). When the big hit flag is set, when the probability variation big hit flag is set, control is performed to transmit the display result 4 designation command (steps S112 and S113). When the sudden probability big hit flag is set, control for transmitting a display result 5 designation command is performed (steps S114 and S115). When the small hit flag is set, control for transmitting a display result 3 designation command is performed (steps S116 and S117). When none of the probability variation big hit flag, sudden probability variation big hit flag, and small hit flag is set, control is performed to transmit a display result 2 designation command (step S118). Then, the value of the special symbol process flag is updated to a value corresponding to the special symbol changing process (step S303) (step S119).

  FIG. 34 is a flowchart showing the special symbol changing process (step S303) in the special symbol process. In the special symbol changing process, the CPU 56 subtracts 1 from the variable time timer (step S121), and when the variable time timer times out (step S122), the value of the special symbol process flag corresponds to the special symbol stop process (step S304). The updated value is updated (step S123). If the variable time timer has not timed out, the process ends.

  FIG. 35 is a flowchart showing the special symbol stop process (step S304) in the special symbol process. In the special symbol stop process, the CPU 56 sets an end flag referred to in the special symbol display control process in step S34 to end the variation of the special symbol, and performs control for deriving and displaying the stop symbol on the special symbol display 8. (Step S131). Moreover, control which transmits the symbol determination designation | designated command to the microcomputer 100 for production control is performed (step S132). When the big hit flag is not set, the process proceeds to step S146 (step S133).

  When the jackpot flag is set, the CPU 56 performs control to transmit a jackpot start designation command (step S135). Specifically, when the probability variation big hit flag is set, a big hit start 3 designation command is transmitted, and when the probability variation big hit flag is suddenly set, a big hit start 4 designation command is transmitted. If it is set, a jackpot start 2 designation command is transmitted. Otherwise, a jackpot start 1 designation command is transmitted.

  Further, a value corresponding to the big hit display time (time for notifying the occurrence of the big hit in the variable display device 9, for example) is set in the big hit display time timer (step S136). If the small hit flag is set, the value of the special symbol process flag is updated to a value corresponding to the small hit release pre-processing (step S308) (steps S137 and S138). If the small hit flag is not set, the value of the special symbol process flag is updated to a value corresponding to the pre-opening process for the big prize opening (step S305) (step S139). The case where the small hit flag is not set is a case where the normal big hit, the probability variation big hit or the sudden probability variation big hit is determined.

  In step S146, the CPU 56 checks whether or not the time reduction end flag is set. If the time saving end flag is not set, the process proceeds to step S149. If the time reduction end flag is set, the time reduction end flag is reset (step S147), and the time reduction flag indicating that the gaming state is the time reduction state is reset (step S148). Then, the value of the special symbol process flag is updated to a value corresponding to the special symbol normal process (step S300) (step S149).

  The time reduction end flag is set in step S69 in the special symbol normal process. In addition, the gaming state shifts to a non-time saving state by resetting the time saving flag. At this stage, if the gaming state is a probability variation state, the gaming state becomes a probability variation state of a non-short-time state. On the other hand, if it is in the non-probable change state, it shifts to a normal state (a state that is not in the probabilistic change state and is not in the time-short state).

  In the big winning opening opening pre-processing, when the big hit display time timer is set, the CPU 56 controls to open the big winning opening when the big hit display time timer times out, and sets the big winning opening opening time timer. Set a value corresponding to the opening time (for example, 29 seconds for normal big hits and probable big hits, and 0.5 seconds for sudden big odds), and the special symbol process flag value is processed while the big prize opening is open The value is updated to a value corresponding to (Step S306). The case where the big hit display time timer is set is the case before the start of the first round. When the interval timer (timer for determining the interval time between rounds) is set, when the interval timer times out, control is performed to open the big prize opening and the opening time ( For example, a value corresponding to 29 seconds is set for a normal big hit and a probable big hit, and a value corresponding to 0.5 seconds is set for a sudden probable big hit, and the value of the special symbol process flag is set to a process for opening a big winning opening (step S306 ) To a value corresponding to.

  In the process during opening of the big prize opening, the CPU 56 does not finish the final round when the big prize opening time timer times out or the number of winning balls to the big prize opening reaches a predetermined number (for example, 10). In this case, control for closing the special winning opening is performed, a value corresponding to the interval time is set in the interval timer, and the value of the special symbol process flag is set to a value corresponding to the pre-opening process for the special winning opening (step S305). Update. When the final round is completed, the value of the special symbol process flag is updated to a value corresponding to the jackpot end process (step S307).

  FIG. 36 is a flowchart showing the jackpot end process (step S307) in the special symbol process. In the jackpot end process, the CPU 56 checks whether or not the jackpot end display timer is set (step S150). If the jackpot end display timer is set, the process proceeds to step S154. If the jackpot end display timer is not set, the jackpot flag is reset (step S151), and control for transmitting a jackpot end designation command is performed (step S152). Here, if the probability variation jackpot flag or the sudden probability variation bonus flag is set, a jackpot end 2 designation command is transmitted, and if the probability variation jackpot flag or the sudden probability variation bonus flag is not set, the jackpot end 1 designation is specified. Send a command. Then, a value corresponding to the display time corresponding to the time during which the jackpot end display is performed on the variable display device 9 (the jackpot end display time) is set in the jackpot end display timer (step S153), and the processing is ended.

  In step S154, 1 is subtracted from the value of the big hit end display timer. Then, the CPU 56 checks whether or not the value of the jackpot end display timer is 0, that is, whether or not the jackpot end display time has elapsed (step S155). If not, the process ends. If it has elapsed, the time reduction flag is set to shift the gaming state to the time reduction state (step S156), and 100 is set in the time reduction counter (step S157).

  Then, it is confirmed whether or not the probability variation big hit flag or the sudden probability variation big flag is set (step S158). If the probability variation big hit flag or sudden probability variation big win flag is set, the set flag (probability big hit flag or sudden probability variation big flag) is reset (step S159), the probability variation flag is set and the gaming state is set. The state is changed to a certain change state (step S161). If the gaming state at that time is a probability variation state, the probability variation flag has already been set. Then, the value of the special symbol process flag is updated to a value corresponding to the special symbol normal process (step S300) (step S162).

  In the pre-opening process for small hits in step S308, the same process as the pre-opening process for the big prize opening (step S305) is performed. However, instead of updating the value of the special symbol process flag to a value corresponding to the large winning opening opening process, the special symbol process flag is updated to a value corresponding to the small hit opening process. Further, in the small hit opening process in step S309, the same process as the big prize opening opening process (step S306) is performed. However, if it is not the final round, the value of the special symbol process flag is updated to a value corresponding to the small hit release pre-processing (step S308). If it is the final round (second round), the value of the special symbol process flag Is updated to a value corresponding to the small hit end processing (step S310).

  FIG. 37 is a flowchart showing the small hit end process (step S310) in the special symbol process. In the small hit end process, the CPU 56 checks whether or not the small hit end display timer is set (step S170). If the small hit end display timer is set, the process proceeds to step S174. When the big hit end display timer is not set, the big hit flag and the small hit flag are reset (steps S171A and S171B), and control for transmitting the big hit end 1 designation command is performed (step S172). Then, the small hit end display timer sets a value corresponding to the display time corresponding to the time during which the small hit end display is performed in the variable display device 9 (small hit end display time) in the small hit end display timer Step S173), the process is terminated.

  In step S174, 1 is subtracted from the value of the small hit end display timer. Then, the CPU 56 checks whether or not the value of the small hit end display timer is 0, that is, whether or not the small hit end display time has elapsed (step S175). If not, the process ends. If it has elapsed, the value of the special symbol process flag is updated to a value corresponding to the special symbol normal process (step S300) (step S176).

  FIG. 38 is a flowchart showing the abnormal winning notification process in step S23. In the abnormal winning notification process, the CPU 56 checks whether or not the abnormal notification prohibition flag is set (step S581). The abnormality notification prohibition flag is set in the main process that is executed when power supply to the gaming machine is started (see step S44 in FIG. 19). When the abnormality notification prohibition flag is not set, the process proceeds to step S585. If the abnormality notification prohibition flag is set, the value of the prohibition period timer set in step S45 is decremented by 1 (step S582). When the value of the prohibition period timer becomes 0, that is, when the prohibition period timer times out, the abnormality notification prohibition flag is reset (steps S583 and S584).

  Next, it is confirmed whether or not the value of the special symbol process flag is 5 or more (step S585). The state where the value of the special symbol process flag is 5 or more is a state where a big hit game or a small hit game is being played. In such a state, there is a possibility that a game ball will win the big winning opening, so it is not confirmed that an abnormal winning has occurred in the big winning opening. That is, if the value of the special symbol process flag is 5 or more, the abnormal winning notification process is terminated.

  If the value of the special symbol process flag is less than 5 (a state where neither big hit game nor small hit game is played), the CPU 56 loads the contents of the switch-on buffer into the register (step S586). Then, the logical product of the content of the loaded switch-on buffer and the count switch input bit determination value (for example, 02 (H)) is calculated (step S587). When the content of the switch-on buffer is 02 (H), that is, when the count switch 23 is on, the logical product operation result is 02 (H). When the count switch 23 is not turned on, the operation result of the logical product is 0 (00 (H)).

  If the result of the logical product is not 0, it is determined that an abnormal winning at the special winning opening has occurred, and control is performed to transmit an abnormal winning notification designation command to the effect control board 80 (steps S588 and S589).

  When the count switch 23 is turned on in a state where neither a big hit game nor a small hit game is performed by the above processing, an abnormal winning notification designation command is transmitted. In addition, the process of steps S581 to S583 prohibits the start of abnormality notification when the effect control microcomputer 100 is performing initialization notification. The production control microcomputer 100 continues to execute the initialization notification until the period corresponding to the prohibition period has elapsed since the start of the initialization notification.

Next, the operation of the effect control means will be described.
FIG. 39 is a flowchart showing main processing executed by the effect control microcomputer 100 (specifically, the effect control CPU 101) mounted on the effect control board 80. The effect control CPU 101 starts executing the main process when the power is turned on. In the main processing, first, initialization processing is performed for clearing the RAM area, setting various initial values, and initializing a timer for determining the activation control activation interval (for example, 1 ms) (step S701). .

  Then, the effect control CPU 101 proceeds to a loop process for monitoring the timer interrupt flag (step S702). When a timer interrupt occurs, the effect control CPU 101 sets a timer interrupt flag in the timer interrupt process. If the timer interrupt flag is set in the main process, the effect control CPU 101 clears the flag (step S703) and executes the effect control process.

  In the effect control process, the effect control CPU 101 first analyzes the received effect control command and executes a process of setting a flag according to the received effect control command (command analysis process: step S704). Next, the effect control CPU 101 executes effect control process processing (step S705). In the effect control process, the process corresponding to the current control state (effect control process flag) is selected from the processes corresponding to the control state, and display control of the variable display device 9 is executed. In addition, a random number update process for updating a counter value of a counter for generating a predetermined random number (for example, a random number for determining a stop symbol) is executed (step S706). Moreover, the notification control process process which performs notification using an effect device such as the variable display device 9 is executed (step S707). Furthermore, the serial input / output process which outputs the data set by the command analysis process, the effect control process process, and the notification control process process to the serial output circuit 353, and reads the data received from the input ICs 620 and 621 from the serial input circuit 354. Is executed (step S708). Thereafter, the process proceeds to step S702.

  FIG. 40 is an explanatory diagram showing a configuration example of a command reception buffer for storing the effect control command received from the game control microcomputer 560 of the main board 31. In this example, a command reception buffer in the form of a ring buffer capable of storing six 2-byte effect control commands is used. Therefore, the command reception buffer is configured by a 12-byte area of reception command buffers 1 to 12. A command reception number counter indicating in which area the received command is stored is used. The command reception number counter takes a value from 0 to 11. The ring buffer format is not necessarily required.

  The effect control command transmitted from the game control microcomputer 560 is received by an interrupt process based on the effect control INT signal, and is stored in a buffer area formed in the RAM. In the command analysis process, it is analyzed which command (see FIG. 25) the effect control command stored in the buffer area is.

  41 to 43 are flowcharts showing specific examples of command analysis processing (step S704). The effect control command received from the main board 31 is stored in the reception command buffer, but in the command analysis process, the effect control CPU 101 confirms the contents of the command stored in the command reception buffer.

  In the command analysis process, the effect control CPU 101 first checks whether or not a reception command is stored in the command reception buffer (step S611). Whether it is stored or not is determined by comparing the value of the command reception number counter with the read pointer. The case where both match is the case where the received command is not stored. When the received command is stored in the command receiving buffer, the effect control CPU 101 reads the received command from the command receiving buffer (step S612). When read, the value of the read pointer is incremented by +2 (step S613). The reason for +2 is that 2 bytes (1 command) are read at a time.

  If the received effect control command is a variation pattern command (step S614), the effect control CPU 101 stores the variation pattern command in a variation pattern command storage area formed in the RAM (step S615). Then, a variation pattern command reception flag is set (step S616).

  If the received effect control command is a display result specifying command (step S617), the effect control CPU 101 stores the display result specifying command in a display result specifying command storage area formed in the RAM (step S618). . Then, a display result specifying command reception flag is set (step S619).

  If the received effect control command is a symbol confirmation designation command (step S621), the effect control CPU 101 sets a confirmed command reception flag (step S622).

  If the received effect control command is one of the jackpot start 1-4 designation commands (step S623), the effect control CPU 101 sets the jackpot start 1-4 designation command reception flag (step S624).

  If the received presentation control command is a power-on designation command (initialization designation command) (step S631), the presentation control CPU 101 displays an initial screen on the variable display device 9 indicating that the initialization process has been executed. Control is performed (step S632A). The initial screen includes an initial display of predetermined production symbols. Also, an initial notification flag is set (step S632B), and a RAM clear flag is set (step S632C).

  If the received effect control command is a power failure recovery designation command (step S633), a predetermined power failure recovery screen (screen for displaying information notifying the player that the gaming state is continuing) is displayed. Display control is performed (step S634), and an initial notification flag is set (step S635).

  If the received effect control command is a jackpot end 1 designation command (step S641), the effect control CPU 101 sets a jackpot end 1 designation command reception flag (step S642). If the received effect control command is a jackpot end 2 designation command (step S643), the effect control CPU 101 sets a jackpot end 2 designation command reception flag (step S644).

  If the received effect control command is an abnormal prize notification designation command (step S645), the effect control CPU 101 sets an abnormal prize notification designation command reception flag (step S646).

  If the received effect control command is a random number circuit error designation command (step S647), the effect control CPU 101 sets a random number circuit error flag (step S648).

  If the received production control command is a full tank error release designation command (step S649), the production control CPU 101 resets the full tank error notification flag set in step S652 described later and sets an error notification release flag ( Step S650).

  If the received production control command is a full tank error notification designation command (step S651), the production control CPU 101 sets a full tank error notification flag (step S652).

  If the received effect control command is a door opening error release designation command (step S653), the effect control CPU 101 resets the door opening error notification flag set in step S656, which will be described later, and sets the error notification cancellation flag. (Step S654).

  If the received effect control command is a door opening error notification designation command (step S655), the effect control CPU 101 sets a door opening error notification flag (step S656).

  If the received effect control command is a ball break error release designation command (step S657), the effect control CPU 101 resets a ball break error notification flag set in step S660 described later and sets an error notification cancel flag. (Step S658).

  If the received effect control command is a ball-out error notification designation command (step S659), the effect control CPU 101 sets a ball-out error notification flag (step S660).

  If the received effect control command is a prize ball error release designation command (step S661), the effect control CPU 101 resets the prize ball error notification flag set in step S664 described later and sets the error notification release flag. (Step S662).

  If the received effect control command is a prize ball error notification designation command (step S663), the effect control CPU 101 sets a prize ball error notification flag (step S664).

  If the received effect control command is another command, the effect control CPU 101 sets a flag corresponding to the received effect control command (step S665). Then, control goes to a step S611.

  Next, lamp control will be described. First, lamp control related to error notification and jackpot game will be described. FIG. 44 is an explanatory diagram illustrating an example of lamp control contents executed in response to process data (including error notification process data) when each production control command is received. As shown in FIG. 44, the effect control CPU 101 receives, for example, a jackpot end 1 designation command and sets the gaming state to the normal state, and the LEDs 125a to 125f of the center decoration lamps on the gaming board 6 and the stage Control is performed so that only the LEDs 126a to 126f of the lamp are lit. Then, while the gaming state is the normal state, an effect is made such that only the LED 125a to 125f of the center decoration lamp and the LEDs 126a to 126f of the stage lamp on the gaming board 6 are lit.

  In addition, for example, when the game control CPU 101 receives a jackpot end 2 designation command and changes the gaming state to a probable change state, the center decoration lamp LEDs 125 a to 125 f and the stage lamp LEDs 126 a to 126 f on the gaming board 6. In addition to the lighting, the LEDs 281a to 281l, 282a to 282f, and 283a to 283f of each lamp (excluding the dish lamp) on the game frame 11 side are controlled to blink at a predetermined time interval (for example, 1 second). While the gaming state is in the probable state, in addition to the lighting of the center decoration lamps 125a to 125f and the stage lamps LEDs 126a to 126f on the gaming board 6, each lamp on the gaming frame 11 side (excluding the dish lamp) The LEDs 281a to 281l, 282a to 282f, and 283a to 283f are flashed at predetermined time intervals (for example, 1 second).

  Further, for example, when the big hit start designation command is received and the big hit is made, the effect control CPU 101 blinks the center decoration lamps 125a to 125f and the stage lamps LEDs 126a to 126f on the game board 6, An effect is made such that the LEDs 281a to 281l, 282a to 282f, and 283a to 283f of each lamp (excluding the dish lamp) on the game frame 11 side are blinked at a time interval (for example, 0.5 seconds) faster than the probability variation state. By performing such an effect, compared to when the gaming state is in the probable state, by flashing more lamps at a faster time interval than in the probable state, compared to when in the promising state when the big hit occurs Can produce a more flashy impression.

  Further, for example, when the CPU 101 for effect control receives an initialization designation command and performs initialization notification and RAM clear notification, the LEDs 281a to 281l of the respective lamps (excluding the dish lamp) on the game frame 11 side. , 282a to 282f and 283a to 283f are performed. In addition, when the CPU 101 for effect control receives, for example, a random number circuit error designation command and notifies the random number circuit error, the LEDs 281a to 281l and 282a to 280a of each lamp (excluding the dish lamp) on the game frame 11 side. An effect is made to light up the lights 282f and 283a to 283f. In addition, for example, when the effect control CPU 101 receives an abnormal winning notification designation command and performs abnormal winning notification, the LEDs 281a to 281l, 282a to 282f of the respective lamps (excluding the dish lamp) on the game frame 11 side are provided. An effect of blinking 283a to 283f is performed. In addition, for example, when the CPU 101 for effect control receives a full tank error notification designation command and performs a full tank error notification, it performs an effect such that the LEDs 82a to 82d constituting the pan lamps blink. For example, when the CPU 101 for effect control receives a door opening error designation command and issues a door opening error notification, the LEDs 281a to 281l and 282a to 282f of the respective lamps (excluding the dish lamp) on the game frame 11 side. , 283a to 283f are flashed. In addition, for example, the effect control CPU 101 receives an out-of-ball error designation command and performs an effect of blinking the LEDs 281a to 281l of the top frame lamps on the game frame 11 side when notifying the out-of-ball error. In addition, for example, when the effect control CPU 101 receives a prize ball error designation command and issues a prize ball error notification, the effect control CPU 101 performs an effect of blinking the LEDs 281a to 281l of the top frame lamps on the game frame 11 side.

  Next, stepwise brightness control of a lamp (specifically, an LED constituting the lamp) will be described. In stepwise brightness control, the brightness state of a lamp is gradually changed from a certain brightness state (for example, all extinguished state), that is, stepwise, to another brightness state (for example, fully lit state (for example, fully lit state). )) Or a stepwise decrease from a certain lightness state (for example, full lighting state) to another lightness state (for example, full light extinction state). In other words, it means that the brightness of the lamp is not immediately set to the target brightness, but is gradually brought closer to the target brightness from the brightness at the start of the control. The lightness between the lightness at the start of control and the target lightness is controlled to an intermediate lightness. Note that the full lighting state means a state in which the lamp is continuously lit during the lamp control period. Further, the all-off state means a state in which the lamp is not lit at all during the lamp control period.

  In this embodiment, the gradual brightness control of the lamp is executed when the decorative pattern is changed, but the gradual brightness control of the lamp is executed when the gaming state is other state. You may do it.

  In this embodiment, brightness 0 to 15 is used as brightness. A lightness of 0 corresponds to the fully turned off state, and a lightness of 15 corresponds to the fully turned on state. FIG. 45 is an explanatory diagram illustrating an example of control for realizing lightness 1 to lightness 15. As shown in FIG. 45, the reference time (unit time for control) of brightness control is 15 ms. When realizing lightness n (n = 1 to 15), the light is turned on (on state) for nms (n milliseconds) in 15 ms, and is turned off for (15-n) ms. For example, when the brightness 1 is realized, the light is turned on for 1 ms in 15 ms and turned off for 14 ms. That is, each brightness is realized by controlling the lighting time (on time) and the light extinguishing time (off time) in a unit time.

  FIG. 46 is an explanatory diagram showing an example of data indicating specific lamp stepwise brightness control over a certain control period. In FIG. 46, (1) to (11) indicate each period in the control period. Data 1 to 8 indicate lamp numbers (specifically, LED numbers). That is, FIG. 46 shows an example in which the brightness of eight LEDs is controlled. Here, although eight LEDs are illustrated, for example, 12 LEDs 281a to 281l as the top frame lamps, 6 LEDs 282a to 282f as the left frame lamps, and 6 LEDs 283a to 280a as the right frame lamps When performing stepwise brightness control for all of 283f, data 1 to 20 are used. For example, when the top frame lamp, the left frame lamp, and the right frame lamp are regarded as one group, and the LEDs in each group are similarly controlled in brightness, data 1 to 3 are used. Further, a value (0, 9 or F in this example) indicated as data indicates the final brightness (target brightness) in each period.

  “ON” of “lightness control” indicates that stepwise lightness control is executed. “Lightness control” OFF indicates that stepwise lightness control is not executed. For example, since it is ON in the period (2), in the period (2), each lamp is gradually targeted from the lightness 15 (hexadecimal F) which is the final lightness in the period (1) which is the immediately preceding period. This indicates that control is performed so as to shift to lightness 0, which is lightness. Further, since it is OFF in the period (3), it indicates that each lamp is immediately controlled to the brightness F regardless of the final brightness in the immediately preceding period. Further, since it is OFF in the period (4), it indicates that each lamp is immediately controlled to lightness 0 regardless of the final lightness in the immediately preceding period.

  FIG. 47 is an explanatory diagram schematically showing changes in lightness during the periods (1) to (11) of the LEDs indicated by data 8 (LEDs with lamp number 8). As shown in FIG. 47, since the brightness control is ON in the periods (1), (2), (5) to (11), the brightness gradually changes during those periods. In the period (5), the target brightness is 0, and the final brightness in the immediately preceding period (period (4)) is also 0, so the brightness does not change. In the example shown in FIG. 46, the LEDs indicated by the data 1, 3, 5, and 7 are controlled so as to change in brightness stepwise from lightness 0 to lightness 9 in the period (5).

  FIG. 48A is an explanatory diagram showing in more detail the change in brightness during the period (1) of the LED indicated by data 8. FIG. 48 (B) is an explanatory diagram showing in more detail the change in brightness during the period (7) of the LED indicated by data 8.

  As shown in FIG. 46, the target brightness of the LED period (1) indicated by the data 8 is brightness F. Further, it is assumed that the brightness before the start of the period (1) is 0 as the initial value. In that case, the brightness is controlled stepwise from brightness 0 to brightness F (15). The target brightness of the LED period (7) indicated by the data 8 is 0. The brightness before the start of the period (7) (the final brightness of the period (6)) is the brightness 9. Therefore, the lightness is controlled stepwise from lightness 9 to lightness 0.

  Note that the “switching time” shown in FIG. 48 indicates the time from when a certain lightness is reached until the next lightness is switched. “Switching frequency” indicates the number of times the brightness is changed, and corresponds to a numerical value of a difference between the initial brightness and the target brightness. “Increase” in “increase / decrease” indicates that the brightness is gradually increased, and “decrease” indicates that the brightness is gradually decreased. As will be described later, the information of “switching time”, “number of times of switching”, and “up / down” is information used by the effect control microcomputer 100 in lamp control.

  FIG. 48 illustrates the cases of periods (1) and (7), but the other periods in which the brightness control is ON are the same as those of periods (1) and (7). The brightness is controlled to increase or decrease in steps.

  As shown in FIG. 48, in the period, the time controlled for each lightness (that is, switching time) is equally allocated, and the switching time is a multiple of 15 ms which is a unit time. However, depending on the length of the period, the switching times may not be equal and the switching time cannot be a multiple of 15 ms. For example, when the length of the period is 480 ms, the initial lightness is lightness 9, and the target lightness is lightness 0, each switching time is made equal and the switching time is made a multiple of 15 ms. I can't. In that case, for example, the time to be controlled to lightness 9 that is the first lightness, the time to be controlled to lightness 0 that is the target lightness, or an arbitrary time in the middle is lengthened. For example, the time of lightness 9 is (45 + 30) ms, the time of other lightness is 45 ms, the time of lightness 9 and the time of lightness 0 is (45 + 15) ms, and the time of other lightness is 45 ms. To do.

  When the length of the period is 490 ms, the initial lightness is lightness 9, and the target lightness is lightness 0, the time controlled to the lightness 9 that is the first lightness or the lightness 0 that is the target lightness. Even if the controlled time or any time in the middle is increased, the length cannot be a multiple of 15 ms. In this case, for example, the time of lightness 9 is set to (45 + 40) ms, the time of other lightness is set to 45 ms, the time of lightness 9 and the time of lightness 0 are set to (45 + 20) ms, and the time of other lightness is set. Or 45 ms for each.

  When the lightness 9 time is set to (45 + 40) ms or (45 + 20) ms, a time that cannot be controlled in units of 15 ms occurs. For example, since (45 + 40) = 15 × 5 + 10 ms, an odd time of 10 ms occurs. In such a case, in the time of 10 ms, the control different from the lightness 9 control shown in FIG. 45 is performed. For example, it is turned on for 6 ms out of 10 ms.

  In FIG. 46 and FIG. 47, 11 periods of period (1) to period (11) are illustrated, but the number of periods 11 is an example, and the number of periods is arbitrary. Moreover, although lightness 0 to lightness 15 is illustrated as lightness, the lightness number, that is, the lightness type number 16 is an example, and the lightness number is arbitrary.

  FIG. 49 is a flowchart showing the effect control process (step S705) in the main process shown in FIG. In the effect control process, the effect control CPU 101 performs one of steps S800 to S806 according to the value of the effect control process flag. In each process, the following process is executed.

  Fluctuation pattern command reception waiting process (step S800): It is confirmed whether or not a variation pattern command has been received from the game control microcomputer 560. Specifically, it is confirmed whether or not the variation pattern command reception flag set in the command analysis process is set. If the variation pattern command has been received, the value of the effect control process flag is changed to a value corresponding to the decorative symbol variation start process (step S801).

  Decoration symbol variation start processing (step S801): Control is performed so that the variation of the ornament symbol is started. Then, the value of the effect control process flag is updated to a value corresponding to the decorative symbol changing process (step S802).

  Decoration symbol variation processing (step S802): Controls the switching timing of each variation state (variation speed) constituting the variation pattern and monitors the end of the variation time. When the variation time ends, the value of the effect control process flag is updated to a value corresponding to the decorative symbol variation stop process (step S803).

  Decoration symbol variation stop process (step S803): Based on the reception of the effect control command (design determination designation command) for instructing all symbols to stop, the variation of the ornament symbol is stopped and the display result (stop symbol) is derived and displayed. Take control. Then, the value of the effect control process flag is updated to a value corresponding to the jackpot display process (step S804) or the variation pattern command reception waiting process (step S800).

  Big hit display processing (step S804): After the end of the variation time, control is performed to display a screen for notifying the variable display device 9 of the occurrence of the big hit. Then, the value of the effect control process flag is updated to a value corresponding to the big hit game processing (step S805).

  Big hit game processing (step S805): Control during big hit game is performed. For example, when a command for opening a special prize opening or a designation command after opening a special prize opening is received, display control of the number of rounds in the variable display device 9 is performed. Then, the value of the effect control process flag is updated to a value corresponding to the big hit end process (step S806).

  Big hit end processing (step S806): In the variable display device 9, display control is performed to notify the player that the big hit gaming state has ended. Then, the value of the effect control process flag is updated to a value corresponding to the variation pattern command reception waiting process (step S800).

  FIG. 50 is a flowchart showing a variation pattern command reception waiting process (step S800) in the effect control process shown in FIG. In the variation pattern command reception waiting process, the effect control CPU 101 confirms whether or not the variation pattern command reception flag is set (step S811). If the variation pattern command reception flag is set, the variation pattern command reception flag is reset (step S812). Then, the value of the effect control process flag is updated to a value corresponding to the decorative symbol variation start process (step S801) (step S813).

  FIG. 51 is an explanatory diagram showing a timer and a counter used when the effect control CPU 101 performs brightness control of the lamp. The brightness continuation timer is set to a certain brightness (any one of the periods (1) to (11) in the example shown in FIG. 46) (any one of the brightness 0 to 15 in the example shown in FIG. 48A). In the example shown in B), it is a timer that prescribes the time for which lightness is 9 to 0). The brightness correspondence counter is a counter used for determining that a certain period (any one of the periods (1) to (11) in the example shown in FIG. 46) has ended. When the brightness-corresponding counter counts up, the effect control CPU 101 performs lamp control at the target brightness during the period (time controlled at brightness 15 in the example shown in FIG. 48A, FIG. 48B). In the example shown in FIG. 8, it is determined that the time (controlled at lightness 0) has elapsed. Note that the value of the lightness corresponding counter represents the lightness controlled at that time.

  The period counter is a counter used to determine whether or not the final period (period (11) in the example shown in FIG. 46) has elapsed. When the period counter counts up, the effect control CPU 101 returns to the state in which the brightness control of the first period (period (1) in the example shown in FIG. 46) is executed. The 15 ms timer is a counter for determining whether or not to light up within a certain brightness level. In the example shown in FIG. 45, in the case of lightness n (n = 1 to 15), the effect control CPU 101 turns on a lamp (specifically, an LED) in a section where the value of the 15 ms timer is 1 to n. Control is performed so that the lamp is turned off in other sections.

  Referring to the example shown in FIG. 48A, the 15 ms timer is used to measure each 15 ms. The brightness continuation timer is used to measure the time (corresponding to the switching time) controlled at each brightness. The lightness correspondence counter is incremented every time the lightness is switched in the period (1) (a period of 480 ms), and whether or not the number of times of switching has reached 16, that is, whether or not the period (1) has ended. Used for judgment. The period counter is incremented every time the period is switched in the periods (1) to (11).

  FIG. 52 is a flowchart showing a decorative symbol variation start process (step S801) in the effect control process shown in FIG. In the decorative symbol variation start process, the effect control CPU 101 reads data indicating the variation pattern command from the variation pattern command storage area (step S816).

  Next, it is confirmed whether or not the display result specifying command reception flag is set (step S817). If the display result specifying command reception flag is not set, the process proceeds to step S820. When the display result specifying command reception flag is set, the display result (stop symbol) of the decorative symbol is displayed according to the data stored in the display result specifying command storage area (that is, the received display result specifying command). Determination is made (step S818).

  FIG. 53 is an explanatory diagram showing an example of a decorative symbol stop symbol in the variable display device 9. In the example shown in FIG. 53, when the received display result specifying command indicates a normal jackpot (when the received display result specifying command is a display result 2 designation command), the effect control CPU 101 uses the stop design as a stop symbol. A combination of decorative symbols in which the left middle right symbol is an even symbol (usually a stop symbol reminiscent of occurrence of a big hit) is determined. When the received display result specifying command indicates a probable big hit (when the received display result specifying command is a display result 4 designation command), the effect control CPU 101 uses the left middle right symbol as an odd symbol as an odd symbol. A combination of decorative symbols arranged in accordance with (a stop symbol reminiscent of occurrence of a probable big hit) is determined. When the received display result specifying command indicates a small hit or suddenly probable big hit (when the received display result specifying command is a display result 3 specifying command or a display result 5 specifying command), the presentation control CPU 101 A combination of “135” (a stop symbol reminiscent of the occurrence of a small hit or suddenly probable big hit) is determined as the left middle right decorative symbol as the stop symbol. In the case of a loss (when the received display result specifying command is a display result 1 designation command), a combination of decorative symbols other than the above is determined. However, when a reach effect is involved, a combination of decorative symbols with left and right aligned is determined. The combination of the left, middle and right decorative symbols derived and displayed on the variable display device 9 is the “stop symbol” of the decorative symbol.

  The effect control CPU 101 extracts, for example, a random number for determining the stop symbol, and uses the stop symbol determination table in which the data indicating the combination of the decorative symbol and the numerical value are associated with each other to generate the stop symbol of the decorative symbol. decide. That is, the stop symbol is determined by selecting data indicating a combination of decorative symbols corresponding to a numerical value that matches the extracted random number.

  As for the decorative symbol, a stop symbol that recalls a big hit is called a big hit symbol. In addition, a stop symbol reminiscent of a probable big hit is called a probable big hit symbol, and a stop symbol reminiscent of a normal big hit is called a normal big hit symbol. A stop symbol that suddenly recalls a probable big hit is called a sudden probable big hit symbol, and a stop symbol that recalls a small hit is called a small hit symbol. And a stop symbol that reminds of a loss is called a loss symbol.

  Further, the effect control CPU 101 resets the display result specifying command reception flag (step S819). Next, a process table corresponding to the variation pattern is selected (step S831A).

  In this embodiment, the effect control CPU 101 performs control so that the decorative pattern is variably displayed by the change pattern corresponding to the change pattern command on a one-to-one basis, but the effect control CPU 101 controls the change pattern command. The variation pattern to be used may be selected from a plurality of types of variation patterns corresponding to.

  Further, a lamp control table corresponding to the variation pattern is selected (step S831B). Then, the switching time and the number of switching are calculated for the first data in the lamp control table, that is, for the period (1) (step S832). Note that step S832 is executed for all the lamps to be subjected to brightness control. The lamp control table includes a table corresponding to each of all lamps to be subjected to brightness control. Therefore, the switching time and the number of switching times are calculated for each of all the lamps.

  The effect control CPU 101 sets “1” as the initial value in the period counter, and sets the first brightness value in the brightness correspondence counter (step S833). The first lightness value is 0 corresponding to lightness 0, for example. However, when the brightness is constant, the value corresponds to the constant brightness. Further, the lightness correspondence counter exists corresponding to each of all the lamps to be subjected to lightness control. Then, the process timer in the process data 1 of the process table selected in step S831A is started (step S834A). Further, a value corresponding to the switching time calculated in step S832 is set in the brightness continuation timer, and an initial value “1” is set in the 15 ms timer (step S834B).

  FIG. 54 is an explanatory diagram of a configuration example of the process table. The process table is a table in which process data referred to when the effect control CPU 101 executes control of the effect device is set. That is, the effect control CPU 101 controls effect devices (effect components) such as the variable display device 9 in accordance with the data set in the process table. In this embodiment, an error notification process table (error notification process table) used when various types of error notification are performed is prepared in addition to the process table used for normal game effects shown in FIG. ing. Details of the error notification process table will be described later.

  The process table includes data in which a plurality of combinations of process timer set values, display control execution data, and sound number data are collected. The display control execution data includes data indicating each variation mode constituting the variation mode during the variable display time (variation time) of the variable display of the decorative symbols. Specifically, data relating to the change of the display screen of the variable display device 9 is described. The process timer set value is set with a change time in the form of the change. The effect control CPU 101 refers to the process table and performs control to display the decorative pattern in the variation mode set in the display control execution data for the time set in the process timer set value.

  The process table shown in FIG. 54 is stored in the ROM of the effect control board 80. A process table is prepared for each variation pattern. A ramp control table is also prepared for each variation pattern.

  FIG. 55 is an explanatory diagram of a configuration example of a lamp control table. The lamp control table shown in FIG. 55 is a table for realizing the brightness change exemplified in FIG. In the configuration example shown in FIG. 55, the number of periods is set at the head in the lamp control table. Next, data indicating whether the “lightness control” corresponding to each of the periods (1) to (11) is ON or OFF, the length (time) of the period, and the brightness value indicating the target brightness in the period Is set. In FIG. 55, (H) indicates a hexadecimal number, and (D) indicates a decimal number.

  FIG. 55 illustrates only a table relating to a lamp (specifically, LED) having lamp number 8 (see FIG. 46), but tables are also prepared for lamps corresponding to other lamp numbers. .

  The production control CPU 101 has an abnormality notification flag indicating that an abnormal winning notification is being made and other error flags (RAM clear flag, random number circuit error flag, full tank error notification flag, door opening error notification flag, ball break error) On the condition that the notification flag and the prize ball error notification flag) are not set, according to the contents of the process data 1 (display control execution data 1 and sound number data 1), the effect device (the variable display device 9 as an effect part, And the control of the speaker 27 as a production component is executed (steps S835A and S835B). For example, in order to display an image corresponding to the variation pattern on the variable display device 9, a command is output to the VDP 109. In addition, a control signal (sound number data) is output to the voice synthesizing IC 173 in order to perform voice output from the speaker 27.

  Further, the CPU 101 for effect control sets data to be output to the lamp (specifically LED) in a predetermined area of the RAM according to the value of the brightness correspondence counter and the value of the 15 ms timer (step S835C). And a serial setting process is performed in order to control various lamps as production parts (step S835D). The relationship between the value of the lightness counter and the value of the 15 ms timer and the data output to the lamp will be described later.

  For example, in the lamp control table selected when the gaming state is the normal state, data for performing brightness control is set only for the LED 125a to 125f for the center decoration lamp and the LEDs 126a to 126f for the stage lamp. . In the serial setting process, the effect control CPU 101 sets the data set in the predetermined area of the RAM in the process of step S835C in the predetermined data storage area. Therefore, when the gaming state is the normal state, data regarding only the LED 125a to 125f of the center decoration lamp and the LEDs 126a to 126f of the stage lamp are set in a predetermined data storage area. Further, in the lamp control table selected when the gaming state is a probable change state, the center decoration lamp LEDs 125a to 125f and the stage lamp LEDs 126a to 126f are turned on, and all of the lamps provided on the gaming frame 11 side are also turned on. Data for performing brightness control is set for the LEDs 281a to 281l, 282a to 282f, and 283a to 283f of the lamps (excluding the dish lamp). In the serial setting process, lamp control signals for these LEDs are set in a predetermined data storage area. The lamp control signal set in the process of step S835D is output to the serial output circuit 353 in the serial input / output process (step S708) in the main process, converted into serial data by the serial output circuit 353, and relay board 606. , 607 to the board side IC substrate 601 and the frame side IC substrates 602 to 604.

  When the abnormality notification flag or the other error flag is set, the rendering device is controlled according to the contents of the process data 1 excluding the sound number data 1 (steps S835A and S835E). In other words, when the abnormality notification flag or other error flag is set, when a new variable display of a decorative design is started, a sound effect according to the variable display is not executed, but an abnormal Sound output corresponding to the winning notification and various error notifications (RAM clear notification, random number circuit error notification, full tank error notification, door opening error notification, ball runout error notification, prize ball error notification) is continued.

  In addition, when performing the process of step S835E, the CPU 101 for effect control does not simply output a command based on the display control execution data 1 to the VDP 109, but also outputs a command for performing “superimposed display” to the VDP 109. That is, the display at that time on the variable display device 9 (notification of abnormal winning, notification of full tank error, notification of random circuit error) and the image of the display effect of variable display of the decorative symbols are variable at the same time. Control is performed so that the image is displayed on the display device 9. That is, when the abnormality notification flag and other error flags are set, when a new variable display of a decorative design is started, only the display effect according to the variable display is not executed. Notifications according to abnormal winning notifications and various error notifications are also continued.

  Then, a value corresponding to the variation time specified by the variation pattern command is set in the variation time timer (step S836), and the value of the effect control process flag is set to a value corresponding to the decorative symbol variation process (step S802). (Step S837).

  In step S820, it is confirmed whether or not a variation pattern command that can be used for both a normal big hit and a probable big hit is received. In this embodiment, as shown in FIG. 23, the fluctuation pattern commands of “reach C / shortening”, “reach C”, and “super reach A” are used both in the normal big hit and the probable big hit. This is a variable pattern command. Therefore, the CPU 101 for effect control receives the variation pattern command that can be used for both the normal big hit and the probable big hit when the data indicating those fluctuation pattern commands is stored in the fluctuation pattern command storage area. It is determined that When it is determined that the variation pattern command that can be used during both the normal big hit and the probable big hit is received, the effect control CPU 101 determines the stop symbol as the normal big hit symbol (step S822). Also, if it is determined that a variation pattern command other than the variation pattern command that can be used for both a normal big hit and a probable big hit is received, the stop symbol is combined with a decorative symbol corresponding to the received variation pattern. (Step S821). In this embodiment, a variation pattern command other than the variation pattern command that can be used for both a normal jackpot and a probable variation jackpot is used at the time of losing or is used according to the type of jackpot ( (See FIG. 23). Therefore, when the variation control command 101 other than the variation pattern command that can be used for both the normal big hit and the probable big hit is received, the effect control CPU 101 determines the deviation based on the received variation pattern command. Whether or not a big hit (including a small hit) is determined, and if it is determined to be a big hit, the type of the big hit can be specified.

  In this way, the effect control microcomputer 100 receives the variation pattern command that can be used for both the normal big hit and the probable big hit, and when the display result specifying command cannot be received, Since the display result (stop symbol) is determined to be a normal jackpot symbol, it is possible to make the player recognize whether or not a specific gaming state occurs even if the display result specifying command cannot be received. In addition, by including information that can specify the decorative pattern display result in the variation pattern command, the effect control microcomputer 100 can display the display result identification command without using a command other than the variation pattern command and the display result identification command. Since the display result of the decorative design can be determined even if it cannot be received, the types of commands transmitted by the game control microcomputer 560 do not increase, and as a result, the control burden on the game control microcomputer 560 does not increase.

  FIG. 56 is a flowchart showing an example of specific processing (switching time / switching count calculation processing) in step S832 in FIG. In the switching time / switching number calculation process, the effect control CPU 101 is a value indicating that “brightness control” is ON (“1” in this example) for the target period in the lamp control table. (Step S861). If it is not a value indicating ON, information indicating "constant brightness" is stored in a predetermined area of the RAM (step S865). When the information of “constant brightness” is stored in the RAM, the CPU 101 for effect control has a value corresponding to a constant brightness regardless of the value of the brightness corresponding counter in the process of step S984 (see FIG. 58). Control for setting a drive signal to the lamp (specifically, LED) is performed according to (value set in the lamp control table). Therefore, the CPU 101 for effect control determines the lightness level per unit time in the period as the target lightness level without performing calculation when the value indicating that “lightness control” is OFF. It will be.

  If “lightness control” is a value indicating ON, (maximum brightness−minimum brightness + 1) is calculated. Then, the calculation result is set to “number of times of switching” (step S862). The maximum brightness is the target brightness (final brightness), and the minimum brightness is the target brightness in the immediately preceding period. However, when the target brightness (final brightness) is lower than the target brightness in the immediately preceding period, the minimum brightness is set to the target brightness (final brightness), and the maximum brightness is set to the target brightness in the immediately preceding period.

  For example, in the example shown in FIG. 55, the target brightness in the period (6) is 9, and the target brightness in the immediately preceding period (period (5)) is 0. Therefore, the maximum brightness is 9, and the minimum brightness is 0. It is. Therefore, the number of times of switching is 10. Further, since the target brightness in the period (7) is 0 and the target brightness in the immediately preceding period (period (6)) is 9, the maximum brightness is 9, and the minimum brightness is 0. Therefore, the number of times of switching is 10. In the period (1), it is assumed that the target brightness in the immediately preceding period is zero.

  In addition, (period time / number of switching times) is calculated, and the calculation result is set as the switching time (step S863). For example, in the example shown in FIG. 55, (period time / number of switching times) in the period (7) is 450/10 = 45, and 45 ms is calculated as the switching time.

  The effect control CPU 101 stores the switching time and the number of switching times in the RAM, and stores information indicating “brightness increase” or “brightness decrease” in a predetermined area of the RAM (step S864). In step S864, “increased brightness” is stored when the target brightness is higher than the target brightness in the immediately preceding period, and “down brightness” is stored when the target brightness is lower than the target brightness in the immediately preceding period.

  In this embodiment, the production control CPU 101 determines the brightness level for each unit time (in this example, 15 ms) in the period (1) to the period (11) by calculation. For example, in the period (1) illustrated in FIG. 48A, the length of the entire period is 480 ms, and therefore, 30 unit times of 15 ms are included therein. Then, the brightness for each unit time is determined. For example, lightness 0 is determined for the first two unit times at 480 ms, and lightness 15 (F) is determined for the last two unit times. In this embodiment, a lamp control table as illustrated in FIG. 55 is used for brightness control, but data for fine brightness control within each period (1) to period (11). A table with is not required. Therefore, the ROM capacity in the production control microcomputer 100 can be reduced as compared with the case where a table in which data for fine brightness control within each period is used.

  FIG. 57 is a flowchart showing the decorative symbol variation process (step S802) in the effect control process. In the decorative symbol variation process, the effect control CPU 101 executes a brightness control process (step S840). Further, the process timer value is decremented by 1 (step S841), and the variable time timer value is decremented by 1 (step S842). When the process timer times out (step S843), the process data is switched. That is, the process timer setting value set next in the process table is set in the process timer (step S844).

  Also, the abnormality notification flag and other error flags (RAM clear flag, random number circuit error flag, full tank error notification flag, door opening error notification flag, ball out error notification flag, prize ball error notification flag) are not set. As a condition, the control state for the rendering device is changed based on the display control execution data and sound number data set next (steps S845A and S845B).

  In step S845B, the effect control CPU 101 outputs a command to the VDP 109 in order to display an image corresponding to the variation pattern on the variable display device 9, for example. In addition, a control signal (sound number data) is output to the voice synthesizing IC 173 in order to perform voice output from the speaker 27.

  When the abnormality notification flag or other error flag is set, the rendering device is controlled according to the contents of process data i (i is any one of 2 to n) (excluding the sound number data i). (Steps S845A and S845D). Therefore, when the abnormality notification flag or other error flag is set, the sound effect according to the variable display of the decorative design is not executed, but an abnormal winning notification or various error notifications (RAM clear notification, Sound output corresponding to random number circuit error notification, full tank error notification, door opening error notification, ball runout error notification, prize ball error notification) is continued.

  Further, when the process of step S845D is performed, the presentation control CPU 101 does not simply output a command based on the display control execution data i to the VDP 109, but also outputs a command for performing “superimposed display” to the VDP 109. . Therefore, when the abnormality notification flag and other error flags are set, not only the display effect according to the variable display of the decorative design is executed, but the notification according to the abnormal winning notification or various error notifications is performed. Will continue.

  If the variation time timer has timed out (step S846), the value of the effect control process flag is updated to a value corresponding to the decorative symbol variation stop process (step S803) (step S848). Even if the variable time timer has not timed out, if the confirmation command reception flag indicating that the symbol confirmation designation command has been received is set (step S847), the process proceeds to step S848. Even if the variation time timer has not timed out, if the symbol confirmation designation command is received, the process shifts to control to stop variation.For example, a variation pattern command indicating a long variation time due to noise between substrates is received. Even in such a case, the variation of the decorative symbol can be terminated when the regular variation time has elapsed (when the variation of the special symbol has ended).

  FIG. 58 is a flowchart showing the brightness control process in step S840. In the brightness control process, the effect control CPU 101 increments the value of the 15 ms timer by 1 (step S981). When the value of the 15 ms timer reaches 16, the value of the 15 ms timer is returned to 1 (steps S982 and S983). Then, data to be output to the lamp (specifically, LED) is set in a predetermined area of the RAM according to the value of the brightness correspondence counter and the value of the 15 ms timer (step S984).

  FIG. 59 is an explanatory diagram showing an example of data output as a lamp in accordance with the value of the brightness correspondence counter and the value of the 15 ms timer. FIG. 59 illustrates a case where the value of the lightness correspondence counter is 9 (that is, lightness 9). When the value of the brightness correspondence counter is 9, when the value of the 15 ms timer is any one of 1 to 9, “1” indicating lighting is set in the RAM. Further, when the value of the 15 ms timer is any one of 10 to 15, “0” indicating that the light is off is set in the RAM.

  Since a drive signal is given to the lamp in accordance with data set in a predetermined area of the RAM, the data is represented as “drive signal” in FIG. In addition, FIG. 59 illustrates the case of lightness 9, but lighting is indicated when the value of the 15 ms timer is 1 to n for lightness n (any of n = 1 to 14). “1” is set in the RAM. In addition, when the value of the 15 ms timer is any one of (n + 1) to 15, “0” indicating turning off is set in the RAM. When the brightness is 0, “0” indicating that the light is off is set in the RAM regardless of the value of the 15 ms timer. When the brightness is 15 (F), “1” indicating lighting is set in the RAM regardless of the value of the 15 ms timer.

  In addition, when the information of “constant brightness” is stored in the RAM, the CPU 101 for effect control uses a value corresponding to the constant brightness and a 15 ms timer in the process of step S984 regardless of the value of the brightness correspondence counter. The data to be output to the lamp (specifically, LED) is set in a predetermined area of the RAM according to the value of. For example, if the constant lightness is lightness 9, regardless of the value of the lightness corresponding counter, “1” indicating lighting is set in the RAM when the value of the 15 ms timer is any one of 1 to 9. When the value of the 15 ms timer is any of 10 to 15, “0” indicating turning off is set in the RAM.

  Next, the production control CPU 101 decrements the value of the brightness continuation timer by 1 (step S985). The lightness continuation timer has a switching time as an initial value (see step S834B). The switching time is 30 ms in the example shown in FIG. 48 (A), and 45 ms in the example shown in FIG. 48 (B).

  The effect control CPU 101 checks the value of the brightness continuation timer (step S986), and when the value of the brightness continuation timer is 0, that is, when time-out has occurred, the process proceeds to step S995.

  When the value of the brightness continuation timer has not timed out, that is, when the time for controlling to a certain brightness has elapsed, the value of the brightness corresponding counter is incremented by +1 or −1 (step S987). In step S987, the production control CPU 101 increments by 1 when information indicating "brightness increase" is stored in the RAM, and when information indicating "brightness decrease" is stored in the RAM-. 1

  If the value of the brightness correspondence counter exceeds the final brightness value (target brightness value), the period (for example, any one of period (1) to period (11)) has ended. In that case, the process proceeds to step S989 (step S988). When the value of the brightness correspondence counter does not exceed the final brightness value, the process proceeds to step S995. In step S <b> 989, when the information indicating that “brightness increase” is stored in the RAM, the CPU 101 for effect control has the value of the lightness corresponding counter at [final lightness value (target lightness value) +1]. If the information indicating “lightness decrease” is stored in the RAM, it is confirmed whether or not the value of the lightness corresponding counter is [final lightness value (target lightness value) −1]. .

  Further, the effect control CPU 101 increments the value of the period counter indicating which of the period (1) to period (11) is +1 (step S989). When the value of the period counter exceeds the number of periods (11 in this example), the value of the period counter is returned to 1 (steps S990 and S991). Then, a switching time / switching count calculation process (see FIG. 56) is executed to set the switching time and the switching count for the new period (step S992). In addition, the first brightness value in the period indicated by the value of the period counter (specifically, the target brightness value in the immediately preceding period) is set in the brightness correspondence counter (step S993).

  In addition, the switching time is set to the brightness continuation timer, and the value of the 15 ms timer is initialized to 1 (step S994). Then, an abnormality notification flag indicating that an abnormal winning notification is being made and other error flags (RAM clear flag, random number circuit error flag, full tank error notification flag, door open error notification flag, ball breakage error notification flag, award Serial setting processing is executed on the condition that the ball error notification flag) is not set (steps S995 and S996). The effect control CPU 101 sets the data set in the predetermined area of the RAM in the process of step S984 in the serial setting process in the predetermined data storage area. The lamp control signal set in the serial processing is output to the serial output circuit 353 in the serial input / output processing (step S708) in the main processing, converted into serial data by the serial output circuit 353, and via the relay boards 606 and 607. Is output to the board side IC substrate 601 and the frame side IC substrates 602 to 604.

  FIG. 60 is a flowchart showing a decoration symbol variation stop process (step S803) in the effect control process. In the decorative symbol variation stop process, the effect control CPU 101 confirms whether or not the confirmed command reception flag is set (step S851). If the confirmed command reception flag is set, the confirmed command reception flag is reset. Then, control is performed to derive and display the determined stop symbol (step S853). Then, the production control CPU 101 confirms whether or not it is determined to be a big hit (step S854). Whether or not it is determined to be a big hit is confirmed by, for example, a display result specifying command stored in the display result specifying command storage area. In this embodiment, it can be confirmed whether or not it is determined to be a big hit based on the determined stop symbol.

  When it is determined to be a big hit, the value of the effect control process flag is updated to a value corresponding to the big hit display process (step S804) (step S855).

  If it is determined not to win, the effect control CPU 101 checks whether or not the time reduction state flag is set (step S856). The short time state flag is set when the gaming state is a short time state (see step S886 described later). If the time reduction state flag is set, the value of the time reduction variation counter is incremented by 1 (step S857).

  Then, the production control CPU 101 confirms whether or not the value of the time-varying variation number counter is 100 (step S858). If the value of the hour / short fluctuation counter is 100, the hour / short state flag is reset (step S859). Then, the value of the effect control process flag is updated to a value corresponding to the variation pattern command reception waiting process (step S800) (step S860).

  In this embodiment, the effect control microcomputer 100 ends the variation (variable display) of the decorative symbols on the condition that the symbol confirmation designation command has been received (see steps S851 and S853). However, if the variation time timer based on the received variation pattern command times out, the variation of the decorative symbol may be controlled to end without receiving the symbol determination designation command. In this case, the game control microcomputer 560 may not transmit the symbol confirmation designation command for designating the end of variable display.

  FIG. 61 is a flowchart showing the jackpot display process (step S804) in the effect control process. In the jackpot display process, the effect control CPU 101 checks whether or not the jackpot start 1-4 designation command reception flag indicating that any of the jackpot start 1-4 designation commands has been received is set (step S871). If any one of the big hit start 1 to 4 designation command reception flags is set, control is performed to display a game start screen corresponding to the set flag on the variable display device 9 (step S872). Further, the set flag (one of the big hit start 1-4 designation command reception flags) is reset (step S873). Then, the value of the effect control process flag is updated to a value corresponding to the big hit game processing (step S805) (step S874).

  In step S872, when receiving the big hit start 2 designation command, the effect control CPU 101 performs control to display a screen for informing the start of the big hit game on the variable display device 9. Further, when the big hit start 4 designation command is received, the variable display device 9 is controlled to display a screen for informing the sudden start of the probable big hit game. When the jackpot start 1 designation command or the jackpot start 3 designation command is received, a screen for informing the start of the jackpot game (a screen for informing the start of the jackpot game and a notice of the start of the sudden probability change jackpot game) The display is controlled on the variable display device 9.

  FIG. 62 is a flowchart showing the big hit end process (step S806) in the effect control process. In the jackpot end process, the effect control CPU 101 checks whether or not the jackpot end effect timer is set (step S880). If the big hit end effect timer is set, the process proceeds to step S885. If the jackpot end effect timer is not set, a jackpot end designation command reception flag (a jackpot end 1 designation command reception flag or a jackpot end 2 designation command reception flag) indicating that the jackpot termination designation command has been received is set. It is confirmed whether or not there is (step S881). When the jackpot end designation command reception flag is set, the jackpot end designation command reception flag is reset (step S882), and a value corresponding to the jackpot end display time is set in the jackpot end presentation timer (step S883). Then, the variable display device 9 is controlled to display a jackpot end screen (screen for informing the end of the jackpot game) (step S884). Specifically, an instruction to display the big hit end screen is given to the VDP 109.

  In this embodiment, even if the type of jackpot is different, the same jackpot end screen is displayed on the variable display device 9. For example, the big hit end display and the small hit end display are the same. However, the big hit end display (including the small hit end display) may be divided according to the type of the big hit.

  In step S885, 1 is subtracted from the value of the big hit end effect timer. Then, the effect control CPU 101 checks whether or not the value of the jackpot end effect timer is 0, that is, whether or not the jackpot end effect time has elapsed (step S886). If not, the process ends. If it has elapsed, the time reduction state flag is set (step S887), and the time reduction number counter is set to 0 (step S888). If the jackpot end 1 designation command is received, the probability variation state flag is reset (steps S889 and S891). When the jackpot end 1 designation command has not been received (when the jackpot end 2 designation command has been received), the probability variation state flag is set (steps S889, S890). Then, the value of the effect control process flag is updated to a value corresponding to the variation pattern command reception waiting process (step S800) (step S892).

  The probability change state flag and the time reduction state flag are used, for example, when the effect control CPU 101 notifies the probability change state and the time reduction state by the background or the decorative light emitter (lamp / LED) in the variable display device 9.

  FIG. 63 is an explanatory diagram showing an example of a notification screen displayed on the variable display device 9. FIG. 63A shows an example of an initial screen displayed on the variable display device 9 by the production control CPU 101 in response to reception of the initialization designation command. FIG. 63B shows an example of a power failure recovery screen displayed on the variable display device 9 by the production control CPU 101 in response to reception of a power failure recovery designation command. FIG. 63 (C) shows an example of an abnormality notification screen displayed on the variable display device 9 in response to the reception of the abnormal prize notification designation command by the effect control CPU 101, and the variation of the decorative design is started. Also, it is shown that the display of the abnormality notification screen is continued (see the right side of FIG. 63C).

  Next, the notification control process process in step S707 will be described. First, various error notification modes executed in the notification control process will be described. FIG. 64 is an explanatory diagram showing an example of various error notification modes executed in the notification control process. As shown in FIG. 64, the RAM clear notification is executed for a predetermined period (for example, 31 seconds) from the power-on of the gaming machine. When performing the RAM clear notification, the effect control CPU 101 lights the LEDs 281a to 281l, 282a to 282f, and 283a to 283f of all the lamps (excluding the dish lamp) on the game frame 11 side, and causes the speaker 27 to generate a predetermined error sound. Control (for example, beep sound) is output.

  The door opening error notification is executed while the game frame 11 is opened (for example, while the detection signal of the door opening sensor 155 is input). When performing the door opening error notification, the effect control CPU 101 performs control to blink the LEDs 281a to 281l, 282a to 282f, and 283a to 283f of all the lamps (excluding the dish lamp) on the game frame 11 side. In addition, control is performed so that a predetermined error sound (for example, a beep sound) is output to the speaker 27 together with a sound “the door is open”.

  Further, the ball break error notification is executed from the occurrence of a ball break until the ball break state is canceled (for example, while a detection signal of a ball break switch is input). The effect control CPU 101 performs control of blinking the LEDs 281a to 281l of the top frame lamp on the game frame 11 side when notifying the ball break error. The full tank error notification is executed from the occurrence of the full tank state of the lower pan until the full tank state is canceled (for example, while the detection signal of the full tank switch is input). When performing the full tank error notification, the effect control CPU 101 performs control to blink the LEDs 82a to 82d of the lower pan lamps on the game frame 11 side and to output a voice saying that the lower pan is full. In addition, control is performed to display “the bottom plate is full” on the variable display device 9. In this case, when display by a game effect (for example, variable display of decorative symbols) is performed on the variable display device 9, a character string “bottom plate is full” is superimposed on the variable display device 9. .

  The prize ball error notification is executed from the occurrence of the prize ball abnormality until the prize ball abnormality state is canceled. When performing the prize ball error notification, the effect control CPU 101 performs control to blink the LEDs 281a to 281l of the top frame lamp on the game frame 11 side. Further, the random number circuit error notification is executed until the power is turned off after the random number circuit error is detected when the gaming machine is turned on. When performing the random number circuit error notification, the effect control CPU 101 lights up the LEDs 281a to 281l, 282a to 282f, and 283a to 283f of all the lamps (excluding the dish lamp) on the game frame 11 side, and a predetermined error sound (for example, (Beep sound) is output. In addition, control is performed to display “error” on the variable display device 9. In this case, when display by a game effect (for example, variable display of decorative symbols) is performed on the variable display device 9, a character string “error” is superimposed on the variable display device 9.

  The abnormal winning error notification is executed for a predetermined period (for example, 30 seconds) from the occurrence of the abnormal winning. When performing the abnormal winning notification, the effect control CPU 101 blinks the LEDs 281a to 281l, 282a to 282f, and 283a to 283f of all the lamps (excluding the dish lamp) on the game frame 11 side, and a predetermined error sound (for example, a beep). (Sound) is output.

  FIG. 65 is a flowchart showing the notification control process (step S707) in the main process shown in FIG. In the notification control process, the effect control CPU 101 performs one of steps S1900 and S1901 according to the value of the notification control process flag. In each process, the following process is executed.

  The notification start processing (step S1900) includes error flags (initial notification flag, random number circuit error flag, abnormal winning notification designation command reception flag, RAM clear flag, full tank error notification flag, prize ball error notification set in the command analysis processing. This is a process of starting error notification based on the flag and the ball break error notification flag. When the error notification is started, the value of the notification control process flag is changed to a value corresponding to the notification process (step S1901).

  The in-notification process (step S1901) is based on each error flag (initial notification flag, random number circuit error flag, abnormality notification flag, RAM clear flag, full tank error notification flag, winning ball error notification flag, out of ball error notification flag). Thus, the error notification process is continued. Further, the error notification is terminated based on the fact that an error notification period (initial notification period, RAM clear notification period) has elapsed or an error notification release flag set in the command analysis process. When the error notification is finished, the value of the notification control process flag is changed to a value corresponding to the notification start process (step S1901).

  FIG. 66 is an explanatory diagram of a configuration example of an error notification process table. The error notification process table is a table in which process data to be referred to when the effect control CPU 101 performs control of the effect device and performs various error notifications is set. That is, the effect control CPU 101 performs error notification by controlling the speaker 27 and each lamp in accordance with data set in the error notification process table. The error notification process table includes data obtained by collecting a plurality of combinations of process timer set values, error lamp control execution data, and error sound number data. In the process timer set value, the duration in the sound output state and the lamp display state is set. The effect control CPU 101 refers to the error notification process table and controls the lighting / non-lighting state of each lamp in a manner set in the lamp display control execution data for the time set in the process timer set value. The sound output using the speaker 27 is controlled.

  Next, the serial setting process will be described. FIG. 67 is a flowchart illustrating an example of the serial setting process. The serial setting process is executed, for example, when a decorative symbol is variably displayed in the effect control process (see steps S835D and S976). Note that various error notifications are also executed in the notification control process.

  In the serial setting process, the production control CPU 101 first reads out data relating to lamp control (such as lamp lighting pattern data and motor control data associated with the variation pattern) from the RAM or ROM (step S950). The effect control CPU 101 reads the data set in the RAM in step S835C (see FIG. 52) or step S984 (see FIG. 58) when performing the serial setting process during the variable display of the decorative symbols. Become. When serial setting processing is performed in the notification control process, error lamp control execution data in the error notification process table shown in FIG. 66 is read.

  Next, the effect control CPU 101 checks whether or not there is a change in the display state of each lamp based on the read data relating to lamp control execution (step S951). If the display state of each lamp is changed, the CPU 101 for effect control extracts the lamp control signal to which the address of the serial-parallel conversion IC of the lamp to be displayed is added from a predetermined lamp control signal storage area ( Step S952). Next, header data (1FFh), a mark bit, and an end bit shown in FIG. 16 are added to the extracted ramp control signal and set in a predetermined data storage area provided in the RAM (step S953). Then, a lamp control signal output request flag is set (step S954).

  FIG. 68 is an explanatory diagram showing an example of a lamp control signal stored in the data storage area. FIG. 68 illustrates lamp control signals for driving the top frame lamp, the right frame lamp, and the left frame lamp. As shown in FIG. 68, the lamp control signal is stored in a predetermined lamp control signal storage area with the addresses of the output destination serial-parallel conversion ICs 611 to 615 added thereto. For example, since the address of the serial-parallel conversion IC 611 that supplies a control signal to some of the LEDs 281a to 281f in the ceiling lamp is “01”, the address “0001” is stored in the 8-digit data body for controlling the lamp. "Is added and stored. In addition, since the address of the serial-parallel conversion IC 612 that supplies the control signal to some of the other LEDs 281g to 281l in the ceiling lamp is “02”, the address of the 8-digit data body for controlling the lamp is addressed. Stored with “0010” added. Since the address of the serial-parallel conversion IC 613 that supplies the control signal to the LEDs 283a to 283f of the right frame lamp is “03”, the address “0011” is added to the 8-digit data body for controlling the lamp. Stored in state. Since the address of the serial-parallel conversion IC 614 that supplies the control signal to the LEDs 282a to 282f of the left frame lamp is “04”, the address “0100” is added to the 8-digit data body for controlling the lamp. Stored in state.

  In this example, a lamp control signal whose control data body is “00111111” is transmitted to each of the serial-parallel conversion ICs 611 to 614 whose addresses are “01” to “04”. That is, a lamp control signal in which the logical values of the bits corresponding to the LEDs of each lamp are all 1 is output, and the LEDs 281a to 281l and 282a to 282f of all the lamps (excluding the dish lamp) provided on the game frame 11 side. , 283a to 283f are turned on.

  Although the case where the top frame lamp, the right frame lamp, and the left frame lamp are driven is illustrated here, the effect control microcomputer 100 outputs a control signal for controlling the lamp provided on the game board 6. When playing, a control signal added with address information that can identify the board-side serial-parallel conversion circuit (see FIG. 11) mounted on the board-side IC board is output in the serial signal system, and is provided in the game frame 11. When outputting a control signal for controlling the lamp, a control signal to which address information capable of specifying the frame side serial-parallel conversion circuit (see FIG. 11) mounted on the frame side IC substrate is added in a serial signal system. Output.

  FIG. 69 is a flowchart illustrating a specific example of the serial input / output process (step S708). In the serial input / output process, the effect control CPU 101 first checks whether or not the lamp control signal output request flag is set (step S970). If set, the lamp control signal output request flag is reset (step S971), and the lamp control signal stored in the data storage area is output to the serial output circuit 353 (step S972). In this case, when a plurality of lamp control signals are set in the data storage area, the effect control CPU 101 sequentially reads each lamp control signal and outputs it to the serial output circuit 353 in step S972. The output lamp control signal is converted into serial data by the serial output circuit 353, and is output to the panel side IC substrate 601 and the frame side IC substrates 602 to 605 by the serial signal system via the relay substrates 606 and 607. Will be.

  Next, the effect control CPU 101 causes the input capture signal output unit 357 to output an input capture signal (latch signal) to the board side IC substrate 601 via the relay substrates 606 and 607 (step S973). The input IC 621 mounted on the panel-side IC board 601 latches the detection signals of the position sensors 151b, 152b, 153b based on the input input signal being input, and relays boards 606, 607 in a serial signal system. Is output to the effect control board 80. Then, the effect control CPU 101 reads the input data from the serial input circuit 354 and stores it in a predetermined storage area of the RAM (step S974). In step S974, the effect control CPU 101 controls the serial input circuit 354 to read the input data from the serial input circuit 354 after delaying the input data from the input IC 621 by a time.

  Next, the effect control CPU 101 causes the input capture signal output unit 357 to output an input capture signal (latch signal) to the frame side IC substrate 605 via the relay substrate 607 (step S975). The input IC 620 mounted on the board-side IC board 605 latches the detection signals of the operation buttons 81a to 81e based on the input input signal being input, and produces the effect via the relay board 607 in a serial signal system. The data is output to the control board 80. Then, the effect control CPU 101 reads the input data from the serial input circuit 354 and stores it in a predetermined storage area of the RAM (step S976). In step S976, the effect control CPU 101 controls the serial input circuit 354 to read the input data from the serial input circuit 354 after delaying by the time for which the serial input circuit 354 receives the input data from the input IC 620.

  As described above, according to this embodiment, the effect control microcomputer 100 is configured to use the LED 125a to 125f, 126a to 126f, and 281a of each lamp based on the effect control command received from the game control microcomputer 560. Control signals for controlling ˜281 l, 282 a to 282 f and 283 a to 283 f are output in a serial signal system. Further, the serial-parallel conversion ICs 616 to 619 mounted on the panel side IC substrate 601 and the serial-parallel conversion ICs 611 to 615 mounted on the frame side IC substrates 602 to 605 are connected through one system wiring. At the same time, different address information is assigned in advance, and only the control signal with its own address information added is converted into parallel data and output. In addition, when the production control microcomputer 100 outputs a control signal for controlling the serial-parallel conversion ICs 616 to 619 provided in the game board 6, address information that can identify the serial-parallel conversion ICs 616 to 619 is provided. The added control signal is output by the serial signal system. In addition, when the production control microcomputer 100 outputs a control signal for controlling the serial-parallel conversion ICs 611 to 615 provided in the game frame 11, address information that can identify the serial-parallel conversion ICs 611 to 615 is provided. The added control signal is output by the serial signal system. Therefore, the number of wirings between the game board 6 and the game frame 11 can be reduced. Therefore, in a gaming machine in which the game frame 11 and the game board 6 are configured to be detachable, it is possible to easily attach and detach the game frame 11 and the game board 6.

  Further, according to this embodiment, the serial-parallel conversion ICs 616 to 619 mounted on the board-side IC board 601 and the serial-parallel mounted on the frame-side IC boards 602 to 604 are formed by the relay boards 606 and 607. The connection with the conversion ICs 611 to 615 is relayed. Further, the relay board 607 relays the connection between the serial-parallel conversion ICs 611 to 615 mounted on the frame side IC boards 602 to 604 and the effect control microcomputer 100. Therefore, the detachment work between the game frame 11 and the game board 6 can be easily performed only by performing the connection work and the removal work to the relay boards 606 and 607.

  Further, according to this embodiment, the frame side IC substrate 602 as a collective substrate on which two serial-parallel conversions 611 and 612 are mounted is provided on the game frame 11 side. A board-side IC board 601 as a collective board on which four serial-parallel conversion ICs 616 to 619 are mounted is provided on the game board 6 side. Therefore, the boards on which the serial-parallel conversion ICs are mounted can be integrated, and the number of parts in the gaming machine can be reduced.

  Further, according to this embodiment, the serial-parallel conversion ICs 616 to 619 mounted on the board-side IC board 601 and the serial-parallel conversion ICs 611 to 615 mounted on the frame-side IC boards 602 to 605 are connected to each other. Are connected through one line of wiring. Therefore, the wiring work between the game frame 11 and the game board 6 can be performed simply by attaching and detaching the connector, and the game frame 11 and the game board 6 can be attached and detached more easily.

  Further, according to this embodiment, the game control microcomputer 560 transmits the effect control command to the effect control microcomputer 100 in the serial signal system using the serial output circuit 78. Therefore, the number of wires between the game control microcomputer 560 and the effect control microcomputer 100 can also be reduced.

  Further, according to this embodiment, the production control microcomputer 100 includes the serial-parallel conversion ICs 616 to 619 mounted on the board side IC substrate 601 and the serial-parallel conversion mounted on the frame side IC substrates 602 to 605. A clock signal used in common for the ICs 611 to 615 and the input ICs 620 and 621 is output. Therefore, the serial-parallel conversion ICs 616 to 619 mounted on the board side IC substrate 601, the serial-parallel conversion ICs 611 to 615 mounted on the frame side IC substrates 602 to 605, and the input ICs 620 and 621 can be easily synchronized. And the number of clock signal wirings can be reduced.

  In this embodiment, the production control microcomputer 100 may store the device IDs of the serial-parallel conversion ICs 611 to 619 as addresses in a predetermined address storage area of the RAM in advance. If comprised in that way, each lamp | ramp 125a-125f, 126a-126f, 281a-281l, 282a-282f, 283a-283f will be controlled using ID information intrinsic | native to serial-parallel conversion IC611-619 as address information. be able to.

  In this embodiment, the production control board 80, the relay board 606, and the relay board are connected as the production control board 80, the board side IC board 601, the frame side IC boards 602 to 605, and the relay boards 606 and 607. 607 is connected by one bus type wiring route, and the serial-parallel conversion ICs 611 to 619 mounted on the board side IC substrate 601 and the frame side IC substrates 602 to 604 are connected by one bus type wiring route. As described above, the serial-parallel conversion ICs 616 to 619 mounted on the panel side IC substrate 601 are connected in series (hereinafter also referred to as daisy chain type connection), or the frame side IC substrates 602 to 605 are connected. The serial-parallel conversion ICs 611 to 615 mounted on the PC are connected in series (daisy chain type connection), so that It may be to reduce the number.

  FIG. 70 is a block diagram illustrating another configuration example of the effect control board 80, the relay boards 606 and 607, the board-side IC board 601, and the frame-side IC boards 602, 603, 604, and 605. In the example shown in FIG. 70, the effect control microcomputer 100 of the effect control board 80 outputs a clock signal to the relay board 607 together with serial data as a control signal. The relay board 607 further supplies serial data and a clock signal input from the production control microcomputer 100 to the board side IC board 601 via the relay board 606.

  The serial data input to the board side IC substrate 601 is first input to the serial-parallel conversion IC 619. As shown in FIG. 70, the serial-parallel conversion ICs 616 to 619 mounted on the board side IC substrate 601 have serial data signal lines connected in a daisy chain type. Therefore, the input serial data is sequentially transferred from the serial-parallel conversion IC 619 to the other serial-parallel conversion ICs 616, 618, and 617 mounted on the board side IC substrate 601. For example, the configuration is such that the output of the last bit of the shift register 652 shown in FIG. What is necessary is just to forward. The serial-parallel conversion ICs 616 to 619 convert the input serial data into parallel data, and supply the parallel data to the LEDs of the lamps provided on the game board 6. The clock signal inputted to the board side IC board 601 is branched on the board side IC board 601 and inputted to the serial-parallel conversion ICs 616 to 619 and the input IC 621.

  The relay board 607 supplies the serial data and the clock signal input from the production control microcomputer 100 to the frame side IC board 604 and the frame side IC board 605. The serial data input to the frame side IC substrate 604 is first input to the serial-parallel conversion IC 614. As shown in FIG. 70, the serial-parallel conversion ICs 611 to 614 mounted on the frame side IC substrates 602 to 604 have serial data signal lines connected in a daisy chain type. Accordingly, the input serial data is sequentially transferred from the serial-parallel conversion IC 614 to the other serial-parallel conversion ICs 611 to 613 mounted on the frame side IC substrates 602 and 603. For example, the configuration is such that the output of the last bit of the shift register 652 shown in FIG. 15 is input to the data latch unit 651 of the next serial-parallel conversion IC, whereby serial data is sequentially sent to each serial-parallel conversion IC 611-614. What is necessary is just to forward. And each serial-parallel conversion IC611-614 converts the input serial data into parallel data, and supplies it to LED of each lamp provided in the game frame 11. FIG.

  The clock signal input to the frame side IC board 602 is branched on the frame side IC board 604 and input to the serial-parallel conversion IC 614 and also input to the frame side IC board 602. The clock signal input to the frame side IC substrate 602 is branched on the frame side IC substrate 602, input to each serial-parallel conversion IC 611, 612, and input to the frame side IC substrate 603. The clock signal input to the frame side IC substrate 603 is branched on the frame side IC substrate 603 and input to the serial-parallel conversion IC 613. The clock signal input to the frame side IC substrate 605 is branched on the frame side IC substrate 605 and input to the serial-parallel conversion IC 615 and the input IC 620.

  Further, in this embodiment, the effect control means receives the variation pattern command, but when the display result specifying command cannot be received, the variation pattern command that can be used for both the normal big hit and the probable big hit. If it is determined that a change pattern command other than the change pattern command that can be used at both the normal big hit and the probable big hit is received is determined. Since the stop symbol is determined to be a combination of decorative symbols corresponding to the received variation pattern, even if the display result specifying command cannot be received due to noise or the like, the variable display device 9 can notify that a big hit will occur.

Embodiment 2. FIG.
In the first embodiment, the lamp control signals with addresses are output to the serial-parallel conversion ICs 611 to 619, whereby the LEDs 125a to 125f, 126a to 126f, 281a to 281l, 282a to 282f, and 283a to 283f of the respective lamps. However, a plurality of serial-parallel conversion ICs are connected in series with the same system wiring, and a fixed signal including a lamp control signal for controlling all the lamps connected with the same system wiring is used. You may make it output the data of length. Hereinafter, by outputting data of a fixed length including a lamp control signal for controlling all lamps connected by wiring of the same system, LEDs 125a to 125f, 126a to 126f, 281a to 281l, and 282a of each lamp are output. A second embodiment for controlling ˜282f and 283a˜283f will be described.

  Note that in this embodiment, detailed description of the parts having the same configuration and processing as those of the first embodiment will be omitted, and parts different from those of the first embodiment will be mainly described.

  FIG. 71 is a block diagram illustrating a circuit configuration example of the relay board 77 and the effect control board 80 in the second embodiment. In the example shown in FIG. 71, only the effect control board 80 is provided for the effect control, but a lamp driver board and an audio output board may be provided. In this case, the lamp driver board and the sound output board are not equipped with a microcomputer, but may be equipped with a microcomputer.

  The effect control board 80 includes an effect control CPU 101, a RAM (not shown), a serial output circuit 353, a serial input circuit 354, a latch signal output unit 355, a clock signal output unit 356, and an input capture signal output unit 357. A control microcomputer 100 is mounted. The RAM may be externally attached. In the effect control board 80, the effect control CPU 101 operates in accordance with a program stored in a built-in or external ROM (not shown), and receives an effect control command via the serial input circuit 102 and the input port 103. In this case, the serial input circuit 102 converts the effect control command received by the serial signal method into parallel data and outputs the parallel data. Further, the effect control CPU 101 causes the VDP (video display processor) 109 to perform display control of the variable display device 9 based on the effect control command.

  The effect control CPU 101 outputs a signal for driving the lamp via the serial output circuit 353. The serial output circuit converts the input signal (parallel data) for driving the LED of the lamp into serial data and outputs the serial data to the relay board 606.

  In this embodiment, as will be described later, among the serial-parallel conversion ICs 611 to 615 provided on the game frame 11 side, four ICs 611 to 614 are connected in series by wires of the same system. When controlling the top frame lamp, the left frame lamp, and the right frame lamp, the effect control CPU 101 includes a lamp control signal for all the serial-parallel conversion ICs 611 to 614 connected by the same system wiring. The length data (control signal string) is output via the serial output circuit 353 in the serial signal system. Then, when the production control CPU 101 finishes outputting the fixed-length control signal sequence, the latch signal output unit 355 outputs a latch signal for causing the serial-parallel conversion ICs 611 to 614 to capture the lamp control signal. .

  Further, in this embodiment, as will be described later, serial-parallel conversion ICs 616 to 619 provided on the game board 6 side are connected in series by wires of the same system. When controlling the center decoration lamp, the stage lamp, and the lamp provided around the skeleton 153 which is a movable member, the effect control CPU 101 includes all the serial-parallel conversion ICs 616 to 616 connected by the same system wiring. Data of a fixed length including a lamp control signal for 619 (control signal string) is output via the serial output circuit 353 in a serial signal system. Then, when the production control CPU 101 finishes outputting the fixed-length control signal sequence, it causes the latch signal output unit 355 to output a latch signal for causing the serial-parallel conversion ICs 616 to 619 to capture the lamp control signal. .

  Of the serial-parallel conversion ICs 611 to 615 provided on the game frame 11 side, four ICs 615 are connected by a single wiring. When controlling the pan lamp and the operation button lamp, the effect control CPU 101 transmits a lamp control signal for the serial-parallel conversion IC 615 connected by the single wiring in a serial signal system via the serial output circuit 353. Output. Then, when the effect control CPU 101 finishes outputting the lamp control signal, it causes the latch signal output unit 355 to output a latch signal for causing the serial-parallel conversion IC 615 to capture the lamp control signal.

  FIG. 72 is a block diagram illustrating a configuration example of the effect control board 80, the relay boards 606 and 607, the board side IC board 601, and the frame side IC boards 602, 603, 604, and 605 according to the second embodiment. The effect control microcomputer 100 of the effect control board 80 outputs a clock signal to the relay board 606 together with serial data as a control signal. In addition, the production control microcomputer 100 outputs a latch signal to the relay board 606 at the timing when the serial data has been output. The relay board 606 supplies serial data, a clock signal and a latch signal input from the production control microcomputer 100 to the board side IC board 601. Further, the relay board 606 supplies serial data, a clock signal, and a latch signal to the frame side IC boards 602 to 605 via the relay board 607.

  The serial data input to the board side IC substrate 601 is first input to the serial-parallel conversion IC 619. As shown in FIG. 72, the serial-parallel conversion ICs 616 to 619 mounted on the board-side IC board 601 are connected in series with the same system wiring. The connection by the same system wiring means that a plurality of serial-parallel conversion ICs are connected in series by a so-called bead connecting wiring. For example, each serial-parallel conversion IC 616 to 619 has a serial data signal line connected in a daisy chain type. Therefore, the input serial data is sequentially transferred from the serial-parallel conversion IC 619 to the other serial-parallel conversion ICs 616, 618, and 617 mounted on the board side IC substrate 601. In this embodiment, as will be described later, the output of the last bit of the shift register 682 mounted in each serial-parallel conversion IC is input to the data latch unit 681 of the next serial-parallel conversion IC (see FIG. 73), serial data may be transferred to the serial-parallel conversion ICs 616 to 619 in order. Each of the serial-parallel conversion ICs 616 to 619 latches the serial data at the timing when the latch signal is input, converts the latched serial data into parallel data, and supplies the parallel data to the LEDs of the lamps provided on the game board 6. To do. The clock signal inputted to the board side IC board 601 is branched on the board side IC board 601 and inputted to the serial-parallel conversion ICs 616 to 619 and the input IC 621.

  The relay board 607 supplies serial data, a clock signal, and a latch signal input from the production control microcomputer 100 to the frame side IC board 604 and the frame side IC board 605. The serial data input to the frame side IC substrate 604 is first input to the serial-parallel conversion IC 614. As shown in FIG. 72, the serial-parallel conversion ICs 611 to 614 mounted on the frame-side IC substrates 602 to 604 are connected in series with the same system wiring. For example, in each of the serial-parallel conversion ICs 611 to 614, signal lines for serial data are connected in a daisy chain type (connected by so-called daisy chain wiring). Accordingly, the input serial data is sequentially transferred from the serial-parallel conversion IC 614 to the other serial-parallel conversion ICs 611 to 613 mounted on the frame side IC substrates 602 and 603. In this embodiment, as will be described later, the output of the last bit of the shift register 682 mounted in each serial-parallel conversion IC is input to the data latch unit 681 of the next serial-parallel conversion IC (see FIG. 73), serial data may be transferred to the serial-parallel conversion ICs 611 to 614 in order. And each serial-parallel conversion IC611-614 latches serial data at the timing which inputted the latch signal, converts the inputted serial data latched into parallel data, LED of each lamp provided in the game frame 11 To supply.

  The clock signal input to the frame side IC board 602 is branched on the frame side IC board 604 and input to the serial-parallel conversion IC 614 and also input to the frame side IC board 602. The clock signal input to the frame side IC substrate 602 is branched on the frame side IC substrate 602, input to each serial-parallel conversion IC 611, 612, and input to the frame side IC substrate 603. The clock signal input to the frame side IC substrate 603 is branched on the frame side IC substrate 603 and input to the serial-parallel conversion IC 613. The clock signal input to the frame side IC substrate 605 is branched on the frame side IC substrate 605 and input to the serial-parallel conversion IC 615 and the input IC 620.

  The serial data input to the frame side IC substrate 605 is input to the serial-parallel conversion IC 615. Each serial-parallel conversion IC 615 latches the serial data at the timing when the latch signal is input, converts the latched input serial data into parallel data, and provides a dish lamp and an operation button lamp provided in the game frame 11. LEDs 82a to 82d and 83 are supplied. The clock signal input to the frame side IC substrate 605 is branched on the frame side IC substrate 605 and input to the serial-parallel conversion IC 615 and the input IC 620.

  Next, the configuration of the serial-parallel conversion IC in the second embodiment will be described. FIG. 73 is a block diagram showing a configuration of each serial-parallel conversion IC in the second embodiment. 73 shows the configuration of each serial-parallel conversion IC 611-614 provided on the game frame 11 side as an example, but each serial-parallel conversion IC 616-619 provided on the game board 6 side, The configuration of another serial-parallel conversion IC 5615 provided on the game frame 11 side is also the same.

  As illustrated in FIG. 73, each serial-parallel conversion IC 611 to 614 includes a data latch unit 681, a shift register 682, and a data buffer 683. As shown in FIG. 73, the serial-parallel conversion ICs 611 to 614 are connected in series by the same system wiring in the order of IC614, IC611, IC612, and IC613.

  The data latch unit 681 is configured by, for example, a latch circuit. When serial data is input, the data latch unit 681 latches the input data bit by bit at a predetermined cycle, for example, the rising timing of the clock signal pulse, and outputs the latched data to the shift register 682. . The shift register 682 sequentially stores unit data, for example, data input bit by bit from the data latch unit 681. The shift register 682 shifts the stored data bit by bit at the rising timing of the clock signal pulse. By shifting the stored data one bit at a time, the shift register 682 is in a state where data is stored in all 8 bits. Further, when input data and a clock signal are further input, the data of the last bit of the shift register 682 is converted into a subsequent stage of the serial-parallel conversion IC (hereinafter referred to as the lower side (the input side of the serial-parallel conversion IC is referred to as the upper side). In this case, the data is input to the data latch unit 681 of the serial-parallel conversion IC. For example, in the example shown in FIG. 73, the last bit data of the shift register 682 of the IC 614 is input to the data latch unit 681 of the lower-order IC 611, and the last bit data of the shift register 682 of the IC 611 is changed to the lower-order IC 612. The data of the last bit of the shift register 682 of the IC 612 is input to the data latch unit 681 of the lower-order IC 613. By doing so, the serial data output from the production control microcomputer 100 is transferred in the order of IC614, IC611, IC612, and IC613.

  In this embodiment, the production control microcomputer 100 outputs a control signal sequence including all lamp control signals for the four serial-parallel ICs 611 to 614 in a serial signal system. In this case, the production control microcomputer 100 starts with the lamp control signal for the IC on the lower side (that is, the lamp control signal for the IC 613, the lamp control signal for the IC 612, the lamp control signal for the IC 611, and the lamp for the IC 614). A control signal sequence including the order of the control signals is output. As described above, when data is transferred in the order of IC614, IC611, IC612, and IC613, and the output of a series of control signal sequences is completed by the production control microcomputer 100, the shift register of the IC613 The lamp control signal for IC613 is stored in 682, the lamp control signal for IC612 is stored in the shift register 682 of IC612, the lamp control signal for IC611 is stored in the shift register 682 of IC611, and the shift register 682 of IC614 is stored. The lamp control signal for the IC 614 is stored. Then, the data is taken in by the serial-parallel conversion ICs 611 to 614 at the timing when the latch signal is output by the production control microcomputer 100.

  The data buffer 683 is constituted by, for example, a latch register. When a latch signal from the effect control microcomputer 100 is input, the data buffer 683 takes in and latches data stored in the shift register 682. The data buffer 683 supplies the fetched data as parallel data (Q0 to Q7) to the LED of each lamp. Note that the timing (predetermined timing) at which the latch signal is input is a timing at which the latch signal falls within a longer span than the time required to send data to the lower-level IC.

  Next, the serial setting process will be described. FIG. 74 is a flowchart illustrating an example of serial setting processing according to the second embodiment. The serial setting process is executed, for example, when a decorative symbol is variably displayed in the effect control process or when various errors are notified.

  In FIG. 74, the processes in steps S950 and S951 are the same as those described in the first embodiment. If there is a change in the display state of each lamp in step S951, the CPU 101 for effect control converts a control signal sequence including a lamp control signal for the serial-parallel conversion IC of the lamp to be controlled for display into a predetermined lamp control signal storage area. (Step S952A). Next, the effect control CPU 101 sets a control signal sequence including the extracted lamp control signal in a predetermined data storage area provided in the RAM (step S953A). Then, a lamp control signal output request flag is set (step S954).

  FIG. 75 is an explanatory diagram illustrating a configuration example of a data storage area in which a control signal sequence including a lamp control signal to be output is set in the second embodiment. In this embodiment, three data storage areas each storing a control signal sequence including a lamp control signal are prepared. In other words, the board side output data storage area for storing the control signal sequence output to each serial-parallel conversion IC 616 to 619 provided on the game board 6 side connected by the same system wiring is connected by the same system wiring. A frame-side output data storage area for storing control signal sequences output to the respective serial-parallel conversion ICs 611 to 614 provided on the game frame 11 side, and a serial-parallel conversion IC 615 provided on the game frame 11 side. A dish-side output data storage area for storing the output control signal sequence is provided.

  FIG. 76 is a flowchart illustrating a specific example of serial input / output processing (step S708) according to the second embodiment. In FIG. 76, the processes in steps S970 and S971 are the same as those described in the first embodiment. When the lamp control signal output request flag is reset, the effect control CPU 101 sends a control signal sequence (data sequence as exemplified in FIG. 68) including the lamp control signal stored in the data storage area to the serial output circuit 353. Output (step S972A). Then, the output control signal sequence including the lamp control signal is converted into serial data by the serial output circuit 353, and is sent to the panel side IC substrate 601 and the frame side IC substrates 602 to 605 via the relay substrates 606 and 607. It will be output in the serial signal system. Next, the production control CPU 101 requires a predetermined time (from the time when the control signal sequence is output to the serial output circuit 353 to the time when the output to the board side IC substrate 601 and the frame side IC substrates 602 to 605 is completed by the serial signal method. After the elapse of time, the latch signal output unit 355 is caused to output a latch signal to each frame side IC substrate 602 to 605 (step S972B).

  When the control signal sequence is stored in any one of the three data storage areas shown in FIG. 75, the effect control CPU 101 repeatedly executes the processes of steps S972A and S972B a plurality of times. For example, if the control signal sequence is stored in all three data storage areas shown in FIG. 75, the effect control CPU 101 first extracts the control signal sequence from the board-side output data storage area and outputs the serial output signal. The data is output to the circuit 353 (see step S972A). Then, after a predetermined time has elapsed, the latch signal output unit 355 is caused to output a latch signal to the board side IC substrate 601 (see step S972B). Next, the effect control CPU 101 extracts a control signal sequence from the frame-side output data storage area and outputs it to the serial output circuit 353 (see step S972A). Then, after a predetermined time has elapsed, the latch signal output unit 355 is caused to output a latch signal to the frame side IC substrates 602 to 604 (see step S972B). Next, the effect control CPU 101 extracts the lamp control signal from the dish-side output data storage area and outputs it to the serial output circuit 353 (see step S972A). Then, after a predetermined time has elapsed, the latch signal output unit 355 is caused to output a latch signal to the frame side IC substrate 605 (see step S972B).

  Note that the processes in steps S973 to S976 are the same as those described in the first embodiment.

  As described above, according to this embodiment, the effect control microcomputer 100 is based on the effect control command received from the game control microcomputer 560, and the LEDs 125a to 125f, 126a to 126f, 281a to 281l of the respective lamps. , 282a to 282f, 283a to 283f, and the like are output in a serial signal system. Further, the serial-parallel conversion ICs 616 to 619 mounted on the panel side IC substrate 601 and the serial-parallel conversion ICs 611 to 615 mounted on the frame side IC substrates 602 to 605 are connected through one system wiring. The Therefore, the number of wirings between the game board 6 and the game frame 11 can be reduced. Therefore, in a gaming machine in which the game frame 11 and the game board 6 are configured to be detachable, it is possible to easily attach and detach the game frame 11 and the game board 6.

  In addition, according to this embodiment, the production control microcomputer 100 has a fixed length including control signal information of all production electrical parts (lamps and motors) connected in series to the same system wiring. This data is output in units of unit data (for example, 1 bit) at a predetermined cycle (for example, the cycle of the clock signal) in a serial signal system. Therefore, it is not necessary to assign different addresses to the serial-parallel conversion ICs 616 to 619 mounted on the board side IC substrate 601 and the serial-parallel conversion ICs 611 to 615 mounted on the frame side IC substrates 602 to 605 in advance. Can do.

  In this embodiment, the serial-parallel conversion ICs 616 to 619 mounted on the board side IC substrate 601 are connected by the same system wiring, and the serial-parallel ICs 602 to 604 mounted on the frame side IC substrate 602 to 604 are connected. Although the case where the parallel conversion ICs 611 to 614 are connected by the same system wiring has been described, the serial conversion parallel ICs 616 to 619 and the frame side IC substrates 602 to 605 mounted on the board side IC substrate 601 are mounted. All of the serial-parallel conversion ICs 611 to 615 may be connected by wiring of the same system.

  FIG. 77 is a block diagram illustrating another configuration example of the effect control board 80, the relay boards 606 and 607, the board side IC board 601, and the frame side IC boards 602, 603, 604, and 605 according to the second embodiment. . In FIG. 77, all the serial-parallel conversion ICs 616 to 619 mounted on the board side IC substrate 601 and the serial-parallel conversion ICs 611 to 615 mounted on the frame side IC substrates 602 to 605 are all of the same system wiring. Connected.

  In the example shown in FIG. 77, the serial data output from the production control microcomputer 100 is first input to the serial-parallel conversion IC 619 mounted on the board-side IC board 601 via the relay board 606. The input serial data is sequentially transferred from the serial-parallel conversion IC 619 to the other serial-parallel conversion ICs 616, 618, and 617 mounted on the board side IC substrate 601.

  Further, the lowest-order serial-parallel conversion IC 617 mounted on the board-side IC board 601 further outputs serial data to the relay board 606. The serial data is input from the relay board 606 to the serial-parallel conversion IC 614 mounted on the frame side IC board 604 via the relay board 607. The input serial data is sequentially transferred from the serial-parallel conversion IC 614 to the other serial-parallel conversion ICs 611, 612, 613, 615 mounted on the frame side IC substrates 602 to 605.

Embodiment 3 FIG.
In the first embodiment, all effect means (variable display device 9, sound output device (speaker) 27 and LEDs 125a to 125f, 126a to 126f, 281a to 281l, 282a to 282f, 283a to 283f) has been described, but each rendering means may be controlled using separate control boards. Hereinafter, a sound / lamp control board for controlling the sound output device 27 and the LEDs 125a to 125f, 126a to 126f, 281a to 281l, 282a to 282f, and 283a to 283f of the lamps, and a symbol control board for controlling the variable display device 9 A third embodiment including the above will be described.

  Note that in this embodiment, detailed description of the parts having the same configuration and processing as those of the first embodiment will be omitted, and parts different from those of the first embodiment will be mainly described.

  FIG. 78 is a block diagram illustrating a circuit configuration example of the relay board 77, the sound / lamp control board 80b, and the symbol control board 80a according to the third embodiment. In this embodiment, the sound / lamp control board 80b performs sound output control of the sound output device 27 and display control of the LEDs 125a to 125f, 126a to 126f, 281a to 281l, 282a to 282f, and 283a to 283f of each lamp. . The symbol control board 80a performs display control of the variable display device 9. In this embodiment, “effect control” includes display control of the variable display device 9, sound output control of the speaker 27, LEDs 125a to 125f, 126a to 126f, 281a to 281l, 282a to 282f of each lamp, By performing display control of 283a to 283f, it means performing an effect such as a game effect. Further, in this embodiment, the effect control means includes a symbol control microcomputer 100a that performs display control of the variable display device 9, sound output control of the speaker 27, and LEDs 125a to 125f, 126a to 126f, and 281a of each lamp. ˜281 l, 282 a to 282 f and 283 a to 283 f are realized by the sound / lamp control microcomputer 100 b which performs display control.

  The sound / lamp control board 80b includes a sound / lamp control microcomputer 100b including a sound / lamp control CPU 101b, a RAM, a serial output circuit 353, a serial input circuit 354, a clock signal output unit 356, and an input capture signal output unit 357. It is equipped with. The RAM may be externally attached. In the sound / lamp control board 80b, the sound / lamp control microcomputer 100b operates in accordance with a program stored in a built-in or external ROM (not shown).

  Further, the sound / lamp control microcomputer 100 b outputs a signal for driving the lamp via the serial output circuit 353. The serial output circuit converts the input signal (parallel data) for driving the LED of the lamp into serial data and outputs the serial data to the relay board 606.

  Further, the clock signal output unit 356 outputs a clock signal to the relay board 606. The clock signal from the clock signal output unit 356 is supplied to the serial-parallel conversion ICs 611 to 615 and the input IC 620 mounted on the frame side IC substrates 602 to 605 via the relay substrate 606. The clock signal from the clock signal output unit 356 is supplied to the serial-parallel conversion ICs 616 to 619 and the input IC 621 mounted on the board side IC substrate 601 via the relay substrate 606. Therefore, in this embodiment, a common clock signal is supplied to the serial-parallel conversion ICs 611 to 619 and the input ICs 620 and 621.

  Further, the input capture signal output unit 357 inputs the input capture signal (latch signal) to the board side IC board 601 or the frame side IC boards 602 to 605 via the relay boards 606 and 607 in accordance with the instruction of the effect control CPU 101. Is output. The input IC 620 mounted on the frame side IC board 605 latches the detection signals of the operation buttons 81a to 81e when an input input signal from the sound / lamp control microcomputer 100b is input, and relays the board 606 in a serial signal system. , 607 to the sound / lamp control microcomputer 100b. The input IC 621 mounted on the board-side IC board 601 latches the detection signals of the position sensors 151b, 152b, and 153b when the input capture signal from the sound / lamp control microcomputer 100b is input, and the serial signal And output to the sound / lamp control microcomputer 100b via the relay substrate 606.

  The sound / lamp control microcomputer 100b outputs the sound number data to the speech synthesis IC 173. The voice synthesizing IC 173 generates a voice or a sound effect corresponding to the sound number data and outputs it to the amplifier circuit 175. The amplifier circuit 175 outputs an audio signal obtained by amplifying the output level of the speech synthesis IC 173 to a level corresponding to the volume set by the volume 176 to the speaker 27. The voice data ROM 174 stores control data corresponding to the sound number data. The control data corresponding to the sound number data is a collection of data indicating the sound effect or sound output mode in a time series in a predetermined period (for example, a decorative symbol variation period).

  The signal for driving the lamp and the sound number data are communicated between the sound / lamp control microcomputer 100b, the lamp driver 352, and the speech synthesis IC 173 (a response signal is transmitted from the signal receiving side to the transmitting side). Communication).

  The symbol control board 80a is equipped with a symbol control microcomputer 100a including a symbol control CPU 101a and RAM. The RAM may be externally attached. In the symbol control board 80a, the symbol control microcomputer 100a operates in accordance with a program stored in a built-in or external ROM (not shown). Further, the symbol control microcomputer 100a performs display control of the variable display device 9 using the LCD on the VDP (video display processor) 109 based on the effect control command received from the main board 31 via the relay board 77. Let it be done.

  The symbol control microcomputer 100a reads necessary data from a character ROM (not shown) in accordance with the effect control command received from the game control microcomputer 560. The character ROM stores character image data that is frequently used among images displayed on the variable display device 9, specifically, people, characters, figures, symbols, and the like (including decorative designs). Is. The symbol control microcomputer 100 a outputs the data read from the character ROM to the VDP 109. The VDP 109 executes display control of the variable display device 9 based on data input from the symbol control microcomputer 100a.

  In this embodiment, the VDP 109 that performs display control of the variable display device 9 is mounted on the symbol control board 80a. The VDP 109 has an address space independent of the symbol control microcomputer 100a, and maps a VRAM therein. The VRAM is a buffer memory for expanding image data generated by the VDP. Then, the VDP 109 outputs the image data in the VRAM to the variable display device 9.

  As a signal direction regulating means, a signal inputted from the main board 31 is allowed to pass through the relay board 77 only in a direction toward the symbol control board 80a (a signal is not passed in the direction from the symbol control board 80a to the relay board 77). The unidirectional circuit is installed. For example, a diode or a transistor is used as the unidirectional circuit. FIG. 78 illustrates a diode.

  In addition, the symbol control microcomputer 100 a transmits (transfers) an effect control command (a variation pattern command or a display result designation command) from the main board 31 to the sound / lamp control board 80 b via the input / output port 104.

  FIG. 79 shows a configuration example of the symbol control board 80a, the sound / lamp control board 80b, the relay boards 606 and 607, the board side IC board 601, and the frame side IC boards 602, 603, 604, and 605 in the third embodiment. FIG. The sound / lamp control microcomputer 100b of the sound / lamp control board 80b (specifically, the sound / lamp control CPU 101b) outputs a clock signal to the relay board 607 together with serial data as a control signal. In addition, an input capture signal for causing the input ICs 620 and 621 to latch the input signal is output to the relay board 606.

  The relay board 606 supplies the serial data and the clock signal input from the sound / lamp control microcomputer 100 b to the serial-parallel conversion ICs 616 to 619 mounted on the board side IC board 601. And each serial-parallel conversion IC616-619 converts the input serial data into parallel data, LEDLED125a-125f of each lamp provided in the game board 6, 126a-126f, 127a-127c, and each movable member The motors 151a to 151c are supplied.

  Further, the relay board 607 is connected to the relay board 606 through one bus-type wiring route, and the serial data line 300 and the clock signal line 301 connected to the serial-parallel conversion ICs 616 to 619 are the board side IC board. 601 is connected in a bus format.

  In addition, an input IC 621 for inputting a detection signal of a position sensor of each movable member provided on the game board 6 is mounted on the board side IC board 601. In this embodiment, the input IC 621 and the sound / lamp control microcomputer 100b mounted on the board side IC board 601 are connected via the relay board 606 to the input signal line, the clock signal line 301 and the input take-in signal line 303. Are connected, and the sound / lamp control microcomputer 100b outputs an input capture signal to the input IC 621 via the relay board 606 at a predetermined timing. Then, the input IC 621 latches the detection signal of each position sensor based on the input capture signal (latch signal) and outputs it to the sound / lamp control microcomputer 100b via the relay board 606. In this case, the input IC 621 converts the detection signal input in parallel from each position sensor into serial data and outputs it.

  As shown in FIG. 79, the serial data and the clock signal input to the relay board 607 are supplied to the serial-parallel conversion ICs 611 to 615 mounted on the frame side IC boards 602 to 605, respectively. And each serial-parallel conversion IC611-615 converts the input serial data into parallel data, LED281a-281l of each lamp provided in the game frame 11, 282a-282f, 283a-283f, 82a-82d, 83.

The serial data lines and clock signal lines connected to the serial-parallel conversion ICs 611 to 614 are connected in a bus format on the frame side IC substrates 602 to 604. In this embodiment, as shown in FIG. 79, first, the serial-parallel conversion IC 614 of the frame side IC substrate 604 is input, and the serial-parallel conversion IC 614 and the serial-parallel conversion IC 611 and the serial-parallel of the frame side IC substrate 602 are input. The signals are input in the order of the parallel conversion IC 612, and further input from the serial-parallel conversion IC 612 to the serial-parallel conversion IC 613 of the frame side IC substrate 603. The serial data line 300 and the clock signal line 301 connected to the serial-parallel conversion IC 615 are directly connected from the relay substrate 607.

  In addition, an input IC 620 for inputting detection signals of the operation buttons 81 a to 81 e provided on the game frame 11 is mounted on the frame side IC board 605. In this embodiment, the input IC 620 and the sound / lamp control microcomputer 100b mounted on the frame side IC substrate 605 are connected to the input signal line 302, the clock signal line 301, and the input capture signal line via the relay substrate 607. The sound / lamp control microcomputer 100b is connected to the input IC 620 via the relay boards 606 and 607 at a predetermined timing. In this case, the sound / lamp control microcomputer 100b outputs the input capture signal to the input IC 620 at a timing different from the timing of outputting the input capture signal to the input IC 621. Then, the input IC 620 latches the detection signals from the operation buttons 81a to 81e based on the input capture signal (latch signal), and outputs it to the sound / lamp control microcomputer 100b via the relay boards 606 and 607. In this case, the input IC 620 converts detection signals input in parallel from the operation buttons 81a to 81e into serial data and outputs the serial data.

  In this embodiment, each serial-parallel conversion IC 611-619 is assigned an address in advance, and the sound / lamp control microcomputer 100b is assigned an address when outputting a control signal converted into serial data. Output serial data. When each serial-parallel conversion IC 611-619 inputs serial data, it checks whether the address added to the input serial data matches its own address, and if it matches, converts it to parallel data. To the LED of each lamp. If the addresses do not match, the LED of each lamp is not supplied.

  Next, the operation of the symbol control microcomputer 100a will be described. FIG. 80 is a flowchart showing main processing executed by the symbol control microcomputer 100a according to the third embodiment. When power supply to the gaming machine is started and the reset signal becomes high level, the symbol controlling microcomputer 100a starts main processing. In the main process, the symbol control microcomputer 100a first performs an initialization process for clearing the RAM area, setting various initial values, and initializing a timer for determining the activation control activation interval ( Step S781). Thereafter, the symbol controlling microcomputer 100a shifts to a loop process for confirming monitoring of the timer interrupt flag (step S782). When a timer interrupt occurs, the symbol control microcomputer 100a sets a timer interrupt flag in the timer interrupt process. If the timer interrupt flag is set in the main process, the symbol control microcomputer 100a clears the flag (step S783) and executes the following symbol control process.

  A timer interrupt takes, for example, every 33 ms. That is, the symbol control process is activated every 33 ms, for example. In this embodiment, only the flag is set in the timer interrupt process, and the specific symbol control process is executed in the main process. However, the symbol control process may be executed in the timer interrupt process.

  In the symbol control process, the symbol control microcomputer 100a first analyzes the received effect control command (command analysis process: step S784). In this case, the symbol control microcomputer 100a is similar to the command analysis processing (command analysis processing executed by the effect control microcomputer 100 shown in FIGS. 41 to 43) shown in the first embodiment. The effect control command is analyzed according to

  Next, the symbol control microcomputer 100a performs symbol control process processing (step S785). In this case, the symbol control microcomputer 100a performs processing according to the same processing as the effect control process shown in the first embodiment (the effect control process executed by the effect control microcomputer 100 shown in FIG. 49) ( However, only the part related to the control of the variable display device 9 is executed.

  Then, the symbol controlling microcomputer 100a executes a process of updating the random number counter (step S786). Further, notification control process processing for performing notification using the variable display device 9 is executed (step S787). In this case, the symbol control microcomputer 100a executes the same processing as the notification processing using the variable display device 9 in the notification control process shown in the first embodiment.

  Further, the symbol control microcomputer 100a performs a process of sending (transferring) the effect control command received from the main board 31 to the sound / lamp control board 80b (command control process: step S788). Thereafter, the process returns to the process of checking the timer interrupt flag in step S782.

  In the command control process of step S788, the symbol control microcomputer 100a may transmit the effect control command received from the game control microcomputer 560 to the sound / lamp control microcomputer 100b as it is, or the received effect. The control command may be processed and transmitted to the sound / lamp control microcomputer 100b. For example, the symbol control microcomputer 100a may recreate the variation pattern command and the display result command into one effect control command, and transmit it to the sound / lamp control microcomputer 100b. In this case, for example, the design control microcomputer 100a newly creates an effect control command that can specify only the type and effect time of the effect to be executed during the variation of the decorative symbol based on the change pattern command and the display result command. It is generated and transmitted to the sound / lamp control microcomputer 100b. With this configuration, the number of commands transmitted from the symbol control microcomputer 100a to the sound / lamp control microcomputer 100b can be reduced.

  Next, the operation of the sound / lamp control microcomputer 100b will be described. FIG. 81 is a flowchart showing a main process executed by the sound / lamp control microcomputer 100b according to the third embodiment. When power supply to the gaming machine is started and the reset signal becomes high level, the sound / lamp control microcomputer 100b starts main processing. In the main process, the sound / lamp control microcomputer 100b first performs an initialization process for clearing the RAM area, setting various initial values, initializing a timer for determining the activation control activation interval, and the like. This is performed (step S881). Thereafter, the sound / lamp control microcomputer 100b proceeds to a loop process for monitoring the timer interrupt flag (step S882). When a timer interrupt occurs, the sound / lamp control microcomputer 100b sets a timer interrupt flag in the timer interrupt process. If the timer interrupt flag is set in the main process, the sound / lamp control microcomputer 100b clears the flag (step S883) and executes the following sound / lamp control process.

  A timer interrupt takes, for example, every 33 ms. That is, the sound / lamp control process is activated every 33 ms, for example. In this embodiment, only the flag is set in the timer interrupt process, and the specific sound / lamp control process is executed in the main process, but the sound / lamp control process is executed in the timer interrupt process. Also good.

  In the sound / lamp control process, the sound / lamp control microcomputer 100b first analyzes the effect control command received from the symbol control microcomputer 100a (command analysis process: step S884). In this case, the sound / lamp control microcomputer 100b is the same as the command analysis process (command analysis process executed by the effect control microcomputer 100 shown in FIGS. 41 to 43) shown in the first embodiment. The effect control command is analyzed in accordance with the process.

  Next, the sound / lamp control microcomputer 100b performs a sound / lamp control process (step S885). In this case, the sound / lamp control microcomputer 100b follows the same process as the effect control process shown in the first embodiment (the effect control process executed by the effect control microcomputer 100 shown in FIG. 49). The processing (however, only the part relating to the control of the LED 27a to 125f, 126a to 126f, 281a to 281l, 282a to 282f, and 283a to 283f of the speaker 27 and each lamp) is executed.

  Then, the sound / lamp control microcomputer 100b executes a process of updating the random number counter (step S886). Further, a notification control process for performing notification using the speaker 27 and the LEDs 125a to 125f, 126a to 126f, 281a to 281l, 282a to 282f, and 283a to 283f of the lamps is executed (step S887). In this case, the sound / lamp control microcomputer 100b includes the speaker 27 and the LEDs 125a to 125f, 126a to 126f, 281a to 281l, 282a to 282f of the lamps in the notification control process shown in the first embodiment. Processing similar to the notification processing using 283a to 283f is executed. Further, the data set in the command analysis process, the sound / lamp control process process, and the notification control process process is output to the serial output circuit 353, and the data received from the input ICs 620 and 621 is read from the serial input circuit 354. Output processing is executed (step S888). Thereafter, the process proceeds to step S882.

  As described above, according to this embodiment, the sound / lamp control microcomputer 100b uses the LED 125a to 125f, 126a to 126f, 126a to 126f of each lamp based on the effect control command transferred from the symbol control microcomputer 100a. Control signals for controlling 281a to 281l, 282a to 282f, and 283a to 283f are output in a serial signal system. Further, the serial-parallel conversion ICs 616 to 619 mounted on the panel side IC substrate 601 and the serial-parallel conversion ICs 611 to 615 mounted on the frame side IC substrates 602 to 605 are connected through one system wiring. At the same time, different address information is assigned in advance, and only the control signal with its own address information added is converted into parallel data and output. Further, when the sound / lamp control microcomputer 100b outputs a control signal for controlling the serial-parallel conversion ICs 616 to 619 provided in the game board 6, an address that can specify the serial-parallel conversion ICs 616 to 619 is specified. A control signal with information added is output in a serial signal system. Further, when the sound / lamp control microcomputer 100b outputs a control signal for controlling the serial-parallel conversion ICs 611 to 615 provided in the game frame 11, an address that can identify the serial-parallel conversion ICs 611 to 615. A control signal with information added is output in a serial signal system. Therefore, similarly to the first embodiment, the number of wirings between the game board 6 and the game frame 11 can be reduced. Therefore, in a gaming machine in which the game frame 11 and the game board 6 are configured to be detachable, it is possible to easily attach and detach the game frame 11 and the game board 6.

  In this embodiment, the pattern / control board 80a, the sound / lamp control board 80b, the board-side IC board 601, the frame-side IC boards 602-605, and the relay boards 606, 607 are connected as sound / lamp control. Although the case where the board 80b, the relay board 606, and the relay board 607 are connected by one bus type wiring route has been described, the serial-parallel conversion ICs 616 to 619 mounted on the board side IC board 601 are connected in series ( The number of wires can be reduced by connecting the serial-parallel conversion ICs 611 to 615 mounted on the frame side IC substrates 602 to 605 in series (for example, daisy chain connection). May be.

  82 shows another configuration of the symbol control board 80a, the sound / lamp control board 80b, the relay boards 606 and 607, the board side IC board 601, and the frame side IC boards 602, 603, 604, and 605 according to the third embodiment. It is a block diagram which shows an example. In the example shown in FIG. 82, the sound / lamp control microcomputer 100b (specifically, the sound / lamp control CPU 101b) of the sound / lamp control board 80b sends the clock signal together with the serial data as the control signal to the relay board. The data is output to 606, respectively. The relay board 606 supplies the serial data and the clock signal input from the sound / lamp control microcomputer 100 b to the relay board 607 and the board side IC board 601.

  The serial data input to the board side IC substrate 601 is first input to the serial-parallel conversion IC 619. As shown in FIG. 82, the serial-parallel conversion ICs 616 to 619 mounted on the board side IC substrate 601 have serial data signal lines connected in a daisy chain type. Therefore, the input serial data is sequentially transferred from the serial-parallel conversion IC 619 to the other serial-parallel conversion ICs 616, 618, and 617 mounted on the board side IC substrate 601. For example, the configuration is such that the output of the last bit of the shift register 652 shown in FIG. What is necessary is just to forward. The serial-parallel conversion ICs 616 to 619 convert the input serial data into parallel data, and supply the parallel data to the LEDs of the lamps provided on the game board 6. The clock signal inputted to the board side IC board 601 is branched on the board side IC board 601 and inputted to the serial-parallel conversion ICs 616 to 619 and the input IC 621.

  The relay board 607 supplies the serial data and the clock signal input from the production control microcomputer 100 to the frame side IC board 604 and the frame side IC board 605. The serial data input to the frame side IC substrate 604 is first input to the serial-parallel conversion IC 614. As shown in FIG. 82, the serial-parallel conversion ICs 611 to 614 mounted on the frame side IC substrates 602 to 604 have serial data signal lines connected in a daisy chain type. Accordingly, the input serial data is sequentially transferred from the serial-parallel conversion IC 614 to the other serial-parallel conversion ICs 611 to 613 mounted on the frame side IC substrates 602 and 603. For example, the configuration is such that the output of the last bit of the shift register 652 shown in FIG. 15 is input to the data latch unit 651 of the next serial-parallel conversion IC, whereby serial data is sequentially sent to each serial-parallel conversion IC 611-614. What is necessary is just to forward. And each serial-parallel conversion IC611-614 converts the input serial data into parallel data, and supplies it to LED of each lamp provided in the game frame 11. FIG.

  The clock signal input to the frame side IC board 602 is branched on the frame side IC board 604 and input to the serial-parallel conversion IC 614 and also input to the frame side IC board 602. The clock signal input to the frame side IC substrate 602 is branched on the frame side IC substrate 602, input to the serial-parallel conversion ICs 611 and 612, and input to the frame side IC substrate 603. The clock signal input to the frame side IC substrate 603 is branched on the frame side IC substrate 603 and input to the serial-parallel conversion IC 613. The clock signal input to the frame side IC substrate 605 is branched on the frame side IC substrate 605 and input to the serial-parallel conversion IC 615 and the input IC 620.

  In this embodiment, the lamp control signals with addresses are output to the serial-parallel conversion ICs 611 to 619, whereby the LEDs 125a to 125f, 126a to 126f, 281a to 281l, 282a to 282f, and 283a to 283f of the respective lamps. In the same way as in the second embodiment, a plurality of serial-parallel conversion ICs are connected in series with the same system wiring, and all lamps connected with the same system wiring are connected. You may make it output the data of fixed length containing the lamp control signal for controlling.

  FIG. 83 is a block diagram illustrating another circuit configuration example of the relay board 77, the sound / lamp control board 80b, and the symbol control board 80a according to the third embodiment. In the example shown in FIG. 83, the sound / lamp control board 80b includes a sound / lamp control CPU 101b, a RAM, a serial output circuit 353, a serial input circuit 354, a latch signal output unit 355, a clock signal output unit 356, and an input capture signal. A sound / lamp control microcomputer 100b including an output unit 357 is mounted. The RAM may be externally attached. In the sound / lamp control board 80b, the sound / lamp control microcomputer 100b operates in accordance with a program stored in a built-in or external ROM (not shown).

  The sound / lamp control CPU 101 b outputs a signal for driving the lamp via the serial output circuit 353. The serial output circuit 353 converts the input signal (parallel data) for driving the LED of the lamp into serial data and outputs the serial data to the relay board 606.

  In the example shown in FIG. 83, as in the second embodiment, four ICs 611 to 614 out of the serial-parallel conversion ICs 611 to 615 provided on the game frame 11 side are connected in series with the same system wiring. Yes. When controlling the top frame lamp, the left frame lamp, and the right frame lamp, the sound / lamp control CPU 101b outputs lamp control signals for all the serial-parallel conversion ICs 611 to 614 connected by the same system wiring. The data having a fixed length (control signal sequence) is output via the serial output circuit 353 in the serial signal system. When the sound / lamp control CPU 101b finishes outputting the fixed-length control signal sequence, the latch signal output unit 355 supplies a latch signal for causing the serial-parallel conversion ICs 611 to 614 to capture the lamp control signal. Output.

  In the example shown in FIG. 83, as in the second embodiment, serial-parallel conversion ICs 616 to 619 provided on the game board 6 side are connected in series by wires of the same system. When controlling the center decoration lamp, the stage lamp, and the lamp provided around the skeleton 153 which is a movable member, the sound / lamp control CPU 101b is connected to all the serial-parallel conversions connected by the same system wiring. The fixed-length data (control signal string) including the lamp control signals for the ICs 616 to 619 is output via the serial output circuit 353 in the serial signal system. When the sound / lamp control CPU 101b finishes outputting the fixed-length control signal sequence, the latch signal output unit 355 provides a latch signal for causing the serial-parallel conversion ICs 616 to 619 to capture the lamp control signal. Output.

  As in the second embodiment, four ICs 615 among the serial-parallel conversion ICs 611 to 615 provided on the game frame 11 side are connected by a single wiring. When controlling the pan lamp or the operation button lamp, the sound / lamp control CPU 101b sends the lamp control signal for the serial-parallel conversion IC 615 connected by the single wiring to the serial signal via the serial output circuit 353. Output in the method. When the sound / lamp control CPU 101b finishes outputting the lamp control signal, the sound / lamp control CPU 101b causes the latch signal output unit 355 to output a latch signal for causing the serial-parallel conversion IC 615 to capture the lamp control signal.

  FIG. 84 shows still another example of the symbol control board 80a, the sound / lamp control board 80b, the relay boards 606 and 607, the board side IC board 601, and the frame side IC boards 602, 603, 604, and 605 according to the third embodiment. It is a block diagram which shows the example of a structure. The sound / lamp control microcomputer 100b of the sound / lamp control board 80 outputs a clock signal to the relay board 606 together with serial data as a control signal. The sound / lamp control microcomputer 100b outputs a latch signal to the relay board 607 at the timing when the serial data has been output. The relay board 606 supplies serial data, a clock signal, and a latch signal input from the sound / lamp control microcomputer 100 b to the board side IC board 601. Further, the relay board 606 supplies serial data, a clock signal, and a latch signal to the frame side IC boards 602 to 605 via the relay board 607.

  The serial data input to the board side IC substrate 601 is first input to the serial-parallel conversion IC 619. As shown in FIG. 84, the serial-parallel conversion ICs 616 to 619 mounted on the board-side IC substrate 601 are connected in series with the same system wiring. For example, each serial-parallel conversion IC 616 to 619 has a serial data signal line connected in a daisy chain type. Therefore, the input serial data is sequentially transferred from the serial-parallel conversion IC 619 to the other serial-parallel conversion ICs 616, 618, and 617 mounted on the board side IC substrate 601. In the example shown in FIG. 84, the output of the last bit of the shift register 682 mounted in each serial-parallel conversion IC is input to the data latch unit 681 of the next serial-parallel conversion IC, as in the second embodiment. With this configuration (see FIG. 73), serial data may be sequentially transferred to the serial-parallel conversion ICs 616 to 619. Each of the serial-parallel conversion ICs 616 to 619 latches the serial data at the timing when the latch signal is input, converts the latched serial data into parallel data, and supplies the parallel data to the LEDs of the lamps provided on the game board 6. To do. The clock signal inputted to the board side IC board 601 is branched on the board side IC board 601 and inputted to the serial-parallel conversion ICs 616 to 619 and the input IC 621.

  The relay board 607 supplies serial data, a clock signal, and a latch signal input from the sound / lamp control microcomputer 100 b to the frame side IC board 604 and the frame side IC board 605. The serial data input to the frame side IC substrate 604 is first input to the serial-parallel conversion IC 614. As shown in FIG. 84, the serial-parallel conversion ICs 611 to 614 mounted on the frame side IC substrates 602 to 604 are connected in series by the same system wiring. For example, each serial-parallel conversion IC 611 to 614 has serial data signal lines connected in a daisy chain type. Accordingly, the input serial data is sequentially transferred from the serial-parallel conversion IC 614 to the other serial-parallel conversion ICs 611 to 613 mounted on the frame side IC substrates 602 and 603. In the example shown in FIG. 84, the output of the last bit of the shift register 682 mounted in each serial-parallel conversion IC is input to the data latch unit 681 of the next serial-parallel conversion IC, as in the second embodiment. With this configuration (see FIG. 73), serial data may be sequentially transferred to the serial-parallel conversion ICs 611 to 614. And each serial-parallel conversion IC611-614 latches serial data at the timing which inputted the latch signal, converts the inputted serial data latched into parallel data, LED of each lamp provided in the game frame 11 To supply.

  The clock signal input to the frame side IC board 602 is branched on the frame side IC board 604 and input to the serial-parallel conversion IC 614 and also input to the frame side IC board 602. The clock signal input to the frame side IC substrate 602 is branched on the frame side IC substrate 602, input to each serial-parallel conversion IC 611, 612, and input to the frame side IC substrate 603. The clock signal input to the frame side IC substrate 603 is branched on the frame side IC substrate 603 and input to the serial-parallel conversion IC 613. The clock signal input to the frame side IC substrate 605 is branched on the frame side IC substrate 605 and input to the serial-parallel conversion IC 615 and the input IC 620.

  The serial data input to the frame side IC substrate 605 is input to the serial-parallel conversion IC 615. Each serial-parallel conversion IC 615 latches the serial data at the timing when the latch signal is input, converts the latched input serial data into parallel data, and provides a dish lamp and an operation button lamp provided in the game frame 11. LEDs 82a to 82d and 83 are supplied. The clock signal input to the frame side IC substrate 605 is branched on the frame side IC substrate 605 and input to the serial-parallel conversion IC 615 and the input IC 620.

  In the example shown in FIGS. 83 and 84, each serial-parallel conversion IC is configured similarly to the configuration shown in the second embodiment (see FIG. 73). In the example shown in FIGS. 83 and 84, the control signal sequence including the lamp control signal in the second embodiment is used. In the example shown in FIGS. 83 and 84, the sound / lamp control microcomputer 100b (specifically, the sound / lamp control CPU 101b) is the production control microcomputer 100 shown in the second embodiment. The serial setting process and the serial input / output process are executed in accordance with the same process (see FIGS. 74 to 76).

  If configured as shown in FIGS. 83 and 84, the sound / lamp control microcomputer 100b is provided with the LEDs 125a to 125f, 126a to 126f, 126a to 126f of the respective lamps based on the effect control commands transferred from the design control microcomputer 100a. Control signals for controlling 281a to 281l, 282a to 282f, and 283a to 283f are output in a serial signal system. Further, the serial-parallel conversion ICs 616 to 619 mounted on the panel side IC substrate 601 and the serial-parallel conversion ICs 611 to 615 mounted on the frame side IC substrates 602 to 605 are connected through one system wiring. The Therefore, similarly to the second embodiment, the number of wirings between the game board 6 and the game frame 11 can be reduced. Therefore, in a gaming machine in which the game frame 11 and the game board 6 are configured to be detachable, it is possible to easily attach and detach the game frame 11 and the game board 6.

  In this embodiment, as an example of controlling each presentation means using separate control boards, a case has been described in which a gaming machine includes a symbol control board 80a and a sound / lamp control board 80b. A plurality of control boards may be provided. For example, the gaming machine has a symbol / sound control board that controls the variable display device 9 and the speaker 27, and lamps that control the LEDs 125a to 125f, 126a to 126f, 281a to 281l, 282a to 282f, and 283a to 283f of each lamp. And a control board. In this case, for example, the symbol / sound control microcomputer mounted on the symbol / sound control board first receives an effect control command from the game control microcomputer 560 and transfers (transmits) it to the lamp control board. Then, the lamp control microcomputer mounted on the lamp control board outputs a control signal in a serial signal system based on the transferred effect control command, thereby allowing the LEDs 125a to 125f, 126a to 126f, 281a to 281l, 282a to 282f, 283a to 283f are controlled.

  Further, for example, the gaming machine controls the variable display device 9 and the pattern / lamp control board for controlling the LEDs 125a to 125f, 126a to 126f, 281a to 281l, 282a to 282f, and 283a to 283f of the lamps, and the speaker 27. And a sound control board to be provided. In this case, for example, the sound control microcomputer mounted on the sound control board first receives an effect control command from the game control microcomputer 560 and transfers (transmits) it to the symbol / lamp control board. Then, the symbol / lamp control microcomputer mounted on the symbol / lamp control board outputs a control signal in a serial signal system based on the transferred presentation control command, thereby causing the LEDs 125a to 125f and 126a to 126- 126f, 281a to 281l, 282a to 282f, 283a to 283f are controlled.

  As described above, in the above embodiment, the gaming machine controls a lamp provided in the gaming machine by outputting a driving signal to the lamp (for example, for effect control). A microcomputer 100), and the lamp control means includes brightness change control means for controlling the brightness level of the lamp by controlling the length of the ON period of the drive signal output in unit time, and the brightness change control means includes the lamp Brightness level calculation means for determining the brightness level per unit time in a predetermined time by calculation based on the brightness level at the time of starting the control to change the brightness and the target brightness level after the predetermined time has elapsed, and the brightness level calculation Brightness change execution means for controlling the length of the ON period of the drive signal output in accordance with each brightness level obtained by the operation. Which is configured urchin, control means for controlling a lamp (e.g., presentation control means) can be prevented to increase the data storage capacity in. Further, the brightness change control means can be easily applied to other models having different brightness level numbers and different types of brightness change patterns.

  Further, when the brightness is not changed at a predetermined time, the brightness level for each predetermined unit time in the predetermined time is determined as a target brightness level without performing the calculation. The burden of the control means to control is reduced. That is, an increase in program capacity can be suppressed.

  In the above embodiment, the production control microcomputer 100 determines the predetermined time (the time from the present to the target brightness level) based on the current brightness level and the target brightness level (at the start of brightness control). ), The lightness level of a single color per unit time is determined by calculation. However, the present invention can also be applied to a case where the tone (color intensity) or the color itself is gradually changed. In that case, a three-color LED (for example, a red LED, a green LED, and a blue LED) is used as the LED.

  For example, when the current emission color is blue (only the blue LED emits light) and the target emission color is red (only the red LED emits light), the effect control microcomputer 100 calculates blue for each unit time by calculation. The LED brightness level (gradually decreasing) and the red LED brightness level (gradually increasing) per unit time are calculated, and brightness control is performed in the same manner as shown in FIG. 46 according to the calculation result. It should be noted that an intermediate color between blue and red is visually recognized by the player between the current time and the elapse of a predetermined time.

  In addition, the pachinko gaming machine of each of the above embodiments can be given a predetermined game value to a player mainly when the special symbol that is variably displayed on the variable display unit based on the start winning prize becomes a predetermined symbol. A pachinko machine that can be given a predetermined gaming value to a player when there is a prize in a predetermined area of an electric game that is released based on a start prize, or a start prize The present invention is applied even to a pachinko game machine in which a predetermined right is generated or continued when there is a prize for a predetermined electric combination that is released when the stop symbol of the symbol variably displayed becomes a predetermined symbol combination. it can. Furthermore, the present invention can be applied to a slot machine that inserts game medals and sets a bet number and plays a game, or a game machine that inserts game balls instead of game medals and sets a bet number and plays a game.

  The present invention is applied to a gaming machine such as a pachinko gaming machine provided with light emitting means such as a lamp for production.

It is the front view which looked at the pachinko game machine from the front. It is a front view which shows the front of a game frame. It is a front view which shows the front of a game board. It is explanatory drawing which shows operation | movement of the truck as a movable member. It is explanatory drawing which shows operation | movement of the beam as a movable member. It is explanatory drawing which shows operation | movement of the skeleton as a movable member. It is explanatory drawing which shows the state which opened the game frame. It is explanatory drawing which shows the back surface of a game board. It is a block diagram which shows the circuit structural example of a game control board (main board). It is a block diagram which shows the circuit structural example of a relay board | substrate and an effect control board. FIG. 11 is a block diagram illustrating a configuration example of an effect control board, a relay board, a board side IC board, and a frame side IC board. It is explanatory drawing which shows the example of the address provided to each serial-parallel conversion IC. It is explanatory drawing which shows the example of the address provided to each serial-parallel conversion IC. It is explanatory drawing which shows the example of the address provided to each input IC. It is a block diagram which shows the structure of each serial-parallel conversion IC. It is explanatory drawing which shows the example of the format of the serial data output from the microcomputer for production control. It is a timing diagram which shows the example of the input timing of the serial data and clock signal to serial-parallel conversion IC, and the output timing of parallel data. It is a block diagram which shows the structure of each input IC. It is a flowchart which shows the main process which CPU in a main board | substrate performs. It is a flowchart which shows a 2 ms timer interruption process. It is explanatory drawing which shows each random number. It is explanatory drawing which shows an example of a big hit determination value. It is explanatory drawing which shows an example of a fluctuation pattern. It is explanatory drawing which shows the example of the format of the production control command transmitted by a serial signal system. It is explanatory drawing which shows an example of the content of an effect control command. It is explanatory drawing which shows an example of the transmission timing of an effect control command. It is a flowchart which shows a special symbol process process. It is a flowchart which shows a special symbol process process. It is a flowchart which shows a starting port switch passage process. It is a flowchart which shows a special symbol normal process. It is a flowchart which shows a special symbol normal process. It is a flowchart which shows a fluctuation pattern setting process. It is a flowchart which shows a display result specific command transmission process. It is a flowchart which shows the special symbol change process. It is a flowchart which shows a special symbol stop process. It is a flowchart which shows a big hit end process. It is a flowchart which shows a small hit end process. It is a flowchart which shows an abnormal winning notification process. It is a flowchart which shows the presentation control main process which CPU for presentation control performs. It is explanatory drawing which shows the structural example of a command reception buffer. It is a flowchart which shows a command analysis process. It is a flowchart which shows a command analysis process. It is a flowchart which shows a command analysis process. It is explanatory drawing which shows the example of the control content of a lamp. It is explanatory drawing which shows the example of control for implement | achieving the lightness 1-the lightness 15. It is explanatory drawing which shows an example of the data which show the stepwise brightness control of a lamp | ramp. It is explanatory drawing which shows typically the brightness change of period (1)-(11). It is explanatory drawing which shows a brightness change in more detail. It is a flowchart which shows production control process processing. It is a flowchart which shows a fluctuation pattern command reception waiting process. It is explanatory drawing which shows the timer and counter used when performing the brightness control of a lamp | ramp. It is a flowchart which shows a decoration design change start process. It is explanatory drawing which shows an example of the stop symbol of a decoration symbol. It is explanatory drawing which shows the structural example of process data. It is explanatory drawing which shows the structural example of a lamp control table. It is a flowchart which shows a switching time and switching frequency calculation process. It is a flowchart which shows a process during decoration design change. It is a flowchart which shows a brightness control process. It is explanatory drawing which shows an example of the data output by a lamp according to the value of a lightness corresponding | compatible counter, and the value of a 15 ms timer. It is a flowchart which shows a decoration design change stop process. It is a flowchart which shows a big hit display process. It is a flowchart which shows a big hit end process. It is explanatory drawing which shows the example of the alerting | reporting screen displayed on a variable display apparatus. It is explanatory drawing which shows the example of the aspect of the various error alerting | reporting performed in alerting | reporting control process processing. It is a flowchart which shows alerting | reporting control process processing. It is explanatory drawing which shows the structural example of the process table for error alerting | reporting. It is a flowchart which shows an example of a serial setting process. It is explanatory drawing which shows an example of the lamp control signal stored in the data storage area. It is a flowchart which shows the specific example of a serial input / output process. It is a block diagram which shows the other structural example of an effect control board, a relay board | substrate, a board | substrate side IC board, and a frame side IC board. It is a block diagram which shows the circuit structural example of the relay board | substrate and effect control board in 2nd Embodiment. It is a block diagram which shows the structural example of the presentation control board in a 2nd Embodiment, a relay board | substrate, a board | substrate side IC board, and a frame side IC board. It is a block diagram which shows the structure of each serial-parallel conversion IC in 2nd Embodiment. It is a flowchart which shows the example of the serial setting process in 2nd Embodiment. It is explanatory drawing which shows the example of 1 structure of the data storage area | region where the control signal sequence containing the lamp control signal and motor control signal of the output object in 2nd Embodiment is set. It is a flowchart which shows the specific example of the serial input / output process in 2nd Embodiment. It is a block diagram which shows the other structural example of the production | presentation control board in a 2nd embodiment, a relay board, a board side IC board, and a frame side IC board. It is a block diagram which shows the circuit structural example of the relay board | substrate in 3rd Embodiment, a sound / lamp control board, and a symbol control board. It is a block diagram which shows the structural example of the symbol control board in a 3rd embodiment, a sound / lamp control board, a relay board, a board side IC board, and a frame side IC board. It is a flowchart which shows the main process which the microcomputer for symbol control in 3rd Embodiment performs. It is a flowchart which shows the main process which the microcomputer for sound / lamp control in 3rd Embodiment performs. It is a block diagram which shows the other structural example of the symbol control board in a 3rd embodiment, a sound / lamp control board, a relay board, a board side IC board, and a frame side IC board. It is a block diagram which shows the other circuit structure example of the relay board | substrate in 3rd Embodiment, a sound / lamp control board, and a symbol control board. It is a block diagram which shows the further another structural example of the symbol control board in a 3rd embodiment, a sound / lamp control board, a relay board, a board side IC board, and a frame side IC board.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Pachinko machine 8 Special symbol display 9 Variable display device 13 1st start winning opening 14 2nd starting winning opening 20 Special variable winning ball apparatus 31 Game control board (main board)
56 CPU
560 Microcomputer for game control 78 Serial output circuit 80 Production control board 82a-82d Dish lamp (LED)
100 effect control microcomputer 101 effect control CPU
109 VDP
125a-125f Center decoration lamp (LED)
126a-126f Stage lamp (LED)
281a-281l Ceiling lamp (LED)
282a-282f Left frame lamp (LED)
283a-283f Right frame lamp (LED)
353 Serial output circuit 354 Serial input circuit 601 Board side IC board 602 to 605 Frame side IC board 606,607 Relay board 611 to 619 Serial-parallel conversion IC

Claims (6)

A gaming machine in which a player can perform a predetermined game using a game medium,
Light emitting means for emitting light in response to the drive signal;
A light emission control means for controlling the light emission means by outputting a drive signal to the light emission means,
The light emission control means includes
Brightness change control means for controlling the brightness level of the light emitting means by controlling the length of the ON period of the drive signal output in a predetermined unit time;
A control table in which a plurality of combinations of a predetermined time and a target brightness level after the predetermined time have elapsed are set,
The brightness change control means includes:
The current brightness level when starting the control for changing the brightness level of said light emitting means, and the predetermined time set in the control table, based on the target brightness level after lapse of the predetermined time, the predetermined time period Brightness level calculation means for determining by calculation the number of times the brightness level is switched, the time until switching to the next brightness level, and the brightness level at each time,
A lightness change execution means for controlling the length of the ON period of the drive signal output in accordance with each lightness level obtained by the lightness level calculation means. The gaming machine according to claim 1, wherein the lightness change control means includes non-computed lightness level determination means for determining a lightness level for each predetermined unit time in a predetermined time as a target lightness level without calculation. A gaming machine comprising a gaming frame that is openable and closable with respect to an outer frame, and a gaming board that is attached to the gaming frame and includes a predetermined plate-like body and various components attached to the plate-like body. ,
Light emitting means is provided on the game frame and the game board,
A game control means for executing a game control process for controlling the progress of the game, and an effect control means for controlling the light emission means based on a command transmitted by the game control means;
The brightness change control means is included in the effect control means,
The production control means includes a signal output means for outputting a control signal for controlling the light emission means in a serial signal system based on the command transmitted by the game control means,
The board side serial-parallel conversion circuit that converts the control signal output from the signal output means into a parallel signal system and outputs the parallel signal system to the light emitting means provided in the game board, and the control signal output from the signal output means. A frame-side serial-parallel conversion circuit that converts to a parallel signal system and outputs the light to the light emitting means provided in the game frame,
The board-side serial-parallel conversion circuit and the frame-side serial-parallel conversion circuit are connected via a single line of wiring, and are assigned different address information in advance, and control signals to which their own address information is added Convert only to parallel signal system and output,
The signal output means includes
When outputting a control signal for controlling the light emitting means provided in the game board, a control signal added with address information capable of specifying the board side serial-parallel conversion circuit is output in a serial signal system,
2. When outputting a control signal for controlling the light emitting means provided in the game frame, a control signal to which address information capable of specifying the frame side serial-parallel conversion circuit is added is output by a serial signal system. Or the game machine of Claim 2. A gaming machine comprising a gaming frame that is openable and closable with respect to an outer frame, and a gaming board that is attached to the gaming frame and includes a predetermined plate-like body and various components attached to the plate-like body. ,
Light emitting means is provided on the game frame and the game board,
A game control means for executing a game control process for controlling the progress of the game, and an effect control means for controlling the light emission means based on a command transmitted by the game control means;
The brightness change control means is included in the effect control means,
The production control means includes a signal output means for outputting a control signal for controlling the light emission means in a serial signal system based on the command transmitted by the game control means,
The board side serial-parallel conversion circuit that converts the control signal output from the signal output means into a parallel signal system and outputs the parallel signal system to the light emitting means provided in the game board, and the control signal output from the signal output means. A frame-side serial-parallel conversion circuit that converts to a parallel signal system and outputs the light to the light emitting means provided in the game frame,
At least a part of the panel side serial-parallel conversion circuit or the frame side serial-parallel conversion circuit is connected in series,
The signal output means includes
A fixed-length data including control signal information for all of the panel-side serial-parallel conversion circuits or the frame-side serial-parallel conversion circuits connected in series is output in a serial signal system for each predetermined period of unit data.
The panel-side serial-parallel conversion circuit or the frame-side serial-parallel conversion circuit connected in series is connected to the panel-side serial-parallel conversion circuit or the frame-side serial-parallel conversion circuit connected to the lower side. The gaming machine according to claim 1 or 2, wherein unit data output every predetermined cycle is sequentially transferred as it is, and a control signal is output based on the unit data at a predetermined timing. The relay board is provided between the board side serial-parallel conversion circuit and the frame side serial-parallel conversion circuit, or the relay board is provided between the frame side serial-parallel conversion circuit and the effect control means. The gaming machine according to claim 4. The gaming machine according to claim 3 or 4, further comprising a collective board on which a plurality of frame side serial-parallel conversion circuits or board side serial-parallel conversion circuits are mounted.

Images