JP5939245B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine.

  For example, some gaming machines such as pachinko machines are provided with a symbol display device having a display screen. For example, on the display screen in a pachinko machine, the design is variably displayed on the condition that the game ball passes through the operation port provided in the game area, and the effect of enhancing the interest of the game is performed, or when the predetermined condition is established Is displayed in a stopped state, and a special game state that is advantageous to a player such as a jackpot is taught. As an effect that enhances the interest of the game, for example, there is a reach effect that is closely related to the jackpot and increases the expectation of the player on the jackpot. Further, in recent years, in order to further enhance the interest of the game, in addition to the symbols that are variably displayed for each game time, an effect character or the like is displayed and a reach effect is performed using this character, or displayed on the display screen. A device such as increasing the number of symbols has been devised, and display effects are diversifying (for example, Patent Document 1).

JP 2001-218895 A

Here, in order to enhance the interest of the game, a light emitting element is provided separately from the symbol display device, and a driving circuit as an element driving means for driving the light emitting element is mounted. The drive circuit is connected to a control device that performs control related to the game via, for example, wiring, and causes the light emitting element to emit light when a control signal is input from the control device. The fun of the game is improved by the light emission.

  In such a configuration, for example, if noise enters the drive circuit, the light emitting element malfunctions, and the malfunction may give a misunderstanding to the player, and the game characteristics intended for the player may not be transmitted.

  The above-described problem is a problem common to a gaming machine including a light-emitting element and an element driving unit that drives the light-emitting element.

  The present invention has been made in view of the above-described circumstances and the like, and in a gaming machine including a light emitting element and an element driving unit for driving the light emitting element, a gaming machine capable of suitably driving the light emitting element. Is intended to provide.

The present invention
A light emitting element for informing about a game by emitting light;
Drive signal output means for outputting a predetermined drive signal according to the game situation;
Drive means for causing the light emitting element to emit light when the drive signal is output from the drive signal output means;
A wiring for connecting the drive signal output means and the drive means and transmitting the drive signal;
Noise removing means for removing noise mixed in the drive signal;
Equipped with a,
The noise removing means is provided in the middle of the route of the wiring, and when the state in which the drive signal is output from the drive signal output means continues for a predetermined period, the drive signal is sent to the drive means. A transmission means for transmitting,
It said drive signal output means is characterized output enable der Rukoto the drive signal continues longer than the period for light emitting the light emitting element.

  According to the present invention, it is possible to suitably drive the light emitting element.

The front view which shows the pachinko machine in 1st Embodiment. The front view which shows the structure of a game board. The block diagram which shows the electrical constitution of a pachinko machine. Explanatory drawing for demonstrating the display content in the display screen of a symbol display apparatus. Explanatory drawing for demonstrating the display content in the display screen of a symbol display apparatus. Explanatory drawing for demonstrating the content of the various counters used for a lottery lottery etc. The flowchart which shows the timer interruption process in MPU of a main controller. The flowchart which shows a normal process. The flowchart which shows game times control processing. The flowchart which shows a fluctuation | variation start process. The flowchart which shows a game state transfer process. The flowchart which shows a big prize opening / closing process. The block diagram which shows the electrical constitution of an audio | voice lamp control apparatus. The circuit diagram of a data output circuit. The circuit diagram which shows the various circuits mounted in the LED board. The block diagram which shows the internal structure of drive IC. 4 is a timing chart for explaining the operation of the driving IC. The circuit diagram of the circuit for winning notification. The flowchart which shows the starting process in an audio | voice lamp control apparatus. The flowchart which shows the audio | voice light emission control processing in an audio | voice lamp control apparatus. The flowchart which shows the change start process in an audio | voice lamp control apparatus. The timing chart for demonstrating the transmission aspect of LED drive data. The flowchart which shows the process during a fluctuation | variation in an audio lamp control apparatus. The timing chart for demonstrating operation | movement of LED for winning notification. The block diagram which shows the internal structure of the drive IC in 2nd Embodiment. The flowchart which shows the update process in a drive IC. The block diagram which shows the internal structure of the drive IC in 3rd Embodiment. The flowchart which shows the update process in a drive IC. The circuit diagram of the LED drive part in 4th Embodiment.

<First Embodiment>
Hereinafter, a first embodiment of a pachinko gaming machine (hereinafter referred to as a “pachinko machine”), which is a type of gaming machine, will be described with reference to the drawings. FIG. 1 is a front view of the pachinko machine 10.

  As shown in FIG. 1, the pachinko machine 10 includes an outer frame 11 that forms an outer shell of the pachinko machine 10, and a gaming machine body 12 that is rotatably attached to the outer frame 11. . The gaming machine main body 12 includes an inner frame (not shown), a front door frame 14 arranged in front of the inner frame, and a back pack unit (not shown) arranged behind the inner frame.

  The inner frame of the gaming machine main body 12 is rotatably supported by the outer frame 11 with one of the left and right side portions serving as a support side. Further, the front door frame 14 is rotatably supported by the inner frame, and can be rotated forward by using one of the left and right side portions as a support side. Further, the back pack unit is rotatably supported by the inner frame, and can be rotated rearward with one of the left and right side portions as a support side.

  Note that the gaming machine body 12 is provided with a locking device (not shown) at its rotating tip, and has a function of locking the gaming machine body 12 to the outer frame 11 so that it cannot be opened. In addition, the front door frame 14 has a function of locking the front door frame 14 to the inner frame so as not to be opened. Each of these locked states is released by performing an unlocking operation using the unlocking key on the cylinder lock 17 that is exposed on the front surface of the pachinko machine 10.

  A game board 20 is mounted on the inner frame. Here, the structure of the game board 20 is demonstrated based on FIG. FIG. 2 is a front view of the game board 20.

  The game board 20 is formed with a plurality of large and small openings penetrating in the front-rear direction by being subjected to router processing. Each opening has a general winning port 21, a variable winning device 22, an upper operating port (first starting ball entering portion) 23, a lower operating port (second starting ball entering portion) 24, a through gate 25, a variable display unit 26, A main display unit 33, an accessory display unit 34, and the like are provided.

  When a ball enters the general winning port 21, the variable winning device 22, the upper operating port 23, and the lower operating port 24, it is detected by a detection sensor (not shown) disposed on the back side of the game board 20, Based on the detection result, a predetermined number of prize balls are paid out.

  In addition, an out port 27 is provided at the lowermost part of the game board 20, and game balls that have not entered various winning ports etc. are discharged from the game area through the out port 27. The game board 20 is provided with a large number of nails 28 for dispersing and adjusting the falling direction of the game ball as appropriate, and various members (functions) such as a windmill.

  Here, the entry ball means that the game ball passes through a predetermined opening, and is not only a mode of being discharged from the game area after passing through the opening, but is discharged from the game area after passing through the opening. Embodiments that are not included are also included. However, in the following description, in order to clearly distinguish the game ball from entering the out port 27, the game ball enters the variable winning device 22, the upper operating port 23, the lower operating port 24 or the through gate 25. Is also expressed as a prize.

  The upper operating port 23 and the lower operating port 24 are unitized as operating port devices and are installed in the game board 20. Both the upper working port 23 and the lower working port 24 are opened upward. Further, both the operation ports 23 and 24 are arranged in the vertical direction so that the upper operation port 23 is on the upper side. The lower working port 24 is provided with an electric accessory 24a as a guide piece (support piece) composed of a pair of left and right movable pieces. In the closed state (non-supported state or non-guided state) of the electric accessory 24a, the game ball cannot win the lower operating port 24, and the electric operating member 24a is in the open state (supported state or guide state). It is possible to win 24.

  The variable winning device 22 includes a large winning opening 22a that leads to the back side of the game board 20, and an open / close door 22b that opens and closes the large winning opening 22a. The open / close door 22b is normally in a closed state in which a game ball cannot be won or difficult to win, and a predetermined game ball is likely to win when winning the opening / closing execution mode (open / close execution state) in the internal lottery. It can be switched to the open state. Here, the opening / closing execution mode is a mode to be shifted to when a big win is won. The opening / closing execution mode will be described in detail later. As a release mode of the variable winning device 22, the variable winning device 22 is repeatedly opened with a predetermined time (for example, 30 seconds) or a predetermined number (for example, 10) of winnings as one round and a plurality of rounds (for example, 15 rounds) as an upper limit. There is an embodiment.

  The main display portion 33 and the accessory display portion 34 are provided on a decorative member 29 disposed along the outer edge on the lower side of the game area. The decorative member 29 extends from the board surface of the game board 20 to the front of the pachinko machine 10. More specifically, the front surface of the decorative member 29 faces the window panel 53 provided on the front door frame 14 so that the game area can be viewed from the front of the pachinko machine 10. The distance between them is narrower than that of one game ball. This prevents the game ball from dropping in front of the front surface of the decorative member 29.

  A main display unit 33 and an accessory display unit 34 are provided so as to be exposed from the front surface of the decorative member 29. That is, the main display unit 33 and the accessory display unit 34 are visible from the front of the pachinko machine 10 through the window panel 53 of the front door frame 14, and a game ball is in front of both the display units 33 and 34. It is prevented from falling.

  In the main display unit 33, the display of the variation of the picture is performed with the winning of the upper working port 23 or the lower working port 24 as a trigger, and as a result of stopping the variation display, the winning to the upper working port 23 or the lower working port 24 is achieved. The result of the internal lottery performed based on the display is clearly shown. That is, in the present pachinko machine 10, the winning to the upper working port 23 and the winning to the lower working port 24 are not distinguished in the internal lottery, and are performed based on the winning to the upper working port 23 or the lower working port 24. The result of the internal lottery is displayed on the main display section 33 which is a common display area. When the result of the internal lottery based on the winning to the upper working port 23 or the lower working port 24 is a winning result corresponding to the shift to the opening / closing execution mode, a predetermined stop result is displayed on the main display unit 33. After the display and the change display are stopped, the mode shifts to the opening / closing execution mode.

  The main display unit 33 is configured by a segment display in which a plurality of segment light emitting units are arranged in a predetermined manner. However, the main display unit 33 is not limited to this, and a liquid crystal display device, an organic EL display device, You may be comprised by other types of display apparatuses, such as CRT and a dot matrix. In addition, as a pattern that is variably displayed on the main display unit 33, a configuration in which a plurality of types of characters are variably displayed, a configuration in which a plurality of types of symbols are variably displayed, a configuration in which a plurality of types of characters are variably displayed, or a plurality A configuration in which the color of the seed is switched and displayed can be considered.

  The accessory display unit 34 displays a variation of the picture triggered by a winning to the through gate 25, and the result of the internal lottery performed based on the winning to the through gate 25 as a result of stopping the variation display. Explicit by display. When the result of the internal lottery based on the winning to the through gate 25 is a winning result corresponding to the transition to the electric role open state, a predetermined stop result is displayed on the accessory display unit 34 and displayed in a variable manner. After is stopped, it shifts to the electric utility open state. In the electric combination open state, the electric combination 24a provided in the lower working port 24 is opened in a predetermined manner.

  The variable display unit 26 is provided with a symbol display device 31 that performs variable display (or variable display or switching display) of a symbol that is a kind of symbol. The variable display unit 26 is provided with a center frame 32 so as to surround the symbol display device 31. The center frame 32 has an upper portion extending forward of the pachinko machine 10. As a result, the game ball is prevented from dropping in front of the display screen of the symbol display device 31, and the inconvenience that the visibility of the display screen is reduced due to the fall of the game ball is not caused. .

  The symbol display device 31 is configured as a liquid crystal display device including a liquid crystal display, and display contents are controlled by a display control device described later. The symbol display device 31 is not limited to a liquid crystal display device, and may be another display device such as a plasma display device, an organic EL display device, or a CRT.

  On the symbol display device 31, for example, symbols are displayed side by side in the top, middle and bottom, and these symbols are variably displayed as they are scrolled in the horizontal direction. In this case, the change display on the symbol display device 31 is started based on winning in the upper working port 23 or the lower working port 24. That is, when variable display is performed on the main display unit 33, variable display is performed on the symbol display device 31 accordingly. Then, for example, the symbol display device 31 is set in advance to a game number of times that shifts to the opening / closing execution mode corresponding to 15 rounds, in which the large winning opening 22a of the variable winning device 22 is opened 15 times as the opening / closing execution mode. A predetermined combination of symbols is stopped and displayed on the active line.

  By the way, based on the winning at any one of the operating ports 23, 24, the variable display is started on the main display unit 33 and the symbol display device 31, the predetermined stop result is displayed, and the above variable display is stopped. It corresponds to one game time.

  A first holding lamp portion 35 corresponding to the main display portion 33 and the symbol display device 31 is provided at the upper left portion on the front side of the center frame 32. The first holding lamp unit 35 is composed of LEDs. A maximum of four game balls won in the upper operation port 23 or the lower operation port 24 are reserved, and the number of reservations is displayed when the first reservation lamp unit 35 is turned on.

  In the upper right portion of the center frame 32, a second holding lamp portion 36 corresponding to the accessory display portion 34 is provided. The second holding lamp unit 36 is composed of LEDs. The number of times that the game ball has passed through the through gate 25 is held up to a maximum of 4 times, and the number of the held balls is displayed when the second holding lamp unit 36 is turned on. In addition, it is good also as a structure by which the function of each holding | maintenance lamp | ramp part 35 and 36 is fulfill | performed by the display in the one part area | region of the symbol display apparatus 31. FIG.

  Here, the game board 20 is provided with a winning notification LED 37 as a specific light emitting element. The winning notification LED 37 is disposed on the upper portion of the center frame 32. Since the symbol display is performed on the symbol display device 31 as already described, the player's attention is easily attracted to the symbol display device 31 and the center frame 32. For this reason, it can be said that the LED 37 for winning notification is installed in a place that is easily noticeable to the player (a place that is easily visible).

  The winning notification LED 37 is set so as to emit light when a privilege is given to the player, specifically, when winning in the opening / closing execution mode (opening / closing execution state) is won. Thereby, the player can easily pay attention to the variation display mode of the symbol display device 31 and the light emission mode of the winning notification LED 37. Thereby, the attention degree to a game can be improved.

  In particular, the luminance of the winning notification LED 37 is set to be higher than that of the other lamp units 35 and 36 and higher than the luminance related to the image display of the symbol display device 31. As a result, when the winning notification LED 37 emits light, it is possible to visually recognize the impact light on the player. Therefore, the degree of attention to the game can be increased through the effect that the winning notification LED 37 emits light. The configuration related to the light emission of the winning notification LED 37 will be described in detail later.

  An inner rail portion 41 and an outer rail portion 42 are attached to the game board 20, and a guide rail is configured by the inner rail portion 41 and the outer rail portion 42, and is mounted below the game board 20 in the inner frame. A game ball launched from the game ball launching mechanism (not shown) is guided to the upper part of the game area. The game ball launching mechanism launches a game ball by operating a launch handle 51 provided on the front door frame 14.

  A front door frame 14 is provided so as to cover the entire front side of the inner frame. As shown in FIG. 1, the front door frame 14 is formed with a window portion 52 so that almost the entire game area can be viewed from the front. The window portion 52 has a substantially elliptical shape, and the above-described window panel 53 is fitted therein. The window panel 53 is colorless and transparent formed of glass, but is not limited thereto, and may be formed colorless and transparent using a synthetic resin.

  Around the window portion 52, light emitting means such as various lamps are provided. A display lamp part 54 is provided above the window part 52 as a part of the various lamp parts. These various lamp units are composed of LEDs. In addition, on both the left and right sides of the display lamp unit 54, speaker units 55 for outputting sound effects according to the gaming state are provided.

  Below the window portion 52 in the front door frame 14, an upper bulging portion 56 and a lower bulging portion 57 that bulge to the near side are arranged side by side. An upper plate 56a that opens upward is provided inside the upper bulge portion 56, and a lower plate 57a that also opens upward is provided inside the lower bulge portion 57. The upper plate 56a has a function of temporarily storing game balls paid out from a payout device described later and guiding them to the game ball launching mechanism side while aligning them in a line. In addition, the lower tray 57a has a function of storing game balls that are surplus in the upper tray 56a. The game balls paid out from the payout device mounted on the back pack unit are discharged to the upper plate 56a and the lower plate 57a.

  A main control device, an audio lamp control device, and a display control device are mounted on the back side of the inner frame. Further, as described above, a back pack unit is provided on the back surface of the inner frame. The back pack unit includes a payout mechanism including a payout device, a payout control device, a power source and a firing control device. Is installed. Hereinafter, the electrical configuration of the pachinko machine 10 will be described.

<Basic electrical configuration of the pachinko machine 10>
FIG. 3 is a block diagram showing a basic electrical configuration of the pachinko machine 10.

  The main control device 60 includes a main control board 61 that controls the main control of the game, and a power failure monitoring board 65 that monitors the power supply. In the main controller 60, a substrate box that accommodates the main control substrate 61 or the like is provided with a trace means for leaving a trace of its opening or a trace structure for leaving a trace of its opening. It may be. As the trace means, a plurality of case bodies constituting the substrate box are unseparably coupled, and a configuration of a coupling portion (caulking portion) that requires destruction of a predetermined part at the time of separation, or an adhesive layer is attached by peeling off. A configuration is conceivable in which a seal seal that leaves a trace of being peeled off by being left is attached so as to straddle the boundary between a plurality of case bodies. Moreover, as a trace structure, the structure which apply | coats an adhesive agent with respect to the boundary between the some case bodies which comprise a board | substrate box can be considered.

  An MPU 62 is mounted on the main control board 61. The MPU 62 includes a ROM 63 that stores various control programs executed by the MPU 62 and fixed value data, and a memory that temporarily stores various data when the control program stored in the ROM 63 is executed. A RAM 64, an interrupt circuit, a timer circuit, a data input / output circuit, various counter circuits as a random number generator, and the like are incorporated.

  The MPU 62 is provided with an input port and an output port. A power failure monitoring board 65 and a payout control device 70 provided in the main control device 60 are connected to the input side of the MPU 62. In this case, the power failure monitoring board 65 is connected to a power supply and launch control device 80 having a function of supplying operating power, and the MPU 62 is supplied with power via the power failure monitoring board 65.

  Various sensors such as various winning detection sensors 67a to 67e are connected to the input side of the MPU 62. Each of the various winning detection sensors 67a to 67e has a one-to-one detection with respect to a winning-corresponding pitched portion such as a general winning port 21, a variable winning device 22, an upper operating port 23, a lower operating port 24, and a through gate 25. A sensor is included, and the MPU 62 performs a winning determination (entering determination) for each entering part. In addition, the MPU 62 executes a lottery generation lottery based on the winnings to the upper operating port 23 and the lower operating port 24 and also performs the support generating lottery based on the winnings to the through gate 25.

  A power failure monitoring board 65, a payout control device 70, and an audio lamp control device 90 are connected to the output side of the MPU 62. For example, the payout control device 70 outputs a winning ball command based on the winning determination result to the winning corresponding winning portion. In this case, when outputting the prize ball command, the command information storage area 63d of the ROM 63 is referred to.

  Various commands such as a change command, a type command, a change end command, an opening command, and an ending command are output to the sound lamp control device 90. In this case, the command information storage area 63d of the ROM 63 is referred to when these various commands are output. Details of these various commands will be described later.

  Further, on the output side of the MPU 62, a variable winning drive unit 22c for opening / closing the open / close door 22b of the variable winning device 22, an electric combination driving unit 24b for opening / closing the electric combination 24a of the lower working port 24, and a main display unit. 33 and the accessory display unit 34 are connected. The main control board 61 is provided with various driver circuits, and the MPU 62 performs drive control of various drive units through the driver circuits.

  That is, in the opening / closing execution mode, the MPU 62 executes drive control of the variable winning drive unit 22c so that the special winning opening 22a is opened and closed. Further, when the electric combination 24a is won, the MPU 62 performs drive control of the electric combination drive unit 24b so that the electric combination 24a is opened and closed. In each game round, the display control of the main display unit 33 is executed in the MPU 62. In addition, when the lottery result indicating whether or not the electric accessory 24a is to be opened is clearly indicated, display control of the accessory display unit 34 is executed in the MPU 62.

  The power failure monitoring board 65 relays between the main control board 61 and the power supply and launch control device 80, and monitors the DC stable voltage of 24 volts, which is the maximum voltage output from the power supply and launch control device 80. The payout control device 70 performs payout control of prize balls and rental balls by the payout device 71 based on the prize ball command input from the main control device 60.

  The power source and launch control device 80 is connected to, for example, a commercial power source (external power source) in a game hall or the like. And based on the external electric power supplied from the commercial power supply, the necessary operating power is generated for each of the main control board 61, the payout control device 70, etc., and the generated operating power is supplied. The power supply and launch control device 80 is responsible for launch control of the game ball launch mechanism 81, and the game ball launch mechanism 81 is driven when predetermined launch conditions are met.

  The sound lamp control device 90 is an LED board that controls driving of various light emitting elements including various lamp portions 35 and 36 provided on the game board 20, an LED 37 for winning notification, and a display lamp portion 54 provided on the front door frame 14. 91, and by driving predetermined drive data to the LED substrate 91 based on various commands input from the main controller 60, various light emitting elements are driven and controlled. The sound lamp control device 90 controls the display control device 100 while driving and controlling the speaker unit 55 provided on the front door frame 14. In the display control device 100, display control of the symbol display device 31 is executed based on the command input from the sound lamp control device 90.

  Here, the display content of the symbol display device 31 will be described with reference to FIGS. FIG. 4 is a diagram individually showing symbols variably displayed on the symbol display device 31, and FIG. 5 is a diagram showing a display screen G of the symbol display device 31.

  As shown in FIGS. 4 (a) to (j), a design which is a kind of design is composed of nine main designs with numbers "1" to "9", respectively, and a shell-shaped design. It consists of sub-designs. More specifically, the main symbols are configured by attaching numbers “1” to “9” to nine types of character symbols such as octopus.

  As shown in FIG. 5A, on the display screen G of the symbol display device 31, three symbol rows Z1, Z2, and Z3 of an upper stage, a middle stage, and a lower stage are set as a plurality of display areas. Each of the symbol rows Z1 to Z3 includes a main symbol and a sub symbol arranged in a predetermined order. Specifically, nine types of main symbols “1” to “9” are arranged in descending order of numbers in the upper symbol row Z1, and one sub symbol is arranged between each main symbol. . In the lower symbol row Z3, nine types of main symbols “1” to “9” are arranged in ascending numerical order, and one sub symbol is arranged between the main symbols.

  That is, the upper symbol row Z1 and the lower symbol row Z3 are composed of 18 symbols. On the other hand, in the middle symbol row Z2, nine types of main symbols “1” to “9” are arranged in ascending numerical order, and then between the main symbol “9” and the main symbol “1”. In addition, a main symbol “4” is additionally arranged, and one sub symbol is arranged between each main symbol. In other words, only the middle symbol row Z2 is composed of 20 symbols by arranging 10 main symbols. On the display screen G, the symbols in the symbol rows Z1 to Z3 are displayed in a variable manner so as to scroll in a predetermined direction with periodicity.

  As shown in FIG. 5B, on the display screen G, 3 symbols are stopped and displayed for each symbol row, and as a result, a total of 9 symbols of 3 × 3 are stopped and displayed. It is like that. The display screen G has five effective lines, that is, a left line L1, a middle line L2, a right line L3, a right lowering line L4, and a right uppering line L5. Then, the variable display stops in the order of the upper symbol row Z1 → the lower symbol row Z3 → the middle symbol row Z2, and all the symbol rows Z1 are formed in a state in which a combination of symbols having the same number attached to any one of the effective lines is formed. When the fluctuation display of .about.Z3 is completed, the jackpot moving image is displayed as a normal jackpot result or a 15R probability variable jackpot result which will be described later.

  In this pachinko machine 10, the main symbols with odd numbers (1, 3, 5, 7, 9) correspond to “specific symbols”, and when a 15R probability variation jackpot result is generated, The combination is stopped. The main symbols with even numbers (2, 4, 6, 8) correspond to “non-specific symbols”. When a normal jackpot result occurs, the combination of the same non-specific symbols is stopped and displayed. The

  In addition, when an explicit 2R probability variation jackpot result to be described later is obtained, the variation display of all the symbol rows Z1 to Z3 is finished in a state where a predetermined symbol combination different from the same symbol combination is formed, and then, An explicit video is displayed.

  In addition, the mode of the variable display of the symbol in the symbol display device 31 is not limited to the above, and is arbitrary. The number of symbol columns, the direction of the symbol variable display in the symbol column, the number of symbols in each symbol column, etc. Can be appropriately changed. The designs that are variably displayed on the symbol display device 31 are not limited to the above-described symbols, and for example, only numbers may be variably displayed as the symbols.

<About various counters and reserved ball storage area>
Next, the operation of the pachinko machine 10 configured as described above will be described.

  The MPU 62 uses lots of counter information during the game to perform jackpot occurrence lottery, display setting of the main display unit 33, setting of symbol display of the symbol display device 31, setting of display of the accessory display unit 34, and the like. Specifically, as shown in FIG. 6, a jackpot random number counter C1 used for lottery generation for jackpots, a jackpot type counter C2 used for determining jackpot types such as a probable jackpot result and a normal jackpot result, In the reach random number counter C3 used for the reach generation lottery when the symbol display device 31 moves out and fluctuates, the random number initial value counter CINI used for setting the initial value of the big hit random number counter C1, the main display unit 33 and the symbol display device 31 The variation type counter CS that determines the variation display time is used. Furthermore, the electric accessory release counter C4 used for the lottery to determine whether or not the electric accessory 24a of the lower working port 24 is in the electric utility open state is used.

  Each of the counters C1 to C3, CINI, CS, and C4 is a loop counter that adds 1 to the previous value every time it is updated and returns to 0 after reaching the maximum value. Each counter is updated at short time intervals, and the updated value is appropriately stored in a lottery counter buffer 64 a set in a predetermined area of the RAM 64. Among these, in the lottery counter buffer 64a, the information corresponding to the big hit random number counter C1, the big hit type counter C2 and the reach random number counter C3 is obtained information storage when a winning to the upper working port 23 or the lower working port 24 occurs. It is stored in the reserved ball storage area 64b as a means.

  The holding ball storage area 64b includes a holding area RE and an execution area AE. The holding area RE includes a first holding area RE1, a second holding area RE2, a third holding area RE3, and a fourth holding area RE4, and matches the winning history to the upper operating port 23 or the lower operating port 24. The numerical information of the jackpot random number counter C1, the jackpot type counter C2 and the reach random number counter C3 stored in the lottery counter buffer 64a is stored in one of the holding areas RE1 to RE4 as holding information.

  In this case, in the first reservation area RE1 to the fourth reservation area RE4, when the winning to the upper operation port 23 or the lower operation port 24 is continuously generated a plurality of times, the first reservation area RE1 → the second reservation area. Each numerical information is stored in time series in the order of RE2 → third reserved area RE3 → fourth reserved area RE4. By providing the four holding areas RE1 to RE4 as described above, up to four game balls winning histories to the upper operating port 23 or the lower operating port 24 are stored on hold. In addition, the holding area RE includes a holding number storage area NA, in order to specify the number in which the winning history to the upper operating port 23 or the lower operating port 24 is stored in the holding number storage area NA. Is stored.

  Note that the number that can be reserved and stored is not limited to four, but may be any other number such as two, three, or five or more.

  The execution area AE is an area for moving each value stored in the first holding area RE1 of the holding area RE when starting the variable display on the main display unit 33, and at the start of one game round. Based on various numerical information stored in the execution area AE, determination of whether or not is made is performed.

  Each counter will be described in detail.

  For details of each counter, the jackpot random number counter C1 is configured such that, for example, 1 is sequentially added within a range of 0 to 599, and after reaching the maximum value, it returns to 0. In particular, when the jackpot random number counter C1 makes one round, the value of the random number initial value counter CINI at that time is read as the initial value of the jackpot random number counter C1. The random number initial value counter CINI is a loop counter similar to the jackpot random number counter C1 (value = 0 to 599). The big hit random number counter C1 is periodically updated and stored in the reserved ball storage area 64b of the RAM 64 at the timing when the game ball wins the upper operation port 23 or the lower operation port 24.

  The value of the random number for winning the jackpot is stored as a success / failure table (availability information group) in a success / failure table storage area 63a as a success / failure information group storage means in the ROM 63. As the success / failure table, a success / failure table for the low probability mode (low probability success / failure information group) and a high probability mode's success / failure table (high probability success / failure information group) are set. That is, in the present pachinko machine 10, a low probability mode (low probability state) and a high probability mode (high probability state) are set as the lottery mode in the winning lottery means.

  In the gaming state in which the winning / failing table for the low probability mode is referred to at the time of the lottery, the number of random numbers that win the jackpot is two. On the other hand, in the gaming state in which the winning / failing table for the high probability mode is referred to at the time of the lottery, the number of random numbers that will win the jackpot is 20. If the winning probability in the high probability mode is higher than that in the low probability mode, the number of random numbers to be won is arbitrary.

  The jackpot type counter C2 is configured so that 1 is added in order within a range of 0 to 29, and after reaching the maximum value, it returns to 0. The big hit type counter C <b> 2 is periodically updated and stored in the reserved ball storage area 64 b of the RAM 64 at the timing when the game ball wins the upper operation port 23 or the lower operation port 24.

  In the pachinko machine 10, a plurality of jackpot results are set. These multiple jackpot results are: (1) the mode of opening / closing control of the variable winning device 22 in the opening / closing execution mode, (2) the lottery mode in the winning lottery means after the opening / closing execution mode ends, and (3) the bottom after the opening / closing execution mode ends. A plurality of jackpot results are set by providing a difference in the three conditions of the support mode in the electric accessory 24a of the operating port 24.

  As an aspect of the opening / closing control of the variable winning device 22 in the opening / closing execution mode, the variable winning device 22 can be controlled so that the frequency of occurrence of winnings in the variable winning device 22 is relatively high from the start to the end of the opening / closing execution mode. A frequency winning mode and a low frequency winning mode are set. Specifically, in the high-frequency winning mode, the opening / closing of the special winning opening 22a is performed 15 times (number of times for high frequency) from the start to the end of the opening / closing execution mode, and one opening is 30 sec (high frequency time) ) Or until the number of winning prizes to the big winning opening 22a reaches 10 (high frequency). On the other hand, in the low-frequency winning mode, the opening / closing of the special winning opening 22a is performed twice (number of times for low frequency) from the start to the end of the opening / closing execution mode, and one opening is 0.2 sec (low frequency time). Or until the number of winning prizes in the special winning opening 22a reaches 6 (the number of low frequency).

  In the present pachinko machine 10, in a situation where the launch handle 51 is operated by the player, the game ball launching mechanism 81 is driven and controlled so that one game ball is launched toward the game area in 0.6 sec. . On the other hand, in the low frequency winning mode, as described above, the opening time of one large winning opening 22a is 0.2 sec. That is, in the low-frequency winning mode, the opening time of the one big winning opening 22a is shorter than the game ball firing cycle. Therefore, in the opening / closing execution mode according to the low frequency winning mode, the winning of the game ball does not substantially occur.

  It should be noted that the number of opening / closing of the large winning opening 22a in the high-frequency winning mode and the low-frequency winning mode, the opening limit time (or opening limit period) for one opening, and the opening limit number for one opening are the same as those in the high-frequency winning mode. If the occurrence frequency of winning in the variable winning device 22 is higher than that in the low frequency winning mode until the opening / closing execution mode is started and ended, the value is not limited to the above value. Is optional. Specifically, if the high frequency winning mode has a larger number of opening and closing times than the low frequency winning mode, the opening limit time for one opening is longer, or if the opening limit number for one opening is set to be larger. Good.

  However, in order to clarify the difference in privilege between the high-frequency winning mode and the low-frequency winning mode, in the opening / closing execution mode according to the low-frequency winning mode, the winning to the variable winning device 22 does not substantially occur. It may be configured. For example, in the high-frequency winning mode, the product of the launch period of the game ball and the open limit number is set shorter than the open limit time for one release, while in the low-frequency winning mode, It is good also as a structure which sets the product of the launching period of a game ball and the open limit number longer than open limit time. In addition, even if the launch interval of the game balls and the opening time of one large winning opening 22a are not the above, in the low frequency winning mode, by setting the latter to be shorter than the former, It is possible to easily realize a configuration in which a winning to the variable winning device 22 does not occur substantially.

  As a support mode for the electric combination 24a of the lower working port 24, the electric combination 24a of the lower working port 24 is compared when the game ball is continuously being fired in the same manner with respect to the game area. Low frequency support mode (low frequency support state or low frequency guide state) and high frequency support mode (high frequency support state or high frequency guide state) so that the frequency of the open state per unit time is relatively high or low. And are set.

  Specifically, in the low-frequency support mode and the high-frequency support mode, the probability of winning the power combination open state in the electric combination release lottery using the electric combination release counter C4 is the same (for example, both 4/5) However, in the high frequency support mode, the number of times that the electric utility item 24a is opened is set more frequently than in the low frequency support mode. The time is set longer. In this case, in the high-frequency support mode, when the electrified open state is selected and the open state of the electric accessory 24a occurs a plurality of times, the closed state from the end of one open state until the next open state is started The time is set shorter than one opening time. Furthermore, in the high frequency support mode, a shorter time is secured as a minimum secured time after the next electric character opening lottery is performed after the electric character object opening lottery is performed than in the low frequency support mode. Is set to be selected.

  As described above, in the high frequency support mode, there is a higher probability of winning a prize to the lower working port 24 than in the low frequency support mode. In other words, in the low frequency support mode, there is a higher probability that a prize will be generated in the upper operating port 23 than in the lower operating port 24, but in the high frequency support mode, the lower operating port 24 is connected to the lower operating port 24. The probability of winning a prize increases. When a prize is awarded to the lower operating port 24, a predetermined number of game balls are paid out. Therefore, in the high frequency support mode, the player plays a game while not reducing the number of possessed balls so much. be able to.

  The configuration for increasing the frequency at which the high frequency support mode is set to the power release state per unit time as compared with the low frequency support mode is not limited to the above-described configuration, for example, the electric component release lottery It is good also as a structure which makes high the probability that it will be elected in the electric character open state in. In addition, a secured time (for example, on the display part 34 based on a winning to the through gate 25) secured after the next electrification opening lottery is performed after the first electrification opening lottery is performed. In the configuration in which multiple types of variable display time) are prepared, the short support time is more easily selected in the high frequency support mode or the average secure time is shorter than in the low frequency support mode. May be. Further, the number of times of opening is increased, the opening time is lengthened, and the secured time that is secured when the next electric winning combination opening lottery is performed after the first electric winning combination releasing lottery is shortened (that is, In this case, one condition or any combination of conditions is applied among shortening the average time of the reserved time and increasing the winning probability. Thus, the advantage of the high frequency support mode over the low frequency support mode may be increased.

  The distribution destination of game results for the big hit type counter C2 (that is, the lottery result by the lottery determination and the distribution lottery) is stored in the distribution table (distribution information) in the distribution table storage area 63b as the distribution information group storage means in the ROM 63. Group). As such distribution destinations, a normal jackpot result (low-probability-compatible special game result), an explicit 2R probability-variable jackpot result (an explicit high-probability-matched game result or a result that suddenly changes into a probability state), and a 15R probability-variable jackpot result (high probability) Corresponding special game result) is set.

  The normal jackpot result is a jackpot result in which the opening / closing execution mode becomes the high-frequency winning mode, and after the opening / closing execution mode ends, the winning / not-lotting mode becomes the low probability mode and the support mode becomes the high-frequency support mode. However, the high-frequency support mode shifts to the low-frequency support mode when the number of games reaches the end reference number (specifically, 100 times) after the shift. In other words, the normal jackpot result is a jackpot result for shifting the gaming state to the normal jackpot state (special gaming state corresponding to low probability).

  The explicit 2R probability variation jackpot result is a jackpot result in which the open / close execution mode becomes the low-frequency winning mode, and after the open / close execution mode ends, the success / failure lottery mode becomes the high probability mode and the support mode becomes the high-frequency support mode. . These high-probability mode and high-frequency support mode are continued until the lottery result in the success / failure lottery becomes a big hit state win and shifts to the big win state by that. In other words, the explicit 2R probability variation jackpot result is a jackpot result for shifting the gaming state to the explicit 2R probability variation jackpot state (explicit high probability corresponding gaming state).

  The 15R probability variation jackpot result is a jackpot result in which the opening / closing execution mode becomes the high-frequency winning mode, and after the opening / closing execution mode ends, the success / failure lottery mode becomes the high probability mode and the support mode becomes the high-frequency support mode. These high-probability mode and high-frequency support mode are continued until the lottery result in the success / failure lottery becomes a big hit state win and shifts to the big win state by that. In other words, the 15R probability variation jackpot result is a jackpot result in which the gaming state is shifted to the 15R probability variation jackpot state (a special gaming state corresponding to high probability).

  Note that the normal gaming state in relation to the above gaming states refers to a state in which the winning / losing lottery mode is the low probability mode and the support mode is the low frequency support mode.

  In the distribution table, among the values of the jackpot type counter C2 of “0 to 29”, “0 to 9” corresponds to the normal jackpot result, and “10 to 14” corresponds to the explicit 2R probability variable jackpot result. “15 to 29” corresponds to the 15R probability variation jackpot result.

  As described above, since the explicit 2R probability variation jackpot result is set as the probability variation jackpot result, the modes of the probability variation jackpot result are diversified. That is, when two types of probability variation jackpot results are compared, the advantage for the player is that the 15R probability variation jackpot result, which is the high-frequency winning mode in the opening / closing execution mode and the high-frequency support mode in the support mode, is the highest. Although the mode is the low-frequency winning mode, the support mode has the lowest explicit 2R probability variation jackpot result that is the high-frequency support mode. Thereby, monotonization of a game is suppressed and it becomes possible to raise the attention degree to a game.

  As a kind of probability variation jackpot result, the open / close execution mode becomes the low-frequency winning mode, and after the open / close execution mode ends, the winning / failing lottery mode becomes the high probability mode, and the support mode is maintained in the previous mode. An explicit 2R probability change jackpot result (an explicit high probability corresponding game result or a result of a latent probability change state) may be included. In this case, further diversification of the probabilistic jackpot results is achieved.

  Furthermore, as a kind of losing result in the winning / losing lottery, there may be included a special losing result that shifts to the opening / closing execution mode of the low-frequency winning mode and that does not shift to the winning / losing lottery mode and the support mode after the completion. . In the configuration in which both the above-described non-explicit 2R probability variation jackpot result and the special outlier result are set, the switching execution mode shifts to the low-frequency winning mode, and the support mode is maintained in the previous mode. However, if one of the results of non-explicit 2R probability change jackpot or special outage occurs in the normal gaming state, for example, it will be It is possible to cause the player to predict which result actually corresponds to.

  For example, the reach random number counter C3 is incremented one by one within a range of 0 to 238, for example, and reaches a maximum value and then returns to 0. The reach random number counter C3 is periodically updated and stored in the reserved ball storage area 64b of the RAM 64 at the timing when the game ball wins the upper operation port 23 or the lower operation port 24.

  Here, in this pachinko machine 10, an expected effect is set as a kind of display effect in the symbol display device 31. Expected effects include a symbol display device 31 that can perform variable display (or variable display) of symbols (patterns), and variable display in game times where the open / close execution mode of the variable winning device 22 is the high-frequency winning mode. In the gaming machine in which the subsequent stop display result is a special display result, the stage before the stop display result is derived and displayed after the variable display (or variable display) of the symbol (picture) on the symbol display device 31 is started, This means a display state for making the player think that a variable display state is likely to result in a special display result.

  In the expected effect, two types are set: the reach display and a notice display for expecting the occurrence of reach display or the generation of a special display result at a stage before the reach display occurs.

  In the reach display, a combination of jackpot symbols corresponding to the occurrence of the high-frequency winning mode is obtained by stopping and displaying symbols for some of the symbol sequences displayed on the display screen of the symbol display device 31. A display state is displayed in which combinations of reach symbols that may be established are displayed, and in that state, symbols in the remaining symbol rows are displayed in a variable manner. In addition, in the state where the combination of reach symbols is displayed as described above, the variation of the symbols is displayed in the remaining symbol rows, and a predetermined character or the like is displayed as a moving image on the background screen. In addition, there are those that perform a reach effect by displaying a predetermined character or the like as a moving image on substantially the entire display screen after reducing or not displaying a combination of reach symbols.

  More specifically, the reach display related to the symbol variation display is performed in order to generate a high-frequency winning mode on a preset active line in the display screen of the symbol display device 31 as a stage before the symbol variation display is terminated. A reach line is formed by stopping and displaying a reach symbol combination for which a corresponding jackpot symbol combination may be established, and in the situation where the reach line is formed, a symbol variation display is displayed by the final stop symbol sequence. Is to do.

  The display contents of FIG. 5 will be described in detail. In the state where the symbol variation display is first ended in the upper symbol row Z1, and the symbol variation display is further terminated in the lower symbol row Z3, any effective A reach line is formed by stopping and displaying the main symbols having the same numbers on the lines L1 to L5, and in the situation where the reach line is formed, the symbol variation display is performed in the middle symbol row Z2. Reach display. When the high-frequency winning mode occurs, the main symbol with the same number as the main symbol forming the reach line is stopped and displayed on the reach line in the middle symbol row Z2. The symbol variation display is terminated.

  In the notice display, the symbol display on the display screen of the symbol display device 31 is started in a situation where the symbols are variably displayed in all the symbol columns Z1 to Z3 after the symbol variation display is started, or in some symbol columns. In a situation where the symbols are variably displayed in a plurality of symbol rows, a mode in which a character is displayed separately from the symbols on the symbol rows Z1 to Z3 is included. Moreover, what makes a background screen the predetermined aspect different from the aspect until then, and what makes the symbol on the symbol row | line | column Z1-Z3 the predetermined aspect different from the previous aspect are also contained. Such a notice display can occur in any game times when reach display is performed and when reach display is not performed, but the case where reach display is performed is higher than the case where reach display is not performed. It is set to occur with probability.

  The reach display is executed regardless of the value of the reach random number counter C3 in the game times that shift to the opening / closing execution mode. In the game times that do not shift to the opening / closing execution mode, the reach random number counter C3 acquired at a predetermined timing is referred to the reach table stored in the reach table storage area of the ROM 63 in response to the occurrence of the reach display. It is executed when On the other hand, the determination as to whether or not to perform the notice display is performed not by the main control device 60 but by the display control device 100. This will be described in detail later.

  The variation type counter CS is, for example, incremented by 1 within a range of 0 to 198, and returns to 0 after reaching the maximum value. The variation type counter CS is used when the MPU 62 determines the variation display time on the main display unit 33 and the symbol variation display time on the symbol display device 31. The variation type counter CS is updated once every time a normal process to be described later is executed once, and is repeatedly updated even within the remaining time in the normal process. Then, the buffer value of the variation type counter CS is acquired at the time of determining the variation pattern at the start of variation display in the main display unit 33 and at the time of symbol variation start by the symbol display device 31.

  The electric accessory release counter C4 is, for example, configured to increment one by one within a range of 0 to 250 and return to 0 after reaching the maximum value. The electric accessory release counter C4 is periodically updated, and stored in the electric utility reservation area 64c of the RAM 64 at a timing when a game ball wins the through gate 25. Then, at a predetermined timing, a lottery is performed as to whether or not to control the electric accessory 24a to the open state based on the stored value of the electric accessory release counter C4.

  As already described, in the MPU 62, at least the buffer value of the variation type counter CS is used to determine the variation display time in the main display unit 33. In this determination, the variation display time table storage area 63c of the ROM 63 is used. It is done.

<Various processes executed by main controller 60>
Next, a timer interrupt process and a normal process that are executed when the MPU 62 in the main controller 60 advances the game at each game time will be described. In addition to the timer interrupt process and the normal process, the MPU 62 executes a main process that is started when the power is turned on and an NMI interrupt process that is started when a power failure signal is input to the NMI terminal (non-maskable terminal). However, description of these processes is omitted.

<Timer interrupt processing>
First, timer interrupt processing will be described with reference to the flowchart of FIG. This process is started periodically by the MPU 62 (for example, at a cycle of 2 msec).

  In step S101, various detection sensor reading processes are executed. The reading process includes a process of reading the states of the various winning detection sensors 67a to 67e, determining the states of the various winning detection sensors 67a to 67e, and storing the winning detection information.

  After executing the reading process in step S101, the process proceeds to step S102. In step S102, the random number initial value counter CINI is updated. Specifically, the random number initial value counter CINI is incremented by 1 and cleared to 0 when the counter value reaches the maximum value. Then, the update value of the random number initial value counter CINI is stored in the corresponding buffer area of the RAM 64.

  In subsequent step S103, the big hit random number counter C1, the big hit type counter C2, the reach random number counter C3, and the electric accessory release counter C4 are updated. Specifically, the jackpot random number counter C1, the jackpot type counter C2, the reach random number counter C3, and the electric accessory release counter C4 are each incremented by 1 and cleared to 0 when the counter values reach the maximum value. Then, the updated values of the counters C1 to C4 are stored in the corresponding buffer area of the RAM 64.

  In subsequent step S104, a through winning process is performed in accordance with winning through the through gate 25. In the through winning process, when a winning to the through gate 25 has occurred, the number of stored bonus items stored in the electronic role holding area 64c is less than the upper limit number (for example, “4”). On the condition, the value of the electric accessory release counter C4 updated in step S103 is stored in the electric utility reservation area 64c. Moreover, the process for making the 2nd reservation lamp | ramp part 36 of the variable display unit 26 corresponding to the number of articles | goods reservation memory | storage corresponding to the audio lamp control apparatus 90 is performed.

  In a succeeding step S105, a winning process for the operating port accompanying winning in the upper operating port 23 or the lower operating port 24 is executed. In the winning process for the operating port, when a winning is made to the upper operating port 23 or the lower operating port 24, the start reserved memory number stored in the reserved ball storage area 64b is the upper limit number (for example, “ 4)), the values of the jackpot random number counter C1, the jackpot type counter C2 and the reach random number counter C3 updated in step S103 are stored in the holding area RE of the holding ball storage area 64b. In this case, the data is stored in the first reserved area among the empty reserved areas RE1 to RE4 of the reserved area RE, that is, the reserved area corresponding to the current start reserved memory number. Further, a process for lighting the first hold lamp unit 35 of the variable display unit 26 corresponding to the start hold storage number is executed for the voice lamp control device 90. After executing the process of step S105, the timer interrupt process is terminated.

<Normal processing>
Next, the flow of normal processing will be described with reference to the flowchart of FIG. The normal process is a process that is started after the main process that is activated when the power is turned on, and the main process of the game is executed in the normal process. As an outline, the processing of steps S201 to S207 is executed as a periodic processing with a period of 4 msec, and the counter update processing of steps S209 and S210 is executed with the remaining time.

  In the normal process, in step S201, output data such as a command set in the timer interrupt process or the previous normal process is transmitted to each control device on the sub side. Specifically, the presence or absence of a prize ball command is determined, and if a prize ball command is set, it is transmitted to the payout control device 70. Further, when a production command such as a variation command, a type command, a variation end command, or the like is set, the command is transmitted to the sound lamp control device 90.

  In the subsequent step S202, the variation type counter CS is updated. Specifically, the variation type counter CS is incremented by 1, and the counter value is cleared to 0 when the counter value reaches the maximum value. Then, the update value of the variation type counter CS is stored in the corresponding buffer area of the RAM 64.

  In subsequent step S203, a game number control process for controlling a game in each game time is executed. In this game times control process, jackpot determination, symbol variable display setting by the symbol display device 31, display control of the main display unit 33, and the like are performed. Details of the game times control process will be described later.

  Thereafter, in step S204, a game state transition process for shifting the game state is executed. Although details will be described later, the gaming state shifts to an opening / closing execution mode, a high probability mode, a high frequency support mode, and the like by this gaming state transition processing.

  In a succeeding step S205, an electric combination support process for driving and controlling the electric combination 24a provided in the lower operation port 24 is executed. In this electronic combination support process, the information stored in the electronic combination holding area 64c of the RAM 64 is used to determine whether or not to open the electric combination 24a, to open / close the electric combination 24a, and for the combination Display control of the display unit 34 is performed.

  Thereafter, in step S206, a game ball launch control process is executed. In the game ball launch control process, the solenoid of the game ball launch mechanism 81 is excited once every predetermined period (for example, 0.6 sec) on condition that a launch permission signal is input from the power source and launch control device 80. . Thereby, the game ball is launched toward the game area.

  In a succeeding step S207, it is determined whether or not a power failure flag is stored in the RAM 64. The power failure flag is a flag that is stored when the occurrence of a power failure is confirmed in the power failure monitoring board 65 and a power failure signal is input from the power failure monitoring board 65 to the NMI terminal of the MPU 62 and is erased in the next main processing.

  When the power failure flag is not stored, the last process of the plurality of processes that are repeatedly executed is completed, so whether or not the execution timing of the next normal process is reached in step S208, that is, the previous normal process It is determined whether a predetermined time (4 msec in this embodiment) has elapsed since the start of the process. Then, the random number initial value counter CINI and the variation type counter CS are repeatedly updated within the remaining time until the next normal processing execution timing.

  That is, in step S209, the random number initial value counter CINI is updated. Specifically, the random number initial value counter CINI is incremented by 1 and cleared to 0 when the counter value reaches the maximum value. Then, the update value of the random number initial value counter CINI is stored in the corresponding area of the RAM 64. In step S210, the variation type counter CS is updated. Specifically, the variation type counter CS is incremented by 1 and cleared to 0 when the counter values reach the maximum value. Then, the update value of the variation type counter CS is stored in the corresponding area of the RAM 64.

  On the other hand, if it is determined in step S207 that the power failure flag is stored, the power interruption has occurred, so the power interruption process from step S211 is executed. That is, in step S211, the generation of the timer interrupt process is prohibited, and after that, the RAM judgment value is calculated and stored in step S212. After the access of the RAM 64 is prohibited in step S213, the power supply is completely shut down and processed. Continue infinite loop until no longer runs.

<Game times control processing>
Next, the game times control process of step S203 will be described with reference to the flowchart of FIG.

  In the game times control process, first, in step S301, it is determined whether or not the opening / closing execution mode is in effect. Specifically, it is determined whether or not the opening / closing execution mode flag is stored in the opening / closing execution mode flag storage area in the various flag storage areas 64e of the RAM 64. The opening / closing execution mode flag is stored when the gaming state is shifted to the opening / closing execution mode in the gaming state transition process described later, and is erased when the opening / closing execution mode is ended in the gaming state transition process.

  When in the opening / closing execution mode, the game is executed without executing any of the processes after step S302, that is, the game turn starting process in steps S303 to S305 and the game turn progress process in steps S306 to S309. End control processing. In other words, in the open / close execution mode, the game times are not started regardless of whether or not a winning for the operation ports 23 and 24 has occurred.

  If it is not in the opening / closing execution mode, it is determined in step S302 whether or not the main display unit 33 is in a variable display. This determination is performed by determining whether or not the variable display flag is stored in the variable display flag storage area in the various flag storage areas 64e of the RAM 64. The variable display in-progress flag is stored when the main display unit 33 starts variable display, and is deleted when the variable display ends.

  When the main display unit 33 is not in a variable display, the process proceeds to the game turn starting process in steps S303 to S305. In the processing for starting game times, first, in step S303, the number-of-holds storage area N, which is the number of pieces of on-hold information stored, is referred to by referring to the number-of-holds storage area NA of the holding ball storage area 64b. Determine whether. The case where the start hold storage number N is “0” means that the hold information is not stored in the hold ball storage area 64b. Accordingly, the game turn control process is terminated as it is. If the start pending storage number N is not “0”, a data setting process is executed in step S304.

  In the data setting process, first, the start pending storage number N is decremented by one. Further, the data stored in the first holding area RE1 of the holding area RE in the holding ball storage area 64b is moved to the execution area AE. Thereafter, a process of shifting the data stored in the holding areas RE1 to RE4 of the holding area RE is executed. This data shift process is a process of sequentially shifting the data stored in the first reservation area RE1 to the fourth reservation area RE4 to the lower area side, and clears the data in the first reservation area RE1 and the second The data in each area is shifted such as the reserved area RE2 → the first reserved area RE1, the third reserved area RE3 → the second reserved area RE2, and the fourth reserved area RE4 → the third reserved area RE3.

  In the data setting process, a process for causing the voice lamp control device 90 to recognize that the hold information has been shifted and changing the display on the first hold lamp unit 35 in accordance with the decrease in the number of hold is executed. To do.

  After executing the data setting process, the game start control process is terminated after the change start process is executed in step S305. Here, the variation start process will be described with reference to the flowchart of FIG.

  In step S401, a validity determination process is executed. In the success / failure determination process, first, it is determined whether or not the success / failure lottery mode is a high probability mode. In the case of the high probability mode, with reference to the high probability mode success / failure table among the tables stored in the success / failure table storage area 63a, the information for the success / failure determination among the information stored in the execution area AE, that is, It is determined whether or not the value related to the jackpot random number counter C1 matches the high probability jackpot value information. In the case of the low probability mode, the value related to the jackpot random number counter C1 stored in the execution area AE with reference to the low probability mode success / failure table among the tables stored in the success / failure table storage area 63a. Is matched with the jackpot numerical information for low probability.

  In a succeeding step S402, it is determined whether or not the result of the success / failure determination process in the step S401 is a jackpot winning result. If it is a big win result, a type determination process is executed in step S403.

  In the type determination process, the information for type determination among the information stored in the execution area AE, that is, the information related to the jackpot type counter C2 is grasped. Then, with reference to the sorting table stored in the sorting table storage area 63b, it is specified which jackpot type corresponds to the information related to the above-obtained jackpot type counter C2.

  In subsequent step S404, it is determined whether or not the jackpot type identified in the type determination process in step S403 corresponds to the probability variation jackpot result. If it corresponds to the probability variation jackpot result, it is determined in step S405 whether or not the jackpot type corresponds to the 15R probability variation jackpot result.

  If it is a 15R probability variation jackpot result, stop result setting processing for 15R probability variation jackpot is executed in step S406. If it is a probability variation jackpot result but not a 15R probability variation jackpot result, an explicit 2R probability variation jackpot is determined in step S407. Execute stop result setting process. If it is not the probability variation jackpot result (step S404: NO), a stop result setting process for normal jackpot is executed in step S408. Furthermore, when it is determined that the result of the success / failure determination process in step S401 is not the big hit winning result, a stop result setting process for losing is executed in step S409.

  In the stop result setting process of step S406 to step S409, information on the pattern mode to be finally stopped and displayed on the main display unit 33 is specified from information stored in advance in the ROM 63, and the specified information is stored in the RAM 64. To do. Further, in step S406, step S407, and step S408, the RAM 64 stores information for specifying in the MPU 62 that the determination result of the current game round is a 15R probability variation jackpot result, an explicit 2R probability variation jackpot result, or a normal jackpot result. To store. Specifically, a 15R probability variation flag is stored in step S406, an explicit 2R probability variation flag is stored in step S407, and a normal jackpot flag is stored in step S408.

  After executing any one of steps S406 to S409, a variable display time setting process is executed in step S410.

  In this process, the value of the variation type counter CS stored in the variation type counter buffer in the lottery counter buffer 64a of the RAM 64 is acquired. Further, it is determined whether or not a reach display is generated in the symbol display device 31 in the current game round. Specifically, it is determined whether any of the 15R probability variation flag, the explicit 2R probability variation flag, or the normal jackpot flag is stored in the RAM 64. If any flag is stored, it is determined that reach display occurs. Even if none of the flags is stored, if the value related to the reach random number counter C3 stored in the execution area AE is a value corresponding to the occurrence of reach, the reach display is performed. Determine that it occurs.

  When it is determined that the reach display is generated, the fluctuation display corresponding to the value of the current fluctuation type counter CS is referred to by referring to the reach generation fluctuation display time table stored in the fluctuation display time table storage area 63c of the ROM 63. Time information is acquired, and the variable display time information is set in a variable display time counter (variable display time measuring means) provided in various counter areas 64d of the RAM 64. On the other hand, when it is determined that the reach display does not occur, the value corresponding to the value of the current variation type counter CS is referred to by referring to the reach non-occurrence variation display time table stored in the variation display time table storage area 63c. The variable display time is acquired, and the variable display time information is set in the variable display time counter.

  Note that the variable display time information when no reach occurs is set such that the variable display time is shortened as the number of start pending storage numbers N increases. Also, in the situation where the support mode is the high frequency support mode, the non-reach time is selected so that the shorter variable display time is selected compared to the situation where the number of pending information is the same as in the situation where the low frequency support mode. The generation variation display time table is set. However, the present invention is not limited to this, and the configuration may be such that the variable display time does not vary according to the number N of starting reserved balls and the support mode, and the above relationship may be reversed. Furthermore, the above configuration may be applied to the variable display time when reach occurs. In addition, in the case of 15R probability variable jackpot results, explicit 2R probability variable jackpot results, normal jackpot results, out-of-reach and complete out-of-shift cases, separate variable display time tables are set. Also good. In this case, the variable display time is allocated according to each game result.

  After the variable display time setting process is executed in step S410, a variable command and a type command are set in step S411. The change command includes information on presence / absence of reach and information on change display time. The type command includes game result information. That is, the type command includes 15R probability variation jackpot result information, explicit 2R probability variation jackpot result information, normal jackpot result information, outage result information, and the like as game result information.

  The variation command and the type command set in step S411 are transmitted to the sound lamp control device 90 in step S201 in the normal process (FIG. 8). The sound lamp control device 90 determines the light emission pattern of the display lamp unit 54 and the sound output pattern from the speaker unit 55 in the game time based on the received variation command and type command, and the contents of the determined effect The display lamp unit 54 and the speaker unit 55 are controlled so as to be executed. The audio lamp control device 90 transmits the change command and the type command to the display control device 100 while maintaining the information form. The display control device 100 determines a variation display pattern in the symbol display device 31 in the game time based on the received variation command and type command, and the symbol display device 31 is executed so that the variation display pattern is executed. Control display. Specific contents of the display control will be described later.

  After performing the process of step S411, the main display part 33 starts the display of the change of a pattern in step S412. Then, this variation start process is terminated.

  Returning to the description of the game times control process (FIG. 9), when the main display unit 33 is in a variable display, the game times progress process of steps S306 to S309 is executed.

  In the process for advancing game times, first, in step S306, it is determined whether or not the variation display time of the current game time has elapsed. Specifically, it is determined whether or not the value of the variable display time information stored in the variable display time counter of the RAM 64 has become “0”. The value of the variable display time information is set in the variable display time setting process (step S410) as described above. The value of the set variable display time information is decremented by 1 every time the timer interrupt process (FIG. 7) is started.

  If the variable display time has not elapsed, the variable display process is executed in step S307. In the variable display process, the display mode on the main display unit 33 is changed. Then, this game times control process is complete | finished.

  If the change display time has elapsed, change end processing is executed in step S308. In the change end process, the information stored in the RAM 64 in the process of any one of steps S406 to S409 is specified, and the main display unit 33 displays the pattern form corresponding to the information on the main display unit 33. The display of the unit 33 is controlled.

  In the subsequent step S309, a change end command is set. The set change end command is transmitted to the sound lamp control device 90 in step S201 in the normal process (FIG. 8). The sound lamp control device 90 transmits the received change end command to the display control device 100 while maintaining the information form. In the display control device 100, by receiving the change end command, the combination of the final stop symbols in the game round is confirmed and displayed (final stop display). Then, this game times control process is complete | finished.

<Game state transition processing>
Next, the gaming state transition processing in step S204 will be described with reference to the flowchart in FIG.

  First, in step S501, it is determined whether or not the opening / closing execution mode is in effect. If it is not in the opening / closing execution mode, the process proceeds to step S502, and it is determined whether or not it is the timing when the variation display of the pattern on the main display unit 33 of one game time is finished. If it is not the timing when the variable display is finished, the gaming state transition process is finished as it is.

  If it is the timing when the variable display is finished, it is determined in step S503 whether or not the game result of the current game time corresponds to the transition to the opening / closing execution mode. Specifically, it is determined whether any of the 15R probability variation flag, the explicit 2R probability variation flag, or the normal jackpot flag is stored in the RAM 64. If none of the above flags is stored, the gaming state transition process is terminated as it is.

  If any of the above flags is stored, start processing of the opening / closing execution mode is executed in step S504. In the start process, an opening waiting time (starting waiting period) is set for waiting without opening the large winning opening 22a of the variable winning device 22 for opening in the opening / closing execution mode. Specifically, the waiting time information for opening stored in advance in the ROM 63 is set in the waiting time counter area provided in the various counter areas 64 d of the RAM 64. In this case, the waiting time information that is set differs depending on whether the opening / closing execution mode is the high-frequency winning mode, and the waiting time information indicates that the waiting time information is lower in the low-frequency winning mode than in the high-frequency winning mode. It is set to be shorter. For example, in the high frequency winning mode, the count value of the standby time information is set so that the standby time is 1 sec. In the low frequency winning mode, the count value of the standby time information is set so that the standby time is 0.2 sec. Is set. The value of the waiting time information set here is decremented by 1 every time the timer interrupt process (FIG. 7) is executed.

  In a succeeding step S505, it is determined whether or not the current opening / closing execution mode is the high-frequency winning mode. Specifically, it is determined whether either the 15R probability variation flag or the normal jackpot flag is stored in the RAM 64. If it is not the high-frequency winning mode, that is, if it is the low-frequency winning mode, “2” is set in the round counter RC provided in the various counter areas 64d of the RAM 64 in step S506. The round counter RC is a counter area for counting the number of times the special winning opening 22a is opened. On the other hand, if it is the high-frequency winning mode, “15” is set in the round counter RC in step S507.

  After executing the process of step S506 or step S507, after setting an opening command in step S508, the gaming state transition process is terminated. The opening command set in step S508 is transmitted to the sound lamp control device 90 in step S201 in the normal process (FIG. 8). This opening command includes information indicating whether the high-frequency winning mode or the low-frequency winning mode is set.

  The sound lamp control device 90 determines the light emission pattern of the display lamp unit 54 and the sound output pattern from the speaker unit 55 in the opening / closing execution mode based on the received opening command, and the content of the determined effect is executed. In this manner, the display lamp unit 54 and the speaker unit 55 are controlled. In addition, the sound lamp control device 90 transmits the opening command to the display control device 100 while maintaining the information form. The display control device 100 causes the symbol display device 31 to start an effect corresponding to the opening / closing execution mode based on the received opening command. Specific contents of the display control will be described later.

  On the other hand, when it is in the opening / closing execution mode (step S501: YES), the process proceeds to step S509. In step S509, it is determined whether or not the opening standby time has elapsed. If the opening standby time has not elapsed, the gaming state transition process is terminated. When the waiting time for the opening has elapsed, a special winning opening opening / closing process is executed in step S510. Here, the special winning opening opening / closing process will be described with reference to the flowchart of FIG.

  First, in step S601, it is determined whether or not the special winning opening 22a is being opened. Specifically, this determination is performed based on the driving state of the variable prize driving unit 22c. If the big prize opening 22a is not being opened, it is determined whether or not the value of the round counter RC is “0” in step S602, and the timer T provided in the various counter areas 64d of the RAM 64 is determined in step S603. It is determined whether or not the value is “0”.

  When the value of the round counter RC is “0” or when the value of the timer T is not “0”, the big prize opening / closing process is ended as it is. On the other hand, when the value of the round counter RC is not “0” and the value of the timer T is “0”, the process proceeds to step S604, and the variable prize driving unit 22c is set in the driving state to open the big prize opening 22a. To do.

  In subsequent step S605, setting processing for each round is executed. In the setting process for each round, it is first determined whether or not the high-frequency winning mode is set. If the high-frequency winning mode is set, “15000” (that is, 30 sec) is set in the timer T. The count value set here is decremented by 1 every time the timer interrupt process (FIG. 7) is started, that is, every 2 msec. Also, “10” is set in the winning counter area PC provided in the various counter areas 64d of the RAM 64 in order to count the number of winning game balls to the big winning opening 22a. On the other hand, when it is not the high-frequency winning mode, that is, when it is the low-frequency winning mode, “100” (that is, 0.2 sec) is set in the timer T, and “6” is set in the winning counter area PC. .

  Thereafter, an opening command is set in step S606, and the main prize winning opening / closing process is terminated. The set release command is transmitted to the sound lamp control device 90 in step S201 in the normal process (FIG. 8). The sound lamp control device 90 changes the effect contents in the display lamp unit 54 and the speaker unit 55 based on the received release command. Further, the sound lamp control device 90 transmits the release command to the display control device 100 while maintaining the information form. The display control device 100 switches the effect for the opening / closing execution mode in the symbol display device 31 based on the received opening command. Specific contents of the display control will be described later.

  On the other hand, when the special winning opening 22a is being opened (step S601: YES), the process proceeds to step S607 to determine whether or not the value of the timer T is “0”. If the value of the timer T is not “0”, it is determined in step S608 whether or not a game ball has won the big winning opening 22a based on the detection state of the detection sensor corresponding to the variable winning device 22. If no winning has occurred, the main prize winning opening / closing process is terminated. On the other hand, if a winning has occurred, the value of the winning counter area PC is decremented by 1 in step S609, and then it is determined whether or not the value of the winning counter area PC is “0” in step S610. If not, the main prize winning opening / closing process is terminated.

  If the value of the timer T is “0” in step S607 or if the value of the winning counter area PC is “0” in step S610, it means that the special winning opening closing condition is established. In such a case, in step S611, the variable winning drive unit 22c is set in a non-driven state to close the special winning opening 22a.

  In subsequent step S612, 1 is subtracted from the value of the round counter RC. In step S613, it is determined whether or not the value of the round counter RC is “0”. When the value of the round counter RC is “0”, the main prize winning opening / closing process is finished as it is. If the value of the round counter RC is not “0”, it is determined in step S614 whether or not the high-frequency winning mode is set.

  When the high-frequency winning mode is set, the timer T is set to “1000” (that is, 2 sec), and when the low-frequency winning mode is set, the timer T is set to “100” (that is, 0.2 sec). That is, in the low frequency winning mode, the time during which the large winning opening 22a is closed between rounds is set shorter than in the high frequency winning mode. Thereafter, a closing command is set in step S617, and the main prize winning opening / closing process is terminated.

  The set closing command is transmitted to the sound lamp control device 90 in step S201 in the normal process (FIG. 8). Based on the received closing command, the sound lamp control device 90 specifies that the opening of the big winning opening 22a for one round has been completed. Further, the sound lamp control device 90 transmits the close command to the display control device 100 while maintaining the information form. The display control device 100 specifies that the opening of the large winning opening 22a for one round has been completed based on the received closing command, and executes processing corresponding thereto. Specific contents of such processing will be described later.

  Returning to the description of the game state transition process (FIG. 11), after executing the big prize opening / closing process in step S510, it is determined in step S511 whether or not the value of the round counter RC is “0”. In S512, it is determined whether or not the ending standby time has elapsed. Here, the pachinko machine 10 is configured such that when the opening / closing execution mode ends, an effect for ending is executed by the symbol display device 31 or the like, and the waiting time for ending is the effect for the ending. This is a period for waiting for the start of the next game time in the main control device 60 until the game ends.

  When the value of the round counter RC is not “0” or when the ending waiting time has not elapsed, the gaming state transition process is terminated as it is. On the other hand, if the value of the round counter RC is “0” and the waiting time for ending has elapsed, an ending command is set in step S513. The ending command is transmitted to the sound lamp control device 90 in step S201 in the normal process (FIG. 8). The sound lamp control device 90 ends the effect for the opening / closing execution mode in the display lamp unit 54 and the speaker unit 55 based on the received ending command. Further, the audio lamp control device 90 transmits the ending command to the display control device 100 while maintaining the information form. The display control device 100 ends the effect for the opening / closing execution mode in the symbol display device 31 based on the received ending command. Specific contents of the display control will be described later.

  In the subsequent step S514, a transition process at the end of the opening / closing execution mode is executed. In the transition process, it is determined whether the 15R probability change flag, the explicit 2R probability change flag, or the normal jackpot flag is stored in the RAM 64. When the 15R probability variation flag or the explicit 2R probability variation flag is stored, the success / failure lottery mode is set to the high probability mode, the support mode is set to the high frequency support mode, and the normal jackpot flag is stored. In this case, the success / failure lottery mode is set to the low probability mode and the support mode is set to the high frequency support mode.

  Incidentally, when the normal jackpot flag is stored, “100” as the end reference number is set in the game number counter in the various counter areas 64d of the RAM 64. The game number counter is decremented by 1 every time the above-described variation start process is executed, and when the value of the game number counter becomes “0”, the support mode is set to the high frequency support mode.

  After that, in step S515, after executing the opening / closing execution mode end processing, the gaming state transition processing ends. In the open / close execution mode end processing, if any of the explicit 2R probability variation flag, 15R probability variation flag, or normal jackpot flag is stored, it is deleted, and if it is not already stored, the state is maintained. To do.

<Electrical Configuration of Audio Lamp Control Device 90>
Next, the electrical configuration of the sound lamp control device 90 will be described with reference to the block diagram of FIG.

  The sound lamp control device 90 is provided with a sound lamp control board 110. The sound lamp control board 110 is provided with a sub CPU 111, a ROM 112, and a RAM 113.

  The sub CPU 111 has a function as a main control unit in the sound lamp control device 90. The sub CPU 111 is connected to the main control device 60 via the input port 114 provided on the sound lamp control board 110, and various commands transmitted from the main control device 60, specifically, a change command, a type command, A command for controlling game times (game time control information) such as a change end command and a command for jackpot effect (information for jackpot effect) such as an opening command, an ending command, an open command, and a close command are sent to the sub CPU 111 through the input port 114. Entered. The sub CPU 111 is connected to the ROM 112 and the RAM 113 via a bus.

  The ROM 112 is a non-volatile storage unit for storing control information such as various control programs executed by the sub CPU 111 and fixed value data. Specifically, the ROM 112 includes a NOR type flash memory. Part of the fixed value data is stored in advance in each of the areas 112a to 112b of the ROM 112. The details of each of these areas 112a to 112b will be described together with the description of the processing executed by the sub CPU 111.

  The RAM 113 is a control volatile storage unit for temporarily storing work data, flags, and the like used when various programs are executed by the sub CPU 111, and is specifically configured by a DRAM. Work data, flags and the like are stored in the RAM 113.

  When various commands are input from the main control device 60, the sub CPU 111 uses the ROM 112 and the RAM 113 to execute processing corresponding to the input commands. Specifically, the sub CPU 111 is provided with an arithmetic circuit 121 and a register 122 capable of temporarily storing the result of the arithmetic operation by the arithmetic circuit 121. When various commands are input, the sub CPU 111 reads a program corresponding to the command input from the ROM 112 and executes the program in the arithmetic circuit 121. Then, the calculation result by the calculation circuit 121 is written into the register 122 and the RAM 113. Data written in the register 122 and the like is output to the LED substrate 91, the speaker unit 55, and the display control device 100, and the LED substrate 91, the speaker unit 55, and the display control device 100 operate based on the data.

  The sub CPU 111 outputs each command received from the main control device 60 to the display control device 100 while maintaining the information form, and the display control device 100 displays the display screen G on the basis of each command. The symbol display device 31 is controlled so that an image is displayed.

  Specifically, on the output side of the sub CPU 111, the audio lamp control board 110 is provided with output ports 131, 132, 133 corresponding to the LED board 91, the speaker unit 55, and the display control device 100, respectively. In addition, data output circuits 134, 135, and 136 that output the data of the register 122 to the output ports 131, 132, and 133 are provided. Each output port 131, 132, 133 is connected to the sub CPU 111 via a corresponding data output circuit 134, 135, 136, respectively. The output ports 131, 132, and 133 are connected to the corresponding LED board 91, the speaker unit 55, and the display control device 100, respectively. The data set in the register 122 is output to the output ports 131, 132, 133 by the data output circuits 134, 135, 136, and the LED board 91, the speaker through the output ports 131, 132, 133. Is output to the unit 55 and the display control apparatus 100.

<Electrical configuration related to drive control of various light emitting elements>
As already described, the pachinko machine 10 is provided with various lamp units, and these lamp units include LEDs as light emitting elements. These LEDs are driven based on data output from the data output circuit 134 to the LED board 91 via the output port 131. Therefore, the configuration of the data and the configuration of the data output circuit 134 will be described below with reference to the circuit diagram of FIG.

  As shown in FIG. 14, the data output circuit 134 includes a plurality of buses (in detail, five) for connecting the sub CPU 111 and the output port 131. Different data is output to each bus. Specifically, LED drive data SD, clock signal SG1, data write signal SG2, first permission signal SG3, and second permission signal SG4 are output to output port 131. The output port 131 includes a plurality of terminals, and the LED drive data SD and each signal are configured to be input to corresponding terminals among the plurality of terminals. Hereinafter, the configuration related to the LED drive data SD and each signal will be individually described.

  First, the configuration related to the LED drive data SD will be described. The register 122 is provided with an LED drive register 141 corresponding to the LED drive data SD for determining whether or not the LED emits light. The LED driving register 141 includes a first data register 141a and a second data register 141b as storage areas having a storage capacity of 8 bits, and can store 16-bit information as a whole. Each data register 141a, 141b is connected to a data output circuit 134. The data output circuit 134 is configured to output the LED drive data SD toward the output port 131 based on the information stored in the data registers 141a and 141b.

  Specifically, the data output circuit 134 is provided with an n-type MOSFET 142 as a switching element. The source of the MOSFET 142 is grounded, and the drain is connected to the DATA terminal of the output port 131 while being pulled up to + 5V. A voltage of +5 V is applied between the source and drain. The gate of the MOSFET 142 is connected to the LED driving register 141 and is pulled up to + 3.3V. The + 3.3V is a voltage value larger than the threshold voltage of the MOSFET 142. A voltage (HI signal or LOW signal) corresponding to bit information stored in the LED driving register 141 is applied to the gate of the MOSFET 142.

  Specifically, when “0” information (LOW signal) is stored in a predetermined bit of the LED driving register 141, 0 V is applied to the gate of the MOSFET 142. In this case, the MOSFET 142 is turned off, and + 5V corresponding to the HI signal is input to the DATA terminal.

  On the other hand, when information (HI signal) of “1” is stored in a predetermined bit of the LED driving register 141 or when the information of the predetermined bit is indefinite, + 3.3V is applied to the gate of the MOSFET 142. Entered. In this case, the MOSFET 142 is turned on, and the source and drain are conducted. As a result, 0 V corresponding to the LOW signal is input to the DATA terminal.

  From the above, the data (voltage) output to the DATA terminal differs according to the bit information stored in the LED driving register 141.

  In such a configuration, the LED driving register 141 sequentially outputs each bit information to the DATA terminal in time series by sequentially changing the reference destination of the bit information that determines the input voltage to the gate of the MOSFET 142. It has become. As a result, the LED drive data SD stored in the LED drive register 141 is sequentially output to the DATA terminal of the output port 131.

  Here, in the situation where the LED drive data SD stored in one of the first data register 141a and the second data register 141b is being output, the LED to be output to the other data register in the future Setting of drive data SD is executed. Thereby, the transmission period of the LED drive data SD can be shortened by the period related to the writing of the LED drive data SD to the LED drive register 141.

  Next, the configuration related to the clock signal SG1 will be described. The register 122 is provided with a clock signal register 143 for controlling the clock signal SG1. The clock signal register 143 has a storage capacity of 1 bit, and information “1” and information “0” are alternately input at a predetermined cycle. The clock signal register 143 is connected to the data output circuit 134. The data output circuit 134 outputs a clock signal SG1 having a predetermined cycle to the output port 131 based on the switching of information in the clock signal register 143.

  Specifically, the data output circuit 134 is provided with an n-type MOSFET 144 as a switching element. The MOSFET 144 is connected to the CLK terminal of the output port 131 while the source is grounded and the drain is pulled up to + 5V. The gate of the MOSFET 144 is connected to the clock signal register 143 while being pulled up.

  According to such a configuration, the MOSFET 144 is alternately switched between ON and OFF based on the information written in the clock signal register 143 being alternately switched between “1” and “0” in a predetermined cycle. By switching ON / OFF of the MOSFET 144, the clock signal SG1 having the predetermined cycle is input to the CLK terminal. The clock signal SG1 is used for transmission of LED drive data SD in the LED board 91. Details of the transmission will be described later.

  Next, the configuration related to the data write signal SG2 will be described. The register 122 is provided with a data write signal register 145 corresponding to the data write signal SG2. The data write signal register 145 has a 1-bit storage capacity and is set so that information “1” is written when a predetermined condition is satisfied. The data write signal register 145 is connected to the data output circuit 134. The data output circuit 134 outputs a signal based on the information written in the data write signal register 145 to the output port 131.

  Specifically, the data output circuit 134 is provided with an n-type MOSFET 146 as a switching element. The MOSFET 146 is connected to the L terminal of the output port 131 while the source is grounded and the drain is pulled up to + 5V. The gate of the MOSFET 146 is connected to the data write signal register 145 while being pulled up.

  According to this configuration, when the information “1” is written in the data write signal register 145 or when the information stored in the data write signal register 145 is indefinite, the gate of the MOSFET 146 is connected to the HI. A voltage corresponding to the signal is input, and the MOSFET 146 is turned on. As a result, 0 V corresponding to the LOW signal is input to the L terminal.

  On the other hand, when “0” information is written in the data write signal register 145, 0V corresponding to the LOW signal is input to the gate of the MOSFET 146, and the MOSFET 146 is turned off. As a result, +5 V corresponding to the HI signal is input to the L terminal. The data write signal SG2 is used when setting LED drive data SD for each LED. Details of the setting will be described later.

  Next, the structure concerning each permission signal SG3, SG4 is demonstrated. The register 122 is provided with a first permission signal register 147 corresponding to the first permission signal SG3 and a second permission signal register 148 corresponding to the second permission signal SG4. Each of the enable signal registers 147 and 148 has a storage capacity of 1 bit and stores information of “1” or “0”. The permission signal registers 147 and 148 are connected to the data output circuit 134 via different buses. The data output circuit 134 outputs a signal corresponding to the information written in each of the permission signal registers 147 and 148 to the output port 131.

  Specifically, the data output circuit 134 is provided with an n-type MOSFET 149 corresponding to the first permission signal register 147 and an n-type MOSFET 150 corresponding to the second permission signal register 148. It has been. The sources of the MOSFETs 149 and 150 are grounded. The drain of the MOSFET 149 is connected to the E1 terminal of the output port 131 while being pulled up to + 5V, and the drain of the MOSFET 150 is connected to the E2 terminal of the output port 131 while being pulled up to + 5V. The gate of the MOSFET 149 is connected to the first permission signal register 147, and the gate of the MOSFET 150 is connected to the second permission signal register 148.

  According to such a configuration, a signal corresponding to the information written in the first permission signal register 147 is input to the E1 terminal, and a signal corresponding to the information written in the second permission signal register 148 is received. Input to the E2 terminal. Specifically, for example, when information “1” is set in the first permission signal register 147, a LOW signal is input to the E1 terminal, and information “0” is set in the first permission signal register 147. If it is, the HI signal is input to the E1 terminal.

  Here, in correspondence with the fact that the permission signal registers 147 and 148 are individually provided, two buses for connecting the permission signal registers 147 and 148 and the output port 131 are also provided. The output port 131 is provided with an E1 terminal and an E2 terminal. That is, the first permission signal SG3 and the second permission signal SG4 are configured to be transmitted in different systems. As a result, the first permission signal SG3 and the second permission signal SG4 can be individually controlled, and even if noise enters one of the signals, the influence of the noise hardly affects the other. It has become. These permission signals SG3 and SG4 are used to control lighting / extinction of each light emitting element. Details of the control will be described later.

  As already described, since the inputs to the gates of the MOSFETs 142, 144, 146, 149, 150 are pulled up, when the information in the register 122 is indefinite, the MOSFETs 142, 144, 146, 149, 150 Becomes ON. Thus, a LOW signal is input to each terminal (DATA terminal, CLK terminal, L terminal, E1 terminal, E2 terminal).

  Further, a + 5V power supply is connected in parallel to the bus connecting the drains of the MOSFETs 142, 144, 146, 149, and 150 and the output port 131, but on the bus connecting the bus and the + 5V power supply, , A clamp diode 160 is provided. The clamp diode 160 is connected with the + 5V power supply side as a cathode. As a result, when the potential on the bus temporarily rises due to noise entering the bus connecting the drain and the output port 131, a current temporarily flows to the + 5V power supply side, and the output A large current is prevented from flowing to the port 131 side.

  Further, a gate resistor 161 for preventing vibration is provided at the gate of each of the MOSFETs 142, 144, 146, 149, 150. The gate resistor 161 reduces the Q value (stability) of the parasitic resonance circuit due to the parasitic capacitances and parasitic inductances of the MOSFETs 142, 144, 146, 149, and 150, and makes it difficult for parasitic resonance to occur. Thereby, the influence by the said parasitic resonance can be suppressed.

  The output port 131 is provided with a + 5V terminal and a GND terminal. A + 5V power source is connected to the + 5V terminal, and + 5V is applied from the + 5V power source. On the other hand, the GND terminal is grounded.

  Next, a configuration in which each light emitting element is driven using these various signals will be described with reference to FIG. FIG. 15 is a circuit diagram of various circuits mounted on the LED substrate 91.

  As shown in FIG. 15, the LED board 91 is provided with an input port 171 having a plurality of input terminals, and various signals output from the output port 131 are individually input to the input port 171. The Various signals are output to the LED drive unit 172 provided on the LED substrate 91 via wiring. The LED driving unit 172 is connected to a plurality of LEDs 173 as a plurality of light emitting elements, and drives the LED 173 based on input of various signals.

  A Schmitt trigger type inverter 180 is provided on each wiring. The inverter 180 has a hysteresis characteristic in which the threshold voltage for HI output and the threshold voltage for LOW output are different. Thereby, it is possible to suppress the influence of noise mixed in various signals, for example, the occurrence of chattering.

  The LED driving unit 172 includes a plurality of LED driving ICs, and specifically, a first driving IC 191 to which LED driving data SD is input among various signals, and the first driving IC 191 in series. And a second driving IC 192 connected thereto. Each drive IC 191 and 192 has a plurality of input terminals and output terminals. Specifically, a DATAIN terminal (data input unit), a CLK terminal, an L terminal, an E terminal, a VDD terminal, and a GND terminal are input terminals. It has a DATAOUT terminal (data output unit) and a plurality of OUT terminals as output terminals. The DATAIN terminal of the first driving IC 191 is connected to the DATA terminal of the input port 171 via a wiring (wiring from the element control means), and the DATAIN terminal of the second driving IC 192 is connected to the wiring (series connection wiring). ) To the DATAOUT terminal of the first drive IC 191.

  The VDD terminal is connected to a + 5V power supply, and the GND terminal is grounded. The CLK terminal, the L terminal, and the E terminal are configured to receive the clock signal SG1, the data write signal SG2, and the first permission signal SG3 among various signals. The CLK terminal of 192 and the CLK terminal of the input port 171 are connected by wiring, the L terminal of each driving IC 191 and 192 and the L terminal of the input port 171 are connected by wiring, and each driving IC 191 and 192 are connected. The E terminal and the E1 terminal of the input port 171 are connected by wiring. In this case, the wirings are branched so that the clock signal SG1, the data write signal SG2, and the first permission signal SG3 are input to the drive ICs 191 and 192 in parallel. Accordingly, the clock signal SG1, the data write signal SG2, and the first permission signal SG3 are simultaneously input to the drive ICs 191 and 192. The first drive IC 191 and the second drive IC 192 are configured to transmit the LED drive data SD using the clock signal SG1, and to individually set each LED 173 using the data write signal SG2 and the first permission signal SG3. Has been.

  The internal configuration of each of the drive ICs 191 and 192 will be described in detail with reference to the block diagram of FIG. Here, since the internal configurations of the drive ICs 191 and 192 are the same, the first drive IC 191 will be described, and the description of the internal configuration of the second drive IC 192 will be omitted.

  As shown in FIG. 16, the first drive IC 191 includes an update circuit 191a that acquires and updates the LED drive data SD, and a register 191b in which the LED drive data SD is written. The update circuit 191a includes an update buffer 191c. The update buffer 191c has an 8-bit data area D0 to D7 and an output outdata area DA. The out data area DA is a copy area of the data area D7, and is the area in which the same information as the data area D7 is set. The out data area DA is connected to the DATAOUT terminal of the first drive IC 191 and is connected to the DATAIN terminal (data input unit) of the second drive IC 192 via the DATAOUT terminal and the wiring (series connection wiring). Yes. The update circuit 191a is connected to the DATAIN terminal to which the LED drive data SD is input, and is connected to the CLK terminal to which the clock signal SG1 is input. The update circuit 191a writes the LED drive data SD in the data area D0 in synchronization with the rising edge of the clock signal SG1, and sequentially shifts the data already written in the data areas D0 to D7. The update circuit 191a is configured to output data written in the out data area DA to the second drive IC 192 in synchronization with the falling edge of the clock signal SG1.

  An example of a specific configuration of the update circuit 191a will be briefly described. The update circuit 191a includes eight D flip-flops corresponding to the data areas D0 to D7. Each D flip-flop has an input terminal (D terminal), an output terminal (Q terminal), and a clock terminal, and a clock signal SG1 is input to each clock terminal. Each D flip-flop is configured to output the information input to the input terminal from the output terminal in synchronization with the rising edge of the clock signal SG1. Each D flip-flop is connected in series. Specifically, the output terminal of the D flip-flop corresponding to a predetermined data area Dx (for example, D0) has a data area D next to the predetermined data area Dx. The input terminal of the D flip-flop corresponding to (x + 1) (for example, D1) is connected via a bus. The LED driving data SD is input to the input terminal of the D flip-flop corresponding to the data area D0.

  The D flip-flop corresponding to the out data area DA is connected to the output terminal of the D flip-flop corresponding to the data area D7. Unlike the D flip-flops in the data areas D0 to D7, the D flip-flop is configured to output information input to the input terminal from the output terminal in synchronization with the falling edge of the clock signal SG1.

  The second drive IC 192 has the same configuration, but in order to distinguish it from the first drive IC 191, the update circuit of the second drive IC 192 is the update circuit 192a, the register of the second drive IC 192 is the register 192b, and the second drive The update buffer of the IC 192 is referred to as an update buffer 192c, the data areas of the update buffer 192c are referred to as data areas D8 to D15, and the OUT terminals of the second drive IC 192 are referred to as OUT8 terminals to OUT15 terminals.

  The configuration of the update circuit 191a is not limited to the D flip-flop, and for example, a JK flip-flop may be used. In short, the update circuit 191a has a plurality of information holding units and is configured to be able to input and output data, and is sequentially held in each information holding unit at a predetermined update timing. What is necessary is just to update data and to input / output data.

  In addition, a control CPU (control circuit) that outputs a control signal capable of individually controlling each data stored in the update buffer 191c may be provided.

  Here, as already described, since the DATAIN terminal of the second drive IC 192 and the DATAOUT terminal of the first drive IC 191 are electrically connected via a wiring, the update circuit 192a is synchronized with the rising edge of the clock signal SG1. Then, the LED drive data SD output from the first drive IC 191 (specifically, the data written in the out data area DA of the update buffer 191c of the update circuit 191a of the first drive IC 191) is written in the data area D8. The data already written in the data areas D8 to D15 are sequentially shifted. Further, the update circuit 192a outputs the data written in the out data area DA in synchronization with the falling edge of the clock signal SG1.

  The operation of the update circuit 191a will be described with reference to the timing chart of FIG. 17A shows the waveform of the clock signal SG1 input to the CLK terminal of the input port 171. FIG. 17B shows the data mode of the LED drive data SD input to the DATA terminal of the input port 171. 17C shows the actual waveform of the LED drive data SD input to the DATA terminal of the input port 171, FIG. 17D shows the mode of each data area D0 to D7, and FIG. 17E shows the DATAOUT terminal. The output waveform from is shown.

  Here, timings t2, t4, t5, and t7 are rising timings of the clock signal SG1, and timings t6 and t8 are falling timings of the clock signal SG1.

  As shown in FIGS. 17A, 17B, and 17C, the LED driving at the rising timing is synchronized with the rising edge of the clock signal SG1 in a situation where the LED driving data SD is sequentially input in time series. Data SD is set in data areas D0 to D7.

  Specifically, first, output of the LED drive data SD is started at a timing t1. Specifically, as shown in FIG. 17B, LED drive data SD (for example, “1”) set in the data area D8 of the second drive IC 192 is output. Thereafter, the update process by the update circuits 191a and 192a is performed when the clock signal SG1 rises at the timing of t2. In this case, since the LED drive data SD is “1” (HI signal), “1” is set to the data area D0. Specifically, the HI signal is output from the Q terminal of the D flip-flop corresponding to the data area D0.

  Subsequently, the LED drive data SD is updated at the timing of t3. Specifically, LED drive data SD (for example, “0”) set in the data area D7 is output. Thereafter, at time t4, the information “1” stored in the data area D0 is shifted to the data area D1, and the information of the LED drive data SD is set in the data area D0. Specifically, at the timing of t4, since the output of the LED drive data SD is “0” (LOW signal), “0” is set in the data area D0.

  As described above, every time the clock signal SG1 rises, the data stored in the data areas D0 to D7 are sequentially shifted (Dx → D (x + 1)) and output at that time. LED drive data SD is written in the data area D0. In this case, the LED drive data SD is sequentially updated, and the updated LED drive data SD is sequentially taken into the data area D0.

  Here, the update timing of the LED drive data SD (timing of t1, t3) and the updating timing of the data areas D0 to DA (timing of t2, t4) are set so as not to synchronize. Specifically, the rising timing of the clock signal SG1 is shifted by a predetermined period T1 with respect to the update timing of the LED drive data SD (specifically, it is delayed), and the update interval of the LED drive data SD is the clock. It is set to an integral multiple of the period T2 of the signal SG1 (specifically, equal multiple). As a result, the update timing of the LED drive data SD and the rising timing of the clock signal SG1 do not coincide, so that the update of the LED drive data SD and the update of the data areas D0 to D7 are not performed simultaneously. Yes. This makes it difficult for an acquisition error to occur when acquiring the LED drive data SD.

  That is, if the acquisition timing of the LED drive data SD and the update timing of the LED drive data SD are the same, it is not known whether the acquired LED drive data SD is the one before the update or after the update. Become. On the other hand, according to the present embodiment, since the acquisition timing of the LED drive data SD is delayed by a predetermined period T1 with respect to the update timing of the LED drive data SD, the LED drive data SD in a stable state is acquired. It becomes possible to do. Thereby, an acquisition error of the LED drive data SD is less likely to occur.

  In particular, the update interval of the LED drive data SD is set to be the same as the cycle T2 of the clock signal SG1. As a result, the update of the LED drive data SD and the update of the data area Dx are alternately performed, so that the same LED drive data SD is not reflected in the data area Dx.

  The predetermined period T1 may be set longer than the period required for updating the LED drive data SD, specifically, the period required for the rise of the LED drive data SD or the period required for the fall.

  At the timing t5 when the LED drive data SD is set for each of the data areas D0 to D7, the information of the data area D7 is written to the out data area DA as the data is written to the data area D7.

  Thereafter, at the timing of t6, the data written in the out data area DA is output. In this case, since the data to be written in the data area D8, specifically, information “1” is set in the out data area DA, an HI signal corresponding to “1” is output (FIG. 17 (e)). )reference).

  Thereafter, the data areas D0 to D7 are updated at the timing of t7. Specifically, the data in the data area Dx is shifted to the data area D (x + 1), and information on the LED drive data SD at the timing t7, specifically “1”, is written in the data area D0. Then, the information in the out data area DA is updated with the update of the information in the data area D7.

  In addition, the data areas D8 to D15 in the second drive IC 192 are updated in synchronization with the rising edge of the clock signal SG1. For this reason, at the timing of t7, data corresponding to the data area D8 output from the DATAOUT terminal of the first drive IC 191 is acquired, the data is written to the data area D8, and the data in the data areas D8 to D15 is shift. As a result, the LED drive data SD is set for the update buffer 192c. The LED drive data SD transmission mode and the operation of the second drive IC 192 performed between the first drive IC 191 and the second drive IC 192 will be described in detail later.

  At time t8, “0” written in the out data area DA is output.

  In other words, the LED drive data SD is taken in each time a predetermined update timing (rising timing of the clock signal SG1), and the data written in the data area Dx is transferred to the next data area D (x + 1). Shifted sequentially. The data in the out data area DA, which is a copy of the data area D7, is output every time when the timing is different from the update timing (falling timing of the clock signal SG1). As a result, the LED drive data SD is transmitted from the update buffer 191c of the first drive IC 191 to the update buffer 192c of the second drive IC 192.

  Note that the specific configuration of the update circuits 191a and 192a is not limited to that using the D flip-flop, and is arbitrary as long as it realizes the above operation.

  Returning to the description of FIG. 16, the register 191b has 8-bit data areas D′ 0 to D′ 7, and the data areas D′ 0 to D′ 7 are data areas D0 to D7 of the update buffer 191c, respectively. Connected to. The data areas D′ 0 to D′ 5 are each connected to the LED 173 via an output terminal. Further, the register 191b is configured to receive the data write signal SG2 and the first permission signal SG3. The register 191b transfers the data set in the data areas D0 to D7 to its own data areas D′ 0 to D′ 7 based on the rise of the data write signal SG2 in the situation where the first permission signal SG3 is LOW. And the data is output to the LED 173 via each OUT terminal (OUT0 terminal to OUT7 terminal). Each LED 173 is configured to operate based on the output data.

  Specifically, the anode of each LED 173 is connected to a + 5V power source, and the cathode of each LED 173 is connected to the corresponding data region D'0 to D'5. According to this configuration, for example, when the data area D0 is “1”, “1” is set in the data area D′ 0, and the potential corresponding to the data area D′ 0 to “1” (in detail). + 5V) is output. In this case, since no potential difference occurs between the anode and cathode of the LED 173, the LED 173 does not emit light. On the other hand, when the data area D0 is “0”, “0” is set in the data area D′ 0, and the potential corresponding to “0” (specifically, 0 V) is output from the data area D′ 0. Is done. In this case, a potential difference is generated between the anode and cathode of the LED 173, and the LED 173 emits light. In other words, when the data area Dx is “0”, it can be said that the cathode of the LED 173 is grounded, and the LED 173 is supplied with power capable of emitting light.

  Returning to the description of FIG. 15, the LED board 91 is provided with a winning notification circuit 201 for driving the winning notification LED 37. The winning notification circuit 201 is connected to the second drive IC 192, and the LED drive data SD is transmitted from the second drive IC 192. The winning notification circuit 201 is configured to receive a clock signal SG1, a data write signal SG2, and a second permission signal SG4, and drives the winning notification LED 37 based on these signals.

  The winning notification circuit 201 will be described with reference to the circuit diagram of FIG.

  The winning notification circuit 201 includes a voltage applying circuit 202 that applies a voltage to the winning notification LED 37 and a third driving IC 203 that controls the driving of the voltage applying circuit 202. Similar to the first drive IC 191, the third drive IC 203 includes a DATAIN terminal, a CLK terminal, an L terminal, and an E terminal as input terminals, and includes an OUT16 terminal to an OUT23 terminal and a DATAOUT terminal as output terminals. . Each terminal (DATAIN terminal, CLK terminal, L terminal) is configured to receive LED drive data SD, clock signal SG1, and data write signal SG2, respectively.

  Here, the third drive IC 203 is connected in series to the first drive IC 191 and the second drive IC 192. Specifically, the DATAOUT terminal of the second drive IC 192 is wired (in series) to the DATAIN terminal of the third drive IC 203. Connected via a connection wiring). As a result, the LED drive data SD is input to the third drive IC 203 via the first drive IC 191 and the second drive IC 192. In this case, it can be said that the third drive IC 203 is provided on the most downstream side of the transmission path through which the LED drive data SD is transmitted. Since the operation of the third drive IC 203 is the same as that of the first drive IC 191, description thereof is omitted.

  Unlike the drive ICs 191 and 192, the third drive IC 203 receives the second permission signal SG4. Specifically, the E2 terminal of the input port 171 is connected to the E terminal of the third drive IC 203 (see FIG. 15). Therefore, the third drive IC 203 outputs a signal corresponding to the LED drive data SD via the OUT16 terminal to the OUT23 terminal based on the rise of the data write signal SG2 in a situation where the second permission signal SG4 is LOW. .

  The voltage application circuit 202 is connected to the third driving IC 203 and receives the second permission signal SG4. The voltage application circuit 202 applies a voltage at which the winning notification LED 37 can emit light to the winning notification LED 37 when the signal from the third driving IC 203 and the second permission signal SG4 satisfy a predetermined condition.

  Specifically, the voltage application circuit 202 includes a winning notification LED 37, and a p-type MOSFET 211 and an n-type MOSFET 212 connected in series to the winning notification LED 37. The winning notification LED 37 is connected to a + 5V power source via a p-type MOSFET 211 and is grounded via an n-type MOSFET 212. Specifically, the drain of the p-type MOSFET 211 is connected to the anode of the winning notification LED 37, the source is connected to the + 5V power source, and the drain of the n-type MOSFET 212 is connected to the cathode of the winning notification LED 37. The source is grounded. The gate of the p-type MOSFET 211 is connected to the OUT16 terminal of the third drive IC 203, and the gate of the n-type MOSFET 212 is connected to the E2 terminal via the Schmitt inverter 213.

  According to such a configuration, when (A) LOW is output from the OUT16 terminal of the third drive IC 203 and (B) the second permission signal SG4 is LOW, both MOSFETs 211 and 212 are turned on, and the winning notification is made. A voltage is applied to the LED 37 and the winning notification LED 37 emits light. In this case, even if either one of the conditions (A) and (B) is satisfied, no current flows through the winning notification LED 37, and the winning notification LED 37 does not emit light.

  Since the gate of the n-type MOSFET 212 is pulled down, the n-type MOSFET 212 is turned off when the second permission signal SG4 is indefinite. Thus, when the second permission signal SG4 is indefinite, the winning notification LED 37 is not turned on.

  Here, a time constant circuit 221 for processing the LED drive data SD output from the OUT16 terminal is provided on the wiring connecting the OUT16 terminal of the third drive IC 203 and the p-type MOSFET 211. The time constant circuit 221 includes a resistor 222 provided on the wiring and a capacitor 223 connected in parallel to the resistor 222. One end of the resistor 222 is connected to the OUT16 terminal, and the other end of the resistor 222 is connected to the gate of the p-type MOSFET 211. One end of the capacitor 223 is connected to the other end of the resistor 222, and the other end of the capacitor 223 is grounded. Further, the wiring connecting the OUT16 terminal of the third driving IC 203 and one end of the resistor 222 is connected to the + 5V power source via the pull-up resistor 224 and pulled up.

  According to such a configuration, HI is input to the p-type MOSFET 211 when the signal output from the OUT16 terminal is HI or open. For this reason, the p-type MOSFET 211 is turned off.

  On the other hand, when the signal output from the OUT16 terminal becomes LOW, the LOW signal output from the OUT16 terminal is delayed and input to the gate of the p-type MOSFET 211 due to the transient phenomenon of the resistor 222 and the capacitor 223. Specifically, when the signal output from the OUT16 terminal becomes LOW, the charge accumulated in the capacitor 223 is discharged (discharge state), and a voltage corresponding to the charge discharged to the gate of the p-type MOSFET 211 is obtained. Applied. As a result, the LOW signal is input to the gate of the p-type MOSFET 211 after a predetermined period has elapsed since the signal output from the OUT16 terminal becomes LOW, and the p-type MOSFET 211 is turned on. The predetermined period is determined by the resistance value R of the resistor 222 and the capacitance C of the capacitor 223. Specifically, the predetermined period is set longer than the execution period of the sound emission control process performed by the sound lamp control device 90 described later. ing.

  In this case, when the signal at the OUT16 terminal becomes HI during the discharging state of the capacitor 223, the capacitor 223 shifts from the discharging state in which charges are discharged to the charging state in which charges are accumulated. For this reason, the p-type MOSFET 211 is kept OFF. That is, the p-type MOSFET 211 is turned on based on the LOW signal continuing from the OUT16 terminal for the predetermined period. As a result, when the output from the OUT16 terminal temporarily becomes LOW due to the influence of noise or the like, or a LOW signal temporarily enters the wiring connecting the OUT16 terminal and the gate of the p-type MOSFET 211 due to noise or the like. Even in this case, the p-type MOSFET 211 remains OFF, so that the winning notification LED 37 does not emit light. Therefore, it is possible to suppress malfunction of the winning notification LED 37 due to noise. In other words, the time constant circuit 221 outputs the LOW signal to the voltage application circuit 202 based on the output of the LOW signal as the drive signal from the third drive IC 203 over a predetermined period. You can say that.

  Further, the time constant circuit 221 has frequency characteristics, and a signal having a frequency higher than the specific frequency f0 predetermined by the time constant circuit 221 is attenuated, while a signal having a frequency lower than the specific frequency f0 passes. To do. Thereby, when the high frequency noise of the frequency higher than the specific frequency f0 is mixed in the signal passing through the time constant circuit 221, the high frequency noise is removed. As a result, a signal from which high-frequency noise has been removed is input to the gate of the p-type MOSFET 211, thereby avoiding the disadvantage that the p-type MOSFET 211 malfunctions due to high-frequency noise.

  The specific frequency f0 is determined by the capacitance C of the capacitor 223 and the resistance value R of the resistor 222 (f0 = 1 / 2πRC), and the time constant circuit 221 is a signal that controls the driving of the winning notification LED 37. The capacitance C and the resistance value R are set so as not to be removed. Specifically, the specific frequency f0 is set to be larger than the light emission frequency (light emission interval) of the winning notification LED 37. Here, the winning notification LED 37 is set to emit light in seconds from the viewpoint of attracting attention to the player. For this reason, each electrostatic capacitance C and resistance value R are set so that the specific frequency f0 is 1 Hz or more.

  Further, only the voltage application circuit 202 is connected to the OUT16 terminal of the third driving IC 203, and the other OUT terminals (OUT17 to OUT23 terminals) are open. This suppresses noise from being mixed into the signal output from the OUT16 terminal due to the influence of the wiring connected to the other OUT terminal.

  Furthermore, since the voltage application circuit 202 is provided, unlike the drive ICs 191 and 192, the current flowing through the winning notification LED 37 does not flow directly into the third drive IC 203. This makes it difficult for the third drive IC 203 to be broken due to a high current flowing in the third drive IC 203.

  That is, in order to make the emission intensity of the LED 37 for winning notification larger than that of the other LEDs 173, it is necessary to increase the current flowing through the LED 37 for winning notification. In this situation, if the current flowing through the winning notification LED 37 directly flows into the third drive IC 203, the third drive IC 203 may be destroyed. On the other hand, according to the present embodiment, the third drive IC 203 only controls the p-type MOSFET 211, and the current path of the winning notification LED 37 is independent of the third drive IC 203. This prevents the current flowing through the winning notification LED 37 from flowing into the third drive IC 203.

<Various Processes Executed by the Audio Lamp Control Device 90>
Next, various processes performed by the sub CPU 111 of the sound lamp control device 90 will be described. Various processes performed by the sub CPU 111 include a sound emission control process for controlling the speaker unit 55 and the LED 173, and a startup process performed when the power is turned on. Hereinafter, these processes will be described.

  First, the startup processing of the sound lamp control device 90 will be described with reference to the flowchart of FIG. The start-up process is executed when the pachinko machine 10 is turned on.

  First, in step S701, each permission signal SG3, SG4 is set so that each drive IC 191, 192, 203 does not operate. Specifically, “1” is set to each of the permission signal registers 147 and 148 so that the permission signals SG3 and SG4 become HI.

  In this case, as already described, since the bus connecting each permission signal register 147, 148 and the gate of the corresponding MOSFET 149, 150 is pulled up, the information in each permission signal register 147, 148 is indefinite. Even if it exists, each permission signal SG3, SG4 becomes HI. Thus, the drive ICs 191, 192, and 203 are less likely to malfunction even before the process of setting “1” to each of the permission signal registers 147 and 148.

  In subsequent step S702, various start-up processes are executed. Specifically, initialization processing of the RAM 113 in the sub CPU 111 is executed, or abnormality determination processing for determining whether or not there is an abnormality is executed. In addition, an initialization signal is output to the display control device 100, the speaker unit 55, and the LED substrate 91 connected to the audio lamp control device 90, and the display control device 100, the speaker unit 55, and the LED substrate 91 are initialized. Control to be performed.

  Thereafter, in step S703, it is determined whether or not a predetermined period has elapsed. If the predetermined period has not elapsed, the process of step S703 is executed again. The predetermined period is set longer than the period related to the initialization of the display control device 100, the speaker unit 55, and the LED substrate 91. Thereby, it can be said that the audio lamp control device 90 is on standby until the initialization of the device to be controlled is completed.

  Note that the measurement during this period is performed by counting the number of processing times in step S703. For example, if the time required from executing a negative determination in step S703 to executing the process in step S703 again is 0.1 msec, the count value becomes 10,000 times, so that various startup processes in step S703 are performed. It is determined that 1 sec has passed. Note that the specific configuration of the period measurement is arbitrary. For example, the period measurement may be performed using a real-time clock. If it is determined in step S703 that the predetermined period has elapsed, the process proceeds to step S704.

  In step S704, the first permission signal SG3 is set to LOW while the second permission signal SG4 is set to HI. Specifically, “0” is set to the first permission signal register 147, while “1” is set to the second permission signal register 148. As a result, the first drive IC 191 and the second drive IC 192 are operable, while the third drive IC 203 is inoperable.

  From the above, by setting each permission signal SG3, SG4 to HI at the stage before executing various start-up processes, the drive ICs 191, 192, 203 do not operate during the various start-up processes. Yes. Accordingly, it is possible to prevent the drive ICs 191, 192, and 203 from malfunctioning when the power is turned on, and the LED 173 and the winning notification LED 37 from malfunctioning. Then, after the start-up is completed, each of the drive ICs 191 and 192 can be operated, and each LED 173 can emit light. In this case, since the second permission signal SG4 is HI, the winning notification LED 37 does not emit light.

  Next, the sound emission control process will be described with reference to the flowchart of FIG. The sound emission control process is activated at a predetermined cycle, specifically, at a cycle of 4 msec. The sound emission control process executes a process corresponding to various commands transmitted from the main control device 60.

  First, in step S801, it is determined whether or not the command received from the main control device 60 is a changing command. If it is a change command, the process advances to step S802 to execute change start processing.

  The variation start process will be described with reference to the flowchart of FIG.

  First, in step S901, based on the change command and the type command, the presence / absence of a jackpot in the current game round is determined, and if it is a jackpot, the type and reach occurrence are determined.

  Thereafter, in step S902, it is determined whether or not the jackpot is based on the grasped result. If it is determined that the game is a big win, a winning notification effect lottery process is executed in step S903.

  Specifically, an effect lottery counter area 113a is provided in the RAM 113 of the sound lamp control device 90, and an effect lottery counter that is updated at a predetermined cycle is stored in the area. In step S903, the value of the current effect lottery counter is acquired, and the value of the counter is determined in advance by referring to the winning notification effect lottery table stored in the winning notification effect lottery table storage area 112a. It is determined whether or not it corresponds.

  Note that a plurality of predetermined winning values are set in the winning notification effect drawing lottery table, and the winning probability is determined by the ratio between the number of winning values and the number of values that the drawing lottery counter can take. In such a configuration, a plurality of winning notification effect lottery tables with different numbers of winning values set may be provided, and the winning probability of the winning notification effect may be switched by switching the winning notification effect lottery table to be referenced according to the game situation. Good.

  If the winning notification effect is won, the process proceeds to step S904, and the LED drive pattern table corresponding to the winning notification effect is set. The ROM 112 is provided with an LED drive pattern table storage area 112b, and a plurality of types of LED drive pattern tables are stored in the LED drive pattern table storage area 112b. Each LED drive pattern table is a table in which the LED drive data SD is set in a one-to-one correspondence with the information of the period from when the variable display on the main display unit 33 is started. Thereby, when a predetermined period has elapsed since the start of the variable display, the LED drive data SD corresponding to the period is obtained by referring to the LED drive pattern table, and the obtained LED drive data SD is obtained. By setting, each LED 173 is driven and controlled.

  In the process of step S905, the LED drive pattern table corresponding to the winning notification effect is selected as the LED drive pattern table to be referred to in the current game round. The LED drive pattern table corresponding to the winning notification effect is a table set so that the winning notification LED 37 emits light at a predetermined timing.

  On the other hand, if it is not a big win (step S902: NO), or if the winning notification effect is not won (step S904: NO), the process proceeds to step S906, and other effect determination processing is executed. In other effects determination processing, effects other than the winning notification effect are determined.

  Thereafter, in step S907, an LED drive pattern table corresponding to other effects is selected as the LED drive pattern table to be referred to in the current game round. The LED drive pattern table corresponding to the other effects is a table set so that the winning notification LED 37 does not emit light.

  After execution of the process of step S905 or step S907, writing of the LED drive data SD is started in step S908. Specifically, all LED drive data SD corresponding to the change start timing is acquired by referring to the LED drive pattern table selected in step S905 or step S907. Of the acquired all LED drive data SD, the data corresponding to the storage capacity (8 bits) of each of the data registers 141a and 141b is transferred to one of the data registers 141a and 141b (specifically, the first data register 141a).

  In a succeeding step S909, processing for outputting the clock signal SG1 is executed. Specifically, information “1” and information “0” are alternately set in the clock signal register 143. Thereby, transmission of the LED drive data SD is started. In this case, when the output of the clock signal SG1 is started, the LED drive data SD stored in the first data register 141a is first set to be transmitted first.

  Thereafter, in step S910, the LED drive data SD is written. Specifically, the non-input LED drive data SD is written into a data register different from the previously written data register. For example, if the LED drive data SD is written to the first data register 141a in the previous LED drive data write process, the LED drive data SD is written to the second data register 141b. Switch the writing target. In this case, the LED driving register 141 is configured to transmit the information of the data register to which data has not been written. That is, the LED drive data SD is alternately written to the first data register 141a and the second data register 141b, and the LED drive data SD of the register that has not been written is transmitted. . Thereby, the transmission period of the LED drive data SD can be shortened.

  In subsequent step S911, it is determined whether or not writing of all LED drive data SD to the LED drive register 141 is completed, and the writing process of LED drive data SD and the above determination process are repeated until the writing is completed. Specifically, in step S911, it is determined whether there is any LED drive data SD that has not yet been input to the LED drive register 141 among all the LED drive data SD. If it is determined in the determination process that there is uninput LED drive data SD, the non-input LED drive data SD is sequentially written in step S910.

  Here, the relationship between the writing of the LED drive data SD and the output of the clock signal SG1 will be described. The output of the clock signal SG1 is started after the writing of the LED drive data SD is started. Specifically, the output of the clock signal SG1 is started after the first writing of the LED drive data SD is performed. Thereafter, the LED drive data SD is written while performing a writing process to the clock signal register 143 so that the clock signal SG1 is output. This suppresses transmission of indefinite information that does not correspond to the acquired LED drive data SD.

  Note that the determination process in step S911 is not limited to this. For example, the number of times the LED drive data SD has been written is counted, and whether or not the count is the number of times required to write all the LED drive data SD is determined. It is good also as a structure to determine. Further, when the LED drive data SD is written, it may be determined whether there is a free area in the data register to which the writing is performed. In short, it is optional as long as it is possible to specify that writing of all LED drive data SD has been completed.

  When the writing of the LED drive data SD is completed, the process proceeds to step S912, and a process for raising the data write signal SG2 is executed. Specifically, “0” is set to the data write signal register 145. As a result, the data write signal SG2 rises. In synchronization with the rise, each drive IC 191, 192, 203 outputs a signal corresponding to the LED drive data SD from each OUT terminal.

  Here, although not shown in the figure, between step S911 and step S912, there is a wait period for transmitting the last written LED drive data SD, specifically, a period corresponding to eight cycles of the clock signal SG1. Is provided. This avoids the inconvenience that the data write signal SG2 rises before the last written LED drive data SD is transmitted. That is, it is specified that the transmission of the LED drive data SD is completed by the determination process in step S911 (and the process of setting the wait period after the determination process is affirmed). In other words, it can be said that the determination process of step S911 is a process of determining whether or not the transmission of the LED drive data SD is completed.

  Thereafter, in step S913, a process of stopping the clock signal SG1 is executed, and in step S914, other processes related to the control of the speaker unit 55 and the control of the display control device 100 are executed, and this variation start process is ended. To do.

  The operation of the first drive IC 191 and the second drive IC 192 when such processing is performed will be described with reference to the timing chart of FIG. 22A shows the waveform of the clock signal SG1 input to the CLK terminal of the input port 171. FIG. 22B shows the waveform of the LED drive data SD input to the DATA terminal of the input port 171. 22 (c) shows the modes of the data areas D0 to D7 and the out data area DA, FIG. 22 (d) shows the output waveform of the DATAOUT terminal of the first drive IC 191, and FIG. 22 (e) shows the data areas D8 to D15 and the out data area DA. FIG. 22F shows the waveform of the data write signal SG2 input to the L terminal of the input port 171. FIG. The timings t12, t13, t15, t17, t18, and t21 are the rising timings of the clock signal SG1, and the timings t14, t16, and t19 are the falling timings of the clock signal SG1.

  First, the writing of the LED drive data SD to the LED drive register 141 is started at the timing t11, and the output of the LED drive data SD is started. Thereafter, at the timing t12, the output of the clock signal SG1 is started, and the update of the data areas D0 to D7 is started. In this case, since the clock signal SG1 is simultaneously input to each of the first driving IC 191 and the second driving IC 192, the data areas D8 to D15 are also updated in the second driving IC 192.

  Since the outdata area DA of the first drive IC 191 is indefinite at the timing t12, the second drive IC 192 acquires indefinite information. For convenience of explanation, a data area in which indefinite information is stored is indicated by a blank. The output from the DATAOUT terminal when the outdata area DA is indefinite is shown as 0V.

  After that, when the information “1” acquired at the timing t12 is set in the data area D7 of the first drive IC 191 at the timing t13, t14 which is the subsequent falling timing of the clock signal SG1. At this timing, the information “1” is output from the DATAOUT terminal.

  At the timing t15, the data areas D0 to D7 of the first drive IC 191 are updated, and the data areas D8 to D15 of the second drive IC 192 are updated. In this case, since the information “1” is output from the DATAOUT terminal of the first drive IC 191, the second drive IC 192 sets the information “1” for the data area D8. On the other hand, the first drive IC 191 acquires new LED drive data SD in the data area D0 and sequentially shifts information written in the data areas D0 to D7. As a result, the information in the data area D7 is updated to “0”, and the information in the outdata area DA is updated to “0”.

  Thereafter, the information in the outdata area DA is output to the second drive IC 192 via the DATAOUT terminal at the timing of t16. As a result, the output from the DATAOUT terminal becomes “0”. Then, at the timing t17, the second drive IC 192 shifts the information written in the data area D8 to the data area D9 and writes the information “0” in the data area D8.

  That is, the LED drive data SD is sequentially set to the data regions D8 to D15 of the second drive IC 192 by sequentially shifting the LED drive data SD from the first drive IC 191 toward the second drive IC 192 like a bucket relay. Is done. Thereby, the LED drive data SD can be transmitted to the second drive IC 192 without setting the LED drive data SD directly to the second drive IC 192. Therefore, it is not necessary to separately provide wiring for transmitting the LED driving data SD for each of the driving ICs 191 and 192, and thus wiring for driving the LED 173 can be reduced.

  Here, the LED drive data SD acquisition timing (update timing of the data areas D0 to D16) and the LED drive data SD transmission timing (output timing of the out data area DA) in each of the drive ICs 191 and 192 are different. Specifically, the acquisition timing of the LED drive data SD is delayed by a half cycle of the clock signal SG1 from the transmission timing of the LED drive data SD. As a result, transmission errors are less likely to occur when LED drive data SD is transmitted between the drive ICs 191 and 192.

  In other words, if the acquisition timing of the LED drive data SD and the transmission timing of the LED drive data SD are the same, the acquired LED drive data SD is the newly output LED drive data SD or is output until then. It is not known whether the LED driving data SD has been made, and it becomes unstable. In other words, the LED drive data SD may be transmitted correctly or may not be transmitted correctly. On the other hand, according to the present embodiment, since the acquisition timing of the LED drive data SD is delayed by a predetermined period (half cycle of the clock signal SG1) with respect to the transmission timing of the LED drive data SD, the stable state LED drive data SD can be acquired. As a result, transmission errors of the LED drive data SD between the drive ICs 191 and 192 are less likely to occur. Therefore, inconveniences that may occur due to the configuration in which the LED drive data SD is transmitted between the drive ICs 191 and 192 can be avoided.

  In particular, the acquisition timing of the LED drive data SD and the transmission timing of the LED drive data SD are shifted using the same clock signal SG1. Specifically, the data areas D0 to D15 are updated at the rising edge of the clock signal SG1, and the LED drive data SD is output at the falling edge of the clock signal SG1. As a result, even if the clock signal SG1 is delayed by the influence of noise, parasitic capacitance, etc. and input to each of the drive ICs 191 and 192, the period corresponding to the deviation, specifically, the half cycle of the clock signal SG1 The period of minutes is secured. Thereby, the inconvenience that the acquisition timing and the transmission timing are synchronized due to the delay of the clock signal SG1 or the like can be avoided.

  The interval from the rising edge to the falling edge of the clock signal SG1, that is, the pulse width is set to be longer than the period required for updating the update circuit 191a and the like. Thus, it is possible to avoid the output of the LED drive data SD before the update of the update circuit 191a is completed.

  Further, the interval from the falling edge to the rising edge of the clock signal SG1 is set to be longer than the period required to output the LED drive data SD in the out data area DA. As a result, the update process of the update circuit 191a is performed before the output of the LED drive data SD is completed, and it is possible to avoid a transmission error of the LED drive data SD.

  The interval adjustment between the acquisition timing and the transmission timing can be easily realized by adjusting the duty ratio and the frequency of the clock signal SG1. In other words, by adjusting the duty ratio and the frequency of the clock signal SG1, the acquisition timing of the LED drive data SD and the output of the LED drive data SD from the out data area DA so that the transmission error of the LED drive data SD does not easily occur. The interval with the timing can be adjusted. Thereby, generation | occurrence | production of the transmission error of LED drive data SD can be reduced more suitably.

  Further, the clock signal SG1 is configured to be input in parallel to the drive ICs 191 and 192. As a result, the clock signal SG1 is less likely to shift between the drive ICs 191 and 192, and the inconvenience that the acquisition timing and the transmission timing are synchronized due to the shift of the clock signal SG1 is avoided.

  Similarly, for the third drive IC 203, the LED drive data SD is acquired from the second drive IC 192, and the acquired LED drive data SD is set for the data area D0. In this case, similarly to the transmission of the LED drive data SD between the first drive IC 191 and the second drive IC 192, the acquisition timing of the LED drive data SD is delayed with respect to the output timing of the LED drive data SD.

  Incidentally, the delay of the LED drive data SD will be described. The transmission distance of the LED drive data SD in each drive IC 191, 192, 203 is sufficiently shorter than the transmission distance between the drive ICs 191, 192 or between the drive ICs 192, 203. For this reason, the delay caused by the transmission of the LED drive data SD between the drive ICs 191 and 192 or between the drive ICs 192 and 203 is dominant.

  Thereafter, at the timing t18, writing of the LED driving data SD to the LED driving register 141 is completed, and transmission of the LED driving data SD to the driving ICs 191 and 192 is completed. The period from the timing t11 to the timing t18 is a period required for transmitting the LED drive data SD.

  Here, the LED drive data SD when the winning notification effect is not performed, that is, the LED drive data SD set in the LED drive pattern table corresponding to the other effects (also simply referred to as normal LED drive data SDa in the following description). Only has information corresponding to the first driving IC 191 and the second driving IC 192, and does not have information corresponding to the third driving IC 203. Specifically, the normal LED drive data SDa corresponds only to the data area D0 to the data area D15, and has 16-bit information as a whole. As a result, the processing load for writing the LED drive data SD is reduced by the amount of processing related to the setting of the LED drive data SD corresponding to the LED 37 for winning notification, and the period required for transmitting the LED drive data SD is reduced. ing.

  In addition, if a data area (in detail, a data area corresponding to the output of the OUT16 terminal in the third drive IC 203) that controls the drive of the winning notification LED 37 is arranged upstream of the data areas D0 to D15, The LED drive data SD corresponding to the data areas D0 to D15 is set via the data area corresponding to the winning notification LED 37, and the period required for transmission of the LED drive data SD is increased by the amount corresponding to the above. .

  On the other hand, according to the present embodiment, the third driving IC 203 that drives the winning notification LED 37 is disposed downstream of the first driving IC 191 and the second driving IC 192. The data area corresponding to is arranged downstream of the data areas D0 to D15. As a result, the LED drive data SD is set for each of the data areas D0 to D15 without going through the data area corresponding to the winning notification LED 37, so the comparison is made with the configuration in which the third drive IC 203 is arranged on the upstream side. Thus, the period required for transmitting the LED drive data SD can be shortened.

  Thereafter, the data write signal SG2 rises at timing t19. In synchronization with the rise of the data write signal SG2, the LED drive data SD written in the update buffers 191c and 192c on the condition that the first permission signal SG3 is LOW is registered in the registers 191b and 191b of the drive ICs 191 and 192, respectively. Each LED 173 written to 192b and connected to each drive IC 191 and 192 is driven. On the other hand, since the second permission signal SG4 is HI, the third drive IC 203 does not operate. A period T3 from the timing t11 to t19 is a period required for the drive ICs 191 and 192 to control the LEDs 173, and is a period required for control of the LEDs 173 when the winning notification effect is not performed.

  The period T3 is set to be shorter than 4 msec, which is the execution cycle of the sound emission control process. Specifically, the frequency of the clock signal SG1 is set so that the period T3 is shorter than the execution cycle of the sound emission control process, and specifically, the frequency of the clock signal SG1 is set to several hundred MHz. Thereby, the setting of the mode of each LED 173 is completed within the execution cycle of the sound emission control process.

  Further, since the LED write data SG2 rises after the transmission of the LED drive data SD is completed, the LED drive data SD is written to the register 122, so that the LEDs 173 are driven simultaneously. As a result, there is no variation in the drive timing of the LED 173 that may be caused by sequentially transmitting the LED drive data SD.

  Thereafter, the output of the clock signal SG1 is stopped at the timing t20. Thereby, each drive IC191,192 maintains the state currently set. Therefore, each LED 173 maintains its light emission mode for a predetermined period after the timing t19, specifically, until the next LED drive data SD is transmitted and the rising edge of the data write signal SG2 occurs. It becomes.

  Thereafter, at the timing of t21, the data areas D0 to D15 are updated based on the input of the clock signal SG1 and the input of the LED drive data SD.

  Returning to the description of the sound emission control process (FIG. 20), if a change command has not been received, the process proceeds to step S803 to determine whether or not the change is in progress. If it is changing, the process proceeds to step S804, and the changing process for updating the LED drive data SD is executed.

  The changing process will be described with reference to the flowchart of FIG.

  First, in step S1001, it is determined whether it is the update timing of the LED drive data SD by referring to the LED drive pattern table. As already described, in the LED drive pattern table, period information indicating a period from the variation start timing is set, and whether or not the elapsed period from the variation start timing in this processing time corresponds to the period information. Determine.

  If it is not the update timing of the LED drive data SD, the process proceeds to step S1016. If it is the update timing of the LED drive data SD, it is determined in step S1002 whether the current game time corresponds to the winning notification effect. Determine whether. Specifically, it is determined whether or not the selected LED drive pattern table is a variation pattern table corresponding to the winning notification effect.

  If it is the LED drive pattern table corresponding to the winning notification effect, the process proceeds to step S1003. In step S1003, it is determined by referring to the LED drive pattern table whether or not it is the winning notification effect start timing. In the LED drive pattern table corresponding to the winning notification effect, specific information capable of specifying the winning notification effect start timing is set corresponding to the period information, and in the process of step S1003, the specific information is set. It is determined whether or not it has been done.

  If it is the winning notification effect start timing, the process proceeds to step S1004, where “0” is set in the second permission signal register 148. As a result, the second permission signal SG4 becomes LOW, the third drive IC 203 becomes operable, and the n-type MOSFET 212 of the voltage application circuit 202 is turned on.

  In a succeeding step S1005, a process for updating the LED drive data SD is executed. Specifically, by referring to the LED drive pattern table, the LED drive data SD corresponding to this processing time is grasped. The LED drive data SD is data set so that the winning notification LED 37 emits light. Specifically, “0” data is output so that “0” is output from the OUT 16 terminal of the third drive IC 203. Is added. That is, the LED driving data SD (hereinafter also referred to as specific LED driving data SDb) when performing the winning notification effect performs the winning notification effect as much as it has data that determines the output mode of the third driving IC 203. The amount of information is set to be larger than the LED drive data SD (ordinary LED drive data SDa) set when there is not, and the information amount is 17 bits as a whole.

  On the other hand, if it is not the winning notification effect start timing, the process proceeds to step S1006 to determine whether it is the winning notification effect end timing. Specifically, in the LED pattern table corresponding to the winning notification effect, specific information for specifying the end timing of the winning notification effect is set in correspondence with the period information, and in the process of step S1006, It is determined whether specific information is set.

  If it is determined that it is not the winning notification effect end timing, the process proceeds to step S1007 to execute a process of updating the LED drive data SD. Specifically, the LED drive data SD corresponding to this processing time is grasped by referring to the LED drive pattern table corresponding to the winning notification effect. The LED drive data SD is specific LED drive data SDb set so that the winning notification LED 37 emits light. Specifically, “0” is output from the OUT 16 terminal of the third drive IC 203. This is data to which information of “0” is added.

  On the other hand, if it is determined that it is the end timing of the winning notification effect, the process proceeds to step S1008, and “1” is written in the second permission signal register 148. As a result, the second permission signal SG4 becomes HI.

  Thereafter, in step S1009, processing for updating the LED drive data SD is executed. Specifically, the LED drive data SD corresponding to this processing time is grasped by referring to the LED drive pattern table corresponding to the winning notification effect. The LED drive data SD does not have data for determining the output mode of the third drive IC 203, but has only data for determining the output mode of the first drive IC 191 and the second drive IC 192. Data SDa.

  That is, when performing the winning notification effect, the specific LED driving data SDb to which data for determining the output mode of the third driving IC 203 is added during the winning notification effect period is updated. The specific LED drive data SDb is LED drive data SD set to be LOW output from the OUT16 terminal of the third drive IC 203.

  Here, the update timing of the LED drive data SD is set so that the LOW signal output from the OUT16 terminal of the third drive IC 203 continues for at least a plurality of processing times (specifically, 3 times). Thereby, the LOW signal output from the OUT16 terminal is continued over a period corresponding to a plurality of processing times. Note that the present invention is not limited to the above configuration. For example, in the LED drive pattern table corresponding to the winning notification effect, the LED drive data SD output LOW from the OUT16 terminal of the third drive IC 203 over a period corresponding to a plurality of processing times. It is good also as a structure set so that it may update.

  If the current game time does not correspond to the winning notification effect (step S1002: NO), an LED drive data update process is executed in step S1010. Specifically, by referring to the LED drive pattern table selected in the current game round, specifically the LED drive pattern table corresponding to other effects, the LED drive data SD corresponding to the current processing round is obtained. To grasp. The LED drive data SD is usually LED drive data SDa.

  After executing the processing of step S1005, step S1007, step S1009, or step S1010, the drive control processing of each LED 173 and winning notification LED 37 is executed in step S1011 to step S1016. Since this process is the same as steps S908 to S913 of the change start process, the description thereof is omitted. Then, in step S1017, other processes are executed, and this in-fluctuation process ends. Since this other process is the same as that of step S914, description is abbreviate | omitted.

  Next, the operation of the winning notification LED 37 when the above processing is performed will be described with reference to the timing chart of FIG. FIG. 24A shows the execution timing of the sound emission control process, FIG. 24B shows the waveform of the second permission signal SG4 input to the E2 terminal of the input port 171, and FIG. FIG. 24D shows the gate voltage of the p-type MOSFET 211, and FIG. 24E shows the operation mode of the LED 37 for winning notification. The timings t31, t33, t34, and t36 indicate the execution timing of the sound emission control process performed by the sub CPU 111, and the period Ta indicates the execution period of the sound emission control process (specifically, 4 msec).

  In the sound emission control process at the timing of t31, a process related to the start of the winning notification effect (steps S1004 to S1005) is performed, and the second permission signal SG4 becomes LOW by the process (see FIG. 24B).

  Then, the LOW signal is output from the OUT16 terminal of the third drive IC 203 at the timing t32 when the period required for transmitting the LED drive data SD (period T3 shown in FIG. 24) has elapsed from the timing t31 (FIG. 24). (See (c)). Note that the period T3 is a period sufficiently shorter than the execution period of the sound emission control process of 4 msec (a period indicated by Ta in FIG. 24), but is shown with a predetermined interval for the sake of the drawing.

  Based on the output of the LOW signal from the OUT16 terminal of the third driving IC 203, the gate voltage input to the gate of the p-type MOSFET 211 due to the transient phenomenon of the time constant circuit 221 as shown in FIG. Gradually decreases.

  After that, the threshold voltage Vth at which the p-type MOSFET 211 is turned ON is reached at timing t35 after two sound emission control processes executed at timing t33 and timing t34. Accordingly, the p-type MOSFET 211 is turned on, a voltage is applied to the winning notification LED 37, and the winning notification LED 37 emits light. The player can recognize that the player has won the jackpot by the light emission.

  In this case, the ON timing of the p-type MOSFET 211 with respect to the LOW signal output timing from the third driving IC 203 is delayed by the time constant circuit 221 by a delay period T4 from the timing t2 to the timing t35. The delay period T4 is set longer than the execution cycle (period Ta) of the sound emission control process, and specifically, is set to a period for a plurality of processing times. Thereby, when the LOW signal from the third drive IC 203 continues over a plurality of processing times, the winning notification LED 37 emits light. As a result, even if a LOW signal is temporarily output from the third drive IC 203 due to a transmission error or noise of the LED drive data SD, the winning notification LED 37 does not emit light. As a result, the inconvenience that the winning notification LED 37 malfunctions when not intended can be avoided.

  Here, as already explained, since the winning notification LED 37 is set to emit light when it is a big hit, whether or not the winning notification LED 37 emits light is an important point of interest for the player. . For this reason, the player's attention to the winning notification LED 37 is high. Furthermore, in order to increase the impact given to the player by the light emission of the winning notification LED 37, the light emission intensity of the winning notification LED 37 is set higher than that of the other LEDs 173, and the center is relatively easy to see for the player. It is provided on the frame 32. Therefore, the malfunction of the winning notification LED 37 is conspicuous, and it is easy to misunderstand the player.

  On the other hand, according to the present embodiment, since the time constant circuit 221 is provided, the LOW signal is temporarily output from the third drive IC 203 due to transmission error or noise of the LED drive data SD. Even so, the winning notification LED 37 does not emit light.

  The delay period T4 is set to be longer than twice the execution period of the sound emission control process, but is not limited thereto, and may be, for example, three times, four times,.

  Thereafter, when the process (steps S1008 to S1009) related to the end timing of the winning notification effect is executed at the timing of t36, the second permission signal SG4 becomes HI. Based on the second permission signal SG4 becoming HI, the n-type MOSFET 212 of the voltage application circuit 202 is turned OFF. As a result, the winning notification LED 37 is immediately turned OFF and does not emit light.

  Further, based on the second permission signal SG4 becoming HI, the third drive IC 203 is not operated, and outputs from the respective OUT terminals of the third drive IC 203 are opened. In this case, since the gate voltage of the p-type MOSFET 211 is pulled up, the gate voltage of the p-type MOSFET 211 gradually increases. Then, the gate voltage of the p-type MOSFET 211 becomes the threshold voltage Vth at the timing of t37, and the p-type MOSFET 211 is turned off after the timing of the t37.

  That is, the timing at which the winning notification LED 37 emits light is delayed by the time constant circuit 221 by a predetermined period (a period in which the period T3 and the delay period T4 are combined) with respect to the processing execution timing related to the start of the winning notification effect. On the other hand, the timing at which the light emission of the winning notification LED 37 stops is immediately after the processing related to the stopping of the winning notification effect is performed regardless of the time constant circuit 221. Accordingly, it is possible to quickly stop the light emission of the winning notification LED 37 while suppressing malfunction of the winning notification LED 37.

  That is, since the time constant circuit 221 is provided, the timing when the p-type MOSFET 211 is turned off is delayed with respect to the timing when the second permission signal SG4 becomes HI. For this reason, the light emission stop of the winning notification LED 37 is delayed, and the winning notification effect may not be suitably performed. In particular, the delay period T5 (the period T5 from the timing t36 to the timing t37) becomes longer as the delay period T4 becomes longer. For this reason, if the delay period T4 is set to be long from the viewpoint of preventing malfunctions, a shift in the stop timing of the winning notification effect is increased, and the winning notification effect is likely to be hindered.

  On the other hand, according to the present embodiment, the n-type MOSFET 212 that switches the voltage application to the winning notification LED 37 by being turned ON / OFF according to the second permission signal SG4 is provided. By controlling SG4, the light emission of the winning notification LED 37 can be stopped immediately regardless of the time constant circuit 221.

  The second permission signal SG4 is set to be LOW only while the winning notification effect is being performed. Accordingly, when the winning notification effect is not performed, the third driving IC 203 does not operate (outputs from all OUT terminals are open), and the voltage application circuit 202 does not operate (the voltage with respect to the winning notification LED 37). Is not applied). Therefore, the malfunction notification LED 37 is less likely to malfunction.

  Here, since the winning notification LED 37 is set to emit light in the case of a big hit, the light emission frequency is less than that of the LED 173 or the like that is constantly lit. Focusing on this point, the first permission signal SG3 is input to the first drive IC 191 and the second drive IC 192 that drive the LED 173 having a relatively high light emission frequency, while the second permission signal SG4. Can be said to be set to be input to the third drive IC 203 for driving the winning notification LED 37 having a relatively low light emission frequency. In this case, the first permission signal SG3 is always set to LOW, and the second permission signal SG4 is set to HI, so that it can be said that malfunction of an LED having a low light emission frequency is suppressed.

  Returning to the description of the sound emission control process (FIG. 20), when it is determined that the change is not occurring (step S803: NO), it is determined whether or not it is a change end timing in step S805. If it is the variation end timing, the process proceeds to step S806, and the LED drive data SD corresponding to the variation end timing is grasped by referring to the currently selected LED drive pattern table.

  In a succeeding step S807, a process for controlling the LED 173 using the grasped LED drive data SD is executed. Specifically, the processing of step S908 to step S913 is executed. Thereafter, in step S808, the clock signal SG1 is stopped and the sound emission control process is terminated.

  On the other hand, if it is not the change end timing, other command response processing is executed in step S809, and the sound emission control processing ends. In other command response processing, the received command is specified, and processing corresponding to the command is executed.

  According to the embodiment described in detail above, the following excellent effects are obtained.

  A plurality of drive ICs 191, 192, 203 capable of individually driving the plurality of LEDs 173 and the winning notification LED 37 are provided, and these drive ICs 191, 192, 203 are connected in series. Then, the LED driving data SD for determining the light emission mode of the LED 173 and the winning notification LED 37 is transmitted between the driving ICs 191, 192, and 203. As a result, the wiring connecting the sound lamp control board 110 that outputs the LED drive data SD and the LED board 91 can be reduced, and the input port 171 and the drive ICs 191, 192, and 203 are connected on the LED board 91. Wiring to be performed can be reduced. Thereby, malfunctioning of LED 37 for winning notification etc. by interference of wiring can be suppressed.

  In addition, the data areas D0 to D16 are updated in synchronization with the rising edge of the clock signal SG1, while the LED driving data SD set in the out data area DA is output in synchronization with the falling edge of the clock signal SG1. It was. Thus, even when the clock signal SG1 is delayed due to the influence of noise, interference between wirings, etc., the acquisition timing of the LED drive data SD (update timing of each data area D0 to D16) and the LED drive data SD A predetermined period (half cycle of the clock signal SG1) is ensured between the output timings. Therefore, the transmission error of the LED drive data SD due to the above influence can be suppressed, and the complexity of the configuration due to the use of a plurality of clock signals can be suppressed.

  Furthermore, according to the above configuration, by adjusting the duty ratio and the frequency of the clock signal SG1, a transmission error of the LED drive data SD occurs between the acquisition timing of the LED drive data SD and the output timing of the LED drive data SD. It can be adjusted to difficult intervals. Thereby, generation | occurrence | production of a transmission error can be suppressed more suitably.

  A time constant circuit 221 for delaying a signal output from the OUT16 terminal is provided on a wiring connecting the OUT16 terminal and the gate of the p-type MOSFET 211. The time constant circuit 221 is configured to output a LOW signal to the gate of the p-type MOSFET 211 when a LOW signal as a drive signal is output from the OUT16 terminal over a predetermined period. As a result, even when a LOW signal is temporarily output from the OUT16 terminal due to the influence of noise or the like, the winning notification LED 37 does not emit light, so that malfunction of the winning notification LED 37 due to noise or the like can be suppressed. .

  In particular, since the LOW signal is delayed by the time constant circuit 221, it is not necessary to determine whether or not a predetermined period has elapsed on the sub CPU 111 side. As a result, the processing load on the sub CPU 111 can be reduced.

  In addition, since the time constant circuit 221 is provided on the wiring connecting the OUT16 terminal and the gate of the p-type MOSFET 211, it is not necessary to provide the voltage application circuit 202 with a circuit for counting the predetermined period. Thereby, the loss of the electric power which the voltage application circuit 202 applies with respect to LED37 for winning notification can be suppressed. Therefore, a current can be suitably applied to the winning notification LED 37, and the light emission luminance of the winning notification LED 37 can be preferably increased.

  Furthermore, the time constant circuit 221 has a frequency characteristic that cuts off a signal having a frequency higher than a specific frequency. Thereby, high frequency noise mixed in a signal input to the gate of the p-type MOSFET 211 can be removed. Thereby, malfunctioning of LED37 for winning notification by high frequency noise can be suppressed.

  Each drive IC 191, 192, 203 is configured to operate when the permission signal is in a predetermined mode (specifically, LOW). In such a configuration, the first permission signal SG3 and the second permission signal SG4 are set as permission signals in different systems, and the drive ICs 191 and 192 for driving the frequently used (usually used) LED 173 are used. While allowing the first permission signal SG3 to be input, the second permission is applied to the third driving IC 203 that drives the winning notification LED 37 that is used at a low frequency (used when performing the winning notification effect). The signal SG4 is input. Thereby, when performing other effects (when the winning notification effect is not performed), the malfunction of the third drive IC 203 can be suppressed by setting the second permission signal SG4 to HI. The inconvenience that the winning notification LED 37 emits light can be avoided in the situation where the production is performed.

  A voltage application circuit 202 for applying a voltage to the winning notification LED 37 is provided. The voltage application circuit 202 is configured to apply a voltage to the winning notification LED 37 when (A) the LOW signal is output from the OUT16 terminal and (B) the second permission signal SG4 is LOW. Has been. The output signal of the OUT16 terminal and the second permission signal SG4 are separate systems. Thereby, even if the noise which may cause a malfunctioning is mixed in either one, the winning notification LED 37 does not emit light.

  In addition, the voltage application circuit 202 is configured so that the current flowing through the winning notification LED 37 does not flow into the third drive IC 203. As a result, it is possible to avoid the inconvenience that the third drive IC 203 fails due to a large current flowing into the third drive IC 203.

Second Embodiment
In the present embodiment, the configuration of the drive IC is different from that of the first embodiment. Specifically, in the first embodiment, the first drive IC 191 and the like are configured to sequentially shift the LED drive data SD every time the rising timing of the clock signal SG1, but in this embodiment, instead of this, Each time the rising timing of the clock signal SG1 is reached, an empty buffer is specified in the update buffer, and the LED drive data SD is sequentially set in the empty buffer.

  The first drive IC 301 and the second drive IC 302 of this embodiment will be described with reference to FIG. FIG. 25 is a block diagram showing the internal configuration of the drive IC in this embodiment. Since the first drive IC 301 and the second drive IC 302 have the same configuration, only the first drive IC 301 will be described.

  As in the first embodiment, the first drive IC 301 is configured to receive the LED drive data SD, the clock signal SG1, the data write signal SG2, and the first permission signal SG3. Further, the first drive IC 301 is newly provided with a Z terminal as an input terminal, and the Z terminal is connected to the register 122 of the sub CPU 111 via the input port 171 of the LED board 91 and the output port 131 of the sound lamp control board 110. It is connected to the provided acquisition permission flag register. The acquisition permission flag is configured to be set when the LED drive data SD writing process (step S908 or the like) is started. The acquisition permission flag is configured to be erased when the setting of the LED drive data SD is completed, specifically, in the process of turning off the clock signal SG1 (step S913, etc.).

  Similar to the first embodiment, the first drive IC 301 includes an update circuit 301a and a register 301b, and the update circuit 301a includes an update buffer 301c. The update buffer 301c includes data areas D0 to D7 and an outdata area DA, and also includes a set flag area DF and an acquisition permission flag area DZ. The acquisition permission flag area DZ is connected to the Z terminal of the second drive IC 302 via the output terminal.

  Similar to the first embodiment, the update circuit 301a outputs data set in the out data area DA in synchronization with the falling edge of the clock signal SG1. Here, the out data area DA in the present embodiment is not a copy area of the data area D7, but is configured such that the LED drive data SD is separately set by the update circuit 301a.

  The outdata area DA, the set flag area DF, and the acquisition permission flag area DZ are configured to be cleared to 0 at a predetermined timing, specifically, in a process of turning off the clock signal SG1 (step S913, etc.). .

  Next, update processing executed in the update circuit 301a will be described with reference to the flowchart of FIG. The update process is executed in synchronization with the rising edge of the clock signal SG1.

  First, in step S1101, it is determined whether an acquisition permission flag is set. Specifically, in the case of the first drive IC 301, it is determined whether or not the acquisition permission flag is set in the acquisition permission flag register of the sub CPU 111. It is determined whether or not an acquisition permission flag is set in the acquisition permission flag area DZ of the drive IC 301. If the acquisition permission flag is not set, the updating process is terminated as it is. If the acquisition permission flag is present, the process proceeds to step S1102, and the LED drive data SD is acquired.

  Thereafter, in step S1103, it is determined whether or not a set flag is set in the set flag area DF. The set flag is a flag that is set when the setting of the LED drive data SD for each of the data areas D0 to D7 is completed.

  If the set flag has not been set, the process proceeds to step S1104, where the acquired LED drive data SD is sequentially set in empty areas not yet set in the data areas D0 to D7. In this case, it is determined whether or not the data area is empty in the order of the data area D0 → data area D1 →... If it is empty, the acquired LED drive data SD is set. As a result, the LED drive data SD is set in the order of the data area D0 → data area D1 →.

  Instead of the process of determining whether or not it is free, a counter circuit may be provided separately, and the process of updating the counter each time the data areas D0 to D7 are set may be performed. In this case, it is preferable to execute a process of specifying a data area in which the LED drive data SD is to be set in the current processing time by referring to the value of the counter.

  In a succeeding step S1105, it is determined whether or not the setting of the LED drive data SD is completed for all the data areas D0 to D7. If all the data areas D0 to D7 have not been set, the update process is terminated. If all the data areas D0 to D7 have been set, the set flag is set in step S1106. The set flag is set in the area DF, and the update process is terminated.

  On the other hand, when the set flag is set (step S1103: YES), the process proceeds to step S1107. In step S1107, the acquired LED drive data SD is set in the out data area DA.

  Thereafter, in step S1108, an acquisition permission flag is set in the acquisition permission flag area DZ, and this update process is terminated.

  When such processing is performed, the LED drive data SD is sequentially set for the data areas D0 to D7 of the first drive IC 301. When the setting is completed, the acquired LED drive data SD is converted to the out data. It is output toward the second drive IC 302 via the area DA. In this case, the information set in each data area D0 to D7 is not shifted. That is, when the setting of the LED drive data SD for each of the data areas D0 to D7 is completed, the first drive IC 301 is configured to output the acquired LED drive data SD as it is to the second drive IC 302. . Then, the update circuit 302a of the second drive IC 302 updates the LED drive data SD input from the first drive IC 301 on the condition that the acquisition permission flag is set in the acquisition permission flag area DZ of the first drive IC 301. The data areas D8 to D15 of the update buffer 302c provided in the circuit 302a are sequentially set.

  In this case, since the acquisition permission flag is set after setting the LED drive data SD for the out data area DA, the second after the LED drive data SD is set for the out data area DA of the first drive IC 301. In the drive IC 302, information on the outdata area DA is acquired. Thereby, dummy data that is not the LED drive data SD is acquired in the second drive IC 302, and the dummy data is not set in an empty area. Thereby, setting of dummy data for each of the data areas D8 to D15 is avoided.

<Third Embodiment>
In the first embodiment and the like, the clock signal SG1 is input in parallel to the drive ICs 191 and 192. On the other hand, in this embodiment, the clock signal SG1 is configured to be input in series to each drive IC. Each drive IC is configured to transmit the clock signal SG1 to the connected drive IC when a predetermined condition is satisfied.

  The first drive IC 401 and the second drive IC 402 of this embodiment will be described with reference to FIG. FIG. 27 is a block diagram showing an internal configuration of the drive IC in the present embodiment. Since the first drive IC 401 and the second drive IC 402 have the same configuration, only the first drive IC 401 will be described.

  The first drive IC 401 includes an update circuit 401a and a register 401b, and the update circuit 401a is provided with an update buffer 401c. The update buffer 401c is provided with data areas D0 to D7 and an outdata area DA, as well as a set flag area DF. Since these are the same as those described in the first and second embodiments, a detailed description thereof will be omitted.

  Here, the update buffer 401c is provided with a clock signal permission flag area DC for controlling transmission of the clock signal SG1. The clock signal permission flag area DC has 1-bit information and is configured to store a clock signal permission flag. When the clock signal permission flag is set in the clock signal permission flag area DC, that is, when the information “1” is set, the clock signal SG1 is a clock as an output terminal provided in the first driving IC 401. When the clock signal permission flag is not set in the clock signal permission flag area DC, that is, when information of “0” is set, the clock signal is output via the signal terminal. The signal SG1 is not output.

  Here, information “0” is set in the clock signal permission flag area DC in the initial state. Specifically, the first drive IC 401 has a configuration in which a startup process is performed when power is turned on, and a configuration in which “0” is set in the clock signal permission flag region DC in the startup process. It has become.

  Similar to the first and second embodiments, the update circuit 401a having such a configuration executes an update process for acquiring the LED drive data SD and updating the data areas D0 to D7 in synchronization with the rising edge of the clock signal SG1. At the same time, a process of outputting the data stored in the out data area DA is executed in synchronization with the fall of the clock signal SG1.

  The update process performed by the update circuit 401a will be described with reference to the flowchart of FIG.

  First, in step S1201, LED drive data SD is acquired. Thereafter, in step S1202, a process of determining whether or not a set flag is set in the set flag area DF is executed.

  If the set flag has not been set, the process proceeds to step S1203, and the acquired LED drive data SD is sequentially set in empty areas not yet set in the data areas D0 to D7. In this case, it is determined whether or not the data areas D0 to D7 are vacant in the order of the data area D0 → data area D1 →... If they are vacant, the acquired LED drive data SD is set. As a result, the LED drive data SD is set in the order of the data area D0 → data area D1 →.

  In a succeeding step S1204, a process for determining whether or not the setting of all the data areas D0 to D7 is completed is executed. If all the data areas D0 to D7 have not been set, the updating process is terminated. If all the data areas D0 to D7 have been set, the process proceeds to step S1205 and has been set. The flag is set and the update process is terminated.

  On the other hand, when the set flag is set (step S1202: YES), the process proceeds to step S1206. In step S1206, a process of setting the acquired LED drive data SD for the out data area DA is executed.

  After that, in step S1207, a clock signal permission flag is set for the clock signal permission flag area DC, and this updating process is terminated. Based on the setting of the clock signal permission flag, the clock signal SG1 is output to the second driving IC 402. Thereby, the update process of the second drive IC 402 is started, and the LED drive data SD is set for the second drive IC 402.

  When such processing is performed, the setting of the LED drive data SD for the second drive IC 402 is started after the LED drive data SD for the first drive IC 401 is set. In this case, after the LED drive data SD is set for the first drive IC 401, the LED drive data SD and the clock signal SG1 are input to the second drive IC 402. As a result, the update process of the second drive IC 402 is started before the transmission of the LED drive data SD is started, and the inconvenience of acquiring dummy data that is not the LED drive data SD and setting the dummy data in an empty area is avoided. can do.

<Fourth embodiment>
In the first embodiment, each driving IC 191, 192, 203 is configured to operate using the same clock signal SG1. On the other hand, in this embodiment, the input clock signals are different between the drive ICs 191, 192, and 203. The different points will be described with reference to FIG. FIG. 29 is a block diagram of various circuits mounted on the LED substrate 91. In addition, about the same structure as 1st Embodiment, while attaching | subjecting the same code | symbol, description is abbreviate | omitted.

  A phase shift circuit 501 for shifting the phase of the clock signal SG1 by a predetermined amount is provided on the wiring connecting the CLK terminal of the second drive IC 192 and the CLK terminal of the input port 171. The phase shift circuit 501 is a wiring that connects the CLK terminal of the second drive IC 192 and the CLK terminal of the input port 171 to a position that does not affect the clock signal SG1 input to the first drive IC 191. Of these, the first drive IC 191 and the second drive IC 192 are provided at a downstream position on the second drive IC 192 side with respect to the branch point that branches from the first drive IC 191 and the second drive IC 192. Based on the input of the clock signal SG1 through the input port 171, the phase shift circuit 501 delays the phase of the clock signal SG1 by a predetermined amount (specifically, 1/4 period) and the delay. The delayed clock signal DSG1 is output to the second driving IC 192. In this case, the rising timing of the delayed clock signal DSG1 input to the second driving IC 192 is delayed by a predetermined amount with respect to the rising timing of the clock signal SG1 input to the first driving IC 191. Therefore, the first driving IC 191 The update of the data areas D0 to D7 and the update of the data areas D8 to D15 in the second drive IC 192 are not performed simultaneously. Thus, even if the LED drive data SD stored in the out data area DA is output in synchronization with the rising edge of the clock signal SG1, the output timing of the LED drive data SD in the first drive IC 191 The acquisition timing of the LED drive data SD in the second drive IC 192 does not match. Thereby, the transmission error of the LED drive data SD which may arise when the said output timing and the said acquisition timing correspond can be suppressed.

  The delayed clock signal DSG1 whose phase is shifted by the phase shift circuit 501 is output to the second drive IC 192 and is also output to the third drive IC 203 of the winning notification circuit 201. Specifically, the phase shift circuit 501 is connected in parallel to the second drive IC 192 and the third drive IC 203.

  Here, a phase shift circuit 502 is further provided on the wiring connecting the phase shift circuit 501 and the third drive IC 203. The phase shift circuit 502 has the same internal configuration as the phase shift circuit 501, and delays the delayed clock signal DSG1 output from the phase shift circuit 501 by a predetermined amount (specifically, 1/4 period) to perform the third drive. It is configured to output to the IC 203. As a result, the delayed clock signal DSG2 input to the third drive IC 203 is delayed by ¼ period with respect to the delayed clock signal DSG1 input to the second drive IC 192. In this case, the delayed clock signal DSG2 input to the third drive IC 203 is delayed by a half cycle with respect to the clock signal SG1 input to the first drive IC 191.

  According to this configuration, the clock signals SG1, DSG1, and DSG2 having different phases are input to the drive ICs 191, 192, and 203, and therefore the update timings of the drive ICs 191, 192, and 203 are different. As a result, the drive ICs 191, 192, and 203 acquire the LED drive data SD in synchronization with the rising edges of the clock signals SG1, DSG1, and DSG2, update the data areas D0 to D16, and update the outdata area. Even when the LED drive data SD set to DA is output, a transmission error of the LED drive data SD hardly occurs.

  In particular, the clock signal that triggers the operation is set to gradually delay from the upstream driving IC (first driving IC 191) toward the downstream driving IC (third driving IC 203) (clock signal SG1). → delay clock signal DSG1 → delay clock signal DSG2). Thus, after the setting of the out data area DA by the upstream drive IC is completed, the LED drive data SD is acquired by the downstream drive IC. The inconvenience of acquiring can be avoided.

  In the present embodiment, the phase shift circuits 501 and 502 for shifting the phase of the clock signal SG1 are provided. However, the present invention is not limited to this. For example, a modulation circuit that changes the duty ratio may be provided. Even in this case, the rising timing of the clock signal input to each drive IC 191, 192, 203 can be shifted.

<Other embodiments>
In addition, it is not limited to the description content of embodiment mentioned above, A various deformation | transformation improvement is possible within the range which does not deviate from the meaning of this invention. For example, you may change as follows. Incidentally, the configuration of another embodiment described below may be applied individually or in combination to the configuration of the above embodiment.

  (1) In each of the above embodiments, three drive ICs 191, 192, and 203 are provided. However, the present invention is not limited to this. For example, four or five may be used, and the number of LEDs 173 to be driven is adjusted. Should be provided.

  Here, when the newly provided drive IC is provided in correspondence with the LED that is always lit, the new drive IC is the second drive IC 203 so that the third drive IC 203 is disposed on the most downstream side. The third drive IC 203 may be connected in series to the new drive IC while being connected in series to the downstream side of the drive IC 192. Then, the first permission signal SG3, the clock signal SG1, and the data write signal SG2 are input to the new drive IC, and the information of the LED drive data SD is increased in correspondence with the number of LEDs 173. Accordingly, each drive IC including the new drive IC can be suitably operated. When the winning notification LED 37 is not turned on, the LED drive data SD corresponding to the third drive IC 203 is set and transmitted. By omitting, it is possible to reduce the processing load and shorten the period required for transmitting the LED drive data SD.

  In addition, when a driving IC for driving the winning notification LED 37 is newly provided in correspondence with the provision of a plurality of winning notification LEDs 37, it may be connected in series to the third driving IC 203. Then, the second permission signal SG4, the clock signal SG1, and the data write signal SG2 are input to the new drive IC, and the LED drive data SD is increased corresponding to the newly provided winning notification LED 37. Let Thus, the winning notification LED 37 can be added without any change to the existing driving IC.

  In this case, if the LED driving data SD corresponding to the winning notification LED 37 is set even in a situation where the winning notification LED 37 does not emit light, the LED driving register increases with the increase of the winning notification LED 37. The processing load for writing the LED drive data SD to the 141 increases, and the period required to transmit the LED drive data SD becomes longer. On the other hand, as shown in the first embodiment, when the winning notification LED 37 does not emit light, the normal LED drive data SDa in which the data corresponding to the winning notification LED 37 is omitted is used. The processing load for writing the LED drive data SD and the period required for transmitting the LED drive data SD can be shortened.

  (2) In each of the above embodiments, the LED 173 used for various lamp units for notifying the game situation has been described. However, the present invention is not limited to this. For example, when the symbol display device 31 uses a liquid crystal display device having an LED backlight structure. The present invention may be applied to the LED group of the LED backlight.

  Moreover, although LED173 was used as a light emitting element, it is not restricted to this, For example, you may use other light emitting elements, such as a fluorescent lamp, an incandescent lamp, and organic EL. Even in this case, the present invention can be applied. However, from the viewpoint of installation space, power consumption, etc., the configuration using the LED 173 is superior.

  (3) In each of the above embodiments, the control objects of the drive ICs 191, 192, and 203 are the plurality of LEDs 173 and the winning notification LED 37, but are not limited thereto. When an accessory is provided, the movable accessory for production may be set as a control target. In short, as long as it is a plurality of electric devices (elements) of the same type, any device to be controlled by a plurality of drive ICs is arbitrary.

  (4) In each of the above-described embodiments, the clock signal SG1 is output only when the LED drive data SD is written. However, the present invention is not limited to this, and the clock signal SG1 is continuously output based on power-on. It is good also as a structure to output. Even in this case, as long as the data write signal SG2 does not rise, the driving mode of each LED 173 is not changed. In the case of the above configuration, the LED drive data SD may be configured to continue outputting “1” (or “0”). Thereby, each data area D0-D16 can be initialized.

  (5) In each of the above embodiments, 6 pins among the OUT terminals of the drive ICs 191 and 192 are used for lighting the LED 173. However, the present invention is not limited to this. For example, all 8 pins may be used and are arbitrary. However, considering the total current value flowing into the driving IC and local heat generation, 6 pins are preferable.

  (6) In each of the above embodiments, the amount of information set is different between the normal LED driving data SDa when the winning notification effect is not performed and the specific LED driving data SDb when the winning notification effect is performed. Although set, the present invention is not limited to this, and a configuration in which the settings are the same may be employed. Specifically, information “1” may be added to the normal LED drive data SDa so that the HI signal is output from the OUT16 terminal when the winning notification effect is not performed. However, in view of reducing the processing load and shortening the transmission period of the LED drive data SD, the normal LED drive data SDa not corresponding to the winning notification LED 37 and the specific LED driving data SDb corresponding to the winning notification LED 37 are set. The configuration is better.

  (7) In each of the above embodiments, the time constant circuit 221 is provided only on the wiring that connects the p-type MOSFET 211 and the OUT16 terminal. However, the present invention is not limited to this, and the wiring that connects the normal LED 173 and the driving IC. A time constant circuit 221 may be provided on the top. However, in view of the point that malfunction is not conspicuous, the complexity of the configuration, the installation space, etc., the configuration in which the time constant circuit 221 is provided only on the wiring corresponding to the important LED in the game such as the winning notification LED 37. Is better.

  (8) In each of the above embodiments, the time constant circuit 221 that delays the LOW signal output from the OUT16 terminal by a predetermined period (a period corresponding to a plurality of processing times) is provided. However, the present invention is not limited to this. Instead of 221, a configuration may be provided in which a count circuit that counts rising or falling is provided. In this case, a configuration is adopted in which a predetermined pulse signal is output from the OUT16 terminal every time the sound emission control process is performed in a situation where the winning notification effect is performed, and the count circuit counts a predetermined number of times. It may be configured to output a LOW signal to the gate of the p-type MOSFET 211. Even with such a configuration, malfunction of the p-type MOSFET 211 due to noise can be suppressed, and malfunction of the LED 37 for winning notification can be suppressed. However, from the viewpoint of high-frequency noise removal and the simplification of the configuration, the configuration in which the time constant circuit 221 is provided is superior.

  (9) According to each of the above embodiments, the circuit in which the resistor 222 and the capacitor 223 are connected in parallel is provided as the time constant circuit 221 for removing high frequency noise. However, the present invention is not limited to this. Good. In this case, negative feedback is preferably provided via a feedback resistor, and a capacitor is preferably provided in parallel with the feedback resistor. In short, it is sufficient if it has a function of transmitting only signals of a predetermined frequency range and blocking signals of other frequencies, and the drive signal for driving the winning notification LED 37 is within the specific range. It only has to be set.

  (10) In each of the above embodiments, the permission signals SG3 and SG4 are set to HI in the start-up process. However, the present invention is not limited to this. For example, the permission signals SG3 and SG4 may be set to LOW in the start-up process. In this case, the LED drive data SD set so that each LED 173 emits light may be transmitted, and the process of causing each LED 173 to emit light may be executed. Thereby, it can be confirmed whether or not each LED 173 emits light normally.

  (11) In each of the above embodiments, a current detection sensor for determining whether or not the LED 173 is normally emitting light is provided, and a detection result by the current detection sensor is obtained via the input port 114 of the sound lamp control board 110. It may be input to the sub CPU 111. In this case, the sub CPU 111 determines whether there is an abnormality in the LED 173 based on the detection result, and when there is an abnormality, transmits a command to the display control device 100 so that the display screen G is notified. It is good to execute processing. Thereby, the abnormality inspection of LED173 can be performed easily.

  (12) In each of the above embodiments, the information in each of the data areas D0 to D16 is sequentially updated without being initialized. However, the present invention is not limited to this. For example, the LED drive data SD is written. Based on this, the configuration may be such that the initialization processing of the data areas D0 to D16 is executed in each of the drive ICs 191, 192, and 203. The execution timing of the initialization process may be after the data write signal SG2 rises and is arbitrary.

  (13) In each of the above embodiments, the first permission signal SG3 and the second permission signal SG4 are individually output. The first permission signal SG3 controls the LED 173 having a relatively high light emission frequency, and the second permission signal SG4. However, the present invention is not limited to this. For example, the first permission signal SG3 is used to control the LED corresponding to the first effect, and the first effect and May be configured to use the second permission signal SG4 to control the LED corresponding to the second effect having different effect contents. Further, in the case where the LED for performing various abnormality notifications and the LED for production are different in configuration, the first permission signal SG3 and the second permission signal SG4 may be set corresponding to both. .

  (14) In each of the above embodiments, the voltage application circuit 202 can apply a voltage to the winning notification LED 37 when the second permission signal SG4 is LOW. A configuration in which control is performed only by the output from the OUT16 terminal regardless of the signal SG4 may be employed. However, from the viewpoint of malfunction due to noise and the ability to quickly stop the light emission of the winning notification LED 37, a configuration that can be controlled by the second permission signal SG4 is better.

  (15) In each of the above embodiments, an OR circuit may be newly provided on the LED substrate 91, and the voltage input to the gate of the p-type MOSFET 211 may be determined based on the output of the OR circuit. Specifically, the wiring from the OUT16 terminal is bifurcated, and the bifurcated wiring is connected to the input terminal of the OR circuit. Then, the output terminal of the OR circuit and the gate of the p-type MOSFET 211 are connected. In this case, the time constant circuit 221 is provided in only one of the two-forked wiring. According to such a configuration, when a LOW signal is output from the OUT16 terminal, LOW is immediately input to one input terminal of the OR circuit, while the time constant circuit 221 is provided from the wiring on the side where the time constant circuit 221 is provided. The input of the LOW signal is delayed. As a result, LOW is output to the gate of the p-type MOSFET 211 after a predetermined period of time from the output from the OUT16 terminal, so that it is less susceptible to noise and the like.

  In contrast, when the signal from the OUT16 terminal is switched from LOW to HI, HI is input to one input terminal of the OR circuit due to the switching, and HI is immediately input to the gate of the p-type MOSFET 211. It will be. Thereby, the light emission stop of the LED 37 for winning notification can be quickly performed.

  (16) In each of the above embodiments, the drive ICs 191, 192, and 203 operate when the permission signals SG 3 and SG 4 are LOW. There may be. In this case, each bus and wiring is switched from pull-up to pull-down. However, if attention is paid to the size of the noise margin, the low active type is preferable.

  Further, the LED 173 is configured to emit light when the output from each OUT terminal is “0”, but is not limited thereto, and may be configured to emit light when the output from each OUT terminal is “1”.

  (17) In each of the embodiments described above, the voltage application circuit 202 is provided. However, the present invention is not limited to this. For example, the third drive IC 203 and the winning notification LED 37 may be directly connected. However, in this case, when the second permission signal SG4 becomes HI, the light emission of the winning notification LED 37 cannot be stopped immediately, and the third driving IC 203 may be destroyed. In view of these points, the configuration in which the voltage application circuit 202 is provided is superior.

  (18) In each of the above embodiments, when the output from the OUT16 terminal is LOW, the voltage application circuit 202 applies the drive voltage to the winning notification LED 37. However, the present invention is not limited to this. When the output from the terminal is HI, the voltage application circuit 202 may apply a driving voltage to the winning notification LED 37. In this case, an n-type MOSFET is provided in place of the p-type MOSFET 211, and the gate voltage of the n-type MOSFET is pulled down. However, focusing on the size of the noise margin, the configuration in which the voltage application circuit 202 applies the drive voltage to the winning notification LED 37 when the output from the OUT0 terminal is LOW is superior.

  (19) In each of the above embodiments, the LED board 91 and the sound lamp control device 90 are connected, and the winning notification LED 37 and the like are controlled by the sound lamp control device 90. However, the present invention is not limited to this. For example, the main control device 60 may control the winning notification LED 37.

  (20) In each of the above-described embodiments, the winning notification LED 37 is configured to emit light in the game round in the case of a big win. However, the present invention is not limited thereto. For example, as a configuration in which light is emitted during the high probability mode or the high frequency support mode Also good.

  (21) In each of the above embodiments, when the winning notification LED 37 emits light, the speaker unit 55 may output a predetermined specific sound. Thereby, the winning notification effect can be flashy, and the degree of attention to the winning notification effect can be increased. In this case, since the sound lamp control device 90 is configured to control the speaker unit 55 and the winning notification LED 37, the two can be easily associated with each other.

  (22) In each of the above embodiments, the data areas D0 to D7 and the like are updated in synchronization with the rising edge of the clock signal SG1, and the data in the out data area DA is output in synchronization with the falling edge of the clock signal SG1. However, the present invention is not limited to this, and the data areas D0 to D7 are updated in synchronization with the falling edge of the clock signal SG1, and the data in the out data area DA is output in synchronization with the rising edge of the clock signal SG1. It is good also as composition which is performed.

  Further, the clock signal SG1 that is periodically output is used as a signal for synchronization. However, the present invention is not limited to this. For example, a pulse signal group including a plurality of pulse signals having different pulse widths as one unit is output at a predetermined cycle. A configuration may be adopted in which pulse signal output means is provided and synchronization is performed using the pulse signal group. In short, as long as the signal has a falling edge between a predetermined rising edge and the next rising edge, the interval between rising edges and / or the interval between falling edges may vary. May vary.

  (23) In each of the above embodiments, the output of the clock signal SG1 is started after the writing of the LED drive data SD is started. However, the present invention is not limited to this, and after the clock signal SG1 is output. The LED driving data SD may be written. Specifically, the processing in step S908 and step S1011 may be omitted. In this case, after a predetermined period (specifically, a period required for LED drive data SD to be written to the data register) has elapsed since the clock signal SG1 was turned on, the clocks to the drive ICs 191, 192, 203 are supplied. A delay circuit for delaying the clock signal SG1 may be provided so that the signal SG1 is input. Thereby, even if it is a case where the process of step S908 and step S1011 is abbreviate | omitted, it can suppress that indefinite information is transmitted.

  (24) In each of the above embodiments, a dedicated clock signal output circuit may be separately mounted on the sound lamp control board 110 instead of the clock signal register 143. In this case, the sub CPU 111 may be configured to permit or prohibit transmission of the clock signal output from the clock signal output circuit to the LED substrate 91.

  (25) In each of the above embodiments, the clock signal SG1 may be constantly output in a situation where a game is being performed. However, from the viewpoint of malfunction, it is preferable to turn on the output of the clock signal SG1 when necessary.

  (26) The capacitor 223 may be discharged in advance before the winning notification LED 37 emits light. Thereby, the delay of the light emission timing of the LED 37 for winning notification which may arise by providing the time constant circuit 221 in order to remove noise can be suppressed. However, from the viewpoint of suppressing malfunction of the winning notification LED 37, the first embodiment is superior.

  In addition, as the pre-stage for causing the winning notification LED 37 to emit light, for example, the timing at which the change start process is executed, the timing at which the big hit winning is specified, the timing at which the winning notification effect is won, and the like can be considered. In addition, a function of executing a destination identification process for determining whether or not the game ball has entered the operation ports 23 and 24 at a timing before the timing at which the variation start process related to the ball is performed is provided. In the gaming machine, the timing at which the determination of whether or not by the destination specifying process is performed, the timing at which it is determined to be a big hit by the determination of the success or failure, and the like can be set as the discharge start timing of the capacitor 223.

  For example, an OR circuit in which one input terminal is connected to the output of the time constant circuit 221, the other input terminal is connected to the OUT 17 terminal, and the output terminal is connected to the gate of the p-type MOSFET 211 may be provided. Good. In this case, the signal output from the OUT16 terminal is switched from the HI signal to the LOW signal at a prior timing before the light emission timing of the winning notification LED 37, and the signal output from the OUT17 terminal at the light emission timing is switched from the HI signal. The third drive IC 203 may be controlled so as to switch to the LOW signal. Thereby, the light emission timing of the winning notification LED 37 can be suitably controlled. In this case, the period between the prior timing and the light emission timing may be set longer than the period required for discharging the capacitor 223.

  (27) Other types of pachinko machines different from the above-described embodiments, such as pachinko machines that release a predetermined number of times when a game ball enters a specific area of a special device, or game balls in a specific area of a special device The present invention can also be applied to a pachinko machine that generates a right if a player enters, a pachinko machine equipped with other objects, an arrangement ball machine, a sparrow ball, and the like.

  Also, a non-ball-type gaming machine, for example, a plurality of reels with a plurality of types of symbols attached in the circumferential direction, starts rotation of the reel by inserting a medal and operating a start lever, and a stop switch is operated. Or, if a specific symbol or a combination of specific symbols is established on an active line visible from the display window after the reel has stopped after a predetermined period of time, a privilege such as paying out medals is given to the player The present invention can also be applied to a slot machine.

  In addition, a pachinko machine and a slot machine that have a take-in device and start rotation of a reel by operating a start lever after a predetermined number of game balls stored in the storage unit are taken in by the take-in device The present invention can also be applied to a gaming machine in which is integrated.

<Invention Group Extracted from the Embodiments>
Hereinafter, the features of the invention group extracted from the above-described embodiments will be described while showing effects and the like as necessary. In the following, for easy understanding, the corresponding configuration in the above embodiment is appropriately shown in parentheses and the like, but is not limited to the specific configuration shown in parentheses and the like.

<Feature A group>
Feature A1. A plurality of elements (LEDs 173);
Element driving means (LED driving unit 172) for individually driving the plurality of elements;
An element control means (sub CPU111) for controlling each element individually by connecting to the element driving means via a wiring and outputting predetermined driving data to the element driving means via the wiring;
With
In the gaming machine that drives each element individually in a mode corresponding to the drive data when the drive data is input from the element control means via the wiring,
The element driving means includes a plurality of driving units (driving ICs 191, 192, 203) connected in series with each other,
The plurality of driving units are connected in a state where the plurality of elements are allocated,
The element driving unit sequentially transmits the driving data between the plurality of driving units at each predetermined update timing in a situation where the driving data is input from the element control unit. A game machine characterized by sequentially setting the modes.

  According to the feature A1, the drive state of each element is set by transmitting drive data between a plurality of drive units. Thereby, since it is not necessary to transmit drive data to each drive part, the wiring which connects an element drive means and an element control means can be reduced. In this case, since the space occupied by the wiring can be reduced, it is easy to adjust the position of the wiring and perform a coating process so that ambient noise does not enter the wiring. Therefore, malfunction due to noise of each element can be suppressed.

  From the above, each element can be driven suitably while simplifying the configuration.

  In addition, when a new element is provided, it is only necessary to further provide an element and a drive unit corresponding to the element in series, and design changes to the existing drive part can be reduced. Thereby, it is possible to easily cope with addition of elements and the like.

Feature A2. Each of the plurality of driving units is
A data input section (DATAIN terminal) to which the drive data is input;
A data output unit (DATAOUT terminal) from which the drive data is output;
With
Series connection wiring for connecting each driving unit in series (wiring for connecting the DATAOUT terminal of the first driving IC 191 and the DATAIN terminal of the second driving IC 192, the DATAOUT terminal of the second driving IC 192, and the DATAIN terminal of the third driving IC 203) Wiring to connect), and
The series connection wiring connects the data output unit in a predetermined drive unit and the data input unit in another predetermined drive unit among the plurality of drive units, so that the plurality of drive units are connected in series. And
The gaming machine according to Feature A1, wherein a wiring from the element control means is connected to a data input section of a driving section in which the series connection wiring is not connected to a data input section.

  According to the feature A2, the data output unit of the predetermined drive unit and the data input unit of another predetermined drive unit are connected by the series connection wiring, and the series connection wiring is not connected to the data input unit. Element control means is connected to the data input section of the drive section. As a result, drive data input from the element control means to the specific drive unit can be sequentially transmitted from the specific drive unit to each drive unit.

  The “drive unit in which the series connection wiring is not connected to the data input unit” is specifically arranged at the most upstream position in the drive data transmission path among the plurality of drive units connected in series. Drive unit.

Feature A3. The drive unit is
The drive data acquisition unit (update circuit 191a, update circuit 191a, which acquires the drive data at each predetermined acquisition timing and sets the acquired drive data in a predetermined storage area (data areas D0 to D16). 192a etc.)
A drive data transmission unit (update circuits 191a, 192a, etc.) that transmits drive data stored in the storage area each time a predetermined transmission timing is reached;
With
The gaming machine according to Feature A1 or Feature A2, wherein the acquisition timing and the transmission timing are set to be different.

  According to the feature A3, the drive data is acquired every time the acquisition timing is reached, the acquired drive data is stored in the storage area, and the drive data stored in the storage area is output every time the transmission timing is reached. As a result, the drive data is sequentially transmitted between the plurality of drive units like a bucket relay.

  In such a configuration, if the acquisition timing and the transmission timing are simultaneous, it is unknown whether the drive data already stored in the storage area is transmitted or the drive data newly acquired by the drive data acquisition unit is transmitted. As a result, transmission of drive data becomes unstable. For this reason, drive data may not be transmitted correctly.

  On the other hand, according to this feature, since the transmission timing and the acquisition timing are different, the drive data is transmitted while the drive data stored in the storage area is stable. Thereby, the transmission error of the drive data as described above can be suppressed, and the malfunction of the element due to the transmission error can be suppressed.

Feature A4. The acquisition timing is set to be a predetermined cycle,
The gaming machine according to Feature A3, wherein the difference between the acquisition timing and the transmission timing is set to be smaller than the predetermined period.

  According to the feature A4, the drive data is sequentially acquired at a predetermined cycle. In this case, since the difference between the acquisition timing and the transmission timing is set to be smaller than the drive data acquisition interval, acquisition and output are alternately performed. Thereby, for example, the inconvenience of acquiring the same data in duplicate can be avoided. Therefore, inconveniences that may be caused by shifting the acquisition timing and the transmission timing can be avoided.

Feature A5. A specific signal output means (a function of outputting the clock signal SG1 in the sub CPU 111) that outputs a specific signal in which the HI level signal and the LOW level signal are switched alternately;
The drive data acquisition unit acquires the drive data based on the specific signal being in a predetermined first form, and sets the acquired drive data in a predetermined storage area. Yes,
The gaming machine according to Feature A3 or Feature A4, wherein the driving data transmitting unit outputs the driving data based on the specific signal having a second form different from the first form. .

  According to the feature A5, the drive data is transmitted based on the specific signal having the first form, and the drive data is acquired based on the specific signal having the second form. Since the first form and the second form are different from each other, the acquisition timing and the transmission timing are different. This makes it possible to make the acquisition timing and the transmission timing different using the same specific signal.

  Here, for example, when the drive data acquisition unit and the drive data transmission unit operate with different specific signals, the transmission timing and the acquisition timing may be synchronized due to a delay of one specific signal. On the other hand, according to this feature, since the same specific signal is used, even if the specific signal is delayed, a predetermined interval is secured between the transmission timing and the acquisition timing. . As a result, it is possible to avoid the inconvenience that the transmission and reception of the drive data are synchronized due to the delay of the specific signal.

Feature A6. The specific signal output means is a clock means for outputting a clock signal at a predetermined cycle as the specific signal,
The drive data acquisition unit acquires the drive data based on the clock signal becoming the first form, and sets the acquired drive data in a predetermined storage area.
The gaming machine according to Feature A5, wherein the driving data transmitting unit outputs the driving data based on the clock signal being in the second form.

  According to the feature A6, the effect of the feature A5 can be obtained by using the clock signal as the specific signal.

Feature A7. The first form is one of rising and falling edges of the clock signal,
The gaming machine according to Feature A6, wherein the second form is the other of the clock signals.

  According to the feature A7, the interval between the transmission timing and the acquisition timing of the drive data can be adjusted by adjusting the duty ratio of the clock signal. As a result, the adjustment work for adjusting the interval so that drive data transmission errors do not easily occur can be easily performed.

  Feature A8. The clock means is connected in parallel to each of the plurality of driving units, and outputs the clock signal to each driving unit at the same time. The gaming machine described.

  According to the feature A8, since the clock means is connected in parallel to each drive unit and the clock signal is output to each drive unit, the clock signal is transmitted in series between the drive units. Compared with the structure to which it does, the shift | offset | difference of the clock signal between each drive part does not arise easily. Thereby, the transmission error of the starting data resulting from the shift of the transmission timing or the acquisition timing of the driving data in each driving unit can be suppressed.

  Feature A9. Any of the features A6 to A8, wherein the clock means stops the output of the clock signal to each drive section when the drive data is not inputted to the element drive means. A gaming machine according to claim 1.

  According to the feature A9, in a situation where drive data is not input to the element driving unit, a clock signal is not input to each drive unit. Thereby, since each drive unit does not transmit data, it is possible to avoid the inconvenience that data transmission is erroneously performed and the element malfunctions.

Feature A10. Determining means for determining whether or not the transmission of the drive data has been completed (a function of executing the process of step S911 in the audio lamp control device 90);
When the determination unit determines that the transmission of the drive data is completed, a drive start signal output unit that outputs a drive start signal to each drive unit (the process of step S912 is performed in the audio lamp control device 90). Function)
With
The drive unit is configured to drive each element in a manner corresponding to the drive data based on the input of the drive start signal, according to any one of features A1 to A9. Gaming machine.

  According to the feature A10, when the transmission of the drive data is completed, a drive start signal is output, and each element is driven. Thereby, it is possible to avoid the inconvenience that the driving is started at the timing before the transmission of the driving data is completed.

  Further, since each element is driven based on the input of the drive start signal, the drive start timing of each element can be synchronized. Therefore, it is possible to suppress the inconvenience that the drive start timing of each element varies due to a delay that can be caused by sequentially transmitting drive data.

  The drive start signal output means is preferably connected in parallel to each drive unit and outputs the drive start signal to each drive unit. This makes it difficult for the drive start signal to shift between the drive units.

Feature A11. The wiring is a first wiring (wiring for transmitting LED drive data SD),
Permission signal output means for outputting a predetermined permission signal (function of outputting the first permission signal SG3 and the second permission signal SG4 in the sub CPU 111);
Connecting the permission signal output means and each driving unit, the second wiring of the system different from the first wiring (wiring for transmitting the first permission signal SG3 and the second permission signal SG4),
With
The drive unit drives each element in a manner corresponding to the drive data when the permission signal is input via the second wiring, while the permission signal is input via the second wiring. If not, the gaming machine according to any one of features A1 to A10, wherein each element is not driven.

  According to the feature A11, when the permission signal is input, each element is driven by the driving unit, and when the permission signal is not input, each element is not driven. Thereby, by controlling the permission signal, it is possible to suppress malfunctions of elements that are not desired to be driven.

  In such a configuration, the transmission of the drive data and the transmission of the permission signal are performed by different lines of wiring, so even if noise enters one of the two, the influence on the other is small, and as a result, the drive unit Less susceptible to noise. Thereby, it is possible to avoid the inconvenience that the element malfunctions due to noise.

  In addition, since it is not necessary to set special information such as a flag in the drive data when transmitting the drive data, the configuration of the drive data transmission can be simplified and the special information is set. Transmission errors that may occur due to this can be suppressed.

  Furthermore, it can suppress that both interfere by making it the structure which transmits a permission signal by a different system | strain from drive data. As a result, malfunction of each element that may be caused by interference between the permission signal and the drive data can be suppressed.

Feature A12. Grant determination means (function to execute the process of step S401 in the main control device 60) for determining whether or not to grant a privilege based on the establishment of a predetermined condition;
When the determination result of the grant determination unit is a grant response result for granting a privilege, a privilege grant unit (such as a function for executing a game state transition process in the main control device 60) for granting a privilege to the player; ,
With
The element control means, when the determination result of the application determination means is the application correspondence result, the drive data so that a predetermined specific element among the plurality of elements is driven in a predetermined specific mode. Is output to the element driving means,
The permission signal output means includes
First output means for outputting the permission signal to a specific driving unit corresponding to the specific element (function of outputting the second permission signal SG4 in the sub CPU 111);
Second output means for outputting the permission signal to a drive unit other than the specific drive unit among the plurality of drive units (function of outputting the first permission signal SG3 in the sub CPU 111);
The gaming machine according to Feature A11, wherein the gaming machine is characterized by comprising:

  According to the feature A12, the first output unit and the second output unit are provided, and the specific drive unit drives the specific element based on the permission signal input from the first output unit. Accordingly, when the specific element is not driven, the first output unit is set not to output the permission signal, and the second output unit is set to output the permission signal, so that the specific element malfunctions. It is possible to drive elements other than the specific element while preventing them from occurring.

Feature A13. The element control means includes
A first storage means and a second storage means (LED drive register 141) capable of storing the drive data;
Drive data writing means (function for executing the process of step S908 in the sound lamp control device 90) for executing a writing process for alternately writing the drive data to the first storage means and the second storage means;
A transmission unit that transmits drive data stored in a storage unit that is not subjected to the writing process by the drive data writing unit among the first storage unit and the second storage unit, to the element driving unit;
The gaming machine according to any one of features A1 to A12, comprising:

  According to the feature A13, while the drive data stored in one storage means is being transmitted to the element drive means, the drive data is written in the other storage means. As a result, it is not necessary to wait for the output of drive data until the writing process is completed, so that the period required for transmission of drive data can be shortened. Therefore, it is possible to reduce the lengthening of the transmission period that can be caused by sequentially transmitting drive data.

Feature A14. The element control means includes drive data update means (function for executing LED drive data update processing) for updating the drive data at a predetermined specific cycle (execution cycle of sound emission control processing), and the drive data update The drive data updated by the means is sequentially output,
The gaming machine according to any one of features A1 to A13, wherein transmission of the driving data is set to be completed in a period shorter than the specific period.

  According to the feature A14, the drive data is updated at a predetermined specific cycle, so that the drive state of each element is periodically updated. In such a configuration, since the transmission of the drive data is set to be completed in a period shorter than the specific cycle, the drive mode can follow the update of the drive data. Thereby, it is possible to suppress malfunction of each element that may be caused by updating the drive data before the transmission of the drive data is completed.

  In addition, according to the relationship with the feature A3, “the interval between the acquisition timings and the interval between the transmission timings are set so that the transmission of the drive data is completed in a period shorter than the specific period”. Good.

  Further, according to the relationship with the feature A6, it is preferable that “the frequency of the clock signal is set so that transmission of the drive data is completed in a period shorter than the specific period”.

  Feature A15. The gaming machine according to any one of features A1 to A14, wherein the element includes a light emitting element (LED 173 and winning notification LED 37) that emits light to notify the game.

  According to the feature A15, notification regarding the game is performed by the light emitting element. Thereby, a player's attention can be attracted to a light emitting element, and the attention degree to a game can be raised.

  Here, if the light emitting element malfunctions in a situation where the player's attention is attracted to the light emitting element, there is a possibility that the player will be misunderstood and the game performance intended for the player may not be transmitted. In particular, since a malfunction of a light emitting element is accompanied by light emission, it is more noticeable than other elements.

  On the other hand, since the malfunction of the light emitting element can be suppressed by applying the configuration such as the feature A3, it is possible to avoid the inconvenience that the game performance intended for the player is not transmitted.

  In order to increase the degree of attention to the game, a structure in which a plurality of light emitting elements are provided is preferable. In this regard, by applying the configuration of Feature 1, a plurality of light emitting elements can be easily driven by further adding a driving unit connected to the light emitting elements in series. Thereby, the structure for raising the attention degree to a game is easily realizable.

Feature A16. Grant determination means (function to execute the process of step S401 in the main control device 60) for determining whether or not to grant a privilege based on the establishment of a predetermined condition;
When the determination result of the grant determination unit is a grant response result for granting a privilege, a privilege grant unit (such as a function for executing a game state transition process in the main control device 60) for granting a privilege to the player; ,
With
The element control unit drives a predetermined specific element (winning notification LED 37) of the plurality of elements in a predetermined specific mode when the determination result of the grant determination unit is the grant correspondence result. The gaming machine according to any one of features A1 to A15, wherein the driving data is output to the element driving means.

  According to the feature A16, the specific element is driven in a specific manner when the result is the assignment correspondence result. Thereby, a player's attention can be attracted to a specific element, and the attention degree to a game can be raised.

  Here, if a malfunction of a specific element occurs, the player may be misunderstood and the game characteristics intended for the player may not be transmitted. In particular, in a situation where a player's attention is attracted to a specific element, a malfunction of the specific element is easily noticeable. On the other hand, since the malfunction of the specific element can be suppressed by applying the configuration such as the feature A3, it is possible to avoid the inconvenience that the game performance intended for the player is not transmitted.

  Note that, in the relationship with the feature A15, the specific element may be a specific light emitting element. In this case, in the case where a plurality of light emitting elements are provided as the plurality of elements, the specific light emitting element is preferably set to have a larger light intensity than other light emitting elements. As a result, it is possible to produce a light effect that causes the player to visually recognize the impacting light. On the other hand, if the specific light emitting element malfunctions, the malfunction is easily noticeable. On the other hand, by applying the configuration of the feature A3 or the like, it is possible to avoid inconvenience that may be caused by the strength of the impact while performing an impact notification to the player.

Feature A17. The specific element is connected to a predetermined specific drive unit (third drive IC 203) among the plurality of drive units, and when a predetermined drive signal is input from the specific drive unit, Formed to drive in a specific manner,
The gaming machine according to feature A16, further comprising noise removing means (time constant circuit 221) provided between the specific element and the specific drive unit and configured to remove noise entering the drive signal.

  According to the feature A17, since the noise removing unit is provided, the noise of the drive signal input to the specific element is reduced. As a result, it is possible to avoid the disadvantage that the specific element malfunctions due to noise mixed in the drive signal output from the drive unit to the specific element.

Feature A18. The specific element is connected to a predetermined specific drive unit (third drive IC 203) among the plurality of drive units, and when a predetermined drive signal is input from the specific drive unit, Formed to drive in a specific manner,
Transmission that is provided between the specific element and the specific drive unit and transmits the drive signal to the specific element based on the drive signal being output from the specific drive unit for a predetermined period. A gaming machine according to Feature A16 or Feature A17, comprising means.

  If the specific element is driven immediately upon input of a drive signal, the specific element may be instantaneously driven by noise. For this reason, a misunderstanding is given to the player, and there is a possibility that the game characteristic intended for the player is not transmitted. In particular, in order to increase the degree of attention to the game, when the specific element is arranged at a position that is easy for the player to see, the above-described malfunction is likely to be noticeable.

  On the other hand, according to this feature, when the state in which the drive signal is output from the specific drive unit is maintained for a predetermined period, the drive signal is transmitted to the specific element and the specific element is driven. . Thus, even if a signal corresponding to the drive signal is generated instantaneously due to the influence of noise, the specific element is not driven. Therefore, it can be made difficult to be affected by noise, and the above inconvenience can be avoided.

  The feature group A is effective for the following problems.

  For example, some gaming machines such as pachinko machines are provided with a symbol display device having a display screen. For example, on the display screen in a pachinko machine, the design is variably displayed on the condition that the game ball passes through the operation port provided in the game area, and the effect of enhancing the interest of the game is performed, or when the predetermined condition is established Is displayed in a stopped state, and a special game state that is advantageous to a player such as a jackpot is taught. As an effect that enhances the interest of the game, for example, there is a reach effect that is closely related to the jackpot and increases the expectation of the player on the jackpot. Further, in recent years, in order to further enhance the interest of the game, in addition to the symbols that are variably displayed for each game time, an effect character or the like is displayed and a reach effect is performed using this character, or displayed on the display screen. Various ideas such as increasing the number of symbols have been made, and display effects are diversifying.

  Here, in order to enhance the interest of the game, apart from the symbol display device, for example, a plurality of elements used in various games such as a light emitting element and an electric movable element are provided, and element driving means for driving the element The drive circuit is mounted. The drive circuit is connected to a control device that performs control related to the game via, for example, wiring, and is configured to drive a corresponding element when a control signal is input from the control device.

  In such a configuration, for example, when a plurality of elements are provided in order to enhance the interest of the game, there is a concern that the configuration may be complicated, for example, the wiring connection configuration becomes complicated. In addition, when noise enters the drive circuit, the element may malfunction.

  The above-described problem is a problem common to gaming machines including a plurality of elements and element driving means for driving each element.

  Incidentally, the configuration limited by any one of the following features B1 to B9, the following features C1 to C9, and the following features D1 to D13 may be applied to any one of the features A1 to A18. In this case, the further effect by having applied each structure can be show | played.

<Feature B group>
Feature B1. A light-emitting element (LED 173) for notifying the game by emitting light;
Drive signal output means (drive ICs 191, 192, 203) for outputting a drive signal predetermined according to the game situation;
Drive means (voltage application circuit 202) for causing the light emitting element to emit light when the drive signal is output from the drive signal output means;
A gaming machine comprising noise removing means (time constant circuit 221) for removing noise mixed in the drive signal.

  According to the feature B1, the state of the game can be grasped by causing the light emitting element to emit light according to the state of the game. Thereby, a player's attention can be attracted to a light emitting element, and the attention degree to a game can be raised.

  In such a configuration, if noise is mixed in the drive signal, the light emitting element may emit light instantaneously due to the noise. For this reason, a misunderstanding is given to the player, and there is a possibility that the game characteristic intended for the player is not transmitted. In particular, in order to increase the degree of attention to the game, when the light emitting element is arranged at a position that is easy to see for the player and the light quantity of the light emitting element is set high, the light emission due to the malfunction is easily noticeable.

  On the other hand, according to this feature, since noise removing means is provided, noise of the drive signal input to the light emitting element is reduced. Thereby, it is possible to avoid the disadvantage that the light emitting element malfunctions due to noise mixed in the drive signal output from the driving means to the light emitting element.

  From the above, the light emitting element can be driven appropriately.

Feature B2. In addition to connecting the drive signal output means and the drive means, a wiring for transmitting the driving signal (wiring for connecting the OUT16 terminal and the p-type MOSFET 211),
The gaming machine according to feature B1, wherein the noise removing means is provided on the wiring, and includes a regulating means for regulating transmission of a signal having a predetermined frequency range.

  According to the feature B2, transmission of a signal having a frequency within a predetermined range is restricted by the restriction unit. Thereby, noise having a frequency in a predetermined range can be removed from the drive signal.

  Feature B3. The gaming machine according to Feature B2, wherein the regulating means includes a specific circuit having a resistor provided on the wiring and a capacitor connected in parallel to the resistor.

  According to the feature B3, since the specific circuit is provided, transmission of a signal having a frequency higher than the specific frequency is regulated by the specific circuit, and a signal having a frequency lower than the specific frequency is transmitted through the specific circuit. The The specific frequency is determined based on the capacitance of the capacitor and the resistance value of the resistor. Thereby, the noise can be suitably removed by setting the specific frequency according to the frequency of the noise to be removed by adjusting the capacitance of the capacitor and the resistance value of the resistor.

  Feature B4. The feature B3 is characterized in that the specific circuit outputs the drive signal or a signal corresponding to the drive signal to the drive means based on the drive signal being output for a predetermined period. The gaming machine described.

  If the driving means is configured to immediately emit light from the light emitting element in accordance with the output of the driving signal, the light emitting element may emit light instantaneously due to noise. For this reason, a misunderstanding is given to the player, and there is a possibility that the game characteristic intended for the player is not transmitted. In particular, when the light emitting element is arranged at a position that is easy to see for the player or the light amount of the light emitting element is set high in order to increase the degree of attention to the game, the light emission due to the malfunction is easily noticeable.

  On the other hand, according to this feature, the light emitting element emits light when the drive signal output state is maintained for a predetermined period. Thereby, even when a signal corresponding to the drive signal is generated instantaneously due to the influence of noise, the drive means is not driven. Therefore, it can be made less susceptible to noise, malfunction of the light-emitting element can be suppressed, and the above inconvenience can be avoided.

Feature B5. Drive data update means (function to execute LED drive data update processing) for updating predetermined drive data in a periodic process executed at a predetermined specific cycle,
The drive signal output means outputs the drive signal based on the drive data,
The gaming machine according to Feature B4, wherein the predetermined period is set longer than the specific period.

  According to the feature B5, the drive signal is output based on the drive data output from the update data update unit, and the light emitting element emits light. The drive data is updated by a periodic process performed every specific cycle. In this case, by updating the drive data, for example, an effect of blinking the light emitting elements at a predetermined cycle can be performed.

  In such a configuration, when the output period of the drive signal is longer than the specific period, the drive unit operates and the light emitting element emits light. As a result, even if an error occurs when updating drive data due to the influence of noise, the light emitting element does not emit light unless the error occurs a plurality of times. Accordingly, it is possible to prevent the light emitting element from malfunctioning due to an error that may occur when the drive data is updated or an error that may occur when the drive signal is output based on the drive data. Therefore, it is possible to appropriately control the light emitting element by updating the drive data, and to suppress malfunction of the light emitting element due to an error that may be caused thereby.

  As a specific configuration of this feature, it is conceivable that “the capacitance of the capacitor and the resistance value of the resistor are set so that the predetermined period is longer than the specific period”.

Feature B6. Provided with a permission signal output means for outputting a predetermined permission signal (second permission signal SG4) to the drive signal output means and the drive means (function to output the second permission signal SG4 in the sub CPU 111);
The drive signal output means shifts from a state where the drive signal cannot be output or a state where the drive signal can be output to a state where the drive signal can be output based on the permission signal being input from the permission signal output means. ,
The drive means drives the light emitting element when the permission signal is input from the permission signal output means and the drive signal is input from the drive signal output means,
The gaming machine according to any one of features B1 to B5, wherein the permission signal output means stops output of the permission signal when the light emitting element does not emit light.

  According to the feature B6, it is possible to output the drive signal when the permission signal is output. Thus, when drive data is not output, it is possible to prevent the drive signal from being erroneously output by not outputting the permission signal.

  In addition, since the driving means is configured to drive the light emitting element when the permission signal is input, even if the driving signal is erroneously output, it is driven as long as the permission signal is not input. Means do not work. Accordingly, it is possible to suppress malfunction of the light emitting element when a drive signal or a signal corresponding to the drive signal is input to the drive unit due to malfunction.

  Here, when the noise removing unit is provided, when the drive signal is stopped by the noise removing unit, transmission of the signal related to the stop may be delayed. In particular, as in the feature B4, when a predetermined period is set in order to make it less susceptible to noise, the delay becomes significant and the light emission of the light emitting element is delayed.

  On the other hand, according to this feature, by stopping the output of the permission signal, the light emission of the light emitting element is immediately stopped even when the transmission of the signal related to the stop of the drive signal is delayed by the noise removing unit. be able to. Therefore, inconveniences that can be caused by providing the noise removing means can be avoided.

Feature B7. Provide a plurality of the light emitting elements, and provide a plurality of the drive signal output means corresponding to each light emitting element,
Each drive signal output means is connected in series with each other,
Each drive signal output means is connected in a state where the plurality of light emitting elements are allocated,
Drive data control means (sub-data) that outputs predetermined drive data to at least one drive signal output means among the plurality of drive signal output means and updates the drive data at a predetermined update timing. CPU 111),
Each drive signal output means sequentially transmits the drive data between the drive signal output means each time when a predetermined update timing is reached in the situation where the drive data is output from the drive data control means, The output state of the drive signal is set to one corresponding to the drive data,
Any of the features B1 to B6, wherein the noise removing unit removes noise mixed in a drive signal output from a predetermined drive signal output unit among the plurality of drive signal output units. The gaming machine according to 1.

  According to the feature B7, a plurality of light emitting elements are provided, and a plurality of drive signal output means are provided corresponding to each light emitting element. When drive data is output by the drive data control means, drive data is transmitted between the drive signal output means, and the output state of the drive signal of each drive signal output means corresponds to the drive data. Is set. This eliminates the need to connect the drive data control means and each drive signal output means to transmit drive data, thereby reducing the number of wires connecting the drive data control means and the drive signal output means. Can do. Therefore, it is possible to suitably drive each light emitting element while simplifying the configuration.

  In such a configuration, noise mixed in the drive signal of the predetermined drive signal output means among the plurality of drive signal output means is removed by the noise removal means. Thereby, as a predetermined drive signal, for example, by setting a drive signal for controlling drive of a light emitting element that is particularly noticeable in a game, it is possible to suppress malfunction of the light emitting element that tends to be noticeable. Also, as a predetermined drive signal, for example, by setting a drive signal that is more susceptible to noise compared to other drive signals due to the positional relationship with other gaming machines such as a power supply unit that converts commercial power into DC power, In particular, it is possible to suppress a malfunction of a drive signal that easily causes noise.

Feature B8. Grant determination means (function to execute the process of step S401 in the main control device 60) for determining whether or not to grant a privilege based on the establishment of a predetermined condition;
When the determination result of the grant determination unit is a grant response result for granting a privilege, a privilege grant unit (such as a function for executing a game state transition process in the main control device 60) for granting a privilege to the player; ,
With
The drive data control means sets the drive data so that a predetermined specific light-emitting element among the light-emitting elements emits light in a predetermined specific mode when the result is the assignment correspondence result. ,
The noise removing unit is provided between a specific drive unit that drives the specific light emitting element and a specific drive signal output unit that outputs the drive signal to the specific drive unit, and noise mixed in the drive signal The gaming machine according to Feature B7, wherein

  According to the feature B8, the specific light emitting element emits light in a specific mode when the result is the assignment correspondence result. Thereby, a player's attention can be attracted to a specific light emitting element, and the attention degree to a game can be raised. In this case, due to the high degree of attention to the specific light-emitting element, light emission due to a malfunction of the specific light-emitting element is easily visible to the player and easily noticeable. As a result, the player may be misunderstood and the game characteristics intended for the player may not be transmitted.

  On the other hand, according to this feature, since the noise mixed in the drive signal for driving the specific light emitting element is removed by the noise removing unit, the specific light emitting element is unlikely to malfunction. Thereby, malfunction of a specific light emitting element can be suppressed and the problem which may arise by the malfunction can be avoided.

  Feature B9. The gaming machine according to Feature B8, wherein the specific drive signal output means is provided downstream in a drive data transmission path formed by the plurality of drive signal output means.

  The specific light emitting element is easily changed in design for each type of gaming machine in order to enhance the interest in gaming. In this regard, according to this feature, the specific drive signal output means for outputting the drive signal to the specific drive means for controlling the drive of the specific light emitting element is provided on the downstream side in the drive data transmission path. When the specific light emitting element needs to be changed separately, it is not necessary to change the upstream configuration. Thereby, it is possible to easily change the specific light emitting element and the configuration for driving and controlling the specific light emitting element.

  Incidentally, the configuration limited by any one of the features A1 to A18 and the following features D1 to D13 may be applied to any one of the features B1 to B9. In this case, the further effect by having applied each structure can be show | played.

<Feature C group>
Feature C1. A light-emitting element (LED 173) for notifying the game by emitting light;
Driving means (voltage application circuit 202) for causing the light emitting element to emit light;
Drive signal output means (drive ICs 191, 192, 203) for outputting a predetermined drive signal to the drive means in accordance with the game situation;
Drive control means (time constant circuit 221) for controlling the drive means so that the light emitting element emits light based on the output of the drive signal for a predetermined period;
A gaming machine characterized by comprising:

  According to the feature C1, it is possible to grasp the game situation by causing the light emitting element to emit light according to the game situation. Thereby, a player's attention can be attracted to a light emitting element, and the attention degree to a game can be raised.

  In such a configuration, if the driving unit is configured to immediately cause the light emitting element to emit light in response to the output of the drive signal, the light emitting element may emit light instantaneously due to noise. For this reason, a misunderstanding is given to the player, and there is a possibility that the game characteristic intended for the player is not transmitted. In particular, when the light emitting element is arranged at a position that is easy to see for the player or the light amount of the light emitting element is set high in order to increase the degree of attention to the game, the light emission due to the malfunction is easily noticeable.

  On the other hand, according to this feature, the light emitting element emits light when the drive signal output state is maintained for a predetermined period. Thereby, even when a signal corresponding to the drive signal is generated instantaneously due to the influence of noise, the drive means is not driven. Therefore, it can be made difficult to be affected by noise, and the above inconvenience can be avoided.

  From the above, the light emitting element can be driven appropriately.

Feature C2. Drive data update means (function to execute LED drive data update processing) for updating predetermined drive data in a periodic process executed at a predetermined specific cycle,
The drive signal output means outputs the drive signal based on the drive data,
The gaming machine according to Feature C1, wherein the predetermined period is set longer than the specific period.

  According to the feature C2, the drive signal is output based on the drive data output from the update data update unit, and the light emitting element emits light. The drive data is updated by a periodic process performed every specific cycle. In this case, by updating the drive data, for example, an effect of blinking the light emitting elements at a predetermined cycle can be performed.

  In such a configuration, when the output period of the drive signal is longer than the specific period, the drive unit operates and the light emitting element emits light. As a result, even if an error occurs when updating drive data due to the influence of noise, the light emitting element does not emit light unless the error occurs a plurality of times. Accordingly, it is possible to prevent the light emitting element from malfunctioning due to an error that may occur when the drive data is updated or an error that may occur when the drive signal is output based on the drive data. Therefore, it is possible to appropriately control the light emitting element by updating the drive data, and to suppress malfunction of the light emitting element due to an error that may be caused thereby.

Feature C3. In addition to connecting the drive signal output means and the drive means, a wiring for transmitting the driving signal (wiring for connecting the OUT16 terminal and the p-type MOSFET 211),
The drive control means is provided on the wiring, and transmits the drive signal to the drive means when the drive signal output state from the drive signal output means continues for the predetermined period. The gaming machine according to Feature C1 or Feature C2, further comprising transmission means (time constant circuit 221) for performing the above-described operation.

  In order to increase the luminance of a light emitting element from the viewpoint of increasing the degree of attention to the light emitting element, it is necessary to increase the power supplied to the light emitting element. In this case, if a configuration corresponding to a predetermined period, such as a configuration for measuring the predetermined period, is provided for the driving unit, power loss is generated by the amount corresponding to the configuration, and power supply to the light emitting element is not suitably performed Fear can arise.

  On the other hand, according to this feature, since the transmission means is provided on the wiring connecting the drive signal output means and the drive means, it is necessary to separately provide a configuration corresponding to a predetermined period for the drive means. There is no. Accordingly, power can be suitably supplied to the light emitting element, and the light emission luminance of the light emitting element can be preferably increased. Therefore, it is possible to increase the degree of attention to the light emitting element while ensuring the effect of the feature C1.

Feature C4. The transmission means includes
The gaming machine according to Feature C3, further comprising a specific circuit having a resistor provided on the wiring and a capacitor connected in parallel to the resistor.

  According to the feature C4, since a resistor and a capacitor connected in parallel to the resistor are provided, when the drive signal is output, transmission of the drive signal is delayed by a transient phenomenon due to the resistor and the capacitor. The The delay period is determined by the resistance value of the resistor and the capacitance of the capacitor. As a result, the predetermined period can be adjusted by adjusting the resistance value and the capacitance, and the period can be set to a period in which malfunction does not easily occur.

  Feature C5. The gaming machine according to Feature C3 or Feature C4, wherein the transmission unit includes a regulation unit that regulates transmission of a signal having a frequency higher than a predetermined specific frequency.

  According to the feature C5, since transmission of a signal having a frequency higher than a specific frequency is restricted by the restriction unit, a high-frequency signal mixed in the drive signal is removed. Thereby, it is possible to suppress malfunctions that may occur when the high-frequency signal enters the driving unit.

  Note that, according to the relationship with the feature C4, a signal having a frequency higher than a specific frequency is removed by the specific circuit. That is, the specific circuit functions as a transmission unit and also as a regulation unit. Thereby, each of the above-described effects can be achieved while simplifying the configuration.

Feature C6. Provided with a permission signal output means for outputting a predetermined permission signal (second permission signal SG4) to the drive signal output means and the drive means (function to output the second permission signal SG4 in the sub CPU 111);
The drive signal output means shifts from a state where the drive signal cannot be output or a state where the drive signal can be output to a state where the drive signal can be output based on the permission signal being input from the permission signal output means. ,
The drive means drives the light emitting element when the permission signal is input from the permission signal output means and the drive signal is input from the drive signal output means,
The gaming machine according to any one of features C3 to C5, wherein the permission signal output means stops output of the permission signal when the light emitting element does not emit light.

  According to the feature C6, it is possible to output the drive signal when the permission signal is output. Thus, when drive data is not output, it is possible to prevent the drive signal from being erroneously output by not outputting the permission signal.

  In addition, since the driving means is configured to drive the light emitting element when the permission signal is input, even if the driving signal is erroneously output, it is driven as long as the permission signal is not input. Means do not work. Accordingly, it is possible to suppress malfunction of the light emitting element when a drive signal or a signal corresponding to the drive signal is input to the drive unit due to malfunction.

  Here, when the transmission unit is provided, when the drive signal is stopped by the transmission unit, there is a possibility that transmission of the signal related to the stop is delayed. On the other hand, according to this feature, by stopping the output of the permission signal, even if the transmission of the signal related to the stop of the drive signal is delayed by the transmission means, the light emission of the light emitting element is immediately stopped. Can do. Therefore, inconveniences that can be caused by providing the noise removing means can be avoided.

Feature C7. Provide a plurality of the light emitting elements, and provide a plurality of the drive signal output means corresponding to each light emitting element,
Each drive signal output means is connected in series with each other,
Each drive signal output means is connected in a state where the plurality of light emitting elements are allocated,
Drive data control means (sub-data) that outputs predetermined drive data to at least one drive signal output means among the plurality of drive signal output means and updates the drive data at a predetermined update timing. CPU 111),
Each drive signal output means sequentially transmits the drive data between the drive signal output means each time when a predetermined update timing is reached in the situation where the drive data is output from the drive data control means, The output state of the drive signal is set to one corresponding to the drive data,
The drive control means outputs the drive signal output from the predetermined drive signal output means among the plurality of drive signal output means to the predetermined drive signal output means based on the output of the predetermined period. The gaming machine according to any one of features C1 to C6, wherein the connected light emitting element emits light.

  According to the feature C7, a plurality of light emitting elements are provided, and a plurality of drive signal output means are provided corresponding to each light emitting element. When drive data is output by the drive data control means, drive data is transmitted between the drive signal output means, and the output state of the drive signal of each drive signal output means corresponds to the drive data. Is set. This eliminates the need to connect the drive data control means and each drive signal output means to transmit drive data, thereby reducing the number of wires connecting the drive data control means and the drive signal output means. Can do. Therefore, it is possible to suitably drive each light emitting element while simplifying the configuration.

  In such a configuration, the light emitting element connected to the predetermined drive signal output unit emits light when the drive signal of the predetermined drive signal output unit among the plurality of drive signal output units is output for a predetermined period. Thereby, as the predetermined drive signal output means, for example, the drive signal output means for outputting the drive signal for controlling the drive of the light-emitting element that is particularly noticeable in the game, thereby suppressing the malfunction of the light-emitting element that is easily noticeable. Can do. Also, as the predetermined drive signal output means, for example, a drive signal output means that is more susceptible to noise than other drive signals is set by the positional relationship with other gaming machines such as a power supply unit that converts commercial power into DC power. By doing so, it is possible to suppress malfunctions of drive signals that are particularly susceptible to noise.

Feature C8. Grant determination means (function to execute the process of step S401 in the main control device 60) for determining whether or not to grant a privilege based on the establishment of a predetermined condition;
When the determination result of the grant determination unit is a grant response result for granting a privilege, a privilege grant unit (such as a function for executing a game state transition process in the main control device 60) for granting a privilege to the player; ,
With
The drive data control means sets the drive data so that a predetermined specific light-emitting element among the light-emitting elements emits light in a predetermined specific mode when the result is the assignment correspondence result. ,
The drive control means includes
Provided between a specific drive means for driving the specific light emitting element and a specific drive signal output means for outputting the drive signal to the specific drive means, and the drive signal is output from the specific drive signal output means. The gaming machine according to Feature C7, further comprising: a transmission unit that transmits the drive signal to the specific drive unit when the current state continues for the predetermined period.

  According to the feature C8, when the result is the assignment correspondence result, the specific light emitting element emits light in a specific mode. Thereby, a player's attention can be attracted to a specific light emitting element, and the attention degree to a game can be raised. In this case, due to the high degree of attention to the specific light-emitting element, light emission due to a malfunction of the specific light-emitting element is easily visible to the player and easily noticeable. As a result, the player may be misunderstood and the game characteristics intended for the player may not be transmitted.

  On the other hand, according to this feature, when a drive signal for driving the specific light emitting element is output for a predetermined period, the drive signal is transmitted to the specific drive means, and the specific light emitting element emits light. Thereby, since malfunction of the specific light emitting element due to noise can be suppressed, inconvenience that may be caused by the malfunction can be avoided.

  Feature C9. The gaming machine according to Feature C8, wherein the specific drive signal output means is provided downstream in a drive data transmission path formed by the plurality of drive signal output means.

  The specific light emitting element is easily changed in design for each type of gaming machine in order to enhance the interest in gaming. In this regard, according to this feature, the specific drive signal output means for outputting the drive signal to the specific drive means for controlling the drive of the specific light emitting element is provided on the downstream side in the drive data transmission path. When the specific light emitting element needs to be changed separately, it is not necessary to change the upstream configuration. Thereby, it is possible to easily change the specific light emitting element and the configuration for driving and controlling the specific light emitting element.

  Incidentally, the configuration limited by any one of the features A1 to A18 and the following features D1 to D13 may be applied to the configuration of any one of the features C1 to C9. In this case, the further effect by having applied each structure can be show | played.

  The feature B group and the feature C group are effective for the following problems.

  For example, some gaming machines such as pachinko machines are provided with a symbol display device having a display screen. For example, on the display screen in a pachinko machine, the design is variably displayed on the condition that the game ball passes through the operation port provided in the game area, and the effect of enhancing the interest of the game is performed, or when the predetermined condition is established Is displayed in a stopped state, and a special game state that is advantageous to a player such as a jackpot is taught. As an effect that enhances the interest of the game, for example, there is a reach effect that is closely related to the jackpot and increases the expectation of the player on the jackpot. Further, in recent years, in order to further enhance the interest of the game, in addition to the symbols that are variably displayed for each game time, an effect character or the like is displayed and a reach effect is performed using this character, or displayed on the display screen. Various ideas such as increasing the number of symbols have been made, and display effects are diversifying.

  Here, in order to enhance the interest of the game, a light emitting element is provided separately from the symbol display device, and a driving circuit as an element driving means for driving the light emitting element is mounted. The drive circuit is connected to a control device that performs control related to the game via, for example, wiring, and causes the light emitting element to emit light when a control signal is input from the control device. The fun of the game is improved by the light emission.

  In such a configuration, for example, if noise enters the drive circuit, the light emitting element malfunctions, and the malfunction may give a misunderstanding to the player, and the game characteristics intended for the player may not be transmitted.

  The above-described problem is a problem common to a gaming machine including a light-emitting element and an element driving unit that drives the light-emitting element.

<Feature D group>
Feature D1. A plurality of elements (LEDs 173);
Element driving means (LED driving unit 172) for individually driving the plurality of elements;
An element control means (sub CPU111) for controlling each element individually by connecting to the element driving means via a wiring and outputting predetermined driving data to the element driving means via the wiring;
With
In the gaming machine that drives each element individually in a mode corresponding to the drive data when the drive data is input from the element control means via the wiring,
The element driving means includes a plurality of driving units (driving ICs 191, 192, 203) connected in series with each other,
The plurality of driving units are connected in a state where the plurality of elements are allocated,
The element driving unit sequentially transmits the driving data between the plurality of driving units at each predetermined update timing in a situation where the driving data is input from the element control unit. Are set in order,
Each of the driving units is to allow an element connected to itself to operate in the set mode.
A gaming machine comprising selection means (sub CPU111) for selecting a driving unit to be operated among the plurality of driving units.

  According to the feature D1, the drive state of each element is set by transmitting drive data between a plurality of drive units. Thereby, since it is not necessary to transmit drive data to each drive part, the wiring which connects an element control means and an element drive means can be reduced. In this case, since the space occupied by the wiring can be reduced, it is easy to adjust the position of the wiring and perform a coating process so that ambient noise does not enter the wiring. Therefore, malfunction due to noise of each element can be suppressed.

  In addition, when a new element is provided, it is only necessary to further provide an element and a drive unit corresponding to the element in series, and design changes to the existing drive part can be reduced. Thereby, it is possible to easily cope with addition of elements and the like.

  In such a configuration, a transmission error may occur when driving data is transmitted, and noise may be generated in the driving data. In these cases, an incorrect mode may be set by the element control means, and the element may malfunction.

  On the other hand, according to this feature, the drive data is selected by selecting only the drive unit corresponding to the element to be driven in the drive data and not selecting the drive unit corresponding to the element not to be driven. It is possible to prevent the drive unit corresponding to the element that is not the target from operating. Thereby, it can suppress that the element which is not made to drive by the said transmission error and noise drives.

  From the above, each element can be driven suitably while simplifying the configuration.

Feature D2. The wiring is a first wiring (wiring for transmitting LED drive data SD),
The selection means includes permission signal output means (a function of outputting each permission signal SG3, SG4 in the sub CPU 111) for outputting a predetermined permission signal (first permission signal SG3 and second permission signal SG4),
The permission signal output means is connected to each drive unit via a second wiring (wiring for transmitting each permission signal SG3, SG4) different from the first wiring,
The drive unit is configured to operate when the permission signal is input via the second wiring,
The gaming machine according to Feature D1, wherein the selection unit selects a driving unit to be operated by switching a driving unit to which the permission signal is output.

  According to the feature D2, it is possible to select a drive unit that operates regardless of transmission of drive data by switching the drive unit that is the output target of the permission signal. In this case, the transmission of the drive data and the transmission of the permission signal are performed in different systems, so even if noise enters one of the two, the influence on the other is small, and as a result, the drive unit is affected by the noise. It is hard to receive. Thereby, it is possible to avoid the inconvenience that the element malfunctions due to noise.

  In addition, since it is not necessary to set special information such as a flag in the drive data when transmitting the drive data, the configuration of the drive data transmission can be simplified and the special information is set. Transmission errors that may occur due to this can be suppressed.

  Furthermore, it can suppress that both interfere by making it the structure which transmits a permission signal by a different system | strain from drive data. As a result, malfunction of each element that may be caused by interference between the permission signal and the drive data can be suppressed.

Feature D3. The permission signal output means includes
First output means for outputting a predetermined first permission signal (first permission signal SG3) to a first driving section (first driving IC 191 and second driving IC 192) among the plurality of driving sections (sub-sub). A function of outputting the first permission signal SG3 in the CPU 111);
Second output means for outputting a predetermined second permission signal (second permission signal SG4) to a second driving section (third driving IC 203) different from the first driving section (in the sub CPU 111, 2 function to output the permission signal SG4),
With
The first driving unit is configured to operate when the first permission signal is input;
The second driving unit is configured to operate when the second permission signal is input,
The gaming machine according to claim D2, wherein the selection unit is configured to select a driving unit to operate by controlling each permission signal from the first output unit and the second output unit.

  According to the feature D3, for example, an element connected to the first drive unit is controlled by outputting the first permission signal from the first output means and not outputting the second permission signal from the second output means. Can be driven, but the element connected to the second drive unit cannot be driven. Thereby, it is possible to suppress malfunction of an element that is not desired to be driven by signal control of each output means.

Feature D4. The plurality of elements include a first element (LED 173) connected to the first driving unit and a second element (winning notification LED 37) connected to the second driving unit. And
The gaming machine according to Feature D3, wherein the element control means controls the driving frequency of the first element to be higher than the driving frequency of the second element.

  According to the feature D4, the first driving unit that operates according to the first permission signal and the second driving unit that operates according to the second permission signal are classified according to the driving frequency of the elements connected to each driving unit. ing. Thereby, while outputting the first permission signal and not outputting the second permission signal, the first driving unit corresponding to the first element having a relatively high driving frequency is always operated, and the driving frequency is relatively low. The second drive unit corresponding to the low second element can be prevented from operating. Therefore, the processing load can be reduced by the amount that the second driving unit is not operated, and malfunction of the second element can be suppressed.

Feature D5. The second element includes a specific notification element (LED 37 for winning notification) that performs a notification regarding a game,
Grant determination means (function to execute the process of step S401 in the main control device 60) for determining whether or not to grant a privilege based on the establishment of a predetermined condition;
When the determination result of the grant determination unit is a grant response result for granting a privilege, a privilege grant unit (such as a function for executing a game state transition process in the main control device 60) for granting a privilege to the player; ,
With
The element control means sets the drive data so that the specific notification element is driven in a predetermined specific mode when the result is the assignment correspondence result,
The gaming machine according to Feature D4, wherein the selection unit controls the second output unit so that the second permission signal is output when the result is the grant correspondence result.

  According to the feature D5, in the case of the assignment correspondence result, the specific notification element is driven in a specific manner. Thereby, a player's attention can be attracted to a specific alerting | reporting element, and the attention degree to a game can be raised. In this case, due to the high degree of attention to the specific notification element, driving due to a malfunction of the specific notification element is easily visible to the player and easily noticeable. As a result, the player may be misunderstood and the game characteristics intended for the player may not be transmitted.

  On the other hand, according to this feature, the second drive unit that drives the specific notification element operates only when the result is the assignment correspondence result. Thereby, when it is not a provision correspondence result, the malfunctioning which a specific alerting | reporting element drives is suppressed. Therefore, the inconvenience which gives a misunderstanding to a player can be avoided.

  In the case of a configuration in which a plurality of notification elements are provided as a plurality of elements, the specific notification element may be set to have a larger light amount than other elements.

  Feature D6. The gaming machine according to Feature D5, wherein the second driving unit is provided on a downstream side in a driving data transmission path formed by the plurality of driving units.

  The specific notification element is easily changed in design for each type of gaming machine in order to enhance the interest in gaming. In this regard, according to this feature, since the second drive unit is provided on the downstream side in the drive data transmission path, it is necessary to separately change the specific notification element and the second drive unit that drives the specific notification element. If this happens, there is no need to change the upstream configuration. Thereby, the design change of a specific alerting | reporting element and a 2nd drive part can be performed easily.

  Feature D7. The game machine according to Feature D5 or Feature D6, wherein the specific notification element is a light emitting element.

  According to the feature D7, when the light emitting element emits light, a light effect can be given to the player, and the degree of attention to the game can be increased through the light effect. In such a configuration, it is conceivable to increase the light amount of the light emitting element from the viewpoint of increasing the degree of attention to the game. In this case, attention can be attracted to the light emitting element, but when the light emitting element malfunctions, the malfunction can be noticeable.

  On the other hand, by applying the configuration such as the feature D1 or the like, it is possible to suppress the occurrence of the malfunction, and it is possible to appropriately produce the light effect by the light emission of the light emitting element while avoiding the inconvenience.

  In the case of a configuration including a plurality of light-emitting elements as a plurality of elements, the specific notification element may be a specific light-emitting element that has a light amount set higher than that of the plurality of light-emitting elements. Thereby, a specific light emitting element can be made conspicuous compared with another light emitting element.

Feature D8. The element control means includes supply means (voltage application circuit 202) capable of supplying power that can drive the second element to the second element.
The second drive unit outputs a drive signal predetermined based on the drive data to the supply means (third drive) in a situation where the second permission signal is input. IC203 has a function of outputting a LOW signal from the OUT16 terminal)
The second output means outputs the second permission signal also to the supply means,
The supply means supplies the power to the second element when the second permission signal is input and the drive signal is input. The gaming machine according to any one of D7.

  According to the feature D8, when the second permission signal is not input to the supply unit, the second element is not driven even if the drive signal is input from the drive signal output unit. As a result, even if a signal corresponding to the drive signal is output due to noise, the supply means does not operate unless the second permission signal is input, so that the second element malfunctions due to the noise or transmission error. Can be suppressed.

Feature D9. A drive signal wiring for connecting the supply means and the drive signal output unit and transmitting the drive signal;
Transmission means provided on the drive signal wiring and transmitting the drive signal to the supply means when the state in which the drive signal is output from the drive signal output unit continues for a predetermined period (time) Constant circuit 221),
The gaming machine according to Feature D8, comprising:

  If the drive unit is configured to immediately drive the second element with the output of the drive signal, the second element may be instantaneously driven by noise. In particular, when the specific notification element malfunctions as in the feature D5, the player may be misunderstood and the game characteristics intended for the player may not be transmitted.

  On the other hand, according to this feature, when the state in which the drive signal is output is maintained for a predetermined period, the drive signal is transmitted to the supply unit, and the second drive unit operates, The second element is driven. Thereby, even when a signal corresponding to the drive signal is generated instantaneously due to the influence of noise, the supply means does not operate. Therefore, it can be made less susceptible to noise, the malfunction of the second element can be suppressed, and the above inconvenience can be avoided.

  In such a configuration, when output of the drive signal is stopped, transmission of the signal related to the stop of the drive signal may be delayed by a predetermined period by the transmission unit. On the other hand, by applying the configuration of the feature D8, it is possible to immediately stop the power supply by the supply unit by stopping the output of the second permission signal. Thereby, it is possible to avoid inconveniences that may occur due to the provision of the transmission means.

Feature D10. The element control means includes drive data update means (function to execute LED drive data update processing) for updating the drive data in a periodic process (sound emission control process) executed at a predetermined specific cycle,
The gaming machine according to Feature D9, wherein the predetermined period is set longer than the specific period.

  According to the feature D10, when the output period of the drive signal is longer than the specific period, the supply unit operates and the second element is driven. As a result, even if an error occurs when driving data is updated due to the influence of noise, the second element is not driven unless the error occurs a plurality of times. Thereby, it is possible to prevent the second element from malfunctioning due to an error that may occur when updating the drive data or an error that may occur when the drive signal is output based on the drive data. Therefore, it is possible to appropriately control the second element by updating the drive data, and to suppress malfunction of the second element due to an error that may be caused thereby.

Feature D11. The plurality of elements are a plurality of LEDs;
The driving unit shifts from an inactive state in which the plurality of LEDs cannot be driven to an active state in which the plurality of LEDs can be driven based on the permission signal being input. The gaming machine according to any one of features D2 to D10, wherein:

  According to the feature D11, when the permission signal is input to the driving IC, the driving IC becomes active and each LED can be driven. As a result, by switching the drive IC that is the output target of the permission signal, the drive IC that is in the active state can be selected.

Feature D12. It further comprises control means (sub CPU111) for executing game control relating to the progress of the game,
The control means executes specific processing including initialization processing prior to the game control when operating power is supplied,
The gaming machine according to any one of features D1 to D11, wherein the selection unit is configured to prevent each drive unit from operating during the specific process.

  According to the feature D12, each drive unit does not operate while the specific process is being performed, so that the element does not malfunction during the specific process. Accordingly, it is possible to avoid the disadvantage that each element malfunctions before the game is started and misleads the player.

Feature D13. Each of the plurality of driving units is
A data input section (DATAIN terminal) to which the drive data is input;
A data output unit (DATAOUT terminal) from which the drive data is output;
With
Series connection wiring for connecting each driving unit in series (wiring for connecting the DATAOUT terminal of the first driving IC 191 and the DATAIN terminal of the second driving IC 192, the DATAOUT terminal of the second driving IC 192, and the DATAIN terminal of the third driving IC 203) Wiring to connect), and
The series connection wiring connects the data output unit in a predetermined drive unit and the data input unit in another predetermined drive unit among the plurality of drive units, so that the plurality of drive units are connected in series. And
Any one of the features D1 to D12 is characterized in that a wiring from the element control means is connected to a data input section of a driving section in which the series connection wiring is not connected to a data input section. Game machines.

  According to the feature D13, the data output unit of the predetermined drive unit and the data input unit of another predetermined drive unit are connected by the series connection wiring, and the series connection wiring is not connected to the data input unit. Element control means is connected to the data input section of the drive section. As a result, drive data input from the element control means to the specific drive unit can be sequentially transmitted from the specific drive unit to each drive unit.

  The “drive unit in which the series connection wiring is not connected to the data input unit” is specifically arranged at the most upstream position in the drive data transmission path among the plurality of drive units connected in series. Drive unit.

  The feature group D is effective for the following problems.

  For example, some gaming machines such as pachinko machines are provided with a symbol display device having a display screen. For example, on the display screen in a pachinko machine, the design is variably displayed on the condition that the game ball passes through the operation port provided in the game area, and the effect of enhancing the interest of the game is performed, or when the predetermined condition is established Is displayed in a stopped state, and a special game state that is advantageous to a player such as a jackpot is taught. As an effect that enhances the interest of the game, for example, there is a reach effect that is closely related to the jackpot and increases the expectation of the player on the jackpot. Further, in recent years, in order to further enhance the interest of the game, in addition to the symbols that are variably displayed for each game time, an effect character or the like is displayed and a reach effect is performed using this character, or displayed on the display screen. Various ideas such as increasing the number of symbols have been made, and display effects are diversifying.

  Here, in order to enhance the interest of the game, apart from the symbol display device, for example, a plurality of elements used in various games such as a light emitting element and an electric movable element are provided, and element driving means for driving the element The drive circuit is mounted. The drive circuit is connected to a control device that performs control related to the game via, for example, wiring, and is configured to drive a corresponding element when a control signal is input from the control device.

  In such a configuration, for example, when a plurality of elements are provided in order to enhance the interest of the game, there is a concern that the configuration may be complicated, for example, the wiring connection configuration becomes complicated. In addition, when noise enters the drive circuit, the element may malfunction.

  The above-described problem is a problem common to gaming machines including a plurality of elements and element driving means for driving each element.

  Incidentally, the configuration limited by any one of the features A1 to A18, the features B1 to B9, and the features C1 to C9 may be applied to the configuration of any one of the features D1 to D13. In this case, the further effect by having applied each structure can be show | played.

  The basic configuration of the gaming machine to which the above features can be applied is shown below.

  Pachinko gaming machine: operation means operated by a player, game ball launching means for launching a game ball based on the operation of the operation means, a ball path for guiding the launched game ball to a predetermined game area, and a game A gaming machine that includes each gaming component arranged in an area, and gives a bonus to a player when a gaming ball passes through a predetermined passing portion of each gaming component.

  Revolving type gaming machine such as a slot machine: equipped with a picture display device for variably displaying a plurality of pictures, variably starting display of the plurality of pictures due to the operation of the start operation means, and due to the operation of the stop operation means Then, the variable display of the plurality of patterns is stopped, and the gaming machine gives a privilege to the player according to the pattern after the stop.

  DESCRIPTION OF SYMBOLS 10 ... Pachinko machine, 20 ... Game board, 35, 36 ... Holding lamp part, 37 ... LED for winning notification, 60 ... Main control device, 90 ... Sound lamp control device, 91 ... LED board, 111 ... Sub CPU, 121 ... Arithmetic circuit, 122, register, 131, output port, 134, data output circuit, 141, LED drive register, 143, clock signal register, 145, data write signal register, 147, 148, permission signal register, 171 ... Input port, 173 ... LED, 191,192,203 ... Drive IC, 191a, 192a ... Update circuit, 191b, 192b ... Register, 191c, 192c ... Update buffer, 201 ... Winning notification circuit, 202 ... Voltage application circuit , 211... P-type MOSFET, 212... N-type MOSFET, 221. 2 ... resistors, 223 ... capacitor, 301, 302 ... driving IC, 401 and 402 ... drive IC, 501 and 502 ... phase shift circuit.

Claims (1)

A light emitting element for informing about a game by emitting light;
Drive signal output means for outputting a predetermined drive signal according to the game situation;
Drive means for causing the light emitting element to emit light when the drive signal is output from the drive signal output means;
A wiring for connecting the drive signal output means and the drive means and transmitting the drive signal;
Noise removing means for removing noise mixed in the drive signal;
Equipped with a,
The noise removing means is provided in the middle of the route of the wiring, and when the state in which the drive signal is output from the drive signal output means continues for a predetermined period, the drive signal is sent to the drive means. A transmission means for transmitting,
It said drive signal output means, a game machine, wherein the output enable der Rukoto the drive signal continues longer than the period for light emitting the light emitting element.

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