JP2018198949A - Game machine - Google Patents

Abstract

To provide a game machine capable of appropriately performing communication between control means and an element.SOLUTION: The game machine includes element drive means for driving an element, data storage means in which a drive object does not exist, and element control means electrically connected to the element drive means. The element control means outputs predetermined drive data to the element drive means through wiring. When the drive data is input, the element drive means drives the element in a mode corresponding to the drive data. The element drive means is electrically connected to the data storage means in which a drive object does not exist. The data that has passed through the data storage means is supplied to the element drive means electrically connected to the data storage means.SELECTED DRAWING: Figure 12

Description

  The present invention relates to a gaming machine.

  For example, a gaming machine such as a pachinko machine is provided with a plurality of elements used in various games such as a light-emitting element or an electric movable element to enhance the interest of the game. The element is controlled in accordance with the game situation by a control device that controls the game. In addition, a drive circuit is mounted as an element driving means for driving the element, the drive circuit is connected to the control device via a wiring or the like, and when a control signal is input from the control device, It is comprised so that a corresponding element may be driven (for example, patent document 1).

JP 2008-212271 A

  Here, in the gaming machine such as the above-described example, a configuration capable of suitably performing communication between the control means and the element is required, and there is still room for improvement in this respect.

  The above-described problem is a problem common to gaming machines including a plurality of elements and element driving means for driving each element.

  The present invention has been made in view of the above-described circumstances, and an object thereof is to provide a gaming machine capable of suitably performing communication between a control unit and an element.

In order to solve the above-mentioned problem, the invention described in claim 1 includes a predetermined element driving means for driving an element,
Element control means electrically connected to the predetermined element driving means and controlling elements by outputting predetermined driving data to the predetermined element driving means via wiring;
With
In the gaming machine in which the predetermined element driving unit drives the element in a mode corresponding to the driving data when the driving data is input from the element control unit.
A specific element driving means that is provided separately from the predetermined element driving means and drives the element;
Data storage means for which there is no drive target;
With
The data passing through the data storage means is supplied to the predetermined element driving means electrically connected to the data storage means,
The element control means supplies the same drive data to each of a predetermined control object including the data storage means and the predetermined element driving means and a specific control object including the specific element driving means,
Since the data storage means for which no drive target exists does not exist in the specific control target or the number of the data storage means for which no drive target exists is smaller than the predetermined control target, the predetermined control target at the predetermined timing The data stored in the data storage means and the data supplied to the specific element driving means are the same,
The gaming machine transmits a use trigger signal for providing a trigger to use the driving data supplied to the predetermined element driving unit and the specific element driving unit for driving the element in each element driving unit. It is characterized by comprising a utilization trigger supply means for supplying the drive means and the specific element drive means simultaneously or substantially simultaneously.

  According to the present invention, it is possible to suitably perform communication between the control means and the element.

It is a front view of the pachinko machine in a 1st embodiment. It is a front view which shows the structure of a game board. It is a block diagram which shows the electric constitution of a pachinko machine. It is explanatory drawing for demonstrating the display content on the display screen of a symbol display apparatus. It is explanatory drawing for demonstrating the display content on the display screen of a symbol display apparatus. It is explanatory drawing for demonstrating the content of the various counters used for a success or failure lottery. It is a flowchart which shows the NMI interruption process in MPU of a main controller. It is a flowchart which shows the timer interruption process in MPU of a main controller. It is a flowchart which shows the normal process in MPU of a main controller. It is a block diagram which shows the electric constitution of an audio | voice lamp control apparatus. It is a circuit diagram of the data output circuit mounted in the sound lamp control board. It is a circuit diagram which shows the various circuits mounted in the LED board. (A) It is a block diagram which shows the internal structure of 1st drive IC, (b) It is a block diagram which shows the internal structure of pseudo drive IC and 2nd drive IC. It is a block diagram for demonstrating the connection aspect of the D flip-flop which comprises the update buffer and register | resistor of 1st drive IC. It is a timing chart for demonstrating the update timing of the update buffer of pseudo drive IC. It is a table showing the signal currently written in the update buffer of 1st drive IC, pseudo drive IC, and 2nd drive IC when LED drive data for the first half 8 bits is written. It is a table showing the signal written in the update buffer of 1st drive IC, pseudo drive IC, and 2nd drive IC just before a data write signal rises. It is a flowchart which shows the audio | voice lamp control process in an audio | voice lamp control apparatus. It is a circuit diagram which shows the various circuits mounted in the LED board in 2nd Embodiment. (A) It is a block diagram which shows the internal structure of the 1st drive IC in 2nd Embodiment, (b) It is a block diagram which shows the internal structure of the 2nd drive IC in 2nd Embodiment. It is a block diagram for demonstrating the connection aspect of D flip-flop which comprises the update buffer and register | resistor of 1st drive IC and 2nd drive IC in 2nd Embodiment. It is a timing chart for demonstrating the update timing of the LED drive data in 2nd Embodiment. 10 is a table showing signals written in update buffers of the first drive IC and the second drive IC immediately before the data write signal rises in the second embodiment. It is a block diagram for demonstrating the connection aspect of D flip-flop and T flip-flop which comprise the update buffer and register | resistor of a 1st drive IC in 3rd Embodiment. It is a block diagram for demonstrating the connection aspect of D flip-flop and T flip-flop which comprise the update buffer and register | resistor of a 2nd drive IC in 3rd Embodiment. It is a timing chart for demonstrating the update timing of LED drive data in 3rd Embodiment. It is a block diagram which shows the connection aspect of the audio | voice lamp control apparatus, relay board | substrate, communication IC, various decoration apparatuses, and a vibration detection sensor in 4th Embodiment. It is a circuit diagram which shows the periphery of IC for communication in 4th Embodiment. It is a flowchart which shows the write communication process by IC for decorating devices in 4th Embodiment. It is explanatory drawing for demonstrating the motion of the sliding door type automatic door opened and closed by the accessory drive motor and sensor in 4th Embodiment. (A) It is a block diagram which shows ROM and RAM in sub CPU in 4th Embodiment, (b) It is a block diagram which shows the register in IC for decoration devices. It is a flowchart which shows the audio | voice lamp control process by the audio | voice lamp control apparatus in 4th Embodiment. It is a flowchart which shows the opening process of the door by the audio | voice lamp control apparatus in 4th Embodiment. It is a flowchart which shows the door closing process by the audio | voice lamp control apparatus in 4th Embodiment. It is a flowchart which shows the reading communication process by IC for decorating devices in 4th Embodiment. It is a flowchart which shows the fraud monitoring process by the audio | voice lamp control apparatus in 4th Embodiment. It is a circuit diagram which shows the connection aspect of T flip-flop for converting the clock signal in another example of 2nd Embodiment, and D flip-flop. It is a timing chart for demonstrating the update timing of the LED drive data in another example of 2nd Embodiment. 12 is a table showing data written in four update buffers immediately before a data write signal rises in another example of the second embodiment.

<First Embodiment>
Hereinafter, a first embodiment of a pachinko gaming machine (hereinafter referred to as a “pachinko machine”), which is a type of gaming machine, will be described with reference to the drawings. FIG. 1 is a front view of the pachinko machine 10.

  As shown in FIG. 1, the pachinko machine 10 includes an outer frame 11 that forms an outer shell of the pachinko machine 10, and a gaming machine body 12 that is rotatably attached to the outer frame 11. . The gaming machine main body 12 includes an inner frame (not shown), a front door frame 14 arranged in front of the inner frame, and a back pack unit (not shown) arranged behind the inner frame.

  The inner frame of the gaming machine main body 12 is rotatably supported by the outer frame 11 with one of the left and right side portions serving as a support side. Further, the front door frame 14 is rotatably supported by the inner frame, and can be rotated forward by using one of the left and right side portions as a support side. Further, the back pack unit is rotatably supported by the inner frame, and can be rotated rearward with one of the left and right side portions as a support side.

  Note that the gaming machine body 12 is provided with a locking device (not shown) at its rotating tip, and has a function of locking the gaming machine body 12 to the outer frame 11 so that it cannot be opened. In addition, the front door frame 14 has a function of locking the front door frame 14 to the inner frame so as not to be opened. Each of these locked states is released by performing an unlocking operation using the unlocking key on the cylinder lock 17 that is exposed on the front surface of the pachinko machine 10.

  A game board 20 is mounted on the inner frame. Here, the structure of the game board 20 is demonstrated based on FIG. FIG. 2 is a front view of the game board 20.

  The game board 20 is formed with a plurality of large and small openings penetrating in the front-rear direction by being subjected to router processing. Each opening has a general winning port 21, a variable winning device 22, an upper operating port (first starting ball entering portion) 23, a lower operating port (second starting ball entering portion) 24, a through gate 25, a variable display unit 26, A main display unit 33, an accessory display unit 34, and the like are provided.

  When a ball enters the general winning port 21, the variable winning device 22, the upper operating port 23, and the lower operating port 24, it is detected by a detection sensor (not shown) disposed on the back side of the game board 20, Based on the detection result, a predetermined number of prize balls are paid out.

  In addition, an out port 27 is provided at the lowermost part of the game board 20, and game balls that have not entered various winning ports etc. are discharged from the game area through the out port 27. The game board 20 is provided with a large number of nails 28 for dispersing and adjusting the falling direction of the game ball as appropriate, and various members (functions) such as a windmill.

  Here, the entry ball means that the game ball passes through a predetermined opening, and is not only a mode of being discharged from the game area after passing through the opening, but is discharged from the game area after passing through the opening. Embodiments that are not included are also included. However, in the following description, in order to clearly distinguish the game ball from entering the out port 27, the game ball enters the variable winning device 22, the upper operating port 23, the lower operating port 24 or the through gate 25. Is also expressed as a prize.

  The upper operating port 23 and the lower operating port 24 are unitized as operating port devices and are installed in the game board 20. Both the upper working port 23 and the lower working port 24 are opened upward. Further, both the operation ports 23 and 24 are arranged in the vertical direction so that the upper operation port 23 is on the upper side. The lower working port 24 is provided with an electric accessory 24a as a guide piece (support piece) composed of a pair of left and right movable pieces. In the closed state (non-supported state or non-guided state) of the electric accessory 24a, the game ball cannot win the lower operating port 24, and the electric operating member 24a is in the open state (supported state or guide state). It is possible to win 24.

  The variable winning device 22 includes a large winning opening 22a that leads to the back side of the game board 20, and an open / close door 22b that opens and closes the large winning opening 22a. The open / close door 22b is normally in a closed state where a game ball cannot be won or difficult to win, and a predetermined game ball is likely to win when winning the opening / closing execution mode (open / close execution state) in the internal lottery. It can be switched to the open state. Here, the opening / closing execution mode is a mode to be shifted to when a big win is won. The opening / closing execution mode will be described in detail later. As a release mode of the variable winning device 22, the variable winning device 22 is repeatedly opened with a predetermined time (for example, 30 seconds) or a predetermined number (for example, 10) of winnings as one round and a plurality of rounds (for example, 15 rounds) as an upper limit. There is an embodiment.

  The main display portion 33 and the accessory display portion 34 are provided on a decorative member 29 disposed along the outer edge on the lower side of the game area. The decorative member 29 extends from the board surface of the game board 20 to the front of the pachinko machine 10. More specifically, the front surface of the decorative member 29 faces the window panel 53 provided on the front door frame 14 so that the game area can be viewed from the front of the pachinko machine 10. The distance between them is narrower than that of one game ball. This prevents the game ball from dropping in front of the front surface of the decorative member 29.

  A main display unit 33 and an accessory display unit 34 are provided so as to be exposed from the front surface of the decorative member 29. That is, the main display unit 33 and the accessory display unit 34 are visible from the front of the pachinko machine 10 through the window panel 53 of the front door frame 14, and a game ball is in front of both the display units 33 and 34. It is prevented from falling.

  In the main display unit 33, the display of the variation of the picture is performed with the winning of the upper working port 23 or the lower working port 24 as a trigger, and as a result of stopping the variation display, the winning to the upper working port 23 or the lower working port 24 is achieved. The result of the internal lottery performed based on the display is clearly shown. That is, in the present pachinko machine 10, the winning to the upper working port 23 and the winning to the lower working port 24 are not distinguished in the internal lottery, and are performed based on the winning to the upper working port 23 or the lower working port 24. The result of the internal lottery is displayed on the main display section 33 which is a common display area. When the result of the internal lottery based on the winning to the upper working port 23 or the lower working port 24 is a winning result corresponding to the shift to the opening / closing execution mode, a predetermined stop result is displayed on the main display unit 33. After the display and the change display are stopped, the mode shifts to the opening / closing execution mode.

  The main display unit 33 is configured by a segment display in which a plurality of segment light emitting units are arranged in a predetermined manner. However, the main display unit 33 is not limited to this, and a liquid crystal display device, an organic EL display device, You may be comprised by other types of display apparatuses, such as CRT and a dot matrix. In addition, as a pattern that is variably displayed on the main display unit 33, a configuration in which a plurality of types of characters are variably displayed, a configuration in which a plurality of types of symbols are variably displayed, a configuration in which a plurality of types of characters are variably displayed, or a plurality A configuration in which the color of the seed is switched and displayed can be considered.

  The accessory display unit 34 displays a variation of the picture triggered by a winning to the through gate 25, and the result of the internal lottery performed based on the winning to the through gate 25 as a result of stopping the variation display. Explicit by display. When the result of the internal lottery based on the winning to the through gate 25 is a winning result corresponding to the transition to the electric role open state, a predetermined stop result is displayed on the accessory display unit 34 and displayed in a variable manner. After is stopped, it shifts to the electric utility open state. In the electric combination open state, the electric combination 24a provided in the lower working port 24 is opened in a predetermined manner.

  The variable display unit 26 is provided with a symbol display device 31 that performs variable display (or variable display or switching display) of a symbol that is a kind of symbol. The variable display unit 26 is provided with a center frame 32 so as to surround the symbol display device 31. The center frame 32 has an upper portion extending forward of the pachinko machine 10. As a result, the game ball is prevented from dropping in front of the display screen of the symbol display device 31, and the inconvenience that the visibility of the display screen is reduced due to the fall of the game ball is not caused. .

  The symbol display device 31 is configured as a liquid crystal display device including a liquid crystal display, and display contents are controlled by a display control device described later. The symbol display device 31 is not limited to a liquid crystal display device, and may be another display device such as a plasma display device, an organic EL display device, or a CRT.

  On the symbol display device 31, for example, symbols are displayed side by side in the top, middle and bottom, and these symbols are variably displayed as they are scrolled in the horizontal direction. In this case, the change display on the symbol display device 31 is started based on winning in the upper working port 23 or the lower working port 24. That is, when variable display is performed on the main display unit 33, variable display is performed on the symbol display device 31 accordingly. Then, for example, the symbol display device 31 is set in advance to a game number of times that shifts to the opening / closing execution mode corresponding to 15 rounds, in which the large winning opening 22a of the variable winning device 22 is opened 15 times as the opening / closing execution mode. A predetermined combination of symbols is stopped and displayed on the active line.

  By the way, based on the winning at any one of the operating ports 23, 24, the variable display is started on the main display unit 33 and the symbol display device 31, the predetermined stop result is displayed, and the above variable display is stopped. It corresponds to one game time.

  A first holding lamp portion 35 corresponding to the main display portion 33 and the symbol display device 31 is provided at the upper left portion on the front side of the center frame 32. The first holding lamp unit 35 is composed of LEDs. A maximum of four game balls won in the upper operation port 23 or the lower operation port 24 are reserved, and the number of reservations is displayed when the first reservation lamp unit 35 is turned on.

  In the upper right portion of the center frame 32, a second holding lamp portion 36 corresponding to the accessory display portion 34 is provided. The second holding lamp unit 36 is composed of LEDs. The number of times that the game ball has passed through the through gate 25 is held up to a maximum of 4 times, and the number of the held balls is displayed when the second holding lamp unit 36 is turned on. In addition, it is good also as a structure by which the function of each holding | maintenance lamp | ramp part 35 and 36 is fulfill | performed by the display in the one part area | region of the symbol display apparatus 31.

  Here, the game board 20 is provided with a light-emitting body 37 for winning notification as a specific light-emitting element. The winning notification light emitter 37 is disposed on the upper portion of the center frame 32. Since the symbol display is performed on the symbol display device 31 as already described, the player's attention is easily attracted to the symbol display device 31 and the center frame 32. For this reason, it can be said that the winning notification light-emitting body 37 is installed in a place that is easily noticeable to the player (a place that is easily visible).

  The winning notification light-emitting body 37 is set to emit light when a privilege is given to a player, specifically, when winning in the opening / closing execution mode (opening / closing execution state) is won. Thereby, the player can easily pay attention to the variation display mode of the symbol display device 31 and the light emission mode of the light-emitting body 37 for winning notification. Thereby, the attention degree to a game can be improved.

  The winning notification light emitter 37 includes an LED 173 and a cover. Of the twelve LEDs 173, the upper six LEDs 173 are collectively grouped into an LED group 37a, and the lower six LEDs 173 are grouped into an LED group 37b. The LED group 37a and the LED group 37b are controlled as a group.

  An inner rail portion 41 and an outer rail portion 42 are attached to the game board 20, and a guide rail is configured by the inner rail portion 41 and the outer rail portion 42, and is mounted below the game board 20 in the inner frame. A game ball launched from the game ball launching mechanism (not shown) is guided to the upper part of the game area. The game ball launching mechanism launches a game ball by operating a launch handle 51 provided on the front door frame 14.

  A front door frame 14 is provided so as to cover the entire front side of the inner frame. As shown in FIG. 1, the front door frame 14 is formed with a window portion 52 so that almost the entire game area can be viewed from the front. The window portion 52 has a substantially elliptical shape, and the above-described window panel 53 is fitted therein. The window panel 53 is colorless and transparent formed of glass, but is not limited thereto, and may be formed colorless and transparent using a synthetic resin.

  Around the window portion 52, light emitting means such as various lamps are provided. A display lamp part 54 is provided above the window part 52 as a part of the various lamp parts. These various lamp units are composed of LEDs. In addition, on both the left and right sides of the display lamp unit 54, speaker units 55 for outputting sound effects according to the gaming state are provided.

  Below the window portion 52 in the front door frame 14, an upper bulging portion 56 and a lower bulging portion 57 that bulge to the near side are arranged side by side. An upper plate 56a that opens upward is provided inside the upper bulge portion 56, and a lower plate 57a that also opens upward is provided inside the lower bulge portion 57. The upper plate 56a has a function of temporarily storing game balls paid out from a payout device described later and guiding them to the game ball launching mechanism side while aligning them in a line. In addition, the lower tray 57a has a function of storing game balls that are surplus in the upper tray 56a. The game balls paid out from the payout device mounted on the back pack unit are discharged to the upper plate 56a and the lower plate 57a.

  A main control device, an audio lamp control device, and a display control device are mounted on the back side of the inner frame. Further, as described above, a back pack unit is provided on the back surface of the inner frame. The back pack unit includes a payout mechanism including a payout device, a payout control device, a power source and a firing control device. Is installed. Hereinafter, the electrical configuration of the pachinko machine 10 will be described.

<Basic electrical configuration of the pachinko machine 10>
FIG. 3 is a block diagram showing a basic electrical configuration of the pachinko machine 10.

  The main control device 60 includes a main control board 61 that controls the main control of the game, and a power failure monitoring board 65 that monitors the power supply. In the main controller 60, a substrate box that accommodates the main control substrate 61 or the like is provided with a trace means for leaving a trace of its opening or a trace structure for leaving a trace of its opening. It may be. As the trace means, a plurality of case bodies constituting the substrate box are unseparably coupled, and a configuration of a coupling portion (caulking portion) that requires destruction of a predetermined part at the time of separation, or an adhesive layer is attached by peeling off. A configuration is conceivable in which a seal seal that leaves a trace of being peeled off by being left is attached so as to straddle the boundary between a plurality of case bodies. Moreover, as a trace structure, the structure which apply | coats an adhesive agent with respect to the boundary between the some case bodies which comprise a board | substrate box can be considered.

  An MPU 62 is mounted on the main control board 61. The MPU 62 includes a ROM 63 that stores various control programs executed by the MPU 62 and fixed value data, and a memory that temporarily stores various data when the control program stored in the ROM 63 is executed. A RAM 64, an interrupt circuit, a timer circuit, a data input / output circuit, various counter circuits as a random number generator, and the like are incorporated.

  The MPU 62 is provided with an input port and an output port. A power failure monitoring board 65 and a payout control device 70 provided in the main control device 60 are connected to the input side of the MPU 62. In this case, the power failure monitoring board 65 is connected to a power supply and launch control device 80 having a function of supplying operating power, and the MPU 62 is supplied with power via the power failure monitoring board 65.

  Various sensors such as various winning detection sensors 66 a to 66 e are connected to the input side of the MPU 62. Each of the various winning detection sensors 66a to 66e has a one-to-one detection with respect to a winning-corresponding pitched portion such as a general winning port 21, a variable winning device 22, an upper operating port 23, a lower operating port 24, and a through gate 25. A sensor is included, and the MPU 62 performs a winning determination (entering determination) for each entering part. In addition, the MPU 62 executes a lottery generation lottery based on the winnings to the upper operating port 23 and the lower operating port 24 and also performs the support generating lottery based on the winnings to the through gate 25.

  A power failure monitoring board 65, a payout control device 70, and an audio lamp control device 90 are connected to the output side of the MPU 62. For example, the payout control device 70 outputs a winning ball command based on the winning determination result to the winning corresponding winning portion. In this case, when outputting the prize ball command, the command information storage area of the ROM 63 is referred to.

  Various commands such as a change command, a type command, a change end command, an opening command, and an ending command are output to the sound lamp control device 90. In this case, the command information storage area of the ROM 63 is referred to when these various commands are output. Details of these various commands will be described later.

  Further, on the output side of the MPU 62, a variable winning drive unit 22c that opens and closes the opening / closing door 22b of the variable winning device 22, an electric combination driving unit 24b that opens and closes the electric combination 24a of the lower working port 24, and a main display unit. 33 and the accessory display unit 34 are connected. The main control board 61 is provided with various driver circuits, and the MPU 62 performs drive control of various drive units through the driver circuits.

  That is, in the opening / closing execution mode, the MPU 62 executes drive control of the variable winning drive unit 22c so that the special winning opening 22a is opened and closed. Further, when the electric combination 24a is won, the MPU 62 performs drive control of the electric combination drive unit 24b so that the electric combination 24a is opened and closed. In each game round, the display control of the main display unit 33 is executed in the MPU 62. In addition, when the lottery result indicating whether or not the electric accessory 24a is to be opened is clearly indicated, display control of the accessory display unit 34 is executed in the MPU 62.

  The power failure monitoring board 65 relays between the main control board 61 and the power supply and launch control device 80, and monitors the DC stable voltage of 24 volts, which is the maximum voltage output from the power supply and launch control device 80. The payout control device 70 performs payout control of prize balls and rental balls by the payout device 71 based on the prize ball command input from the main control device 60.

  The power source and launch control device 80 is connected to, for example, a commercial power source (external power source) in a game hall or the like. And based on the external electric power supplied from the commercial power supply, the necessary operating power is generated for each of the main control board 61, the payout control device 70, etc., and the generated operating power is supplied. The power supply and launch control device 80 is responsible for launch control of the game ball launch mechanism 81, and the game ball launch mechanism 81 is driven when predetermined launch conditions are met.

  The sound lamp control device 90 performs drive control of various light emitting elements including various lamp portions 35 and 36 provided in the game board 20, a light emitting body 37 for winning notification and a display lamp portion 54 provided in the front door frame 14. It is connected to the LED board 91, and by driving predetermined drive data to the LED board 91 based on various commands input from the main controller 60, various light emitting elements are driven and controlled.

  The sound lamp control device 90 controls the display control device 100 while driving and controlling the speaker unit 55 provided on the front door frame 14. In the display control device 100, display control of the symbol display device 31 is executed based on the command input from the sound lamp control device 90.

  Here, the display content of the symbol display device 31 will be described with reference to FIGS. FIG. 4 is a diagram individually showing symbols variably displayed on the symbol display device 31, and FIG. 5 is a diagram showing a display screen G of the symbol display device 31.

  As shown in FIGS. 4 (a) to (j), a design which is a kind of design is composed of nine main designs with numbers "1" to "9", respectively, and a shell-shaped design. It consists of sub-designs. More specifically, the main symbols are configured by attaching numbers “1” to “9” to nine types of character symbols such as octopus.

  As shown in FIG. 5A, on the display screen G of the symbol display device 31, three symbol rows Z1, Z2, and Z3 of an upper stage, a middle stage, and a lower stage are set as a plurality of display areas. Each of the symbol rows Z1 to Z3 includes a main symbol and a sub symbol arranged in a predetermined order. Specifically, nine types of main symbols “1” to “9” are arranged in descending order of numbers in the upper symbol row Z1, and one sub symbol is arranged between each main symbol. . In the lower symbol row Z3, nine types of main symbols “1” to “9” are arranged in ascending numerical order, and one sub symbol is arranged between the main symbols.

  That is, the upper symbol row Z1 and the lower symbol row Z3 are composed of 18 symbols. On the other hand, in the middle symbol row Z2, nine types of main symbols “1” to “9” are arranged in ascending numerical order, and then between the main symbol “9” and the main symbol “1”. In addition, a main symbol “4” is additionally arranged, and one sub symbol is arranged between each main symbol. In other words, only the middle symbol row Z2 is composed of 20 symbols by arranging 10 main symbols. On the display screen G, the symbols in the symbol rows Z1 to Z3 are displayed in a variable manner so as to scroll in a predetermined direction with periodicity.

  As shown in FIG. 5B, on the display screen G, 3 symbols are stopped and displayed for each symbol row, and as a result, a total of 9 symbols of 3 × 3 are stopped and displayed. It is like that. The display screen G has five effective lines, that is, a left line L1, a middle line L2, a right line L3, a right lowering line L4, and a right uppering line L5. Then, the variable display stops in the order of the upper symbol row Z1 → the lower symbol row Z3 → the middle symbol row Z2, and all the symbol rows Z1 are formed in a state in which a combination of symbols having the same number attached to any one of the effective lines is formed. When the fluctuation display of .about.Z3 is completed, the jackpot moving image is displayed as a normal jackpot result or a 15R probability variable jackpot result which will be described later.

  In this pachinko machine 10, the main symbols with odd numbers (1, 3, 5, 7, 9) correspond to “specific symbols”, and when a 15R probability variation jackpot result is generated, The combination is stopped. The main symbols with even numbers (2, 4, 6, 8) correspond to “non-specific symbols”. When a normal jackpot result occurs, the combination of the same non-specific symbols is stopped and displayed. The

  In addition, when an explicit 2R probability variation jackpot result to be described later is obtained, the variation display of all the symbol rows Z1 to Z3 is finished in a state where a predetermined symbol combination different from the same symbol combination is formed, and then, An explicit video is displayed.

  In addition, the mode of the variable display of the symbol in the symbol display device 31 is not limited to the above, and is arbitrary. The number of symbol columns, the direction of the symbol variable display in the symbol column, the number of symbols in each symbol column, etc. Can be appropriately changed. The designs that are variably displayed on the symbol display device 31 are not limited to the above-described symbols, and for example, only numbers may be variably displayed as the symbols.

<About various counters and reserved ball storage area>
Next, the operation of the pachinko machine 10 configured as described above will be described.

  The MPU 62 uses lots of counter information during the game to perform jackpot occurrence lottery, display setting of the main display unit 33, setting of symbol display of the symbol display device 31, setting of display of the accessory display unit 34, and the like. Specifically, as shown in FIG. 6, a jackpot random number counter C1 used for lottery generation for jackpots, a jackpot type counter C2 used for determining jackpot types such as a probable jackpot result and a normal jackpot result, In the reach random number counter C3 used for the reach generation lottery when the symbol display device 31 moves out and fluctuates, the random number initial value counter CINI used for setting the initial value of the big hit random number counter C1, the main display unit 33 and the symbol display device 31 The variation type counter CS that determines the variation display time is used. Furthermore, the electric accessory release counter C4 used for the lottery to determine whether or not the electric accessory 24a of the lower working port 24 is in the electric utility open state is used.

  Each of the counters C1 to C3, CINI, CS, and C4 is a loop counter that adds 1 to the previous value every time it is updated and returns to 0 after reaching the maximum value. Each counter is updated at short time intervals, and the updated value is appropriately stored in a lottery counter buffer 64 a set in a predetermined area of the RAM 64. Among these, in the lottery counter buffer 64a, the information corresponding to the big hit random number counter C1, the big hit type counter C2 and the reach random number counter C3 is obtained information storage when a winning to the upper working port 23 or the lower working port 24 occurs. It is stored in the reserved ball storage area 64b as a means.

  The holding ball storage area 64b includes a holding area RE and an execution area AE. The holding area RE includes a first holding area RE1, a second holding area RE2, a third holding area RE3, and a fourth holding area RE4, and matches the winning history to the upper operating port 23 or the lower operating port 24. The numerical information of the jackpot random number counter C1, the jackpot type counter C2 and the reach random number counter C3 stored in the lottery counter buffer 64a is stored in one of the holding areas RE1 to RE4 as holding information.

  In this case, in the first reservation area RE1 to the fourth reservation area RE4, when the winning to the upper operation port 23 or the lower operation port 24 is continuously generated a plurality of times, the first reservation area RE1 → the second reservation area. Each numerical information is stored in time series in the order of RE2 → third reserved area RE3 → fourth reserved area RE4. By providing the four holding areas RE1 to RE4 as described above, up to four game balls winning histories to the upper operating port 23 or the lower operating port 24 are stored on hold. In addition, the holding area RE includes a holding number storage area NA, in order to specify the number in which the winning history to the upper operating port 23 or the lower operating port 24 is stored in the holding number storage area NA. Is stored.

  Note that the number that can be reserved and stored is not limited to four, but may be any other number such as two, three, or five or more.

  The execution area AE is an area for moving each value stored in the first holding area RE1 of the holding area RE when starting the variable display on the main display unit 33, and at the start of one game round. Based on various numerical information stored in the execution area AE, determination of whether or not is made is performed.

  Each of the counters will be described in detail.

  The jackpot random number counter C1 is configured such that one by one is added in order within a range of 0 to 599, for example, and after reaching the maximum value, returns to 0. In particular, when the jackpot random number counter C1 makes one round, the value of the random number initial value counter CINI at that time is read as the initial value of the jackpot random number counter C1. The random number initial value counter CINI is a loop counter similar to the jackpot random number counter C1 (value = 0 to 599). The big hit random number counter C <b> 1 is periodically updated and stored in the reserved ball storage area of the RAM 64 at the timing when the game ball wins the upper operation port 23 or the lower operation port 24.

  The value of the random number for winning the jackpot is stored as a success / failure table (award / failure information group) in a success / failure table storage area as a success / failure information group storage means in the ROM 63. As the success / failure table, a success / failure table for the low probability mode (low probability success / failure information group) and a high probability mode's success / failure table (high probability success / failure information group) are set. That is, in the present pachinko machine 10, a low probability mode (low probability state) and a high probability mode (high probability state) are set as the lottery mode in the winning lottery means.

  In the gaming state in which the winning / failing table for the low probability mode is referred to at the time of the lottery, the number of random numbers that win the jackpot is two. On the other hand, in the gaming state in which the winning / failing table for the high probability mode is referred to at the time of the lottery, the number of random numbers that will win the jackpot is 20. If the winning probability in the high probability mode is higher than that in the low probability mode, the number of random numbers to be won is arbitrary.

  The jackpot type counter C2 is configured so that 1 is added in order within a range of 0 to 29, and after reaching the maximum value, it returns to 0. The big hit type counter C <b> 2 is periodically updated and stored in the reserved ball storage area of the RAM 64 at the timing when the game ball wins the upper operation port 23 or the lower operation port 24.

  In the pachinko machine 10, a plurality of jackpot results are set. These multiple jackpot results are: (1) the mode of opening / closing control of the variable winning device 22 in the opening / closing execution mode, (2) the lottery mode in the winning lottery means after the opening / closing execution mode ends, and (3) the bottom after the opening / closing execution mode ends. A plurality of jackpot results are set by providing a difference in the three conditions of the support mode in the electric accessory 24a of the operating port 24.

  As an aspect of the opening / closing control of the variable winning device 22 in the opening / closing execution mode, the variable winning device 22 can be controlled so that the frequency of occurrence of winnings in the variable winning device 22 is relatively high from the start to the end of the opening / closing execution mode. A frequency winning mode and a low frequency winning mode are set. Specifically, in the high-frequency winning mode, the opening / closing of the special winning opening 22a is performed 15 times (number of times for high frequency) from the start to the end of the opening / closing execution mode, and one opening is 30 sec (high frequency time). Or until the number of winning prizes in the special winning opening 22a reaches 10 (high frequency). On the other hand, in the low-frequency winning mode, the opening / closing of the large winning opening 22a is performed twice (number of times for low frequency) from the start to the end of the opening / closing execution mode, and one opening is 0.2 sec (low frequency time). The process is continued until the time has elapsed or the number of winning prizes in the special winning opening 22a reaches 6 (the number of low frequency).

  In the present pachinko machine 10, in a situation where the launch handle 51 is operated by the player, the game ball launching mechanism 81 is driven and controlled so that one game ball is launched toward the game area in 0.6 sec. . On the other hand, in the low frequency winning mode, as described above, the opening time of one large winning opening 22a is 0.2 sec. That is, in the low-frequency winning mode, the opening time of the one big winning opening 22a is shorter than the game ball firing cycle. Therefore, in the opening / closing execution mode according to the low frequency winning mode, the winning of the game ball does not substantially occur.

  Note that the number of opening / closing of the large winning opening 22a in the high-frequency winning mode and the low-frequency winning mode, the opening limit time (or opening limit period) for one opening, and the opening limit number for one opening are the same as those in the high-frequency winning mode. If the occurrence frequency of winning in the variable winning device 22 is higher than that in the low frequency winning mode until the opening / closing execution mode is started and ended, the value is not limited to the above value. Is optional. Specifically, if the high frequency winning mode has a larger number of opening and closing times than the low frequency winning mode, the opening limit time for one opening is longer, or if the opening limit number for one opening is set to be larger. Good.

  However, in order to clarify the difference in privilege between the high-frequency winning mode and the low-frequency winning mode, in the opening / closing execution mode according to the low-frequency winning mode, the winning to the variable winning device 22 does not substantially occur. It may be configured. For example, in the high-frequency winning mode, the product of the launch period of the game ball and the open limit number is set shorter than the open limit time for one release, while in the low-frequency winning mode, It is good also as a structure which sets the product of the launching period of a game ball and the open limit number longer than open limit time. In addition, even if the launch interval of the game balls and the opening time of one large winning opening 22a are not the above, in the low frequency winning mode, by setting the latter to be shorter than the former, It is possible to easily realize a configuration in which a winning to the variable winning device 22 does not occur substantially.

  As a support mode for the electric combination 24a of the lower working port 24, the electric combination 24a of the lower working port 24 is compared when the game ball is continuously being fired in the same manner with respect to the game area. Low frequency support mode (low frequency support state or low frequency guide state) and high frequency support mode (high frequency support state or high frequency guide state) so that the frequency of the open state per unit time is relatively high or low. And are set.

  Specifically, in the low-frequency support mode and the high-frequency support mode, the probability of winning the power combination open state in the electric combination release lottery using the electric combination release counter C4 is the same (for example, both 4/5) However, in the high frequency support mode, the number of times that the electric utility item 24a is opened is set more frequently than in the low frequency support mode. The time is set longer. In this case, in the high-frequency support mode, when the electrified open state is selected and the open state of the electric accessory 24a occurs a plurality of times, the closed state from the end of one open state until the next open state is started The time is set shorter than one opening time. Furthermore, in the high frequency support mode, a shorter time is secured as a minimum secured time after the next electric character opening lottery is performed after the electric character object opening lottery is performed than in the low frequency support mode. Is set to be selected.

  As described above, in the high frequency support mode, there is a higher probability of winning a prize to the lower working port 24 than in the low frequency support mode. In other words, in the low frequency support mode, there is a higher probability that a prize will be generated in the upper operating port 23 than in the lower operating port 24, but in the high frequency support mode, the lower operating port 24 is connected to the lower operating port 24. The probability of winning a prize increases. When a prize is awarded to the lower operating port 24, a predetermined number of game balls are paid out. Therefore, in the high frequency support mode, the player plays a game while not reducing the number of possessed balls so much. be able to.

  The configuration for increasing the frequency at which the high frequency support mode is set to the power release state per unit time as compared with the low frequency support mode is not limited to the above-described configuration, for example, the electric component release lottery It is good also as a structure which makes high the probability that it will be elected in the electric character open state in. In addition, a secured time (for example, on the display part 34 based on a winning to the through gate 25) secured after the next electrification opening lottery is performed after the first electrification opening lottery is performed. In the configuration in which multiple types of variable display time) are prepared, the short support time is more easily selected in the high frequency support mode or the average secure time is shorter than in the low frequency support mode. May be. Further, the number of times of opening is increased, the opening time is lengthened, and the secured time that is secured when the next electric winning combination opening lottery is performed after the first electric winning combination releasing lottery is shortened (that is, , Shorten the time for one fluctuation display in the accessory display unit 34), shorten the average time of the secured time and increase the winning probability, or apply any one condition or any combination of conditions By doing so, the advantage of the high frequency support mode over the low frequency support mode may be increased.

  The game result distribution destination for the jackpot type counter C2 (that is, the lottery result by the lottery determination and the distribution lottery) is assigned to a distribution table (distribution information group) in the distribution table storage area as the distribution information group storage means in the ROM 63. ). As such distribution destinations, a normal jackpot result (low-probability-compatible special game result), an explicit 2R probability-variable jackpot result (an explicit high-probability-matched game result or a result that suddenly changes into a probability state), and a 15R probability-variable jackpot result (high probability Corresponding special game result) is set.

  The normal jackpot result is a jackpot result in which the opening / closing execution mode becomes the high-frequency winning mode, and after the opening / closing execution mode ends, the winning / not-lotting mode becomes the low probability mode and the support mode becomes the high-frequency support mode. However, the high-frequency support mode shifts to the low-frequency support mode when the number of games reaches the end reference number (specifically, 100 times) after the shift. In other words, the normal jackpot result is a jackpot result for shifting the gaming state to the normal jackpot state (special gaming state corresponding to low probability).

  The explicit 2R probability variation jackpot result is a jackpot result in which the open / close execution mode becomes the low-frequency winning mode, and after the open / close execution mode ends, the success / failure lottery mode becomes the high probability mode and the support mode becomes the high-frequency support mode. . These high-probability mode and high-frequency support mode are continued until the lottery result in the success / failure lottery becomes a big hit state win and shifts to the big win state by that. In other words, the explicit 2R probability variation jackpot result is a jackpot result for shifting the gaming state to the explicit 2R probability variation jackpot state (explicit high probability corresponding gaming state).

  The 15R probability variation jackpot result is a jackpot result in which the opening / closing execution mode becomes the high-frequency winning mode, and after the opening / closing execution mode ends, the success / failure lottery mode becomes the high probability mode and the support mode becomes the high-frequency support mode. These high-probability mode and high-frequency support mode are continued until the lottery result in the success / failure lottery becomes a big hit state win and shifts to the big win state by that. In other words, the 15R probability variation jackpot result is a jackpot result in which the gaming state is shifted to the 15R probability variation jackpot state (a special gaming state corresponding to high probability).

  Note that the normal gaming state in relation to the above gaming states refers to a state in which the winning / losing lottery mode is the low probability mode and the support mode is the low frequency support mode.

  In the distribution table, among the values of the jackpot type counter C2 of “0 to 29”, “0 to 9” corresponds to the normal jackpot result, and “10 to 14” corresponds to the explicit 2R probability variable jackpot result. “15 to 29” corresponds to the 15R probability variation jackpot result.

  As described above, since the explicit 2R probability variation jackpot result is set as the probability variation jackpot result, the modes of the probability variation jackpot result are diversified. That is, when two types of probability variation jackpot results are compared, the advantage for the player is that the 15R probability variation jackpot result, which is the high-frequency winning mode in the opening / closing execution mode and the high-frequency support mode in the support mode, is the highest. Although the mode is the low-frequency winning mode, the support mode has the lowest explicit 2R probability variation jackpot result that is the high-frequency support mode. Thereby, monotonization of a game is suppressed and it becomes possible to raise the attention degree to a game.

  As a kind of probability variation jackpot result, the open / close execution mode becomes the low-frequency winning mode, and after the open / close execution mode ends, the winning / failing lottery mode becomes the high probability mode, and the support mode is maintained in the previous mode. An explicit 2R probability change jackpot result (an explicit high probability corresponding game result or a result of a latent probability change state) may be included. In this case, further diversification of the probabilistic jackpot results is achieved.

  Furthermore, as a kind of losing result in the winning / losing lottery, there may be included a special losing result that shifts to the opening / closing execution mode of the low-frequency winning mode and that does not shift to the winning / losing lottery mode and the support mode after the completion. . In the configuration in which both the above-described non-explicit 2R probability variation jackpot result and the special outlier result are set, the switching execution mode shifts to the low-frequency winning mode, and the support mode is maintained in the previous mode. However, if one of the results of non-explicit 2R probability change jackpot or special outage occurs in the normal gaming state, for example, it will be It is possible to cause the player to predict which result actually corresponds to.

  For example, the reach random number counter C3 is incremented one by one within a range of 0 to 238, for example, and reaches a maximum value and then returns to 0. The reach random number counter C3 is periodically updated, and stored in the reserved ball storage area of the RAM 64 at the timing when the game ball wins the upper working port 23 or the lower working port 24.

  Here, in this pachinko machine 10, an expected effect is set as a kind of display effect in the symbol display device 31. Expected effects include a symbol display device 31 that can perform variable display (or variable display) of symbols (patterns), and variable display in game times where the open / close execution mode of the variable winning device 22 is the high-frequency winning mode. In the gaming machine in which the subsequent stop display result is a special display result, the stage before the stop display result is derived and displayed after the variable display (or variable display) of the symbol (picture) on the symbol display device 31 is started, This means a display state for making the player think that a variable display state is likely to result in a special display result.

  In the expected effect, two types are set: the reach display and a notice display for expecting the occurrence of reach display or the generation of a special display result at a stage before the reach display occurs.

  In the reach display, a combination of jackpot symbols corresponding to the occurrence of the high-frequency winning mode is obtained by stopping and displaying symbols for some of the symbol sequences displayed on the display screen of the symbol display device 31. A display state is displayed in which combinations of reach symbols that may be established are displayed, and in that state, symbols in the remaining symbol rows are displayed in a variable manner. In addition, in the state where the combination of reach symbols is displayed as described above, the variation of the symbols is displayed in the remaining symbol rows, and a predetermined character or the like is displayed as a moving image on the background screen. In addition, there are those that perform a reach effect by displaying a predetermined character or the like as a moving image on substantially the entire display screen after reducing or not displaying a combination of reach symbols.

  More specifically, the reach display related to the symbol variation display is performed in advance of the high-frequency winning mode on the preset effective line in the display screen of the symbol display device 31 as a stage before the symbol variation display is terminated. A reach line is formed by stopping and displaying a reach symbol combination for which a corresponding jackpot symbol combination may be established, and in the situation where the reach line is formed, a symbol variation display is displayed by the final stop symbol sequence. Is to do.

  The display contents of FIG. 5 will be described in detail. In the state where the symbol variation display is first ended in the upper symbol row Z1, and the symbol variation display is further terminated in the lower symbol row Z3, any effective A reach line is formed by stopping and displaying the main symbols having the same numbers on the lines L1 to L5, and in the situation where the reach line is formed, the symbol variation display is performed in the middle symbol row Z2. Reach display. When the high-frequency winning mode occurs, the main symbol with the same number as the main symbol forming the reach line is stopped and displayed on the reach line in the middle symbol row Z2. The symbol variation display is terminated.

  In the notice display, the symbol display on the display screen of the symbol display device 31 is started in a situation where the symbols are variably displayed in all the symbol columns Z1 to Z3 after the symbol variation display is started, or in some symbol columns. In a situation where the symbols are variably displayed in a plurality of symbol rows, a mode in which a character is displayed separately from the symbols on the symbol rows Z1 to Z3 is included. Moreover, what makes a background screen the predetermined aspect different from the aspect until then, and what makes the symbol on the symbol row | line | column Z1-Z3 the predetermined aspect different from the previous aspect are also contained. Such a notice display can occur in any game times when reach display is performed and when reach display is not performed, but the case where reach display is performed is higher than the case where reach display is not performed. It is set to occur with probability.

  The reach display is executed regardless of the value of the reach random number counter C3 in the game times that shift to the opening / closing execution mode. In the game times that do not shift to the opening / closing execution mode, the reach random number counter C3 acquired at a predetermined timing is referred to the reach table stored in the reach table storage area of the ROM 63 in response to the occurrence of the reach display. It is executed when On the other hand, the determination as to whether or not to perform the notice display is performed not by the main control device 60 but by the display control device 100. This will be described in detail later.

  The variation type counter CS is, for example, incremented by 1 within a range of 0 to 198, and returns to 0 after reaching the maximum value. The variation type counter CS is used when the MPU 62 determines the variation display time on the main display unit 33 and the symbol variation display time on the symbol display device 31. The variation type counter CS is updated once every time a normal process to be described later is executed once, and is repeatedly updated even within the remaining time in the normal process. Then, the buffer value of the variation type counter CS is acquired at the time of determining the variation pattern at the start of variation display in the main display unit 33 and at the time of symbol variation start by the symbol display device 31.

  The electric accessory release counter C4 is, for example, configured to increment one by one within a range of 0 to 250 and return to 0 after reaching the maximum value. The electric accessory release counter C4 is periodically updated and stored in the electric utility reservation area of the RAM 64 at the timing when a game ball wins the through gate 25. Then, at a predetermined timing, a lottery is performed as to whether or not to control the electric accessory 24a to the open state based on the stored value of the electric accessory release counter C4.

  As described above, in the MPU 62, at least the buffer value of the variation type counter CS is used to determine the variation display time in the main display unit 33. In this determination, the variation display time table storage area of the ROM 63 is used. .

<Various processes executed by main controller 60>
Next, each control process by the MPU 62 in the main controller 60 will be described with reference to the flowcharts of FIGS. The processing of the MPU 62 is roughly divided into main processing that is started when the power is turned on, timer interrupt processing that is started periodically (in this embodiment, at a cycle of 2 msec), and a power failure signal to the NMI terminal (non-maskable terminal). For convenience of explanation, the NMI interrupt process and the timer interrupt process will be described first, and then the main process will be described.

  FIG. 7 is a flowchart showing the NMI interruption process, which is executed when the power of the pachinko machine 10 is shut down due to the occurrence of a power failure or the like. That is, when the power of the pachinko machine 10 is cut off due to the occurrence of a power failure or the like, a power failure signal is output from the power failure monitoring board 65 to the NMI terminal of the MPU 62, and the MPU 62 interrupts the control being executed and starts NMI interrupt processing. . In the NMI interrupt processing, the power failure flag (power failure information) is stored in the power failure flag storage area (power failure information storage means) provided in the RAM 64 in step S101, and this processing is terminated. Thereafter, when it is confirmed that the power failure flag is stored in the normal processing described later, the power failure processing is executed.

<Timer interrupt processing>
First, timer interrupt processing will be described with reference to the flowchart of FIG. This process is started periodically by the MPU 62 (for example, at a cycle of 2 msec).

  In step S201, various detection sensor reading processes are executed. The reading process includes a process of reading the states of the various winning detection sensors 67a to 67c and determining the states of the various winning detection sensors 67a to 67c and storing the winning detection information.

  After executing the reading process in step S201, the process proceeds to step S202. In step S202, the random number initial value counter CINI is updated. Specifically, the random number initial value counter CINI is incremented by 1 and cleared to 0 when the counter value reaches the maximum value. Then, the update value of the random number initial value counter CINI is stored in the corresponding buffer area of the RAM 64.

  In the subsequent step S203, the big hit random number counter C1, the big hit type counter C2, the reach random number counter C3, and the electric accessory release counter C4 are updated. Specifically, the jackpot random number counter C1, the jackpot type counter C2, the reach random number counter C3, and the electric accessory release counter C4 are each incremented by 1 and cleared to 0 when the counter values reach the maximum value. Then, the updated values of the counters C1 to C4 are stored in the corresponding buffer area of the RAM 64.

  In a succeeding step S204, a winning process for a through accompanying a winning to the through gate 25 is executed. In the through winning process, if a winning to the through gate 25 has occurred, the number of stored item holdings stored in the electronic combination holding area is less than the upper limit number (for example, “4”). As a condition, the value of the electric accessory release counter C4 updated in step S203 is stored in the electric utility reservation area. Moreover, the process for making the 2nd reservation lamp | ramp part 36 of the variable display unit 26 corresponding to the number of articles | goods reservation memory | storage corresponding to the audio lamp control apparatus 90 is performed.

  In a succeeding step S205, a winning process for the operating port accompanying the winning to the upper operating port 23 or the lower operating port 24 is executed. In the winning process for the operating opening, when a winning to the upper operating opening 23 or the lower operating opening 24 has occurred, the start holding storage number stored in the holding ball storage area is the upper limit number (for example, “4 )), The values of the jackpot random number counter C1, the jackpot type counter C2 and the reach random number counter C3 updated in step S203 are stored in the holding area RE of the holding ball storage area. In this case, the data is stored in the first reserved area among the empty reserved areas RE1 to RE4 of the reserved area RE, that is, the reserved area corresponding to the current start reserved memory number. Further, a process for lighting the first hold lamp unit 35 of the variable display unit 26 corresponding to the start hold storage number is executed for the voice lamp control device 90. After executing the process of step S105, the timer interrupt process is terminated.

<Normal processing>
Next, the flow of normal processing will be described with reference to the flowchart of FIG. The normal process is a process that is started after the main process that is started when the power is turned on, and the main process of the game is executed in the normal process. As an outline, the processing of steps S301 to S307 is executed as a periodic processing with a period of 4 msec, and the counter update processing of steps S309 and S310 is executed with the remaining time.

  In the normal process, in step S301, output data such as a command set in the timer interrupt process or the previous normal process is transmitted to each control device on the sub side. Specifically, the presence or absence of a prize ball command is determined, and if a prize ball command is set, it is transmitted to the payout control device 70. Further, when a production command such as a variation command, a type command, a variation end command, or the like is set, the command is transmitted to the sound lamp control device 90.

  In the subsequent step S302, the variation type counter CS is updated. Specifically, the variation type counter CS is incremented by 1, and the counter value is cleared to 0 when the counter value reaches the maximum value. Then, the update value of the variation type counter CS is stored in the corresponding buffer area of the RAM 64.

  In subsequent step S303, a game number control process for controlling a game in each game time is executed. In this game times control process, jackpot determination, symbol variable display setting by the symbol display device 31, display control of the main display unit 33, and the like are performed. Details of the game times control process will be described later.

  Thereafter, in step S304, a game state transition process for shifting the game state is executed. Although details will be described later, the gaming state shifts to an opening / closing execution mode, a high probability mode, a high frequency support mode, and the like by this gaming state transition processing.

  In a succeeding step S305, an electric combination support process for driving and controlling the electric combination 24a provided in the lower working port 24 is executed. In this electronic combination support process, the information stored in the electronic combination holding area 64c of the RAM 64 is used to determine whether or not to open the electric combination 24a, to open / close the electric combination 24a, and for the combination Display control of the display unit 34 is performed.

  Thereafter, in step S306, a game ball launch control process is executed. In the game ball launch control process, the solenoid of the game ball launch mechanism 81 is excited once every predetermined period (for example, 0.6 sec) on condition that a launch permission signal is input from the power source and launch control device 80. . Thereby, the game ball is launched toward the game area.

  In a succeeding step S307, it is determined whether or not a power failure flag is stored in the RAM 64. The power failure flag is a flag that is stored when the occurrence of a power failure is confirmed in the power failure monitoring board 65 and a power failure signal is input from the power failure monitoring board 65 to the NMI terminal of the MPU 62 and is erased in the next main processing.

  When the power failure flag is not stored, the last process of the plurality of processes that are repeatedly executed is completed, so whether or not the execution timing of the next normal process is reached in step S308, that is, the previous normal process It is determined whether a predetermined time (4 msec in this embodiment) has elapsed since the start of the process. Then, the random number initial value counter CINI and the variation type counter CS are repeatedly updated within the remaining time until the next normal processing execution timing.

  That is, in step S309, the random number initial value counter CINI is updated. Specifically, the random number initial value counter CINI is incremented by 1 and cleared to 0 when the counter value reaches the maximum value. Then, the update value of the random number initial value counter CINI is stored in the corresponding area of the RAM 64. In step S310, the variation type counter CS is updated. Specifically, the variation type counter CS is incremented by 1 and cleared to 0 when the counter values reach the maximum value. Then, the update value of the variation type counter CS is stored in the corresponding area of the RAM 64.

  On the other hand, if it is determined in step S307 that the power failure flag is stored, the power interruption has occurred, so the power interruption processing from step S311 is executed. That is, in step S311, the generation of the timer interrupt process is prohibited, and then the RAM judgment value is calculated and stored in step S312, and after the access to the RAM 64 is prohibited in step S313, the power supply is completely shut off and the process is performed. Continue infinite loop until no longer runs.

<Game times control processing>
Next, the game times control process of step S303 will be described.

  In the game times control process, first, it is determined whether or not the opening / closing execution mode is in effect. Specifically, it is determined whether or not the opening / closing execution mode flag is stored in the opening / closing execution mode flag storage area in the various flag storage areas of the RAM 64. The opening / closing execution mode flag is stored when the gaming state is shifted to the opening / closing execution mode in the gaming state transition process described later, and is erased when the opening / closing execution mode is ended in the gaming state transition process.

  If it is in the opening / closing execution mode, the game turn control process is terminated without executing any of the game turn start process and the game turn progress process. In other words, in the open / close execution mode, the game times are not started regardless of whether or not a winning for the operation ports 23 and 24 has occurred.

  If it is not in the opening / closing execution mode, it is determined whether or not the main display section is in a variable display. This determination is performed by determining whether or not the variable display flag is stored in the variable display flag storage area in the various flag storage areas of the RAM 64. The variable display in-progress flag is stored when the main display unit 33 starts variable display, and is deleted when the variable display ends.

  If the main display unit 33 is not in a variable display, the process proceeds to a game turn starting process. In the game turn starting process, first, the number-of-holds storage area N, which is the number of pieces of on-hold information stored, is determined by referring to the number-of-holds storage area NA in the storage area for storing balls. The case where the start hold storage number N is “0” means that the hold information is not stored in the hold ball storage area 64b. Accordingly, the game turn control process is terminated as it is. If the start pending storage number N is not “0”, the data setting process is executed.

  In the data setting process, first, the start pending storage number N is decremented by one. Further, the data stored in the first holding area RE1 of the holding area RE in the holding ball storage area is moved to the execution area AE. Thereafter, a process of shifting the data stored in the holding areas RE1 to RE4 of the holding area RE is executed. This data shift process is a process of sequentially shifting the data stored in the first reservation area RE1 to the fourth reservation area RE4 to the lower area side, and clears the data in the first reservation area RE1 and the second The data in each area is shifted such as the reserved area RE2 → the first reserved area RE1, the third reserved area RE3 → the second reserved area RE2, and the fourth reserved area RE4 → the third reserved area RE3.

  In the data setting process, a process for causing the voice lamp control device 90 to recognize that the hold information has been shifted and changing the display on the first hold lamp unit 35 in accordance with the decrease in the number of hold is executed. To do.

  After executing the data setting process, the game start control process is terminated after the change start process is executed. Here, the fluctuation start process will be described.

  First, the validity determination process is executed. In the winner determination process, it is determined whether or not the winner lottery mode is a high probability mode. In the case of the high probability mode, referring to the high probability mode success / failure table among the tables stored in the success / failure table storage area, the information for determining the success / failure among the information stored in the execution area AE, that is, the jackpot It is determined whether or not the value applied to the random number counter C1 matches the jackpot value information for high probability. In the case of the low probability mode, the value of the jackpot random number counter C1 stored in the execution area AE is referred to the low probability mode success / failure table among the tables stored in the success / failure table storage area. It is determined whether or not it matches the jackpot numerical information for low probability.

  Subsequently, it is determined whether or not the result of the determination process is a jackpot winning result. If it is a big win result, the type determination process is executed.

  In the type determination process, the information for type determination among the information stored in the execution area AE, that is, the information related to the big hit type counter C2 is grasped. Then, with reference to the sorting table stored in the sorting table storage area, it is specified to which jackpot type the information relating to the grasped jackpot type counter C2 corresponds.

  Subsequently, it is determined whether or not the jackpot type specified in the type determination process corresponds to the probability variation jackpot result. If it corresponds to the probability variation jackpot result, it is determined whether the jackpot type corresponds to the 15R probability variation jackpot result.

  If it is a 15R probability variation jackpot result, a stop result setting process for 15R probability variation jackpot is executed, and if it is a probability variation jackpot result but not a 15R probability variation jackpot result, a stop result setting process for explicit 2R probability variation jackpot is performed. To do. If it is not a probabilistic jackpot result, a stop result setting process for normal jackpot is executed. Furthermore, when it is determined that the result of the success / failure determination process is not the jackpot winning result, a stop result setting process for losing is executed.

  In the stop result setting process, information on the pattern mode to be finally stopped and displayed on the main display unit 33 is specified from information stored in advance in the ROM 63, and the specified information is stored in the RAM 64. In the stop result setting process, the MPU 62 stores information for specifying in the RAM 64 that the current game times determination result is a 15R probability variation jackpot result, an explicit 2R probability variation jackpot result, or a normal jackpot result. Specifically, the 15R probability variation jackpot stop result setting process stores a 15R probability variation flag, the explicit 2R probability variation jackpot stop result setting process stores an explicit 2R probability variation flag, and the normal jackpot stop result setting process. Usually stores the jackpot flag.

  After executing the stop result setting process, the variable display time setting process is executed.

  In this process, the value of the variation type counter CS stored in the variation type counter buffer in the lottery counter buffer 64a of the RAM 64 is acquired. Further, it is determined whether or not a reach display is generated in the symbol display device 31 in the current game round. Specifically, it is determined whether any of the 15R probability variation flag, the explicit 2R probability variation flag, or the normal jackpot flag is stored in the RAM 64. If any flag is stored, it is determined that reach display occurs. Even if none of the above flags is stored, if the value applied to the reach random number counter C3 stored in the execution area AE is a value corresponding to the occurrence of reach, the reach display is performed. Determine that it occurs.

  When it is determined that the reach display is generated, the fluctuation display time table corresponding to the value of the current fluctuation type counter CS is referred to the reach generation fluctuation display time table stored in the fluctuation display time table storage area of the ROM 63. Information is acquired, and the variable display time information is set in a variable display time counter (variable display time measuring means) provided in various counter areas of the RAM 64. On the other hand, when it is determined that the reach display does not occur, the fluctuation corresponding to the value of the current fluctuation type counter CS is referred to by referring to the fluctuation non-occurrence fluctuation display time table stored in the fluctuation display time table storage area. The display time is acquired, and the variable display time information is set in the variable display time counter.

  Note that the variable display time information when no reach occurs is set so that the variable display time is shortened as the number of the start pending storage numbers N increases. Also, in the situation where the support mode is the high frequency support mode, the non-reach time is selected so that the shorter variable display time is selected compared to the situation where the number of pending information is the same as in the situation where the low frequency support mode. The generation variation display time table is set. However, the present invention is not limited to this, and the configuration may be such that the variable display time does not fluctuate according to the start pending storage number N and the support mode, and the above relationship may be reversed. Furthermore, the above configuration may be applied to the variable display time when reach occurs. In addition, in the case of 15R probability variable jackpot results, explicit 2R probability variable jackpot results, normal jackpot results, out-of-reach and complete out-of-shift cases, separate variable display time tables are set. Also good. In this case, the variable display time is allocated according to each game result.

  After executing the process for setting the change display time, the change command and the type command are set. The change command includes information on presence / absence of reach and information on change display time. The type command includes game result information. That is, the type command includes 15R probability variation jackpot result information, explicit 2R probability variation jackpot result information, normal jackpot result information, outage result information, and the like as game result information.

  The set change command and type command are transmitted to the sound lamp control device 90 in step S301 in the normal process (FIG. 9). The sound lamp control device 90 determines the light emission pattern of the display lamp unit 54 and the sound output pattern from the speaker unit 55 in the game time based on the received variation command and type command, and the contents of the determined effect The display lamp unit 54 and the speaker unit 55 are controlled so as to be executed. The audio lamp control device 90 transmits the change command and the type command to the display control device 100 while maintaining the information form. The display control device 100 determines a variation display pattern in the symbol display device 31 in the game time based on the received variation command and type command, and the symbol display device 31 is executed so that the variation display pattern is executed. Control display. Specific contents of the display control will be described later.

  After executing the setting process of the change command and the type command, the main display unit 33 starts to display the change display of the pattern. Then, this variation start process is terminated.

  Returning to the description of the game times control process, when the main display unit 33 is in a variable display, the process for advancing game times is executed.

  In the game time progression process, first, it is determined whether or not the current game time variation display time has elapsed. Specifically, it is determined whether or not the value of the variable display time information stored in the variable display time counter of the RAM 64 has become “0”. The value of the variable display time information is set in the variable display time setting process as described above. The value of the set variable display time information is decremented by 1 each time the timer interrupt process (FIG. 8) is started.

  If the variable display time has not elapsed, the variable display process is executed. In the variable display process, the display mode on the main display unit 33 is changed. Then, this game times control process is complete | finished.

  If the change display time has elapsed, change end processing is executed. In the variation end process, the information stored in the RAM 64 in any one of the stop result setting processes is specified, and the main display unit 33 is displayed so that the pattern form corresponding to the information is displayed on the main display unit 33. Control display.

  Subsequently, a change end command is set. The set change end command is transmitted to the sound lamp control device 90 in step S301 in the normal process (FIG. 9). The sound lamp control device 90 transmits the received change end command to the display control device 100 while maintaining the information form. In the display control device 100, by receiving the change end command, the combination of the final stop symbols in the game round is confirmed and displayed (final stop display). Then, this game times control process is complete | finished.

<Game state transition processing>
Next, the game state transition process in step S304 will be described.

  First, it is determined whether or not the opening / closing execution mode is in effect. When it is not in the opening / closing execution mode, it is determined whether or not it is the timing when the display of the variation of the pattern on the main display unit 33 of one game time is finished. If it is not the timing when the variable display is finished, the gaming state transition process is finished as it is.

  When it is the timing when the variable display is finished, it is determined whether or not the game result of the current game time corresponds to the transition to the opening / closing execution mode. Specifically, it is determined whether any of the 15R probability variation flag, the explicit 2R probability variation flag, or the normal jackpot flag is stored in the RAM 64. If none of the above flags is stored, the gaming state transition process is terminated as it is.

  When any of the above flags is stored, the start processing of the opening / closing execution mode is executed. In the start process, an opening waiting time (starting waiting period) is set for waiting without opening the large winning opening 22a of the variable winning device 22 for opening in the opening / closing execution mode. Specifically, opening waiting time information stored in advance in the ROM 63 is set in a waiting time counter area provided in various counter areas of the RAM 64. In this case, the waiting time information that is set differs depending on whether the opening / closing execution mode is the high-frequency winning mode, and the waiting time information indicates that the waiting time information is lower in the low-frequency winning mode than in the high-frequency winning mode. It is set to be shorter. For example, in the high frequency winning mode, the count value of the standby time information is set so that the standby time is 1 sec. In the low frequency winning mode, the count value of the standby time information is set so that the standby time is 0.2 sec. Is set. The value of the waiting time information set here is decremented by 1 every time the timer interrupt process (FIG. 8) is executed.

  Subsequently, it is determined whether or not the current opening / closing execution mode is a high-frequency winning mode. Specifically, it is determined whether either the 15R probability variation flag or the normal jackpot flag is stored in the RAM 64. If it is not the high-frequency winning mode, that is, if it is the low-frequency winning mode, “2” is set in the round counter RC provided in the various counter areas of the RAM 64. The round counter RC is a counter area for counting the number of times the special winning opening 22a is opened. On the other hand, in the case of the high-frequency winning mode, “15” is set in the round counter RC.

  After executing the process of setting RC to 2 or 15, after setting the opening command, the gaming state transition process is terminated. The set opening command is transmitted to the sound lamp control device 90 in step S301 in the normal process (FIG. 9). This opening command includes information indicating whether the high-frequency winning mode or the low-frequency winning mode is set.

  The sound lamp control device 90 determines the light emission pattern of the display lamp unit 54 and the sound output pattern from the speaker unit 55 in the opening / closing execution mode based on the received opening command, and the content of the determined effect is executed. In this manner, the display lamp unit 54 and the speaker unit 55 are controlled. In addition, the sound lamp control device 90 transmits the opening command to the display control device 100 while maintaining the information form. The display control device 100 causes the symbol display device 31 to start an effect corresponding to the opening / closing execution mode based on the received opening command. Specific contents of the display control will be described later.

  On the other hand, if it is in the opening / closing execution mode, it is determined whether or not the opening standby time has elapsed. If the opening standby time has not elapsed, the gaming state transition process is terminated. When the waiting time for the opening has elapsed, the big prize opening / closing process is executed. Here, the special prize opening / closing process will be described.

  First, it is determined whether or not the special winning opening 22a is being opened. Specifically, this determination is performed based on the driving state of the variable prize driving unit 22c. When the big prize opening 22a is not being opened, it is determined whether or not the value of the round counter RC is “0”, and whether or not the value of the timer T provided in the various counter areas 64d of the RAM 64 is “0”. Determine.

  When the value of the round counter RC is “0” or when the value of the timer T is not “0”, the big prize opening / closing process is ended as it is. On the other hand, when the value of the round counter RC is not “0” and the value of the timer T is “0”, the variable prize driving unit 22c is driven to open the big prize opening 22a.

  Subsequently, setting processing for each round is executed. In the setting process for each round, it is first determined whether or not the high-frequency winning mode is set. If the high-frequency winning mode is set, “15000” (that is, 30 sec) is set in the timer T. The count value set here is decremented by 1 every time the timer interrupt process (FIG. 8) is started, that is, every 2 msec. Also, “10” is set in the winning counter area PC provided in the various counter areas 64d of the RAM 64 in order to count the number of winning game balls to the big winning opening 22a. On the other hand, when it is not the high-frequency winning mode, that is, when it is the low-frequency winning mode, “100” (that is, 0.2 sec) is set in the timer T, and “6” is set in the winning counter area PC. .

  Thereafter, an opening command is set, and the main prize winning opening / closing process is terminated. The set release command is transmitted to the sound lamp control device 90 in step S301 in the normal process (FIG. 9). The sound lamp control device 90 changes the effect contents in the display lamp unit 54 and the speaker unit 55 based on the received release command. Further, the sound lamp control device 90 transmits the release command to the display control device 100 while maintaining the information form. The display control device 100 switches the effect for the opening / closing execution mode in the symbol display device 31 based on the received opening command. Specific contents of the display control will be described later.

  On the other hand, when the special winning opening 22a is open, it is determined whether or not the value of the timer T is “0”. When the value of the timer T is not “0”, whether or not a game ball has won the big winning opening 22a is determined based on the detection state of the detection sensor corresponding to the variable winning device 22. If no winning has occurred, the main prize winning opening / closing process is terminated. On the other hand, when a winning has occurred, it is determined whether or not the value of the winning counter area PC is “0” after subtracting 1 from the value of the winning counter area PC. The winning opening and closing process is terminated.

  When the value of the timer T is “0”, or when the value of the winning counter area PC is “0”, it means that the special winning opening closing condition is established. In such a case, the variable winning drive unit 22c is set in a non-driven state to close the special winning opening 22a.

  Subsequently, 1 is subtracted from the value of the round counter RC, and it is determined whether or not the value of the round counter RC is “0”. When the value of the round counter RC is “0”, the main prize winning opening / closing process is finished as it is. When the value of the round counter RC is not “0”, it is determined whether or not the high-frequency winning mode is set.

  When the high-frequency winning mode is set, the timer T is set to “1000” (that is, 2 sec), and when the low-frequency winning mode is set, the timer T is set to “100” (that is, 0.2 sec). That is, in the low frequency winning mode, the time during which the large winning opening 22a is closed between rounds is set shorter than in the high frequency winning mode. Thereafter, a closing command is set and the main prize winning opening / closing process is terminated.

  The set closing command is transmitted to the sound lamp control device 90 in step S301 in the normal process (FIG. 9). Based on the received closing command, the sound lamp control device 90 specifies that the opening of the big winning opening 22a for one round has been completed. Further, the sound lamp control device 90 transmits the close command to the display control device 100 while maintaining the information form. The display control device 100 specifies that the opening of the large winning opening 22a for one round has been completed based on the received closing command, and executes processing corresponding thereto. Specific contents of such processing will be described later.

  Returning to the description of the game state transition process, after executing the big prize opening / closing process, it is determined whether the value of the round counter RC is “0” and whether the waiting time for ending has elapsed. To do. Here, the pachinko machine 10 is configured such that when the opening / closing execution mode ends, an effect for ending is executed by the symbol display device 31 or the like, and the waiting time for ending is the effect for the ending. This is a period for waiting for the start of the next game time in the main control device 60 until the game ends.

  When the value of the round counter RC is not “0” or when the ending waiting time has not elapsed, the gaming state transition process is terminated as it is. On the other hand, when the value of the round counter RC is “0” and the ending waiting time has elapsed, an ending command is set. The ending command is transmitted to the sound lamp control device 90 in step S301 in the normal process (FIG. 9). The sound lamp control device 90 ends the effect for the opening / closing execution mode in the display lamp unit 54 and the speaker unit 55 based on the received ending command. Further, the audio lamp control device 90 transmits the ending command to the display control device 100 while maintaining the information form. The display control device 100 ends the effect for the opening / closing execution mode in the symbol display device 31 based on the received ending command. Specific contents of the display control will be described later.

  Subsequently, a transition process at the end of the opening / closing execution mode is executed. In the transition process, it is determined whether the 15R probability change flag, the explicit 2R probability change flag, or the normal jackpot flag is stored in the RAM 64. When the 15R probability variation flag or the explicit 2R probability variation flag is stored, the success / failure lottery mode is set to the high probability mode, the support mode is set to the high frequency support mode, and the normal jackpot flag is stored. In this case, the success / failure lottery mode is set to the low probability mode and the support mode is set to the high frequency support mode.

  Incidentally, when the normal jackpot flag is stored, “100” as the end reference number is set in the game number counter in the various counter areas 64d of the RAM 64. The game number counter is decremented by 1 every time the above-described variation start process is executed, and when the value of the game number counter becomes “0”, the support mode is set to the high frequency support mode.

  Then, after executing the opening / closing execution mode end processing, the gaming state transition processing is ended. In the open / close execution mode end processing, if any of the explicit 2R probability variation flag, 15R probability variation flag, or normal jackpot flag is stored, it is deleted, and if it is not already stored, the state is maintained. To do.

<Electrical Configuration of Audio Lamp Control Device 90>
Next, the electrical configuration of the sound lamp control device 90 will be described with reference to the block diagram of FIG.

  The sound lamp control device 90 is provided with a sound lamp control board 110. The sound lamp control board 110 is provided with a sub CPU 111, a ROM 112, and a RAM 113.

  The sub CPU 111 has a function as a main control unit in the sound lamp control device 90. The sub CPU 111 is connected to the main control device 60 via the input port 114 provided on the sound lamp control board 110, and various commands transmitted from the main control device 60, specifically, a change command, a type command, A command for controlling game times (game time control information) such as a change end command and a command for jackpot effect (information for jackpot effect) such as an opening command, an ending command, an open command, and a close command are sent to the sub CPU 111 through the input port 114. Entered. The sub CPU 111 is connected to the ROM 112 and the RAM 113 via a bus.

  The ROM 112 is a non-volatile storage unit for storing control information such as various control programs executed by the sub CPU 111 and fixed value data. Specifically, the ROM 112 includes a NOR type flash memory. Part of the fixed value data is stored in advance in each of the areas 112a to 112b of the ROM 112. The details of each of these areas 112a to 112b will be described together with the description of the processing executed by the sub CPU 111.

  The RAM 113 is a control volatile storage unit for temporarily storing work data, flags, and the like used when various programs are executed by the sub CPU 111, and is specifically configured by a DRAM. Work data, flags and the like are stored in the RAM 113.

  When various commands are input from the main control device 60, the sub CPU 111 uses the ROM 112 and the RAM 113 to execute processing corresponding to the input commands. Specifically, the sub CPU 111 is provided with an arithmetic circuit 121 and a register 122 capable of temporarily storing the result of the arithmetic operation by the arithmetic circuit 121. When various commands are input, the sub CPU 111 reads a program corresponding to the command input from the ROM 112 and executes the program in the arithmetic circuit 121. Then, the calculation result by the calculation circuit 121 is written into the register 122 and the RAM 113. Data written in the register 122 and the like is output to the LED substrate 91, the speaker unit 55, and the display control device 100, and the LED substrate 91, the speaker unit 55, and the display control device 100 operate based on the data.

  The sub CPU 111 outputs each command received from the main control device 60 to the display control device 100 while maintaining the information form, and the display control device 100 displays the display screen G on the basis of each command. The symbol display device 31 is controlled so that an image is displayed.

  Specifically, on the output side of the sub CPU 111, the audio lamp control board 110 is provided with output ports 131, 132, 133 corresponding to the LED board 91, the speaker unit 55, and the display control device 100, respectively. In addition, data output circuits 134, 135, and 136 are provided for outputting the data of the register 122 to the output ports 131, 132, and 133, respectively. Each output port 131, 132, 133 is connected to the sub CPU 111 via a corresponding data output circuit 134, 135, 136, respectively. The output ports 131, 132, and 133 are connected to the corresponding LED board 91, the speaker unit 55, and the display control device 100, respectively. The data set in the register 122 is output to the output ports 131, 132, 133 by the data output circuits 134, 135, 136, and the LED board 91, the speaker through the output ports 131, 132, 133. Is output to the unit 55 and the display control apparatus 100.

<Electrical Configuration for Driving Control of Various Light Emitting Elements>
As already described, the pachinko machine 10 is provided with various lamp units, and these lamp units include LEDs 173 (see FIG. 12) as light emitting elements. These LEDs 173 are driven based on data output from the data output circuit 134 to the LED substrate 91 via the output port 131. Therefore, the configuration of the data and the configuration of the data output circuit 134 will be described below with reference to the circuit diagram of FIG.

  As shown in FIG. 11, the data output circuit 134 includes a plurality of buses (three in detail) for connecting the sub CPU 111 and the output port 131. Different data is output to each bus. Specifically, the LED drive data SD, the clock signal SG1, and the data write signal SG2 are output to the output port 131. The output port 131 includes a plurality of terminals, and the LED drive data SD and each signal are configured to be input to corresponding terminals among the plurality of terminals. Hereinafter, the configuration related to the LED drive data SD and each signal will be individually described.

  First, the configuration related to the LED drive data SD will be described. The register 122 is provided with an LED drive register 141 corresponding to the LED drive data SD for determining whether or not the LED emits light. The LED driving register 141 includes a first data register 141a and a second data register 141b as storage areas having a storage capacity of 8 bits, and can store 16-bit information as a whole. Each data register 141a, 141b is connected to a data output circuit 134. The data output circuit 134 is configured to output the LED drive data SD toward the output port 131 based on the information stored in the data registers 141a and 141b.

  Specifically, the data output circuit 134 is provided with an n-type MOSFET 142 as a switching element. The source of the MOSFET 142 is grounded, and the drain is connected to the DATA terminal of the output port 131 while being pulled up to + 5V. A voltage of +5 V is applied between the source and drain. The gate of the MOSFET 142 is connected to the LED driving register 141 and is pulled up to + 3.3V. The + 3.3V is a voltage value larger than the threshold voltage of the MOSFET 142. A voltage (HI signal or LOW signal) corresponding to bit information stored in the LED driving register 141 is applied to the gate of the MOSFET 142.

  Specifically, when “0” information (LOW signal) is stored in a predetermined bit of the LED driving register 141, 0 V is applied to the gate of the MOSFET 142. In this case, the MOSFET 142 is turned off, and + 5V corresponding to the HI signal is input to the DATA terminal.

  On the other hand, when information (HI signal) of “1” is stored in a predetermined bit of the LED driving register 141 or when the information of the predetermined bit is indefinite, + 3.3V is applied to the gate of the MOSFET 142. Entered. In this case, the MOSFET 142 is turned on, and the source and drain are conducted. As a result, 0 V corresponding to the LOW signal is input to the DATA terminal.

  From the above, the data (voltage) output to the DATA terminal differs according to the bit information stored in the LED driving register 141.

  In such a configuration, the LED driving register 141 sequentially outputs each bit information to the DATA terminal in time series by sequentially changing the reference destination of the bit information that determines the input voltage to the gate of the MOSFET 142. It has become. As a result, the LED drive data SD stored in the LED drive register 141 is sequentially output to the DATA terminal of the output port 131.

  Here, in the situation where the LED drive data SD stored in one of the first data register 141a and the second data register 141b is being output, the LED to be output in the future to the other data register Setting of drive data SD is executed. Thus, the transmission period of the LED drive data SD can be shortened by the period required for writing the LED drive data SD to the LED drive register 141.

  Next, the configuration related to the clock signal SG1 will be described. The register 122 is provided with a clock signal register 143 for controlling the clock signal SG1. The clock signal register 143 has a storage capacity of 1 bit, and information “1” and information “0” are alternately input at a predetermined cycle. The clock signal register 143 is connected to the data output circuit 134. The data output circuit 134 outputs a clock signal SG1 having a predetermined cycle to the output port 131 based on the switching of information in the clock signal register 143.

  Specifically, the data output circuit 134 is provided with an n-type MOSFET 144 as a switching element. The MOSFET 144 is connected to the CLK terminal of the output port 131 while the source is grounded and the drain is pulled up to + 5V. The gate of the MOSFET 144 is connected to the clock signal register 143 while being pulled up.

  According to such a configuration, the MOSFET 144 is alternately switched between ON and OFF based on the information written in the clock signal register 143 being alternately switched between “1” and “0” in a predetermined cycle. By switching ON / OFF of the MOSFET 144, the clock signal SG1 having the predetermined cycle is input to the CLK terminal. The clock signal SG1 is used for transmission of LED drive data SD in the LED board 91. Details of the transmission will be described later.

  Next, the configuration related to the data write signal SG2 will be described. The register 122 is provided with a data write signal register 145 corresponding to the data write signal SG2. The data write signal register 145 has a storage capacity of 1 bit. The data write signal register 145 is connected to the data output circuit 134. The data output circuit 134 outputs a signal based on the information written in the data write signal register 145 to the output port 131.

  Specifically, the data output circuit 134 is provided with an n-type MOSFET 146 as a switching element. The MOSFET 146 is connected to the L terminal of the output port 131 while the source is grounded and the drain is pulled up to + 5V. The gate of the MOSFET 146 is connected to the data write signal register 145 while being pulled up.

  According to this configuration, when the information “1” is written in the data write signal register 145 or when the information stored in the data write signal register 145 is indefinite, the gate of the MOSFET 146 is connected to the HI. A voltage corresponding to the signal is input, and the MOSFET 146 is turned on. As a result, 0 V corresponding to the LOW signal is input to the L terminal.

  On the other hand, when “0” information is written in the data write signal register 145, 0V corresponding to the LOW signal is input to the gate of the MOSFET 146, and the MOSFET 146 is turned off. As a result, +5 V corresponding to the HI signal is input to the L terminal. The data write signal SG2 is used when setting LED drive data SD for each LED. Details of the setting will be described later.

  As already described, since the inputs to the gates of the MOSFETs 142, 144, and 146 are pulled up, the MOSFETs 142, 144, and 146 are turned on when the information in the register 122 is indefinite. As a result, a LOW signal is input to each terminal (DATA terminal, CLK terminal, L terminal).

  A + 5V power supply is connected in parallel to the bus connecting the drains of the MOSFETs 142, 144, and 146 and the output port 131. On the bus connecting the bus and the + 5V power supply, the clamp diode 160 is connected. Is provided. The clamp diode 160 is connected with the + 5V power supply side as a cathode. As a result, when the potential on the bus temporarily rises due to noise entering the bus connecting the drain and the output port 131, a current temporarily flows to the + 5V power supply side, and the output A large current is prevented from flowing to the port 131 side.

  Further, a gate resistor 161 for preventing vibration is provided at the gate of each of the MOSFETs 142, 144, and 146. The gate resistor 161 reduces the Q value (stability) of the parasitic resonance circuit due to the parasitic capacitances and parasitic inductances of the MOSFETs 142, 144, and 146, and makes it difficult for parasitic resonance to occur. Thereby, the influence by the said parasitic resonance can be suppressed.

  The output port 131 is provided with a + 5V terminal and a GND terminal. A + 5V power source is connected to the + 5V terminal, and + 5V is applied from the + 5V power source. On the other hand, the GND terminal is grounded.

  Next, a configuration for driving each light emitting element using these various signals will be described with reference to FIG. FIG. 12 is a circuit diagram of various circuits mounted on the LED substrate 91.

  As shown in FIG. 12, the LED board 91 is provided with an input port 171 having a plurality of input terminals, and various signals output from the output port 131 are individually input to the input port 171. The Specifically, the LED drive data SD, the clock signal SG1 and the data write signal SG2 output from the sub CPU 111 of the sound lamp control device 90 via the data output circuit 134 and the output port 131 are respectively the DATA terminal of the input port 171, Input to CLK terminal and L terminal. The input side of the GND terminal of the input port 171 is connected to the output side of the output port 131, and the output side of the GND terminal of the input port 171 is grounded. Various signals are output to the LED drive unit provided on the LED substrate 91 via wiring. The LED driving unit is connected to a plurality of LEDs 173 as a plurality of light emitting elements, and drives the LED 173 based on input of various signals.

  A Schmitt trigger type inverter 180 is provided on each wiring. The inverter 180 has a hysteresis characteristic in which the threshold voltage for HI output and the threshold voltage for LOW output are different. Thereby, it is possible to suppress the influence of noise mixed in various signals, for example, the occurrence of chattering.

  The LED driving unit includes a plurality of ICs for driving LEDs. First, there is a first drive IC 191 to which LED drive data SD is input. The first drive IC 191 drives the six LEDs 173 of the LED group 37a and has a plurality of input terminals and output terminals. Specifically, it has a DATAIN terminal (data input section), a CLK terminal, an L terminal, a VDD terminal, and a GND terminal as input terminals, and also has a DATAOUT terminal (data output section) and a plurality of OUT terminals as output terminals. ing. LED drive data SD output from the sub CPU 111 of the sound lamp control device 90 via the data output circuit 134 and the output port 131 is input to the DATAIN terminal of the first drive IC 191. Similarly, the clock signal SG1 output from the sub CPU 111 via the data output circuit 134 and the output port 131 is input to the CLK terminal, and the data write signal SG2 is input to the L terminal. The VDD terminal is connected to a + 5V power supply, and the GND terminal is grounded. The DATAOUT terminal of the first driving IC 191 is open, and the LED 173 is connected to six OUT terminals among the eight OUT terminals, and the remaining two OUT terminals are open.

  In addition to the first driving IC 191, the LED driving unit has a DATAIN terminal, a CLK terminal, an L terminal, a VDD terminal, and a GND terminal as input terminals in the same manner as the first driving IC 191, and eight OUT terminals and DATAOUT as output terminals. There is a pseudo drive IC 192 having terminals. The eight OUT terminals of the pseudo drive IC 192 are all open, and are different from the first drive IC 191 in this respect. The DATAOUT terminal of the pseudo driving IC 192 has a DATAIN terminal, a CLK terminal, an L terminal, a VDD terminal, and a GND terminal as input terminals, and has eight OUT terminals and a DATAOUT terminal as output terminals, similarly to the first driving IC. The second drive IC 193 is connected to the DATAIN terminal. Other connections of the pseudo drive IC 192 are the same as those of the first drive IC 191. The second drive IC 193 has the same configuration as the first drive IC 191 except for the connection of the DATAIN terminal described above, and drives the six LEDs 173 of the LED group 37b. The first driving IC 191 and the second driving IC 193 are circuits existing on the LED substrate 91 and are driving units for the LED 173. Based on the command input from the main controller 60, the sound lamp controller 90 outputs LED drive data SD for driving the LED to the LED board 91. The output LED driving data SD is input to the first driving IC 191 and the second driving IC 193 to drive the LEDs.

  The signal line 151 coming out from the DATA terminal of the input port 171 is branched into two and connected to the DATAIN terminal of the first drive IC 191 and the pseudo drive IC 192. Further, the signal line 152 extending from the CLK terminal of the input port 171 is branched into three and connected to the CLK terminals of the first drive IC 191, the pseudo drive IC 192, and the second drive IC 193. The signal line 153 extending from the L terminal of the input port 171 is branched into three and connected to the L terminals of the first drive IC 191, the pseudo drive IC 192, and the second drive IC 193.

  The internal configurations of the first drive IC 191, the pseudo drive IC 192, and the second drive IC 193 will be described in detail with reference to the block diagram of FIG. FIG. 13A shows the internal configuration of the first drive IC 191, and FIG. 13B shows the internal configuration of the pseudo drive IC 192 and the second drive IC 193. Here, since the internal configurations of the first drive IC 191, the pseudo drive IC 192, and the second drive IC 193 are the same, only the first drive IC 191 will be described, and only the difference in connection method between the second drive IC 193 and the pseudo drive IC 192 will be described. To do.

  As shown in FIG. 13A, the first drive IC 191 includes an update circuit 191a that acquires and updates the LED drive data SD, and a register 191b in which the LED drive data SD is written. The update circuit 191a includes an update buffer 191c. The update buffer 191c has 8-bit data areas D0 to D7 and an output data-out area DA. The data-out area DA is a copy area of the data area D7, and is an area in which the same information as the data area D7 is set. The update circuit 191a is connected to the DATAIN terminal to which the LED drive data SD is input, and is connected to the CLK terminal to which the clock signal SG1 is input. The update circuit 191a sequentially shifts the data already written in the data areas D0 to D7 in synchronization with the rising edge of the clock signal SG1, and writes the LED drive data SD in the data area D0.

  An example of a specific configuration of the update buffer 191c will be briefly described with reference to FIG. 14. The update buffer 191c includes eight positive edge trigger D flip-flops as data areas D0 to D7. Each D flip-flop has an input terminal (D terminal), an output terminal (Q terminal), and a clock terminal (CLK terminal), and a clock signal SG1 is input to each clock terminal. In each positive edge type D flip-flop, a signal input to the input terminal is written at the moment of rising of the clock signal SG1. Each D flip-flop holds the signal until the next rising edge of the clock signal SG1 and outputs the signal from the Q terminal. Each D flip-flop is connected in series with respect to the LED drive data SD and connected in parallel with respect to the clock signal SG1. That is, the Q terminal of the D flip-flop applied to the predetermined data area Dx (for example, D0) is the input terminal of the D flip-flop applied to the next data area D (x + 1) (for example, D1) with respect to the predetermined data area Dx. Connected to. The LED drive data SD is input to the input terminal of the D flip-flop related to the data area D0. A clock signal is input to the clock terminal of each D flip-flop of the update buffer 191c.

  The D flip-flop corresponding to the data area DA is a negative edge trigger type D flip-flop different from the positive edge trigger type D flip-flops of the data areas D0 to D7. In this case, the signal input to the input terminal at the moment when the clock signal SG1 falls is written to the negative edge trigger type D flip-flop. The negative edge trigger type D flip-flop holds the written signal until the next falling edge of the clock signal SG1, and outputs it from the Q terminal. Therefore, the same signal as D7 written to the negative edge trigger type D flip-flop at the fall of the clock signal SG1 is not changed even if the signal held at D7 is rewritten at the rise of the next clock signal SG1. This is held until the falling edge of the signal SG1.

  Returning to the description of FIG. 13A, the register 191b has 8-bit data areas D′ 0 to D′ 7, and the data areas D′ 0 to D′ 7 are data areas of the update buffer 191c, respectively. It is connected to D0 to D7. Among these, in the data areas D'0 to D'5, the LEDs 173 are connected to the respective Q terminals. Further, the data write signal SG2 is input to the register 191b. Based on the rise of the data write signal SG2, the register 191b writes the data set in each of the data areas D0 to D7 to its own data area D'0 to D'7, and each OUT terminal (OUT0 Terminal to OUT7 terminal) is configured to output the data to the LED 173. Each LED 173 operates based on the output data.

  Specifically, the anode of each LED 173 is connected to a + 5V power source, and the cathode of each LED 173 is connected to the corresponding data region D'0 to D'5. According to this configuration, for example, when the data area D0 is “1”, “1” is set in the data area D′ 0, and the potential corresponding to the data area D′ 0 to “1” (in detail). + 5V) is output. In this case, since no potential difference occurs between the anode and cathode of the LED 173, the LED 173 does not emit light. On the other hand, when the data area D0 is “0”, “0” is set in the data area D′ 0, and the potential corresponding to “0” (specifically, 0 V) is output from the data area D′ 0. Is done. In this case, a potential difference is generated between the anode and cathode of the LED 173, and the LED 173 emits light. In other words, when the data area Dx is “0”, it can be said that the cathode of the LED 173 is grounded, and the LED 173 is supplied with power capable of emitting light.

  Next, a specific configuration of the register 191b of the first drive IC 191 will be briefly described with reference to FIG. The register 191b includes eight positive edge triggered D flip-flops corresponding to the data areas D'0 to D'7. Each D flip-flop has an input terminal (D terminal), an output terminal (Q terminal), and a clock terminal (CLK terminal), and a data write signal SG2 is input to each clock terminal. The input terminal of the D flip-flop corresponding to the data area D′ x is connected to a connection line connecting the Q terminal of the D flip-flop corresponding to the data area Dx of the update buffer 191c and the input terminal of the data area D (x + 1). Branch lines are connected.

  In the register 191b of the first driving IC 191, the LED 173 can be connected to the Q terminal of the positive edge trigger type D flip-flop corresponding to the eight data regions D'0 to D'7. Regarding the first driving IC 191, the LED 173 is connected to the output terminals of the D flip-flops corresponding to the data areas D'0 to D'5.

  Here, with reference to FIG. 14, the flow of writing data to the data area D0 of the update buffer 191c of the first drive IC and shifting to the data areas D1, D2,... D7, DA will be briefly described.

  In synchronization with the rise of the clock signal, the first signal S1 of the LED drive data SD output from the sub CPU 111 of the sound lamp control device 90 via the data output circuit 134 and the output port 131 is written to the data area D0. . The Q terminal of the D flip-flop related to the data area D0 and the input terminal of the D flip-flop related to the data area D1 are connected, and the clock signal is simultaneously sent to the clock terminal of each D flip-flop. Therefore, in a state where the first signal S1 is written in the D flip-flop corresponding to the data area D0, the first signal S1 is written in the D flip-flop related to the data area D1 at the moment when the next clock signal SG1 rises. At the same time, the second signal S2 of the LED drive data SD is written into the D flip-flop applied to the data area D0. Similarly, at the next rising edge of the clock signal, the first signal S1 is written to the D flip-flop for the data area D2, and at the same time, the second signal S2 is written to the D flip-flop for the data area D1. The signal S3 is written to each D flip-flop associated with the data area D0.

  In this manner, the LED drive data SD is sequentially shifted downstream of the D flip-flops connected in series with respect to the LED drive data SD in synchronization with the rising edge of the clock signal. When the first signal S1 is written in the data area D6 and the clock signal SG1 rises next time, the first signal S1 is written in the D flip-flop corresponding to the data area D7, and the subsequent clock signal falls. Synchronously, the first signal S1 is written into the data area DA. This is because the D flip-flop corresponding to the data area DA is a negative edge trigger type. At this time, the same signal is written in the two D flip-flops corresponding to D7 and DA.

  The configuration of the update circuit 191a is not limited to the D flip-flop, and for example, a JK flip-flop may be used. In short, the update circuit 191a has a plurality of information holding units and is configured to be able to input and output data, and is sequentially held in each information holding unit at a predetermined update timing. What is necessary is just to update data and to input / output data.

  In addition, a CPU (control circuit) that outputs a control signal capable of individually controlling each data stored in the update buffer 191c may be provided.

  Next, differences between the pseudo drive IC 192 and the second drive IC 193 from the first drive IC 191 will be described. Here, in order to distinguish from the first drive IC 191, the update circuit of the pseudo drive IC 192 is the update circuit 192a, the update circuit of the second drive IC 193 is the update circuit 193a, the register of the pseudo drive IC 192 is the register 192b, and the register of the second drive IC 193 is Register 193b, update buffer 192c for the pseudo drive IC 192, update buffer 192c for the second drive IC 193, update buffer 193c, update buffer 192c for the pseudo drive IC 192, data areas D8 to D15, The data area of the second driving IC 193 is referred to as D16 to D23, each OUT terminal of the pseudo driving IC 192 is referred to as OUT8 terminal to OUT15 terminal, and each OUT terminal of the second driving IC 193 is referred to as OUT16 terminal to OUT23 terminal.

  The pseudo driving IC 192 is different from the first driving IC 191 in that the output terminals of all eight D flip-flops of the register 192b are open. The output terminal of the negative edge trigger type D flip-flop corresponding to the data area DA of the update buffer 192c of the pseudo drive IC 192 is the positive edge trigger type D flip-flop corresponding to the data area D16 of the update buffer 193c of the second drive IC 193. Connected to the input terminal of the cable.

  The update buffers 192c and 193c of the pseudo drive IC 192 and the second drive IC 193 are configured with nine D flip-flops arranged in the same manner as the first drive IC 191, and the D terminals of the eight D flip-flops excluding the top are It is connected to the Q terminal of the immediately preceding D flip-flop. The leading input terminal of the update buffer 192 c of the pseudo driving IC 192 is connected to the DATA terminal of the input port 171. The Q terminal of the last D flip-flop is connected to the D terminal of the leading D flip-flop among the nine D flip-flops of the update buffer 193c of the second drive IC 193. For this reason, the signal S1 of the LED drive data SD first written in the data area D8 of the pseudo drive IC 192 is sequentially shifted to the data areas D9, D10,..., D15 as in the case of the first drive IC 191, After passing through the data area DA of the driving IC 192, the data is sequentially shifted to the data area D23 through the data areas D16, D17,..., D22 of the second driving IC 193. This will be described below with reference to FIG.

  15A shows a clock signal input to the clock terminal of the D flip-flop corresponding to the data area D8 to DA of the update buffer 192c of the pseudo driving IC 192, and FIG. 15B shows data from the sub CPU 111 of the sound lamp control device 90. LED drive data SD signal transmitted via the output circuit 134 and the output port 131, (c) is a signal written in the data area D8 to DA, and (d) is output from the data area DA of the pseudo drive IC 192. Signal. Regarding the timing tx, when x is an odd number, it corresponds to the falling edge of the clock signal SG1, and when x is an even number, it corresponds to the rising edge of the clock signal SG1.

  First, the clock signal SG1 falls at the timing t1, and the signal of the LED drive data SD is updated synchronously. At the same time, the signal written in the data area D15 is written in the data area DA, and the signal written in the data area DA is output from the output terminal of the pseudo driving IC. This is because only the D flip-flop corresponding to the data area DA is a negative edge trigger type. The clock signal SG1 rises at the timing t2, and the signals written in the data areas D9 to D15 are updated synchronously. At the same time, the LED drive data SD signal is written in the data area D8. At this time, in the update buffer 191c of the first drive IC 191, the signal written in the data areas D1 to D7 is updated and the signal of the LED drive data SD is written in the data area D0.

  The clock signal SG1 falls at the timing of t3, and the signal of the LED drive data SD is updated synchronously. At the same time, the signal written in the data area D15 is written in the data area DA, and the signal written in the data area DA is output from the output terminal of the pseudo driving IC. At this time, in the update buffer 191c of the first drive IC 191, the signal written in the data area D7 is written in the data area DA, and the signal written in the data area DA is output from the output terminal of the first drive IC 191. Is done. The clock signal rises at the timing t4, the signals written in the data areas D9 to D15 are updated in synchronization, and the signal of the LED drive data SD is written in the data area D8. At this time, in the update buffer 191c of the first drive IC 191, the signal written in the data areas D1 to D7 is updated, and the signal of the LED drive data SD is written in the data area D0.

  Thus, until the writing of the LED drive data SD is completed, the signal is shifted from the data area D8 of the pseudo drive IC 192 to the data area DA like a bucket relay. The first signal S1 is written in the data area D15 in synchronization with the rising edge of the next clock signal SG1 after the first signal S1 of the LED drive data SD is shifted to the data area D14, and in synchronization with the subsequent falling edge of the clock signal SG1. Thus, the first signal S1 is written in the data area DA.

  Then, the first signal S1 is written in the data area D16 of the second drive IC 193 at the next rise of the clock signal SG1. This is because the D flip-flop corresponding to the data area D16 is a positive edge trigger type. Thereafter, the first signal S1 is sequentially shifted to the data areas D17, D18,..., D23. After the writing of the first signal S1 to the most downstream data area D23 is completed, the registers 191b, 192b of the first driving IC 191, the pseudo driving IC 192, and the second driving IC 193 at the fall of the next clock signal SG1. The data write signal SG2 sent to the clock terminal 193b rises, and the data in the data areas D0 to D23 is written in the data areas D′ 0 to D′ 23 in synchronization. When the LED 173 is connected to the output terminal of the corresponding D flip-flop among the data areas D′ 0 to D′ 23, the LED 173 emits light when the signal in the data area is “0”.

  The clock signal SG1 is stopped as it is, and the LED 173 maintains the light emission mode until the next data write signal SG2 rises.

  Here, in FIG. 15, the update timing of the LED drive data SD (timing of t1, t3) and the update timing of the data areas D8 to DA (timing of t2, t4) are set so as not to synchronize. Specifically, the rising timing of the clock signal SG1 is shifted by a predetermined period T1 with respect to the update timing of the LED drive data SD (specifically, it is delayed), and the update interval of the LED drive data SD is the clock. It is set to an integral multiple of the period T2 of the signal SG1 (specifically, equal multiple). As a result, the update timing of the LED drive data SD and the rising timing of the clock signal SG1 do not coincide, so that the update of the LED drive data SD and the update of the data areas D8 to D15 are not performed simultaneously. Yes. This makes it difficult for an acquisition error to occur when acquiring the LED drive data SD.

  That is, if the acquisition timing of the LED drive data SD and the update timing of the LED drive data SD are the same, it is not known whether the acquired LED drive data SD is the one before the update or after the update. Become. On the other hand, according to the present embodiment, since the acquisition timing of the LED drive data SD is delayed by a predetermined period T1 with respect to the update timing of the LED drive data SD, the LED drive data SD in a stable state is acquired. It becomes possible to do. Thereby, an acquisition error of the LED drive data SD is less likely to occur.

  FIG. 16 shows data written in the update buffers 191c, 192c, and 193c at the time when the first 8 bits are written in the data areas D0 to D15.

  This is a result of outputting the same 8-bit LED drive data SD to the first drive IC 191 via the serial data line and to the combination of the pseudo drive IC 192 and the second drive IC 193. As shown in FIG. 16, when the first 8 bits are written, D0 to D7 in the update buffer 191c of the first drive IC 191 and D8 to D15 in the update buffer 192c of the pseudo drive IC 192 are in the first half. 8 bits are written.

  FIG. 17 shows signals written in the update buffers 191c, 192c, and 193c at the time when writing to all the data areas D0 to D23 is completed.

  This is the result of outputting the same 16-bit LED drive data SD to the first drive IC 191 via the serial data line and to the combination of the pseudo drive IC 192 and the second drive IC 193. As shown in FIG. 17, the first 8 bits are finally written in the update buffer 193 c of the second drive IC 193. On the other hand, the last 8 bits are written in the update buffer 191c of the first drive IC 191 and the update buffer 192c of the pseudo drive IC 192. As described above, with respect to the serial data line, by arranging one pseudo drive IC 192 upstream of the second drive IC 193, signal transmission can be shifted by 8 bits compared to the first drive IC 191.

  If this is utilized, 16 bits of LED drive data SD are output, with the first 8 bits being the data for the second drive IC 193 and the latter 8 bits being the data for the first drive IC 191, and then the data write signal SG2 is transmitted. Thus, the two LED groups 37a and 37b can be driven simultaneously.

<Various Processes Executed by the Audio Lamp Control Device 90>
Next, processing performed by the sub CPU 111 of the sound lamp control device 90 will be described. The process performed by the sub CPU 111 includes an audio lamp control process for controlling the LED 173. The process will be described below with reference to the flowchart of FIG.

  First, in step S401, it is determined whether or not there is a data write flag. The data write flag is a flag stored in step S408 of the LED control process, and means that LED drive data is being written. If there is no data write flag, the process proceeds to step S402. In step S <b> 402, it is determined whether a variation command is received from main controller 60. When the change command is received, the LED drive pattern table stored in the ROM 112 of the sound lamp control board 110 is set in the RAM 113 of the sound lamp control board 110 in step S403. The ROM 112 is provided with an LED drive pattern table storage area 112b, and a plurality of types of LED drive pattern tables are stored in the LED drive pattern table storage area 112b. Each LED drive pattern table is set with a set of elapsed time from the start of the fluctuation display of the main display section 33 until the update timing of the LED drive data SD and the LED drive data SD updated at the timing. It is a table. When a predetermined period has elapsed since the start of the variable display, the LED drive pattern table is referred to, and LED drive data SD corresponding to the period is stored in the registers 191b and 193b of the first drive IC 191 and the second drive IC 193. By writing, each LED 173 is driven and controlled.

  If no change command has been received in step S402, it is determined in step S404 whether or not the change command is being changed. If it is changing, it is determined whether or not it is the update timing of the LED drive data in step S405, and if it is the update timing, update processing of the LED drive data is performed in step S406. Specifically, the LED driving data SD corresponding to the current processing time is grasped by referring to the LED driving pattern table selected in the current gaming time.

  When the LED drive pattern table is set in step S403 and when the LED drive data update process is performed in step S406, the process proceeds to step S407, and the LED drive data write start process is performed. Specifically, the selected LED drive pattern table is referred to, and LED drive data SD that matches the elapsed time since the start of the variable display is acquired. In the acquired LED driving data SD, data corresponding to the storage capacity (8 bits) of each data register 141a, 141b is first written to the first data register 141a of each data register 141a, 141b. To do. After writing 8 bits of data, writing to the second data register 141b is started.

  In subsequent step S408, the data write flag is stored, and in step S409, transmission of the clock signal SG1 is started. Specifically, information “1” and information “0” are alternately set in the clock signal register. In this case, when the output of the clock signal SG1 is started, the LED drive data SD stored in the first data register 141a is first set to be transmitted first.

  When an affirmative determination is made in step S401 and when transmission of the clock signal SG1 is started in step S409, the process proceeds to step S410 to determine whether writing of a series of 16-bit LED drive data SD has been completed. judge. When the writing is completed, the data writing flag is reset in step S411. Thereafter, in step S412, a process for raising the data write signal SG2 is executed. Specifically, “0” is set to the data write signal register. As a result, the data write signal SG2 rises. In synchronization with the rise, the data written in the update buffers 191c, 192c, 193c is written in the registers 191b, 192b, 193b, and the LEDs are driven. Thereafter, a process of stopping the clock signal is executed in step S413.

  If a negative determination is made in step S404, a negative determination is made in step S405, a negative determination is made in step S410, and if the process of stopping the clock signal is completed in step S413, the process proceeds to step S414, and the speaker The other processing related to the control of the unit 55 and the control of the display control device 100 is performed, and this sound emission control processing is terminated.

  According to the embodiment described in detail above, the following excellent effects are obtained.

  After the serial data line for transmitting the LED drive data SD exits from the output port 131, the serial data line branches into two and is connected to the DATAIN terminals of the first drive IC 191 and the pseudo drive IC 192, respectively. By using a serial data line, it is possible to make a simple wiring with a smaller number of data lines than when data is transmitted in parallel. The place where the serial data line is branched is arbitrary. This makes it possible to branch the serial data line at a necessary location. This is an effective means for avoiding the problem that, when the substrate surface is complicated, a part that physically requires branching or a part that is susceptible to noise appears.

  In the case where the drive ICs 191 and 193 are connected in a daisy chain without branching the serial data line, when noise occurs upstream, the influence is exerted downstream after the occurrence location. On the other hand, in the present embodiment, the serial data line output from the output port 131 is branched and connected to the DATAIN terminals of the first drive IC 191 and the pseudo drive IC 192. The influence is limited to one of the first driving IC 191 and the second driving IC 193.

  The locations of the LED groups 37a and 37b are determined in consideration of the design of the gaming machine, and the optimal positions of the first drive IC 191 and the second drive IC 193 are determined according to the positions of the LED groups 37a and 37b. With respect to the serial data line, if the DATAOUT terminal of the first driving IC 191 is connected to the DATAIN terminal of the second driving IC 193, if there is a part that is susceptible to noise in the middle of the serial data line, wiring is performed avoiding that part. There is a need. However, when such wiring is performed, the connection line becomes long and the possibility of being affected by noise increases. On the other hand, with respect to the serial data line, the DATAOUT terminal of the pseudo drive IC 192 is connected to the DATAIN terminal of the second drive IC 193, and the first drive IC 191 and the pseudo drive IC 192 are connected in parallel, as in the present embodiment. It is possible to increase the degree of freedom in designing the wiring while avoiding easily affected parts.

  The internal configurations of the first drive IC 191, the second drive IC 193, and the pseudo drive IC 192 are the same. As a result, various light emitting modes can be easily realized for a series of serial data simply by arranging a plurality of drive ICs having the same internal configuration and changing the connection.

  The number of LED groups 37a and 37b that are driven together is not limited to two. For example, in the case where x drive ICs having an 8-bit data area are simultaneously driven, (x−1) pseudo drive ICs 192 are arranged upstream of the xth drive IC, thereby stepping by 8 bits. The data can be shifted. If this is utilized, x drive ICs can be driven simultaneously by transmitting a set of 8 bits as x serial data.

  After writing a total of 16 bits of data to the D flip-flops in the data areas D0 to D7 and the data areas D16 to D23, the data write signal SG2 rises, and the data areas D′ 0 to D′ 7 of the registers 191b and 193b A total of 16 bits of data are written to the D flip-flops in the data areas D′ 16 to D′ 23, and the corresponding LED 173 is driven. As a result, 16-bit LED drive data SD can be simultaneously sent to the registers 191b and 193b, and a maximum of 16 LEDs can be controlled simultaneously.

<Second Embodiment>
In the present embodiment, unlike the first embodiment, the pseudo drive IC 192 is not used. Unlike the first embodiment, all the update buffers 195c of the second driving IC 195 are negative edge trigger type D flip-flops. In the first embodiment, the data out area DA is provided in the first drive IC 191 and the second drive IC 193. However, in the present embodiment, the data out area DA is not provided. Further, in the first embodiment, the LED drive data SD is configured such that the signal for the second drive IC 193 is sent first, and the signal for the first drive IC 191 is sent later. The driving IC 194 signal and the second driving IC 195 signal are alternately sent by shifting in units of 1 bit.

  Hereinafter, a different configuration between the second embodiment and the first embodiment will be described. The description of the same configuration as that of the first embodiment is basically omitted.

  FIG. 19 is a circuit diagram showing a connection mode between the input port 171 and the first drive IC 194 and the second drive IC 195. Each of the first driver IC 194 and the second driver IC 195 has a DATAIN terminal, a CLK terminal, an L terminal, a VDD terminal, and a GND terminal on the input side, and has eight OUT terminals on the output side. The LED 173 is connected to each of the six OUT terminals, and the remaining two OUT terminals are open. A signal line 151 extending from the DATA terminal of the input port 171 is branched into two and connected to each DATAIN terminal. A signal line 152 extending from the CLK terminal of the input port 171 is branched into two and connected to each CLK terminal. A signal line 153 extending from the L terminal of the input port 171 is branched into two and connected to each L terminal.

  FIG. 20A is a block diagram for explaining the configuration of the first drive IC 194, and FIG. 20B is a block diagram for explaining the configuration of the second drive IC 195, respectively. As shown in FIG. 20A, the first drive IC 194 includes an update circuit 194a and a register 194b. The update circuit 194a includes an update buffer 194c including data areas D0 to D7, and the register 194b includes data areas D'0 to D'7 and OUT terminals OUT0 to OUT7. As shown in FIG. 20B, the second drive IC 195 includes an update circuit 195a and a register 195b. The update circuit 195a includes an update buffer 195c including data areas D8 to D15, and the register 195b includes data areas D'8 to D'15 and output terminals OUT8 to OUT15.

  FIG. 21 is a circuit diagram for explaining the wiring of the D flip-flops and the LEDs 173 constituting the registers 194b and 195b and the update buffers 194c and 195c of the first drive IC 194 and the second drive IC 195. The LED 173 is connected to the output terminals (Q terminals) of the D flip-flops constituting the registers 194b and 195b of the first drive IC 194 and the second drive IC 195.

  The D flip-flops constituting the update buffer 195c of the second driving IC 195 are negative edge trigger types, and the other D flip-flops are positive edge trigger types. Therefore, a signal is written to the update buffer 194c of the first drive IC 194 at the moment of rising of the clock signal SG1, and a signal is written to the update buffer 195c of the second drive IC 193 at the moment of falling of the clock signal SG1. Written. Since the clock signal SG1 repeats rising and falling, the LED drive data SD is alternately written in the update buffer 194c of the first drive IC 194 and the update buffer 195c of the second drive IC 195. By preparing LED drive data SD in which drive data for the update buffer 194c and drive data for the update buffer 195c are alternately arranged in units of 1 bit in advance, the LED drive data SD is generated from the clock signal SG1. Are alternately written in the update buffer 194c and the update buffer 195c selectively in synchronization with the rise and fall of the signal.

  FIG. 22 is a timing chart showing the output timing of the LED drive data SD.

  First, the data A7 is output from the LED driving register 141 at the timing t1, the clock signal SG1 rises at the timing t2, and the data A7 is written to the positive edge trigger type D flip-flop. Thereafter, the data output from the LED driving register 141 changes to B7 at the timing t3, the clock signal SG1 falls at the timing t4, and the data B7 is written to the negative edge trigger type D flip-flop. In this way, the signal output from the LED driving register 141 changes every half cycle of the clock signal, and the data area of the update buffer 194c formed of a positive edge trigger type D flip-flop at the rising edge of the clock signal. At D0, a new signal is written into the data area D8 of the update buffer 195c formed of a negative edge trigger type D flip-flop at the moment when the clock signal falls.

  The signals A0 and B0 are written in the data areas D0 and D8 of the update buffers 194c and 195c, respectively, at the rising timing of the clock signal SG1 at t19 and the falling timing of the clock signal SG1 at t21. The data write signal SG2 rises at the timing, and the signal held in the update buffers 194c and 195c is written to the registers 194b and 195b in synchronization with the rise of the data write signal SG2, and the signal is written according to the written signal. The LED 173 connected to the OUT terminals of the first drive IC 194 and the second drive IC 195 is drive-controlled.

  Returning to FIG. 21, first, the case of the first drive IC 194 will be described. When the data A7 is written to the D flip-flop associated with the data area D0 of the update buffer 194c of the first driving IC 194, the data A7 is output from the Q terminal of the D flip-flop. Therefore, the data A7 is written to the D flip-flop related to the adjacent data area D1 and the data A6 is written to the D flip-flop related to the data area D0 at the moment of the next rise of the clock signal SG1. In this manner, the data output from the LED driving register 141 is sequentially shifted to the adjacent D flip-flop in synchronization with the rising edge of the clock signal until the data A0 is written to the D flip-flop related to the data area D0. To go.

  Further, when the data B7 is written to the D flip-flop associated with the data area D8 of the update buffer 195c of the second driving IC 195, the data B7 is output from the output terminal of the D flip-flop. Therefore, data B7 is written to the D flip-flop related to the adjacent data area D9 and data B6 is written to the D flip-flop related to the data area D8 at the next falling edge of the clock signal. In this manner, the data output from the LED driving register 141 is sequentially shifted to the adjacent D flip-flop in synchronization with the fall of the clock signal until the data B0 is written to the D flip-flop of the data area D8. I will do it.

  FIG. 23 is a table showing data held in the data areas D0 to D15 of the update buffers 194c and 195c at the timing t22 (FIG. 22). Thus, data A0 to A7 are written in the data areas D0 to D7 of the update buffer 194c, and data B0 to B7 are written in the data areas D8 to D15 of the update buffer 195c. In this state, the data write signal SG2 rises at the timing of t23 (FIG. 22), and A0 appears in the data areas D′ 0 to D′ 15 of the registers 194b and 195b corresponding to the data areas D0 to D15 of the update buffers 194c and 195c. The data of .about.A7 and B0 to B7 are output, and each LED 173 is driven and controlled according to the data.

  According to this embodiment mentioned above, it has the following outstanding effects.

  The signal lines from the DATA terminal, the CLK terminal, and the L terminal of the input port 171 are each branched into two and connected to the DATAIN terminal, the CLK terminal, and the L terminal of the first drive IC 194 and the second drive IC 195. The place where each signal line is branched is arbitrary. As a result, it is possible to increase the degree of freedom of wiring, for example, by performing wiring while avoiding places that are susceptible to noise on the substrate.

  The D flip-flop constituting the update buffer 194c of the first drive IC 194 is set to a positive edge trigger type, and the D flip-flop constituting the update buffer 195c of the second drive IC 195 is set to a negative edge trigger type. With respect to the LED drive data SD, the drive data for the update buffer 194c is written to the first drive IC 194 at the time of the rise and the fall alternately repeated in the clock signal SG1, and at the time of the fall. The driving data for the update buffer 195c is written to the second driving IC 195. In other words, there is drive data that should be written to the first drive IC 194 and drive data that should be written to the second drive IC 195 when the writing of the LED drive data SD is completed, and they are spaced in 1-bit units. And arranged alternately. As a result, the LED drive data SD is written to the data area D0 of the update buffer 194c when the clock signal SG1 rises, and the LED drive to the data area D8 of the update buffer 195c occurs when the clock signal SG1 falls. Data SD is selectively written. Since the LED drive data SD is serial data, it is possible to use a simple wiring with a smaller number of signal lines than in the case of parallel data.

  Among the D flip-flops constituting the update buffers 194c and 195c, except for the D flip-flops related to the data areas D0 and D8, a signal line extending from the Q terminal of the immediately preceding D flip-flop is connected to the data terminal, and the clock signal SG1 is connected to the clock terminal. The signal lines are connected to each other. Accordingly, the signal written in D0 or D8 is sequentially shifted downstream when the clock signal SG1 rises in the update buffer 194c and when the clock signal SG1 falls in the update buffer 195c.

  After data writing for a total of 16 bits is completed in the D flip-flops related to the data areas D0 to D15, the data write signal SG2 rises and the D flip-flops related to the data areas D′ 0 to D′ 15 of the registers 194b and 195b. In this configuration, data for a total of 16 bits is written, and the corresponding LED 173 is driven. As a result, 16-bit LED driving data SD can be simultaneously sent to the registers 194b and 195b, and a maximum of 16 LEDs can be controlled simultaneously.

<Third Embodiment>
In the present embodiment, unlike the first embodiment, the pseudo drive IC 192 is not used. A positive edge trigger type T flip-flop is disposed upstream of the first drive IC 191 in the signal line for transmitting the data write signal SG2. The second driving IC 193 is different from the first driving IC 191 in that the T flip-flop is a negative edge trigger type. In the first embodiment, the data out area DA is provided in the first drive IC 191 and the second drive IC 193. However, in the present embodiment, the data out area DA is not provided. In the first embodiment, the two LED groups 37a and 37b are driven and controlled simultaneously. In the present embodiment, the first drive IC 191 and the second drive IC 193 are alternately driven. .

  Hereinafter, a different configuration between the third embodiment and the first embodiment will be described. The description of the same configuration as that of the first embodiment is basically omitted.

  Each of the first driving IC 191 and the second driving IC 193 has a DATAIN terminal, a CLK terminal, an L terminal, a VDD terminal, and a GND terminal on the input side, and has eight OUT terminals on the output side. The LED 173 is connected to each of the six OUT terminals. A signal line 151 extending from the DATA terminal of the input port 171 is branched into two and connected to each DATAIN terminal. A signal line 152 extending from the CLK terminal of the input port 171 is branched into two and connected to each CLK terminal. A signal line 153 extending from the L terminal of the input port 171 is branched into two and connected to each L terminal.

  The first drive IC 191 includes an update circuit 191a and a register 191b. The update circuit 191a includes an update buffer 191c including data areas D0 to D7, and the register 191b includes data areas D'0 to D'7 and OUT terminals OUT0 to OUT7. The second driving IC 193 includes an update circuit 193a and a register 193b. The update circuit 193a includes an update buffer 193c including data areas D8 to D15, and the register 193b includes data areas D'8 to D'15 and output terminals OUT8 to OUT15.

  FIG. 24 is a circuit diagram for explaining the wiring of the D flip-flop, the T flip-flop, and the LED 173 constituting the register 191b and the update buffer 191c of the first driving IC 191. The LED 173 can be connected to the output terminal (Q terminal) of the D flip-flop constituting the register 191b of the first driving IC 191.

  The L terminal of the input port 171 is connected to the T terminal of the positive edge triggered T flip-flop. The Q terminal of the T flip-flop is connected to the clock terminal of the D flip-flop constituting the register 191b of the first driving IC 191. Therefore, when the data write signal SG2 input to the T terminal rises, the data input to the clock terminals of the data areas D'0 to D'7 is inverted. As an example, a case where “0” is first input to the CLK terminals of the data areas D′ 0 to D′ 7 will be described. In this case, the data written in the data areas D'0 to D'7 is inverted in synchronization with the rise of the first data write signal SG2. That is, as the data write signal SG2 rises, the data input to the data areas D'0 to D'7 becomes "1". Thereafter, even if the data write signal SG2 falls, the data input to the data areas D'0 to D'7 does not change. Next, when the data write signal SG2 rises, the data input to the data areas D'0 to D'7 synchronously changes from "1" to "0". Then, even if the data write signal SG2 subsequently falls, the data input to the data areas D'0 to D'7 does not change. Thus, when the data write signal SG2 repeats rising and falling, the data written to the data areas D'0 to D'7 is inverted only in synchronization with the rising. Therefore, the signal written to the data areas D'0 to D'7 rises at a rate of once every two rises of the data write signal SG2. The data written in the data areas D0 to D7 is written to the data areas D'0 to D'7 in synchronization with the rising edge of the data written to the data areas D'0 to D'7. The LED group 37a connected to the Q terminal of the D flip-flop related to “0 to D” 7 is driven and controlled.

  On the other hand, the L terminal of the input port 171 is connected to the T terminal of the negative edge trigger type T flip-flop. The Q terminal of the T flip-flop is connected to the clock terminal of the D flip-flop constituting the register 193b of the second driving IC 193. FIG. 25 is a circuit diagram for explaining the wiring of the D flip-flop, the T flip-flop, and the LED 173 that constitute the register 193b and the update buffer 193c of the second drive IC 193. The data line coming out from the Q terminal of the T flip-flop is connected to the clock terminals of the data areas D'8 to D'15. Therefore, when the data write signal SG2 output from the T terminal falls, the data input to the clock terminals of the data areas D'0 to D'7 is inverted. As an example, a case where “0” is first input to the data areas D′ 8 to D′ 15 will be described. In this case, even if the first data write signal SG2 rises, the data input to the data areas D'8 to D'15 remains "0". Thereafter, the data input to the data areas D′ 8 to D′ 15 changes to “1” in synchronization with the falling edge of the data write signal SG2. At this time, the data written in the data areas D8 to D15 is written to the data areas D'8 to D'15. Next, even if the data write signal SG2 rises, the data input to the data areas D'8 to D'15 remains "1". Then, when the data write signal SG2 subsequently falls, the data input to the data areas D'8 to D'15 returns to "0". As described above, when the data write signal SG2 repeats rising and falling, the data written in the data areas D'8 to D'15 is inverted only in synchronization with the falling. Therefore, the signal written to the data areas D'0 to D'7 rises at a rate of once every two falling edges of the data write signal SG2. The data written in the data areas D8 to D15 is written to the data areas D′ 8 to D′ 15 in synchronization with the rising edge of the data written to the clock terminal of the D flip-flop constituting the register 193b. The LED group 37b connected to the Q terminal of the D flip-flop related to the regions D′ 8 to D′ 15 is driven and controlled.

  FIG. 26 is a timing chart showing the output timing of the LED drive data SD and the rise and fall timings of the data write signal SG2.

  First, the data A7 is output from the LED driving register 141 at the timing t1, the clock signal SG1 rises at the timing t2, and the data A7 is written to the D flip-flops related to the data area D0 and the data area D8. Thereafter, the data output from the LED driving register 141 changes to A6 at the timing t3, the clock signal SG1 rises at the timing t4, and the data A7 is transferred to the D flip-flops for the data area D1 and the data area D9. And shift from the D flip-flop over the data area D8. Then, the data A6 is written in the D flip-flops related to the data area D0 and the data area D8. In this way, the data output from the LED driving register 141 changes in synchronization with the falling edge of the clock signal SG1, and in synchronization with the rising edge of the clock signal SG1, the data that has been written in the D flip-flop until then. Shifts and new LED driving data is written to the D flip-flops in the data area D0 and the data area D8. At time t7, the data written in the data areas D0 to D6 and the data areas D8 to D14 are shifted to the data areas D1 to D7 and the data areas D9 to D15, and the data A0 is stored in the data areas D0 and D8. When written, in the first drive IC 191, the data Ax is written in the data area Dx. On the other hand, in the second drive IC 193, the data A (x-8) is written in the data area Dx. When the clock signal SG1 falls at the timing of t8 and the data write signal SG2 rises at the timing of t9, the clock of the D flip-flop applied to the data areas D′ 0 to D′ 7 of the register 191b of the first driving IC 191 synchronously. Data input to the terminal changes from “0” to “1”. Therefore, in synchronization with the rise of the data, data A0 to A7 are written in the data areas D'0 to D'7, and the LED group 37a connected to the output terminal is driven and controlled. On the other hand, since the data input to the clock terminals of the D flip-flops applied to the data areas D′ 8 to D′ 15 of the register 193b of the second driving IC 193 remains “0”, the data areas D′ 8 to D ′ are not changed. No data is written into the D flip-flop 15.

  The data B7 is output from the LED drive register 141 at the timing t10, the clock signal SG1 rises at the timing t11, the data written in each data area is shifted, and the data B7 is transferred to the data area D0 and the data area D8. Written. Thereafter, the data output from the LED drive register 141 changes to B6 in synchronization with the falling edge of the clock signal SG1 at the timing of t12, and is written in each data area in synchronization with the rising edge of the clock signal SG1 at the timing of t13. The shifted data is shifted, and data B6 is written in the data area D0 and the data area D8. In this way, the data output from the LED driving register 141 changes in synchronization with the falling edge of the clock signal SG1, and in synchronization with the rising edge of the clock signal SG1, the data that has been written in the D flip-flop until then. Shifts and new LED driving data is written to the D flip-flops in the data area D0 and the data area D8. Then, when the data in each data area shifts at the timing t16 and the data B0 is written in the data area D0 and the data area D8, the first drive IC 191 enters the state where the data Bx is written in the data area Dx. On the other hand, in the second drive IC 193, data B (x-8) is written in the data area Dx. When the clock signal SG1 falls at the timing t17 and the data write signal SG2 falls at the timing t18, the D flip-flops applied to the data regions D′ 8 to D′ 15 of the register 193b of the second driving IC 193 are synchronized. Data input to the clock terminal changes from “0” to “1”. Therefore, in synchronization with the rise of the data, data B0 to B7 are written in the data areas D'8 to D'15, and the LED group 37b connected to the output terminal is driven and controlled. On the other hand, since the data input to the clock terminal of the D flip-flop applied to the data area D′ 0 to D′ 7 of the register 193b of the first driving IC 191 remains “1”, the data area D′ 0 to D ′ is not changed. No data is written to the D flip-flop 7.

  Thereafter, the data write signal SG2 rises at the timing of t19, and the data input to the clock terminal of the D flip-flop related to the data areas D'0 to D'7 changes from "1" to "0" synchronously. On the other hand, the data input to the clock terminals of the D flip-flops corresponding to D′ 8 to D′ 15 remains “1”. Next, the data write signal SG2 falls at the timing t20, and the data input to the clock terminals of the D flip-flops corresponding to the data areas D′ 8 to D′ 15 changes from “1” to “0” synchronously. To do. On the other hand, the data input to the clock terminals of the D flip-flops corresponding to D'0 to D'7 remains "0". In this way, after the drive control is performed in the order of the first drive IC 191 and the second drive IC 193, the data write signal rises and falls once, so that D applied to the data areas D′ 0 to D′ 15 Both data input to the clock terminals of the flip-flops can be returned to “0”. That is, the initial state is restored. Therefore, the first drive IC 191 and the second drive IC 193 can be alternately driven and controlled by repeating a series of operations.

  According to this embodiment mentioned above, it has the following outstanding effects.

  The signal lines coming out from the DATA terminal, the CLK terminal, and the L terminal of the input port 171 are each branched into two and connected to the DATAIN terminal, the CLK terminal, and the L terminal of the first drive IC 191 and the second drive IC 193. The place where each signal line is branched is arbitrary. As a result, it is possible to increase the degree of freedom of wiring, for example, by performing wiring while avoiding places that are susceptible to noise on the substrate.

  For the first driving IC 191, a positive edge trigger type T flip-flop is arranged upstream of the branched signal line for transmitting the data write signal SG2. Further, for the second drive IC 193, a negative edge trigger type T flip-flop is disposed upstream of the branched signal line for transmitting the data write signal SG2. Then, after the 8-bit data to be written to the first driving IC 191 is transmitted first, the data write signal SG2 is raised, and the 8-bit data to be written to the second driving IC 193 is transmitted later to obtain the data write signal. It was set as the structure which falls SG2. Thus, the LED drive data SD is written to the data areas D′ 0 to D′ 7 of the register 191b when the data write signal SG2 rises, and the data area of the register 193b when the data write signal SG2 falls. LED drive data SD is alternately written in D′ 8 to D′ 15. Since the LED drive data SD is serial data, it is possible to use a simple wiring with a smaller number of signal lines than in the case of parallel data.

  The internal structure of the first drive IC 191 and the second drive IC 193 is the same. Both have a T flip-flop upstream of the branched data line transmitting the data write signal SG2. The difference between the two is whether the T flip-flop is a positive edge trigger type or a negative edge trigger type. Thus, since it is the structure which arranges LED drive IC which has the same internal structure, it is simple and is easy to assemble.

<Fourth Embodiment>
In the present embodiment, unlike the first embodiment, communication ICs 224a and 224b are used instead of the first drive IC 191, the pseudo drive IC 192, and the second drive IC 193. Further, the decoration device IC 220 of the audio lamp control device 90 and the communication ICs 224a and 224b are connected in parallel by two lines, a serial clock line and a bidirectional serial data line. Unlike the first embodiment, the display screen G of the symbol display device 31 is provided with a door 228 that opens and closes depending on the production contents.

  Hereinafter, a different configuration between the fourth embodiment and the first embodiment will be described. The description of the same configuration as that of the first embodiment is basically omitted.

  In FIG. 27, in the audio lamp control device 90, the sub CPU 111 and the decoration device IC 220 are connected by a bidirectional data line. The sound lamp control device 90 is connected to the communication ICs 224a and 224b via the relay substrate 221 with five connection lines. Specifically, the connection line Vcc, the connection line Vled, the connection line SDA, the connection line SCL, and the connection line GND are connected. The connection line Vcc is a connection line for supplying power to the relay substrate 221 and the communication ICs 224a and 224b. The connection line Vled is a connection line for supplying power to the LED groups 37a and 37b. The connection line SDA is a bidirectional connection line for communicating data between the decoration device IC 220 and the LED groups 37a and 37b. The connection line SCL is a connection line for inputting and outputting a clock signal used for data communication on the connection line SDA. The connection line GND is a ground of the power supplied by the connection line Vcc and the connection line Vled. The communication ICs 224 a and 224 b are connected in parallel to the decoration device IC 220 of the sound lamp control device 90.

  A unique address is preset in the communication ICs 224a and 224b to which the LED groups 37a and 37b are connected. When the decoration device drive data is input, the communication ICs 224a and 224b drive the input decoration device. It is determined whether the address included in the data matches the set address. If it is determined that the address included in the input decoration device drive data matches the set address, the communication ICs 224a and 224b determine whether the downstream LED group 37a, 37b is driven.

  The relay substrate 221 is a substrate that relays exchanges between the decoration device IC 220 and the communication ICs 224a and 224b. The relay board 221 supplies necessary power to the communication ICs 224a and 224b. Also, when the decoration device IC 220 starts communication, the address, Read / Write request (a distinction between the decoration device IC 220 receiving or transmitting) and the decoration device drive data are transmitted via the serial data line. . The relay board 221 transmits a clock signal via a serial clock line. The communication ICs 224a and 224b that have received it send "ACK" data indicating whether the communication is correct or not via a bi-directional serial data line and send the data when the sent address matches its own address. Prepare (or receive). Thus, the serial data line is monopolized and preparations for starting a one-to-one exchange with the decoration device IC 220 can be made. The “ACK” data is 1-bit data that is returned by one of the communication ICs 224a to 224e when the address transmitted by the decoration device IC 220 matches its own address.

  At the start of communication, the decoration device IC 220 changes the signal of the serial data line from “1” to “0” when the signal of the serial clock line is “1”. At the end of communication, the decoration device IC 220 changes the signal of the serial data line from “0” to “1” when the signal of the serial clock line is “1”. Since normal data exchange changes the signal of the serial data line when the signal of the serial clock line is “0”, it can be distinguished from the condition of communication start and communication end. The communication ICs 224 a and 224 b are connected in parallel to the decoration device IC 220 of the sound lamp control device 90.

  Here, a method in which the decoration device IC 220 controls the LED groups 37a and 37b via the communication ICs 224a and 224b will be described.

  The sound lamp control device 90 determines the production content based on the command input from the main control device 60. Then, the audio lamp control device 90 controls the LED groups 37a and 37b with the determined production content, and relay device 221 includes the decoration device drive data including the address of the communication ICs 224a and 224b to be controlled and the production content. Output to. The decoration device drive data is input from the serial data line to the communication ICs 224a and 224b connected to the sound lamp control device 90 via the relay board 221.

  FIG. 28 is a circuit diagram around the communication IC 224a connected to the LED group 37a.

  The communication IC 224a includes an NC terminal, a RESET terminal, an SCL terminal, an SDA terminal, a Vcc terminal, an A0 to A3 terminal, and a GND terminal as input terminals, and includes PORT0 to PORT15 as output terminals.

  Since the NC terminal is a terminal to which nothing is connected internally, nothing is connected to the NC terminal from the outside. A power supply supplied to the communication IC 224a is connected to the RESET terminal via a pull-up resistor R. Therefore, when no power is applied to the RESET terminal, the communication IC 224a is reset to the initial state.

  A serial clock line is connected to the SCL terminal, and a serial data line is connected to the SDA terminal. A power supply supplied to the communication IC 224a is connected to the Vcc terminal. Further, a bypass capacitor for removing power supply noise is connected to the Vcc terminal.

  The terminals A0 to A3 are terminals for setting addresses in the communication IC 224a. The address of the communication IC 224a is expressed by 4 bits, the voltage of the communication IC 224a is applied to the terminal indicating “1”, and the terminal indicating “0” is grounded. Therefore, the address of the communication IC 224a shown in FIG. 28 is “0100”. The GND terminal is a terminal for grounding a voltage.

  Each PORT0 terminal to PORT6 terminal is connected to the LED 173 via the current limiting resistor R.

  The control processing of the LED groups 37a and 37b by the decoration device IC 220 will be described with reference to the flowchart of FIG. 29 as an example of the writing communication processing when the decoration device IC 220 communicates with the communication IC 224a. A clock signal that triggers the operation is input to the decoration device IC 220, and data written from the sub CPU 111 exists in a register R <b> 1 (FIG. 31B) of the decoration device IC 220 to be described later. When the data is for driving, the write communication process is performed. Communication processing between the communication IC 224c and the decoration device IC 220 is performed when the data written from the sub CPU 111 to the register R1 is data for driving the accessory driving motors 226a and 226b. The communication process is the same as the write communication process.

  First, in step S501, the decoration device IC 220 issues a start condition based on the data sent from the sub CPU 111. This is to indicate the start of the communication sequence to the communication ICs 224a and 224b. Specifically, the start condition is established by changing the serial data SDA from “1” to “0” when the serial clock SCL is “1”. In step S502, the decoration device IC 220 transmits a control byte to the communication ICs 224a and 224b based on the data sent from the sub CPU 111. The control byte includes one of the addresses of the two communication ICs 224a and 224b, and the communication ICs 224a and 224b that have received the address determine whether or not the addresses match their own addresses. If the address does not match its own address, the communication IC 224b enters a standby state, and only the communication IC 224a whose address matches its own address transmits “ACK” data to the decoration device IC. The decoration device IC 220 that has received the “ACK” data in step S503 transmits the 8-bit LED drive data SD to the communication IC 224a that has transmitted the “ACK” data in step S504. The communication IC 224a that has received the 8-bit LED drive data SD transmits "ACK" data again. The decoration device IC 220 that has received the “ACK” data in step S505 issues a stop condition in step S506. This is to indicate the end of the communication sequence to the communication IC 224a. Specifically, when the serial clock SCL is “1”, the serial data SDA is changed from “0” to “1”. Then, the write communication process ends.

  Although the case where the LED groups 37a and 37b are driven for the communication ICs 224a and 224b has been described, in this embodiment, not only the LED 173 but also the accessory driving motor 226a using the initial position sensor 229 and the closed position sensor 230 is used. , 226b can also be controlled by using the same decoration device IC 220.

  As shown in FIG. 27, the LED group 37a is connected to the communication IC 224a, and the LED group 37b is connected to the communication IC 224b. Further, the accessory driving motors 226a and 226b are connected to the communication IC 224c. An initial position sensor 229 is connected to the communication IC 224d, and a closed position sensor 230 is connected to the communication IC 224e.

  Since the addresses of the communication ICs 224a to 224e are expressed by 4 bits, 16 types of addresses can be selected. Accordingly, the addresses of the four communication ICs 224b to 224e other than the communication IC 224a are selected from 15 types excluding the address “0100” used in the communication IC 224a. The four addresses selected for the four communication ICs 224b to 224e are set for the four terminals A00 to A03 of the communication ICs 224b to 224e by applying a voltage to the terminals or by grounding the terminals.

  The communication ICs 224b to 224e are different from the communication IC 224a only in connection between the address and the output side. The addresses are different from each other in order to distinguish the communication ICs 224a to 224e. The LED groups 37a and 37b are connected to the output side of the communication ICs 224a and 224b, whereas the communication IC 224c is connected to the two accessory driving motors 226a and 226b and is connected to the communication IC 224a. An initial position sensor 229 is connected to the IC 224d, and a closed position sensor 230 is connected to the communication IC 224e.

  As shown in FIG. 30, the accessory driving motors 226a and 226b, the initial position sensor 229, and the closing position sensor 230 are used for the effect of opening and closing the door 228. The effect that the door 227 moves from the initial position to the closed position is performed in order to show that the expectation degree of the big win is high in the state where the reach display is performed.

  The door 228 is closer to the player than the display screen G of the symbol display device 31. When the door 227 is in the initial position, the entire display screen G is visible to the player, and when the door 227 is in the closed position, the door 228 closed closer to the player than the display screen G is displayed on the display screen. Since it exists so as to overlap with G, the player can only see the closed door 228.

  Specifically, there is a sliding door type automatic door 228 that is guided by a rail and that the door 227 slides to the left and right. As shown in FIG. 30A, when the door 227 is in the initial position, the door 228 is in an open state. An initial position sensor 229 that detects that the door 227 is in the initial position detects one end of the door closer to the outside.

  By the accessory driving motors 226a and 226b, the door 227 is guided by the rail and moves toward the center of the door 228, and stops when it is completely closed. At this time, as shown in FIG. 30B, one end of the door 227 closer to the center is detected by the closed position sensor 230. The sliding door type automatic door 228 can be opened and closed by the decoration device IC 220.

  The accessory driving motors 226a and 226b, the initial position sensor 229, and the closing position sensor 230 are connected to the communication ICs 224c, 224d, and 224e. The communication ICs 224 c, 224 d, and 224 e are connected to the decoration device IC 220 via the relay substrate 221.

  The accessory driving motors 226a and 226b are connected to the communication IC 224c. The two accessory driving motors 226a and 226b are motors for opening and closing the sliding door type automatic door 228. Since the sliding door type automatic door 228 moves symmetrically, the drive control timing is the same. Therefore, the two accessory driving motors 226a and 226b can be controlled only by the communication IC 224c having one address.

  The decoration device IC 220 transmits an address and a write request to the communication ICs 224a to 224e. The communication IC 224c that has received this returns “ACK” data when the address matches its own address. The decoration device IC 220 that has received the “ACK” data from the communication IC 224c transmits motor drive data for driving the accessory driving motors 226a and 226b only to the communication IC 224c. The communication IC 224c that has received the motor drive data from the decoration device IC 220 drives the accessory drive motors 226a and 226b based on the received motor drive data. When the data received from the communication IC 224c is “10”, power for driving the accessory driving motors 226a and 226b is supplied to open the door 228. When the data is “01”, the door 228 is closed. Is supplied with electric power for driving the accessory driving motors 226a and 226b. In the case of “00”, no electric power for driving the accessory driving motors 226a and 226b is supplied. Data once written in the communication IC 224c is maintained until the next motor drive data is sent from the decoration device IC 220. Accordingly, if the data received from the communication IC 224c is “10” or “01”, then the accessory driving motors 226a and 226b continue to rotate until the motor driving data “00” is received.

  The initial position sensor 229 is connected to the communication IC 224d, and the closed position sensor 230 is connected to the communication IC 224e. The decoration device IC 220 and the communication ICs 224d and 224e are connected by bidirectional data lines. Therefore, when the decoration device IC 220 transmits the address of one of the two communication ICs 224d and 224e and a Read request, the communication IC 224 having the transmitted address returns “ACK” data, and then the communication ICs 224d and 224e. Transmits information obtained from the initial position sensor 229 or the closed position sensor 230 to the decoration device IC 220.

  As shown in FIG. 31A, the ROM 112 of the sub CPU 111 stores a plurality of decoration device control pattern tables. In the decoration device control pattern table, data for controlling the decoration device and transmission timing of data for controlling the decoration device are recorded. The data for controlling the decoration device includes any one address of the communication ICs 224a to 224e that communicate with the decoration device IC 220 and data indicating whether the communication is a Read request or a Write request. . In the case of a Write request, data (decoration device control data) to be written in any one of the communication ICs 224a to 224c that communicate with the decoration device IC 220 is also recorded. Here, the case where the request is a write request is a case where the decoration device is the LED group 37a, 37b or the accessory driving motor 226a, 226b. The case of a Read request is a case where the decoration device is the initial position sensor 229 or the closed position sensor 230. The sub CPU 111 reads one of the decoration device control pattern tables from the ROM 112 and develops it in the RAM 113. Then, the decoration device control data is sequentially written in the register of the decoration device IC 220 in accordance with the developed decoration device control pattern table.

  Specifically, a pointer exists for the decoration device control pattern table developed in the RAM 113, and the position of the pointer is updated to the next position every time the update timing is reached. In the decoration device control pattern table, when there is data for controlling the decoration device after being updated and moved, the sub CPU 111 is a free register among the registers of the decoration device IC 220 and is the most in order. The data for controlling the decoration device is written in the register with the fastest time. On the other hand, if the decoration device control data does not exist at the point where the pointer has moved at the update timing, the pointer remains as it is and waits for the next update timing.

  In order to control the LED groups 37a and 37b and the accessory driving motors 226a and 226b, the corresponding control data may be sent once. On the other hand, monitoring by the initial position sensor 229 and the closed position sensor 230 requires a certain amount of time. The duration of this time is grasped in advance by experimental values and is (n × T) sec. Here, n is a natural number, and T is a pointer update period of the decoration device control pattern table developed from the ROM 112 to the RAM 113. For example, when the time required for monitoring the initial position sensor 229 or the closing position sensor 230 is 1 sec and the pointer update period of the decoration device control pattern table is 50 msec, n is 20. In this case, the decoration device IC 220 has a total of two for controlling the LED groups 37a and 37b, one for controlling the accessory driving motors 226a and 226b, and twenty for controlling the initial position sensor 229 or the closed position sensor 230. 23 registers are prepared. The number of registers is not limited to 23, but may be (n + 3) or more.

  In the decoration device control pattern table stored in advance in the ROM 112, data instructing reading of the initial position sensor 229 or the closed position sensor 230 is written in n chunks. Therefore, when the decoration device control pattern table is developed in the RAM 113, reading of information from the initial position sensor 229 or the closed position sensor 230 continues while the pointer position is updated n times. One register is used at a time for controlling the LED groups 37a and 37b or controlling the accessory driving motors 226a and 226b. In contrast, n registers are used at a time to read information from the initial position sensor 229 or the closed position sensor 230. Therefore, once reading of the information of the initial position sensor 229 or the closed position sensor 230 is started, the information of the initial position sensor 229 or the closed position sensor 230 is read continuously for (n × T) sec.

  Monitoring by the initial position sensor 229 and the closed position sensor 230 is not required at the same time. Therefore, as shown in FIG. 31B, the decoration device IC 220 includes (n + 3) registers R1 to R (n + 3). The decoration device IC 220 transmits data for controlling the decoration device written in the order of the registers R1, R2, R3,..., R (n + 3).

  Specifically, the decoration device IC 220 first transmits the address written in the register R1 and data indicating a Read request or a Write request to the communication ICs 224a to 224e. Then, “ACK” data is received from any one of the communication ICs 224a to 224e. If the data transmitted by the decoration device IC 220 indicates a Read request, information from one of the communication ICs 224d and 224e is received, and "ACK" data is returned. If the data transmitted by the decoration device IC 220 indicates a write request, the decoration device control data is written to any one of the communication ICs 224a to 224c, and "ACK" data is received.

  Thereafter, for the registers R2 to R (n + 3), the data for driving the decoration device written in the register Rx is shifted to R (x-1). The decoration device IC 220 repeats this operation until the registers R1 to R (n + 3) become empty. When data for controlling the decoration device is written again from the sub CPU 111 in a state where the registers R1 to R (n + 3) are empty, the operation is resumed until the registers R1 to R (n + 3) are empty. And repeat.

  Separately, a total of two 1-bit registers R (n + 4) and R (n + 5) for storing signals detected by the initial position sensor 229 and the closed position sensor 230 are provided for each sensor. The sub CPU 111 transmits addressed data to four registers for storing the decoration device drive data, and registers R (n + 4) and R (n + 5) for storing the signals detected by the initial position sensor 229 and the closed position sensor 230. The signal detected by the sensor can be read.

  The sound lamp control process performed at a 2 msec cycle will be described with reference to FIG.

  In step S601, it is determined whether a change command has been received. If received, the decoration device drive pattern table stored in the ROM 112 is expanded in the RAM 113 in step S602. The decoration device control pattern table is a table in which data for controlling the decoration device is set in a one-to-one correspondence with the information of the period from when the variable display on the main display unit 33 is started. That is, it is a table in which the decoration device control data is transmitted, the address, the data indicating the Read request or the Write request, and the decoration device control data.

  If a negative determination is made in step S601, the process proceeds to step S603, where it is determined whether or not the change is in progress. If fluctuating, it is determined in step S604 whether it is LED driving timing. If it is the drive timing of the LED group 37a or the LED group 37b, the LED drive data is transmitted to the register with the earliest order among the vacant registers of the decoration device IC 220 in step S605.

  If a negative determination is made in step S604, the process proceeds to step S606 to determine whether it is the opening timing of the door 228. If it is the opening timing of the door 228, the door 228 is opened in step S607.

  On the other hand, if a negative determination is made in step S606, the process proceeds to step S608 to determine whether it is the closing timing of the door 228. If it is the closing timing of the door 228, the door 228 is closed in step S609.

  After setting the decoration device drive pattern table in step S602, after making a negative determination in step S603, after transmitting the LED drive data in step S605, after opening the door 228 in step S607, After making a negative determination in S608 and after closing the door 228 in step S609, the process proceeds to step S610 to perform other processes related to the control of the speaker unit 55 and the control of the display control device 100. The sound lamp control process is terminated.

  Next, the door 228 opening process in step S607 (FIG. 32) will be described with reference to FIG.

  First, in step S701, it is determined whether an initial position sensor reading flag is stored. The initial position sensor reading flag is stored in step S709 of the opening process of the main door 228. The initial position sensor reading flag is a flag indicating a state in which data of the initial position sensor 229 is sent from the communication IC 224d to the decoration device IC 220. If a negative determination is made in step S701, the process proceeds to step S702 to determine the presence / absence of an opening halfway flag. The opening halfway flag is stored in step S705 of the opening process of the main door 228. The opening halfway flag is a flag indicating that the accessory driving motors 226a and 226b are driven and the door 228 is being opened. If a negative determination is made in step S702, the process advances to step S703 to determine whether it is the opening timing of the door 228. This is performed with reference to the decoration device control pattern table developed in the RAM 113. Specifically, when the position of the pointer on the table is at the same position as the data for controlling the accessory driving motors 226a and 226b, it is determined that it is the opening timing of the door 228. If an affirmative determination is made in step S703, motor drive data for driving the accessory driving motors 226a, 226b with reference to the decoration device control pattern table in step S704 is registered in the registers R1 to R of the decoration device IC 220. Of (n + 3), it is vacant and transmitted to the earliest in order, and the release halfway flag is stored in step S705.

  If an affirmative determination is made in step S702 and if the release halfway flag is stored in step S705, the process proceeds to step S706, where it is determined whether it is the read start timing of the initial position sensor 229. The time required for the reading of the initial position sensor 229 is known in advance by experiments. The reading start timing is recorded in the decoration device control pattern table corresponding to the time. If an affirmative determination is made in step S706, the process proceeds to step S707, and the reading request data of the initial position sensor 229 is transmitted to the register of the decoration device IC 220. Specifically, the decoration device control pattern table developed in the RAM 113 is referred to, and the address of the communication IC 224d and data representing the Read request are transmitted to the register of the decoration device IC 220.

  Thereafter, the process proceeds to step S708, and after the release halfway flag is reset, the initial position sensor reading flag is stored in step S709. If an affirmative determination is made in step S701 and if the initial position sensor reading flag is stored in step S709, the process proceeds to step S710 to determine whether or not the initial position sensor 229 is ON. Specifically, the sub CPU 111 reads data written in the register R (n + 4) of the decoration device IC 220 and determines whether or not the initial position sensor 229 is ON. If the initial position sensor 229 is ON in step S710, the reading flag of the initial position sensor 229 is reset in step S711, and the accessory driving motors 226a and 226b are stopped in step S712. The data is transmitted to the register R1 of the decoration device IC 220. The decoration device IC 220 performs processing in order from the data written in R1 in (n + 3) registers. For this reason, when the initial position sensor 229 is turned on, the stop processing of the accessory driving motors 226a and 226b is preferentially performed even during the reading of the initial position sensor. If a negative determination is made in step S703, step S706, or step S710, or data for stopping the accessory driving motors 226a and 226b is transmitted in step S712, the opening process of the main door 228 is terminated.

  Next, the door 228 closing process in step S609 (FIG. 32) will be described with reference to FIG.

  First, in step S801, it is determined whether a closing position sensor reading flag is stored. The closed position sensor reading flag is stored in step S809 of the closing process of the main door 228. The closed position sensor reading flag is a flag indicating a state in which data of the closed position sensor 230 is sent from the communication IC 224e to the decoration device IC 220. If a negative determination is made in step S801, the process proceeds to step S802 to determine the presence or absence of a closing halfway flag. The closing halfway flag is stored in step S805 of the closing process of the main door 228. The closing halfway flag is a flag indicating that the accessory driving motors 226a and 226b are driven and the door 228 is being closed. If a negative determination is made in step S802, the process proceeds to step S803 to determine whether it is the closing timing of the door 228. This is performed with reference to the decoration device control pattern table developed in the RAM 113. Specifically, when the position of the pointer on the table is at the same position as the data for controlling the accessory driving motors 226a and 226b, it is determined that it is the closing timing of the door 228. If an affirmative determination is made in step S803, motor driving data for driving the accessory driving motors 226a, 226b with reference to the decoration device control pattern table in step S804 is stored in the registers R1 to R of the decoration device IC 220. Of (n + 3), it is vacant and transmitted to the earliest in order, and the closing halfway flag is stored in step S805.

  If an affirmative determination is made in step S802 and if the closing halfway flag is stored in step S805, the process proceeds to step S806, where it is determined whether it is the reading start timing of the closing position sensor 230. The time required to read the closed position sensor 230 is previously determined by experiment. The reading start timing is recorded in the decoration device control pattern table corresponding to the time. If an affirmative determination is made in step S806, the process proceeds to step S807, where the reading request data of the closing position sensor 230 is vacant among the registers R1 to R (n + 3) of the decoration device IC 220 and has the earliest order. Send to. Specifically, the decoration device control pattern table developed in the RAM 113 is referred to, and the address of the communication IC 224e and data representing the Read request are transmitted to the register of the decoration device IC 220.

  Thereafter, the process proceeds to step S808, and after the closing flag is reset, the closing position sensor reading flag is stored in step S809. If an affirmative determination is made in step S801 and if the closed position sensor reading flag is stored in step S809, the process proceeds to step S810, and it is determined whether the closed position sensor 230 is ON. Specifically, the sub CPU 111 reads data written in the register of the decoration device IC 220 and determines whether or not the closing position sensor 230 is ON. If the closed position sensor 230 is ON in step S810, the reading flag of the closed position sensor 230 is reset in step S811, and the accessory driving motors 226a and 226b are stopped in step S812. The data is transmitted to the register R1 of the decoration device IC 220. The decoration device IC 220 performs processing in order from the data written in R1 in (n + 3) registers. For this reason, when the closed position sensor 230 is turned on, the stop processing of the accessory driving motors 226a and 226b is preferentially performed even during reading of the closed position sensor. If a negative determination is made in step S803, step S806, or step S810, or data for stopping the accessory driving motors 226a and 226b is transmitted in step S812, the closing process of the main door 228 is terminated.

  Here, communication processing between the communication ICs 224d and 224e and the decoration device IC 220 will be described with reference to FIG. As described above, based on the decoration device control pattern table developed in the RAM 113 of the sub CPU 111, the addresses of the communication ICs 224a to 224e and the decoration device control data are written in the registers R1 to R (n + 3) of the decoration device IC 220. . The decoration device IC 220 receives a clock signal that triggers its operation, the data written from the sub CPU 111 is present in the register R1 at the timing, and the data is the data from the initial position sensor 229 or the closed position sensor 230. This read communication process is performed when the data is for reading.

  First, the decoration device IC 220 issues a start condition in step S901. Thereafter, in step S902, a control byte is transmitted. At this time, in order to request the communication ICs 224d and 224e to transmit the information of the initial position sensor 229 or the closed position sensor 230, data indicating the Read request is transmitted to the initial position sensor 229 or the closed position sensor 230. Send with address. Thereafter, “ACK” data is received from the communication ICs 224d and 224e in step S903, and information on the initial position sensor 229 or the closed position sensor 230 is received from the communication ICs 224d and 224e in step S904.

  In step S905, “ACK” data indicating that the data has been received is transmitted to the communication ICs 224d and 224e, a stop condition is issued in step S906, and the reading communication process is terminated.

  Here, in the pachinko machine 10, the game board 20 is provided with a vibration detection sensor 251 as an abnormality detection means as shown in FIG. The vibration detection sensor 251 is installed on the back side of the game board 20. As an assumed fraudulent act, an act of forcibly putting a game ball into the upper working port 23 and the lower working port 24 by hitting the front door frame 14 to give vibration to the pachinko machine 10 can be considered. On the other hand, when the vibration detection sensor 251 is provided, it is possible to detect an unauthorized act that gives the vibration. The vibration detection sensor 251 is electrically connected to the fraud detection IC 250, and the fraud detection IC 250 is electrically connected to the sub CPU 111 of the sound lamp control device 90 via the bus 240. Then, the detection result of the vibration detection sensor 251 is input to the sub CPU 111 via the fraud detection IC 250. Note that the arrangement position of the vibration detection sensor 251 is not limited to the above, and the vibration detection sensor 251 may be arranged on the front door frame 14 or the back pack unit.

  Next, the fraud monitoring process will be described with reference to the flowchart of FIG.

  In the fraud monitoring process, in step S1001, it is determined whether or not the vibration detection sensor 251 is ON. Specifically, it is determined whether or not a detection signal indicating that vibration has been detected is input from the vibration detection sensor 251. If a negative determination is made in step S1001, the fraud monitoring process is terminated as it is.

  When the vibration detection sensor 251 is ON, an action to force the game ball to be put into the upper operation port 23 and the lower operation port 24 by applying vibration to the pachinko machine 10 is performed. means. Therefore, it progresses to step S1002 and the audio | voice lamp control apparatus 90 performs an abnormality alerting | reporting process. The abnormality notification process is a process for notifying the game hall manager or the like of the occurrence of an error. Specifically, the display lamp unit 54 is turned on in a predetermined manner. Note that the manner of abnormality notification processing is not limited to this, and for example, a predetermined notification sound or notification sound may be output from the speaker unit 55.

  An injustice to force the game ball into the upper operation port 23 and the lower operation port 24 by hitting the front door frame 14 or the like can always occur. Therefore, the vibration detection sensor 251 is a sensor that needs to be constantly monitored. On the other hand, in the pachinko machine 10, the update of up to four decoration device drive data can occur at the same time, such as a combination of the LED groups 37a and 37b, the accessory driving motors 226a and 226b, and the closing position sensor 230. Also in this case, the decoration device drive data written in the register R1 is sequentially transmitted to the communication ICs 224a to 224e. For this reason, the transmission of the decoration device drive data written in the registers R2 to R (n + 3) may be slightly delayed. For this reason, sensors such as the vibration detection sensor 251 that require constant monitoring and are not allowed to be delayed in processing are connected to the sub CPU 111 via another path.

  According to this embodiment mentioned above, it has the following outstanding effects.

  The decoration device IC 220 and the communication ICs 224a to 224e are connected by two bidirectional serial data lines and serial clock lines, and the decoration device drive data is transmitted by designating an address. As a result, the decoration device IC 220 can transmit the necessary amount of data to the necessary portion or receive the necessary amount of data from the necessary portion after receiving the “ACK” data of the communication ICs 224a to 224e. In addition, the wiring can be simplified. As a result, it is possible to reduce the influence of noise caused by the complicated wiring connection configuration.

  In this embodiment, a relay board for controlling the decoration device (LED groups 37a and 37b, accessory driving motors 226a and 226b, initial position sensor 229, and closed position sensor 230) is provided, and the decoration device IC 220 and the relay board are provided. They were connected with two wires. As a result, the number of wires connected to the decoration device IC 220 is reduced, leading to a reduction in cost.

  In the present embodiment, the serial data line and the serial clock line can be branched at an arbitrary location. Therefore, when the decoration device 222a and the decoration device 222b are fixed at positions separated from each other, it is possible to perform wiring while avoiding a portion that is easily affected by noise.

  The accessory driving motors 226a and 226b that move the door 228 that moves symmetrically are connected to one communication IC 224c. Accordingly, when the accessory driving motors 226a and 226b are simultaneously operated, the accessory driving motors 226a and 226b can be simultaneously operated by designating one address and communicating with one communication IC 224c. .

  The LED groups 37a and 37b, the accessory driving motors 226a and 226b, the initial position sensor 229, and the closing position sensor 230 are configured to be driven and controlled by one decoration device IC 220, while the fraud monitoring vibration detection sensor 251 is provided in another path. Thus, the sub CPU 111 is connected. Thereby, even if the (n + 3) registers R1 to R (n + 3) of the decoration device IC 220 are filled, the improper monitoring vibration detection sensor 251 is always effective.

<Other embodiments>
In addition, it is not limited to the description content of embodiment mentioned above, A various deformation | transformation improvement is possible within the range which does not deviate from the meaning of this invention. For example, you may change as follows. Incidentally, the following configuration of another embodiment may be applied individually or in combination to the configuration of the above embodiment.

  (1) In the first embodiment, only the drive control of the LED 173 is performed. However, the present invention is not limited to this. For example, the accessory drive motor 226 may be controlled.

  (2) In the first embodiment, the winning notification light-emitting body 37 includes 12 LEDs 173 and a cover, and only the 12 LEDs 173 are driven by the first drive IC 191 and the second drive IC 193. . The sub CPU 111 sends a series of serial commands to the first drive IC 191 and the second drive IC 193. However, the LED 173 driven by the first drive IC 191 and the second drive IC 193 is not limited to the LED 173 constituting the winning notification light emitter 37. It is good also as a structure which drives LED173 and other decoration LED173 which comprise the light emission body 37 for winning notification by the same series of serial commands. As another decorative LED 173, for example, an LED 173 indicating the expected degree of winning may be provided on the front door frame 14 of the pachinko machine 10.

  For example, the number of LEDs 173 constituting the winning notification light emitter 37 is reduced to six, and the first driving IC 191 is used to drive the six LEDs 173 constituting the winning notification light emitter 37 to be connected to the pseudo drive IC 192. The second driving IC 193 may be used to drive another decorative LED 173.

  From the sub CPU 111 to the drive ICs 191 and 193, the longer the path length of the data line for transmitting the serial command, the higher the possibility of noise. In the first drive IC 191 in which the DATA terminal and the DATAIN terminal of the input port 171 are directly connected, and in the second drive IC 193 in which the pseudo drive IC 192 exists between the DATA terminal and the DATAIN terminal of the input port, the data line path length is short. The first driving IC 191 is less susceptible to noise. By connecting to the first drive IC 191 the LED 173 constituting the winning notification light emitter 37 that is highly interested by the player, the possibility of misunderstanding the player due to noise can be reduced.

  (3) In the first embodiment, the winning notification light-emitting body 37 includes 12 LEDs 173 and a cover, and only the 12 LEDs 173 are driven by the first drive IC 191 and the second drive IC 193. . The sub CPU 111 sends a series of serial commands to the first drive IC 191 and the second drive IC 193. However, the LED 173 driven by the first drive IC 191 and the second drive IC 193 is not limited to the LED 173 constituting the winning notification light emitter 37. The light emitter for notifying abnormality and the light emitter for effect may be driven by the same series of serial commands.

  For example, the light emitter for notifying abnormality may be driven by the first drive IC 191 and the light emitter for production may be driven by the second drive IC 193 connected to the pseudo drive IC 192.

  From the sub CPU 111 to the drive ICs 191 and 193, the longer the path length of the data line for transmitting the serial command, the higher the possibility of noise. In the first drive IC 191 in which the DATA terminal and the DATAIN terminal of the input port 171 are directly connected, and in the second drive IC 193 in which the pseudo drive IC 192 exists between the DATA terminal and the DATAIN terminal of the input port, the data line path length is short. The first driving IC 191 is less susceptible to noise. By connecting a light emitter for notifying abnormality to the first drive IC 191, it is possible to reduce the possibility of misunderstanding the player due to noise.

  (4) In the first embodiment, only two drive ICs, the first drive IC 191 and the second drive IC 193, are used. However, the present invention is not limited to this, and many drive ICs are connected in parallel with respect to the LED drive data SD. Can be used.

  For example, when three drive ICs are used, when different light emission modes are required for each of the three drive ICs, it is necessary to arrange two pseudo drive ICs 192 upstream of the third drive IC.

  In this way, by disposing n−1 drive ICs upstream of the nth drive IC, all the drive ICs can drive the LEDs in different light emission modes.

  (5) In the first embodiment, the drive ICs 191 and 193 and the pseudo drive IC 192 are combined so that all the drive ICs 191 and 193 have different light emission modes. However, the present invention is not limited to this, and a plurality of drive ICs are the same. You may combine so that it may become a light emission mode. In this case, it is necessary to arrange the same number of pseudo drive ICs 192 upstream of the drive ICs having the same light emission mode.

  (6) In the first embodiment, the first drive IC 191 and the second drive IC 193 are in a parallel relationship with respect to the LED drive data SD. However, the present invention is not limited to this. A combination of connection and series connection may be used. For example, in the first embodiment, the DATAOUT terminal of the second drive IC 193 may be connected to the DATAIN terminal of another new LED drive IC.

  (7) In the first embodiment, the LED drive data SD written to the first drive IC 191 and the second drive IC 193 is shifted in time, and different data is written to the first drive IC 191 and the second drive IC 193. Therefore, a pseudo drive IC 192 having the same internal configuration as the first drive IC 191 and the second drive IC 193 is used. However, the method for causing a time lag in the LED drive data SD written to the first drive IC 191 and the second drive IC 193 is not limited to this, and the data storage means has an internal configuration different from that of the first drive IC 191 and the second drive IC 193. May be used. Specifically, the pseudo drive IC 192 in the first embodiment may be configured to leave the update buffer 192c except for the register 192b. In this case as well, as in the case of using the pseudo drive IC 192, the LED drive data SD passes through the data areas D8 to DA of the update buffer 192c and is written to the second drive IC. For this reason, a time lag occurs in the LED drive data SD written to the first drive IC 191 and the second drive IC 193, and different data can be written.

  (8) In the first embodiment, the first drive IC 191, the pseudo drive IC 192, and the second drive IC 193 are configured on the same substrate. However, the present invention is not limited to this, and the first drive IC 191 and the pseudo drive IC 192 are provided. In addition, the second driving IC 193 may exist on another substrate.

  (9) In the second embodiment, the LED groups 37a and 37b connected to the two LED drive ICs of the first drive IC 191 and the second drive IC 193 are driven. It is good also as a structure which drives two or more LED groups 37a, 37b, .... In this case, as shown in FIG. 37, the signal line of the clock signal is first connected to the T terminal of the T flip-flop, and the signal output from the output terminal (Q terminal) is defined as the clock signal (A). Further, the signal output from the output terminal (Q terminal) of the T flip-flop is input to the D terminal of the negative edge trigger type D flip-flop, the original clock signal is input to the clock terminal of the D flip-flop, and the D A signal output from the output terminal (Q terminal) of the flip-flop is a clock signal (B).

  As shown in FIG. 38, one cycle of the clock signal (A) and the clock signal (B) is twice the cycle of the original clock signal. Further, the clock signal (A) and the clock signal (B) are shifted by a half cycle of the original clock signal. Therefore, after the clock signal (A) rises, the clock signal (B) rises after a half cycle of the original clock signal, and the clock signal (A) falls after a half cycle of the original clock signal. The clock signal (B) falls with a delay of a half cycle of the clock signal. Thereafter, the clock signal (A) rises again with a delay of half a cycle of the original clock signal, and the same rise and fall are repeated.

  For the clock signal (A), two types of buffers, an update buffer composed of a positive edge trigger type D flip-flop and an update buffer composed of a negative edge trigger type D flip flop, are prepared. For B), a total of four types of update buffers can be prepared by preparing two types of update buffers.

  On the other hand, Ax, Bx, Cx, Ex, A (x-1), B (x-1), C (x-1), E (x-1),. , A (x-7), B (x-7), C (x-7), and E (x-7), as shown in the table of FIG. The data areas D0 to D7 of the update buffer A are A0 to A7, the data areas D8 to D15 of the update buffer B are B0 to B7, the data areas D16 to D23 of the update buffer C are C0 to C7, and the update Data E0 to E7 are written in the data areas D24 to D31 of the buffer E, respectively. Thereafter, the four types of LED driving ICs can be controlled by transmitting a data write signal.

  (10) In the third embodiment, the L terminal of the input port 171 and the T terminal of the positive edge trigger type T flip-flop are connected, and the Q terminal of the T flip-flop and the register 191b of the first drive IC 191 are connected. The clock terminal of the D flip-flop to be configured is connected, the L terminal of the input port 171 and the T terminal of the negative edge trigger type T flip-flop are connected, and the Q terminal of the T flip-flop and the register 193b of the second driving IC 193 are connected. Was connected to the clock terminal of the D flip-flop. However, the present invention is not limited to this, and the L terminal of the input port 171 and the clock terminal of the D flip-flop constituting the register 191b of the first drive IC 191 are connected, and the L terminal of the input port 171 and the register 193b of the second drive IC 193 are constructed. Alternatively, an inverting circuit may be connected between the clock terminals of the D flip-flops. In this case, after data is written to the register 193b of the second drive IC 193, it is not necessary to raise and lower the data write signal SG2 regardless of the data write.

  Specifically, as in the third embodiment, when the LED drive data SD of A7 to A0 is transmitted and then the data write signal SG2 is raised, the clock of the D flip-flop constituting the register 191b of the first drive IC 191 Data written to the terminal rises from “0” to “1”. On the other hand, data written to the clock terminal of the D flip-flop constituting the register 193b of the second driving IC 193 falls from “1” to “0”. Therefore, the data A7 to A0 is written only in the register 191b of the first drive IC 191. Thereafter, when the LED drive data SD of B7 to B0 is transmitted and the data write signal SG2 falls, the data written to the clock terminal of the D flip-flop constituting the register 191b of the first drive IC 191 changes from “1” to “0”. ”. On the other hand, the data written to the clock terminal of the D flip-flop constituting the register 193b of the second driving IC 193 rises from “0” to “1”. Therefore, the data B7 to B0 is written only in the register 193b of the second driving IC 193.

  When a series of writing is completed, the data written to the clock terminals of the D flip-flop constituting the register 191b of the first driving IC 191 and the D flip-flop constituting the register 193b of the second driving IC 193 returns to the initial state. Therefore, the LED drive data SD can be written next without raising or lowering the data write signal SG2.

  (11) In the fourth embodiment, the initial position sensor 229 or the closed position sensor 230 is included in the decoration device control pattern table in order to secure a predetermined monitoring period by the initial position sensor 229 or the closed position sensor 230. However, the method of making the monitoring period constant is not limited to this. When the decoration device IC 220 transmits a Read request when transmitting the control byte, a timer corresponding to a predetermined monitoring period is started, and the decoration device IC 220 performs the next communication until the monitoring period ends. There may be no configuration. Only when the initial position sensor 229 or the closed position sensor 230 is turned on, a process for stopping the accessory driving motors 226a and 226b is performed. Also in this case, only reading of data from the initial position sensor 229 or the closed position sensor is performed for a predetermined time without being interrupted by communication related to driving of the LED groups 37a and 37b and the accessory driving motors 226a and 226b. Is called.

  (12) In the fourth embodiment, one decoration device IC 220 and five communication ICs 224a to 224e communicate with each other. However, the present invention is not limited to this, and a plurality of decoration device ICs 220 and five It is good also as a structure which communicates with communication IC. For example, a first decoration device IC that communicates with the communication ICs 224a to 224c and a second decoration device IC that communicates with the communication ICs 224d and 224e may be prepared. In this case, since the reading of data from the initial position sensor 229 and the reading of data from the closing position sensor 230 do not occur at the same time, the second decoration device IC has a predetermined time, the initial position sensor 229 or Data can be continuously read from the closed position sensor 230. In parallel, the first decoration device IC can transmit data to the LED groups 37a and 37b or the accessory driving motors 226a and 226b.

  (13) In the fourth embodiment, the LED group 37a is connected to the communication IC 224a, and the LED group 37b is connected to the communication IC 224b. In addition, the two accessory driving motors 226a and 226b are connected to one communication IC 224c. Not limited to this, the LED group 37a and the accessory driving motor 226a may be connected to one communication IC 224a, and the LED group 37b and the accessory driving motor 226b may be connected to one communication IC 224b. As described above, the number of communication ICs 224a to 224e can be reduced by connecting to the output terminals not connected to the LED groups 37a and 37b among the output terminals of the communication ICs 224a and 224b. In addition, the degree of freedom of the combination of the decoration devices connected to the communication ICs 224a to 224e is increased.

<Invention Group Extracted from the Embodiments>
Hereinafter, the features of the invention group extracted from the above-described embodiments will be described while showing effects and the like as necessary. In the following, for easy understanding, the corresponding configuration in the above embodiment is appropriately shown in parentheses and the like, but is not limited to the specific configuration shown in parentheses and the like.

<Feature A group>
Feature A1. Predetermined element driving means (first driving IC 191) for driving the element (LED 173);
Element control means (sound lamp control) which is electrically connected to the predetermined element driving means and controls the elements by outputting predetermined driving data (LED driving data SD) to the predetermined element driving means via wiring. A function of executing an audio lamp control process in the apparatus 90);
With
In the gaming machine in which the predetermined element driving unit drives the element in a mode corresponding to the driving data when the driving data is input from the element control unit.
A data storage means (pseudo drive IC 192) having no drive target is provided, and data that has passed through the data storage means is supplied to the predetermined element drive means that is electrically connected to the data storage means. A gaming machine.

  According to the feature A1, since the drive data that has passed through the data storage means is supplied to the element drive means, the element control means collectively outputs the drive data corresponding to each of the plurality of element drive means as a series of data. Even in this case, it is possible to cause a deviation in the data range supplied to each element driving means due to the presence of the data storage means. Accordingly, even if a series of data is simultaneously supplied to each of the element driving units, it is possible to supply corresponding driving data to each of the element driving units. It is possible to reduce the influence of noise while appropriately performing the above.

  Feature A2. As the data storage means in which the drive target does not exist, element drive means in which a part of the output terminal is connected to the input terminal of the predetermined element drive means and the other output terminals are all open is used. The gaming machine according to Feature A1.

  According to the feature A2, since the internal configuration of the data storage means having no drive target is the same as the element driving means that actually drives the elements, it becomes possible to control the driving of a plurality of elements only by combining the element driving means. . For this reason, assembly is easy.

  Feature A3. The gaming machine according to feature A2, wherein the data storage means is an element driving means having the same structure as the predetermined element driving means.

  According to the feature A3, it is possible to achieve the excellent effect as described above only by arranging the same element driving means.

  Feature A4. In the drive data supply path from the element control means, the element drive means where the drive target exists does not exist upstream of the data storage means and downstream of the predetermined element drive means. A gaming machine according to any one of A3 to A3.

  According to the feature A4, there is no element driving means in which the driving target exists either upstream or downstream of the element driving means in which the driving target exists. For this reason, it is difficult to generate an event in which noise is generated collectively for a plurality of element driving units.

Feature A5. In addition to the predetermined element driving means, a specific element driving means (second driving IC 193) for driving the element is provided,
The element control means supplies the same drive data to each of a predetermined control object including the data storage means and the predetermined element driving means and a specific control object including the specific element driving means,
Since the data storage means for which no drive target exists does not exist in the specific control target or the number of the data storage means for which no drive target exists is smaller than the predetermined control target, the predetermined control target at the predetermined timing The game machine according to any one of features A1 to A4, wherein the data stored in the data storage means and the data supplied to the specific element driving means are the same.

  According to the feature A5, since the number of data storage means having no drive target is different between the predetermined control target and the specific control target, even if the same drive data is supplied from the element control means, It is possible to cause a shift in the data range supplied to the specific control target. As a result, the predetermined control target and the specific control target can be driven in different manners by the same drive data.

Feature A6. In the predetermined control target, there is an element driving means on the drive data supply path from the element control means on the upstream side of the data storage means and the downstream side of the predetermined element driving means. Without
In the specific control target, there is no element drive means in the drive data supply path from the element control means on the upstream side and downstream side of the specific element drive means. A gaming machine according to Feature A5.

  According to the feature A6, in any control target, there is only one element driving unit in which the drive target exists, so that the influence of noise is reduced.

  Feature A7. A use trigger signal (data write signal SG2) for providing a trigger to use the drive data supplied to the predetermined element drive means and the specific element drive means for driving the elements in each element drive means, The gaming machine according to the feature A5 or A6, further comprising an element driving means and a use opportunity supplying means for supplying the element driving means and the specific element driving means simultaneously or substantially simultaneously.

  According to the feature A7, since the use trigger signal is supplied to the predetermined element driving unit and the specific element driving unit simultaneously or substantially simultaneously, the timing of driving the elements in the predetermined element driving unit and the specific element driving unit can be performed simultaneously or substantially simultaneously. .

  Feature A8. An acquisition trigger signal (clock signal SG1) for providing a trigger for acquiring drive data in the predetermined element driving means and the specific element driving means is supplied to the predetermined element driving means and the specific element driving means simultaneously or substantially simultaneously. The gaming machine according to any one of features A5 to A7, further comprising an acquisition opportunity supply unit.

  According to the feature A8, the acquisition trigger signal is supplied to the predetermined element driving unit and the specific element driving unit simultaneously or substantially simultaneously. Therefore, data acquisition is performed simultaneously or substantially simultaneously in a state where the data range of the drive data supplied to the predetermined element driving unit and the specific element driving unit is different, and the predetermined element driving unit and the specific element are differently configured It becomes possible to control the driving means.

Feature A9. The data storage means in which the element driving means and the driving target do not exist,
A drive data acquisition unit (DATAIN terminal) that acquires element drive data output by the element control means each time a predetermined acquisition timing is reached, and sets the acquired element drive data in a predetermined storage area When,
A drive data transmission unit (DATAOUT terminal) for transmitting the element drive data stored in the storage area every time a predetermined transmission timing is reached;
With
The gaming machine according to any one of features A1 to A8, wherein the acquisition timing and the transmission timing are set to be different.

  According to the feature A9, since the element drive data acquisition timing and the transmission timing are different in the element drive means and the data storage means in which no drive target exists, it is possible to avoid an error in which data rewrite and output occur simultaneously. Become.

Feature A10. A clock means for outputting a clock signal in which an HI level signal and a LOW level signal are switched alternately;
The clock means is electrically connected in parallel to the data storage means and the element driving means;
The gaming machine according to any one of features A1 to A10, wherein the element driving data is updated and the element driving data is acquired in response to the switching of the clock signal.

  According to the feature A10, it is possible to reduce a shift in the transmission of the clock signal by connecting the clock signal in parallel to each driving unit and simultaneously outputting the clock signal. As a result, the deviation of the element drive data acquisition timing between the drive units is reduced.

  Note that any one or more of the features A1 to A10, the features B1 to B5, the features C1 to C2, and the features D1 to D6 may be applied to any one of the features A1 to A10. . Thereby, it becomes possible to produce a synergistic effect by the combined configuration.

<Feature B group>
Feature B1. Element driving means (first driving IC 194, second driving IC 195) for driving the element (LED 173);
Element control means (function for executing sound lamp control processing in the sound lamp control device 90) for supplying drive data for driving the element to the element driving means;
An acquisition trigger supply means for supplying an acquisition trigger signal (clock signal SG1) for providing a drive trigger for acquiring drive data to the element driving means;
With
As the element driving means,
First element driving means (first driving IC 194) for acquiring the driving data when the signal of the first aspect is received as the acquisition trigger signal;
Second element driving means (second driving IC 195) for acquiring the driving data when the signal of the second mode is received as the acquisition trigger signal;
A gaming machine characterized by comprising:

  According to the feature B1, the first element driving unit and the second element driving unit are supplied from the element control unit by supplying the acquisition trigger signal of the first mode and the acquisition trigger signal of the second mode while being shifted in time. The drive data acquisition timing can be shifted. As a result, even if a series of data is simultaneously supplied to each element driving means, it becomes possible to supply corresponding driving data to each element driving means. It is possible to reduce the influence of noise while performing supply appropriately.

  Feature B2. The element control means supplies drive data for the first element driving means to the first element driving means when the acquisition trigger signal becomes the signal of the first mode, and the acquisition trigger signal is the second trigger signal. The gaming machine according to Feature B1, wherein when the signal is an aspect signal, drive data for the second element driving means is supplied to the second element driving means.

  According to the feature B2, the element control unit may supply each element driving unit with one type of element driving data in which the element driving data for the first element driving unit and the element driving data for the second element driving unit are arranged. . For this reason, the freedom degree of the wiring which connects an element control means and each element drive means can be raised. By selecting a place where noise is unlikely to occur and performing wiring, the influence of noise can be reduced.

  Feature B3. The acquisition trigger supply means outputs, as the acquisition trigger signal, a signal in which the state of the first mode and the state of the second mode are repeated, both of the first element driving unit and the second element driving unit. The gaming machine according to Feature B1 or B2, wherein the gaming machine is supplied to

  According to the feature B3, one acquisition trigger signal repeats the first mode and the second mode. For this reason, there is no need to separately supply the acquisition trigger signal of the first aspect and the acquisition trigger signal of the second aspect, and the element drive data is acquired by the first element driver and the second element driver with one acquisition trigger signal. It is possible to give an opportunity.

Feature B4. The acquisition trigger signal is a signal in which a HI level signal and a LOW level signal are alternately repeated,
The first aspect is a rising from the LOW level signal to the HI level signal,
The gaming machine according to Feature B3, wherein the second aspect is a fall from the HI level signal to the LOW level signal.

  According to the feature B4, the first element driving means obtains element driving data in response to the rising from the LOW level signal to the HI level signal, and the second element driving in response to the falling from the HI level signal to the LOW level signal. The means can acquire element drive data.

  Feature B5. The element control means alternately supplies data to be supplied to the first element driving means and data to be supplied to the second element driving means in response to rising and falling edges of the acquisition trigger signal. The gaming machine according to Feature B4, wherein the set driving data is supplied to both the first element driving unit and the second element driving unit.

  According to the feature B5, the element control means sets the same drive data in which the data for the first element drive means and the data for the second element drive means are alternately arranged corresponding to the rise and fall of the acquisition trigger signal. By supplying each element driving means, only the driving data for the first element driving means can be written in the first element driving means, and only the driving data for the second element driving means is written in the second element driving means. be able to.

  Note that one or more configurations of the features A1 to A10, the features B1 to B5, the features C1 to C2, and the features D1 to D6 may be applied to the configurations of the features B1 to B5. Thereby, it becomes possible to produce a synergistic effect by the combined configuration.

<Feature C group>
Feature C1. A first element driving means (first driving IC 191) and a second element driving means (second driving IC 193) for driving the element (LED 173);
Element control means (function for executing sound lamp control processing in the sound lamp control device 90) for supplying drive data for driving the elements to each element driving means;
A use trigger signal (data write signal SG2) for providing a trigger for using the drive data supplied to each element drive means for driving the element in each element drive means is the first element drive means and the Utilization opportunity supply means for supplying both to the second element driving means;
The timing that becomes a signal mode indicating that the usage trigger signal supplied to the first element driving means is a usage trigger, and the usage trigger signal supplied to the second element driving means is a usage trigger. At least one of the usage trigger signal supplied to the first element driving means and the usage trigger signal supplied to the second element driving means is adjusted so that the timing of the signal mode indicating the timing is different. Signal adjusting means (T flip-flop);
A gaming machine characterized by comprising:

  According to the characteristic C1, the timing which becomes a signal mode which shows that a utilization opportunity signal is a utilization opportunity by signal adjustment means differs between each element drive means. For this reason, even if the element control means supplies the same drive data to each element drive means, since the acquisition timing differs between the element drive means, each element drive means obtains different drive data. That is, the element driving means can control the first element driving means and the second element driving means in different manners with one type of driving data. For this reason, the freedom degree of the wiring which connects an element control means and each element drive means can be raised. By selecting a place where noise is unlikely to occur and performing wiring, the influence of noise can be reduced.

Feature C2. The usage trigger signal is a signal in which a HI level signal and a LOW level signal are alternately repeated,
The signal mode indicating the use opportunity is one of a rise from the LOW level signal to the HI level signal and a fall from the HI level signal to the LOW level signal.
In the signal adjusting means, the relationship between the HI level signal and the LOW level signal of the use trigger signal supplied to each element driving means is opposite between the first element driving means and the second element driving means. The gaming machine according to Feature C1, characterized in that:

  According to the feature C2, the first element driving unit and the second element driving unit separately acquire drive data in response to a rise from the LOW level signal to the HI level signal and a fall from the HI level signal to the LOW level signal. be able to. The element control means can control each element driving means in a different manner only by supplying one type of signal in which the LOW level signal and the HI level signal are alternately repeated.

  Note that one or more configurations of the features A1 to A10, the features B1 to B5, the features C1 to C2, and the features D1 to D6 may be applied to the configurations of the features C1 to C2. Thereby, it becomes possible to produce a synergistic effect by the combined configuration.

<Feature D group>
Feature D1. A plurality of electrical components (LED groups 37a and 37b, accessory driving motors 226a and 226b, initial position sensor 229, closed position sensor 230) constituting the gaming machine;
Control means (sound lamp control device 90) for performing a predetermined operation in the gaming machine using the electrical parts;
In a gaming machine equipped with
A plurality of communication means (communication ICs 224a to 224e) provided corresponding to the electrical components and having unique addresses are provided.
The control means includes
Setting means for setting predetermined data corresponding to the communication means to be communicated among the plurality of communication means (function for executing step S602 in the sound lamp control device 90);
Based on predetermined data set by the setting means, an address transmission means (function for executing steps S502 and S902 in the decoration device IC 220) for transmitting address data to the plurality of communication means;
After the address data is transmitted by the address transmitting unit, after transmission to perform post-transmission processing that is at least one of data transmission corresponding to the communication target communication unit and data reception from the communication target communication unit Means (function of executing steps S504 and S904 in the decoration device IC 220);
A gaming machine characterized by comprising:

  According to the feature D1, the control unit includes an address transmission unit that transmits address data to the communication unit and a post-transmission unit that executes post-transmission processing. The communication means has a unique address and is provided corresponding to the electrical component. Therefore, the control unit can transmit data for driving the electrical component or receive data from the electrical component via the communication unit identified by the address. As a result, the communication system can be configured to output from the same line, and the number of communication paths from the control means can be suppressed. In addition, the influence of noise can be suppressed.

Feature D2. The control means includes
A process for executing a predetermined operation in the gaming machine based on the control data, a process execution unit (sub CPU111) having the setting unit;
Communication with the plurality of communication means based on the processing result by the process execution means, the communication execution means (decorative device IC 220) having the address transmission means and the post-transmission means,
A gaming machine according to the feature D1, characterized by comprising:

  According to the feature D2, the control unit includes a process execution unit and a communication execution unit. For this reason, the process of setting predetermined data corresponding to the communication means to be communicated by the process execution means and the transmission of address data and post-transmission processing by the communication execution means can be performed in parallel.

Feature D3. The communication execution means includes storage means (registers R1 to R (n + 3)) capable of storing a plurality of the predetermined data.
The gaming machine according to claim D2, wherein the address transmission unit uses the predetermined data stored in the storage unit as a trigger for transmitting the address data in accordance with a setting order.

  According to the feature D3, the predetermined data is stored in the storage unit of the communication execution unit, and the address transmission unit starts transmitting the address data in the order in which the predetermined data is stored in the storage unit. For this reason, the processing content of the communication execution means is unified, and the configuration can be simplified.

Feature D4. As the electrical component, provided with detection means (initial position sensor 229, closed position sensor 230) for detecting the occurrence of a predetermined event,
When the detection means uses the detection result of the detection means, the control means maintains a communication state with a predetermined communication means corresponding to the detection means over a predetermined detection period. The gaming machine according to any one of the above.

  According to the feature D4, when using the detection result of the detection unit, the communication state with the predetermined communication unit corresponding to the detection unit is maintained over a predetermined detection period. Thereby, the detection result by a detection means can be utilized for a predetermined period, without being disturbed by communication of other electrical components.

  Feature D5. When the control unit uses the detection result of the detection unit, the setting unit corresponds to the predetermined communication unit so that a communication state with the predetermined communication unit is maintained over the detection period. A gaming machine according to Feature D4, wherein a plurality of data are set.

  According to the feature D5, when the detection result of the detection unit is used over a predetermined period, the setting unit sets a plurality of data for the communication unit corresponding to the detection unit in the storage unit. Thereby, it is possible to maintain the communication state with the predetermined communication means for a set number of times.

Feature D6. An abnormality detection means (vibration detection sensor 251) for detecting the occurrence of an abnormal event is provided,
The detection result of the abnormality detection unit is transmitted to the control unit through a communication path different from the communication path between the plurality of communication units and the control unit. The gaming machine according to 1.

  According to the feature D6, the communication path between the abnormality detection unit and the control unit is secured separately from the communication path between the communication unit and the control unit. Therefore, the detection result of the abnormality detection means is transmitted to the control means even during communication between the communication means and the control means. For this reason, even if an abnormality occurs at any timing, the control means can always grasp the abnormality.

  Note that any one or more of the features A1 to A10, the features B1 to B5, the features C1 to C2, and the features D1 to D6 may be applied to any one of the features D1 to D6. . Thereby, it becomes possible to produce a synergistic effect by the combined configuration.

  The invention of the feature A group, the invention of the feature B group, the invention of the feature C group, and the invention of the feature D group can solve the following problems.

  For example, in a gaming machine such as a pachinko machine, a plurality of elements used in various games such as a light emitting element and an electric movable element are provided on a game board, a front portion of a housing, and the like as a means for enhancing the interest of the game. The element is controlled in accordance with the game situation by a control device that controls the game. In addition, a drive circuit is mounted as an element driving means for driving the element, and the drive circuit is connected to the control device via, for example, a wiring, and when a control signal is input from the control device. , Configured to drive corresponding elements.

  Here, in the gaming machine such as the above-described example, a configuration capable of suitably performing communication between the control means and the element is required, and there is still room for improvement in this respect.

  The above-described problem is a problem common to gaming machines including a plurality of elements and element driving means for driving each element.

  The basic configuration of the gaming machine to which the above features can be applied is shown below.

  Pachinko gaming machine: operation means operated by a player, game ball launching means for launching a game ball based on the operation of the operation means, a ball path for guiding the launched game ball to a predetermined game area, and a game A gaming machine that includes each gaming component arranged in an area, and gives a bonus to a player when a gaming ball passes through a predetermined passing portion of each gaming component.

  A spinning machine such as a slot machine: the rotation of the circulating body is started based on the operation of the start operation means, the rotation of the circulating body is stopped based on the operation of the stop operation means, and the player is made according to the pattern after the stop. A gaming machine that grants bonuses.

DESCRIPTION OF SYMBOLS 10 ... Pachinko machine, 37a, 37b ... LED group, 110 ... Sub CPU, 173 ... LED, 191, 194 ... First drive IC, 192 ... Pseudo drive IC, 193, 195 ... Second drive IC, 220 ... For decoration device ICs, 224a to 224e, communication ICs, 226a, 226b, accessory driving motors, 229, initial position sensors, 230, closed position sensors, 251, vibration detection sensors.

Claims (1)

Predetermined element driving means for driving the element;
Element control means electrically connected to the predetermined element driving means and controlling elements by outputting predetermined driving data to the predetermined element driving means via wiring;
With
In the gaming machine in which the predetermined element driving unit drives the element in a mode corresponding to the driving data when the driving data is input from the element control unit.
A specific element driving means that is provided separately from the predetermined element driving means and drives the element;
Data storage means for which there is no drive target;
With
The data passing through the data storage means is supplied to the predetermined element driving means electrically connected to the data storage means,
The element control means supplies the same drive data to each of a predetermined control object including the data storage means and the predetermined element driving means and a specific control object including the specific element driving means,
Since the data storage means for which no drive target exists does not exist in the specific control target or the number of the data storage means for which no drive target exists is smaller than the predetermined control target, the predetermined control target at the predetermined timing The data stored in the data storage means and the data supplied to the specific element driving means are the same,
The gaming machine transmits a use trigger signal for providing a trigger to use the driving data supplied to the predetermined element driving unit and the specific element driving unit for driving the element in each element driving unit. A gaming machine comprising: a drive means and a use opportunity supply means for supplying the specific element drive means simultaneously or substantially simultaneously.

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