JP4593613B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4593613B2 JP4593613B2 JP2007324561A JP2007324561A JP4593613B2 JP 4593613 B2 JP4593613 B2 JP 4593613B2 JP 2007324561 A JP2007324561 A JP 2007324561A JP 2007324561 A JP2007324561 A JP 2007324561A JP 4593613 B2 JP4593613 B2 JP 4593613B2
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- soi
- semiconductor device
- chip
- insulating film
- oxide film
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H—ELECTRICITY
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
本実施の形態は、パッケージを大型化することなく、大電流化、高耐圧化に対応したHVICチップを収めることが可能な半導体装置を実現するものである。
本実施の形態も、パッケージを大型化することなく、大電流化、高耐圧化に対応したHVICチップを収めることが可能な半導体装置を実現するものである。
本実施の形態は、実施の形態1にかかる半導体装置における第1および第2のSOI−HVICチップ1,2のSOI層に形成された集積回路の構造に特徴を有する半導体装置である。
本実施の形態も、実施の形態1にかかる半導体装置における第1および第2のSOI−HVICチップ1,2のSOI層に形成された集積回路の構造に特徴を有する半導体装置である。
本実施の形態は、実施の形態2にかかる半導体装置における第1および第2のSOI−HVICチップ1,2の配置構造に特徴を有する半導体装置である。
本実施の形態は、ウェハの反りの発生を抑制しつつ、高耐圧特性に必要な埋め込み酸化膜の厚膜化を図ることが可能な半導体装置を実現するものである。
本実施の形態は、実施の形態6の変形例である。図7は、本実施の形態にかかる半導体装置を示す図である。なお、図7では実施の形態6にかかる半導体装置と同様の機能を有する要素については同一符号を付している。
実施の形態6および7において記述された補償酸化膜15は、図8に示すように、台座シリコン基板14のウェハに熱酸化法やCVD法等を施すことにより形成することができる。そして、ウェハをダイシングすることにより各台座シリコン基板14が得られる。
本実施の形態は、補償酸化膜15に代わってシリコンラダー系樹脂17を台座シリコン基板14の酸化膜として用いる他の例である。実施の形態8においては、シリコンラダー系樹脂17は、第1のSOI−HVICチップ1の凹み部1d内に埋められた後にベークされたが、本実施の形態においては、後述するように台座シリコン基板14のウェハにシリコンラダー系樹脂17を形成してベークした後、ダイシングすることにより各台座シリコン基板14を得る。
以上、本発明の実施の形態を詳細に開示し記述したが、以上の記述は本発明の適用可能な局面を例示したものであって、本発明はこれに限定されるものではない。即ち、記述した局面に対する様々な修正や変形例を、この発明の範囲から逸脱することの無い範囲内で考えることが可能である。
Claims (5)
- それぞれ電極を含む第1および第2の回路が形成されたシリコン層と、埋め込み絶縁膜と、前記埋め込み絶縁膜が露出する凹み部が前記第1の回路の形成領域に対応する部分に形成された支持基板とが、この順に積層された構成を有するSOIチップと、
表面に絶縁膜が形成された台座基板と
を備え、
前記絶縁膜が前記埋め込み絶縁膜に接合されつつ前記台座基板が前記凹み部内に収まったことを特徴とする、
半導体装置。 - 請求項1に記載の半導体装置であって、
複数の配線が形成された表面を有し、前記複数の配線に前記第1および第2の回路内の前記電極が電気的に接続されつつ、前記SOIチップを支持するダイパッド
をさらに備え、
前記台座基板の厚さは前記凹み部の深さに略等しいことを特徴とする、
半導体装置。 - 請求項1に記載の半導体装置であって、
前記SOIチップおよび前記台座基板を支持するダイパッド
をさらに備え、
前記台座基板を前記SOIチップが覆うように、前記SOIチップの前記支持基板が前記ダイパッド上に接着され、
前記台座基板の厚さは前記凹み部の深さに略等しいことを特徴とする、
半導体装置。 - 請求項1に記載の半導体装置であって、
前記台座基板の前記絶縁膜はシリコンラダー系樹脂であることを特徴とする、
半導体装置。 - 請求項1に記載の半導体装置であって、
前記絶縁膜の端部にはテーパーが付き、
前記凹み部の壁面には傾斜が存在し、
前記テーパーの角度と前記傾斜の角度とは略等しく、
前記絶縁膜の前記端部は前記凹み部の前記壁面に接していることを特徴とする、
半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007324561A JP4593613B2 (ja) | 2007-12-17 | 2007-12-17 | 半導体装置 |
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Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007324561A JP4593613B2 (ja) | 2007-12-17 | 2007-12-17 | 半導体装置 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2000206568A Division JP4142235B2 (ja) | 2000-07-07 | 2000-07-07 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008085371A JP2008085371A (ja) | 2008-04-10 |
JP4593613B2 true JP4593613B2 (ja) | 2010-12-08 |
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ID=39355817
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007324561A Expired - Fee Related JP4593613B2 (ja) | 2007-12-17 | 2007-12-17 | 半導体装置 |
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JP (1) | JP4593613B2 (ja) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0555454A (ja) * | 1991-08-22 | 1993-03-05 | Honda Motor Co Ltd | 半導体装置と、その製造方法 |
JP2001320014A (ja) * | 2000-05-11 | 2001-11-16 | Seiko Epson Corp | 半導体装置及びその製造方法 |
-
2007
- 2007-12-17 JP JP2007324561A patent/JP4593613B2/ja not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0555454A (ja) * | 1991-08-22 | 1993-03-05 | Honda Motor Co Ltd | 半導体装置と、その製造方法 |
JP2001320014A (ja) * | 2000-05-11 | 2001-11-16 | Seiko Epson Corp | 半導体装置及びその製造方法 |
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JP2008085371A (ja) | 2008-04-10 |
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