JP4593526B2 - Semiconductor device screening method and semiconductor device - Google Patents

Description

  The present invention relates to a screening method for a semiconductor device including an insulated gate transistor having a plating electrode, and a semiconductor device to be screened.

  A semiconductor device including an insulated gate transistor having a plated electrode is disclosed in, for example, Japanese Patent Application Laid-Open No. 2002-110981 (Patent Document 1).

  FIG. 6 is a schematic cross-sectional view of the semiconductor device 90 disclosed in Patent Document 1. As shown in FIG.

A semiconductor device 90 shown in FIG. 6 is a semiconductor device composed of a high-power N-channel MOS transistor (Metal Oxide Semiconductor transistor). The semiconductor device 90 includes an N + semiconductor substrate 91, an N-type drain layer 93 formed on the N + semiconductor substrate 91, a P-type base layer 95 formed on the surface portion of the N-type drain layer 93, and a P-type base. And an N-type source layer 97 formed on the surface portion of the layer 95. Further, the semiconductor device 90 includes a metal formed of a trench-type gate wiring layer 13 on the main surface side, an AL electrode layer 17 connected to the source, and a metal material solderable on the surface of the AL electrode layer 17. A plating layer (plating electrode) 37 is provided, and a drain electrode 19 is formed on the back side. In the semiconductor device 90, the lead terminals of the package can be soldered via the metal plating layer 37, and the semiconductor device is a low-resistance semiconductor device.
Japanese Patent Laid-Open No. 2002-110981

  FIG. 7 shows a subthreshold characteristic (Vg) of a sample in which a thermal degradation test was performed on a semiconductor device made of an IGBT (Insulated Gate Bipolar Transistor) having a plated electrode similar to that of the semiconductor device 90 of FIG. -Ic) is a diagram showing the number of thermal cycles as a parameter.

  As shown in FIG. 7, in the sample in which the characteristic deterioration occurs, the threshold voltage is greatly reduced compared to the initial value so as not to show a clear threshold voltage, and the leakage collector current Ic becomes lower than the specified gate voltage Vg. It will begin to flow. Samples with such characteristic deterioration need to be screened (removed) by inspection before shipping, but screening by a thermal cycle test before shipping requires a test period of one week or more and has a large in-process inventory. It will be.

  Accordingly, the present invention provides a screening method for a semiconductor device comprising an insulated gate transistor having a plated electrode, which can obtain a screening result equivalent to a thermal endurance test in a short time, and use of the screening method An object of the present invention is to provide a suitable semiconductor device.

According to a first aspect of the present invention, a gate electrode of an insulated gate transistor is formed on a main surface side of a semiconductor substrate, an interlayer insulating film is formed on the gate electrode and on the semiconductor substrate , and at least one current terminal An electrode is formed on the interlayer insulating film, and the current terminal electrode on the main surface side includes a lower first metal layer and an upper second metal layer formed by plating, in the vicinity of the gate electrode, through a connection hole formed in the interlayer insulating film formed on the gate electrode, the first metal layer is connected to a predetermined area adjacent to the gate electrode, the second metal in the upper of said connecting hole the height of the lowest point of the layers, the method of screening for an interlayer insulating semiconductor device is higher than the set height comprising a film, a predetermined negative electric to the gate electrode with respect to the current terminal electrodes of said main surface After applying the predetermined time, by applying a predetermined positive potential to the gate electrode detects a current flowing through the current terminal electrode, the height of the quality of the lowest point of the second metal layer from the detected current value It is characterized by judging.

  A semiconductor device including an insulated gate transistor having a plating electrode can be a low-resistance semiconductor device because a lead terminal of a package can be soldered through a metal plating layer. On the other hand, there is a sample of the semiconductor device that deteriorates in a thermal endurance test. In the sub-threshold characteristic of the sample, the threshold voltage is greatly reduced as compared with the initial value so that a clear threshold voltage is not observed, and a leaky collector current Ic flows at a gate voltage Vg lower than the standard.

The inventors have a semiconductor device having a current terminal electrode composed of a lower first metal layer and an upper second metal layer formed by plating, and is formed on the gate electrode in the vicinity of the gate electrode. through a connection hole formed in the interlayer insulating film that is, the first metal layer is connected to a predetermined area adjacent to the gate electrode, the lowest point of the second metal layer above the said connecting hole The above-described cooling and heat durability test was performed on a semiconductor device in which the height was set higher than the height of the interlayer insulating film . As a result, in the sample in which the degradation of the subthreshold characteristic occurs, it is found that a current flows at a low Vg in a minute region of the semiconductor element, and the high point of the lowest point of the second metal layer above the connection hole is found at that point. However, the height of the lowest point of the second metal layer is lower than the height of the interlayer insulating film, although the height is set higher than the height of the interlayer insulating film in the design. The lower point entered the inside of the connection hole. Further, the second metal layer that has entered the inside of the connection hole has entered the inside in a state inclined with respect to the connection hole, and has been in contact with the interlayer insulating film around the connection hole.

  In the semiconductor device, the lowest point of the second metal layer enters the inside of the connection hole even though the lowest point of the second metal layer is set higher than the height of the interlayer insulating film by design. There are two possible causes for this sample. That is, the first metal layer in the lower layer is not sufficiently embedded in the connection hole formed in the interlayer insulating film, and in the previous step of forming the upper second metal layer by plating, the surface cleaning solution or the like is used first. It is considered that this is because the formed first metal layer is etched. The reason why the subthreshold characteristic deteriorates in the sample in which the second metal layer enters the inside in a state inclined with respect to the connection hole and the second metal layer contacts the interlayer insulating film around the connection hole is that the second metal layer deteriorates. Since the hardness of the first metal layer is different from that of the first metal layer, the second metal layer moves relative to the cooling cycle and is inclined with respect to the connection hole, and the second metal layer in contact with the interlayer insulating film is in the vicinity. This is considered to be caused by stress applied to the gate electrode.

The screening method for a semiconductor device according to the present invention reversely utilizes the characteristics of a sample whose subthreshold characteristics deteriorate in the above-described thermal durability test. In the above screening method, a negative predetermined potential is applied to the gate electrode for a predetermined time with respect to the current terminal electrode on the main surface side, the upper layer of which is the second metal layer formed by plating, and the height of the lowest point of the second metal layer is increased. determining the difference in quality. That is, in the sample in which the lowest point of the second metal layer enters the inside of the connection hole, the sodium ion remaining near the lowest point of the second metal layer is applied by applying a negative predetermined potential to the gate electrode for a predetermined time. Cations contained in the plating solution such as (Na +) are attracted to the negative potential of the gate electrode and drawn into the gate insulating film, thereby degrading the subthreshold characteristics. As a result, it is possible to screen a sample in which the lowest point of the second metal layer enters the inside of the connection hole and the subthreshold characteristic is likely to deteriorate. According to the screening method, since it is not necessary to perform a thermal endurance test, the evaluation is completed in a short time, and there is no stock in the process.

  As described above, the screening method of the semiconductor device is a screening method of a semiconductor device including an insulated gate transistor having a plating electrode, and can obtain a screening result equivalent to the thermal durability test in a short time. It is a screening method.

  In the screening method, as described in claim 2, the negative predetermined potential is preferably −5 [V] or less. This makes it easier for the cations contained in the plating solution remaining near the lowest point of the second metal layer to be drawn into the gate insulating film, promoting the deterioration of the subthreshold characteristics, and ensuring more reliable screening results. And the test time can be shortened.

  On the other hand, in the above screening method, a predetermined negative potential is applied to the gate electrode of the insulated gate transistor. Therefore, if the applied voltage is too large, the life of the gate electrode is deteriorated. For this reason, in the screening method, as described in claim 3, the negative predetermined potential is preferably −30 [V] or more. In particular, as described in claim 4, the negative potential is The predetermined potential is preferably −20 [V] or higher. Thereby, the lifetime deterioration of the gate electrode by the said screening method can be suppressed.

  In the screening method, as described in claim 5, it is preferable that the negative predetermined potential is applied at a high temperature of room temperature to 200 [° C.]. This also facilitates the movement of cations contained in the plating solution remaining in the vicinity of the lowest point of the second metal layer to promote the deterioration of the subthreshold characteristics, making the screening result more reliable and the test time. Can be shortened.

  In particular, as described in claim 6, when the negative predetermined potential is applied at a high temperature of 100 [° C.] or higher and 150 [° C.] or lower, the packaged semiconductor device is screened. be able to.

  In the screening method, as described in claim 7, the predetermined time may be 10 [min] or less. By appropriately setting the negative potential applied to the gate electrode and the environmental temperature, the lowest point of the second metal layer enters the inside of the connection hole even when the application time is a short time of 10 [min] or less, It is possible to reliably screen a sample whose subthreshold characteristic is likely to deteriorate.

  Regarding the quality determination of the semiconductor device in the screening method, the sub-threshold characteristic of the semiconductor device may be measured, but in order to reduce the measurement time, the quality determination as described in claim 8, It is preferable to apply a positive predetermined potential at two potential values and determine the quality of the semiconductor device from each detected current value. As a result, it is possible to reliably screen in a short time a deteriorated sample of the subthreshold characteristic in which the leaked collector current Ic flows at a gate voltage Vg lower than the standard. Since the pass / fail judgment is performed using the two potentials and the detected current value, even if there is some variation in the initial threshold voltage of the semiconductor device, only the deteriorated sample is reliably screened. be able to.

  On the other hand, when there is almost no variation in the initial threshold voltage of the semiconductor device, the positive predetermined potential is applied at a single potential value in the pass / fail judgment as described in claim 9. The time required for screening can be further reduced by comparing the detected current value with the reference current value to determine whether the semiconductor device is good or bad.

  The invention described in claims 10 to 15 is an invention of a semiconductor device suitable for use in the screening method.

11. The semiconductor device according to claim 10, wherein a gate electrode of an insulated gate transistor and an interlayer insulating film are formed on the gate electrode and on the semiconductor substrate on the main surface side of the semiconductor substrate , and at least one of the currents. A terminal electrode is formed on the interlayer insulating film, and the current terminal electrode on the main surface side includes a lower first metal layer and an upper second metal layer formed by plating, in the vicinity of the gate electrode. , via said connection holes formed in an interlayer insulating film formed on the gate electrode, a semiconductor device formed by connecting in a predetermined area of the first metal layer is adjacent to the gate electrode, the connecting The height of the lowest point of the second metal layer above the hole is set higher than the height of the interlayer insulating film, and the gate electrode has a breakdown voltage of −10 [V] or less. With features To have.

In the semiconductor device, the height of the lowest point of the second metal layer above the connection hole is set higher than the height of the interlayer insulating film formed on the gate electrode at the design stage, The lowest point is basically prevented from entering the inside of the connection hole, thereby suppressing the deterioration of the subthreshold characteristic after the thermal endurance. In addition, the first metal layer is not sufficiently embedded in the connection hole, or the first metal layer is etched by a surface cleaning solution or the like in the pre-process of forming the second metal layer by plating. When the lowest point of the layer has penetrated into the connection hole, the sample can be screened by the screening method described above. In the semiconductor device, since the gate electrode has a withstand voltage of −10 [V] or less, the lifetime of the gate electrode is deteriorated even when a negative potential of −5 to −10 [V] is applied to the gate electrode. Can be suppressed.

  As described above, the semiconductor device is a semiconductor device suitable for use in the screening method described above.

  Particularly in the semiconductor device, as described in claim 11, it is preferable that the gate electrode has a withstand voltage of −20 [V] or less. In the semiconductor device, even when a negative potential of −10 to −20 [V] is applied to the gate electrode, the life deterioration of the gate electrode can be suppressed and a deteriorated sample is reliably screened in a short time. be able to.

  The first metal layer in the semiconductor device can be made of aluminum or an aluminum alloy having low conductivity and high conductivity as described in claim 12, for example.

  Further, the second metal layer in the semiconductor device can be made of nickel or a nickel alloy that is inexpensive and has good solderability, for example, as described in claim 13.

  The semiconductor device can be configured, for example, such that the insulated gate transistor is a MOS transistor, and the current terminal electrodes on the main surface side are a source electrode and a drain electrode. However, the present invention is not limited to this, and the semiconductor device includes, for example, as claimed in claim 14, wherein the insulated gate transistor is an IGBT, and the current terminal electrode on the main surface side is an emitter electrode of the IGBT. Also good.

  The gate electrode in the semiconductor device may be a gate electrode having a general planar structure. However, the present invention is not limited to this, and the gate electrode may be a gate electrode having a trench structure.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

  First, the result of investigating the internal structure of the sample whose subthreshold characteristic has deteriorated in the thermal durability test shown in FIG. 7 will be described.

  1A and 1B are schematic cross-sectional views showing the internal structure of the semiconductor device 100 before the thermal endurance test. FIG. 1A shows a normal sample whose subthreshold characteristics are not deteriorated by the thermal endurance test. FIG. 1B shows the state of the abnormal sample 100a in which the subthreshold characteristic is deteriorated by the thermal durability test. FIG. 2 is a schematic cross-sectional view showing a state after the thermal endurance test of the abnormal sample 100b having deteriorated subthreshold characteristics.

  The semiconductor device subjected to the thermal endurance test of FIG. 7 is a semiconductor device in which an IGBT having a trench gate structure is formed on a semiconductor substrate mainly composed of the N− region 4 as shown in FIG. In semiconductor device 100 made of IGBT, in order to fix the potential of P− region 3 as a channel formation region, N + region 1 as an emitter region, and the channel formation region on the main surface side of semiconductor substrate (N− region) 4. P + region 2 is formed. A P region 5 that is a collector region is formed on the back side of the semiconductor substrate (N− region) 4.

  A gate electrode 8 of a semiconductor device (IGBT) 100 formed on the main surface side of the semiconductor substrate 4 serves as a gate electrode of a trench structure, and enters the trench 6 via a sidewall oxide film 7 which is a gate oxide film. It has a structure in which polysilicon 7 or the like which is a gate electrode is embedded. Emitter electrodes 10 and 12 which are one current terminal electrodes of the semiconductor device (IGBT) 100 are formed on the main surface side of the semiconductor substrate 4, and the semiconductor device (IGBT) 100 is formed on the back surface side of the semiconductor substrate 4. A collector electrode 11 which is the other current terminal electrode is formed. The emitter electrode on the main surface side of the semiconductor device 100 includes a lower first metal layer 10 and an upper second metal layer 12 formed by plating. The first metal layer 10 can be made of aluminum or an aluminum alloy having low conductivity and high conductivity, for example, and has a thickness of 4 μm, for example. The second metal layer 12 can be made of, for example, nickel or a nickel alloy that is inexpensive and has good solderability. The emitter electrodes 10 and 12 are provided in a predetermined region (N + region) of the semiconductor substrate 4 through a connection hole h formed in the interlayer insulating film 9 having a thickness of, for example, 800 nm on the semiconductor substrate 4 in the vicinity of the gate electrode 8. 1 and P + region 2).

  As described above, the semiconductor device 100 shown in FIG. 1A is a semiconductor device having a plating electrode (second metal layer 12). Since the semiconductor device 100 made of an IGBT having the plated electrode (second metal layer 12) can solder-connect the package lead terminals via the metal plated layer (second metal layer 12), it has a low resistance. A semiconductor device can be obtained. On the other hand, as shown in FIG. 7, the semiconductor device 100 of FIG. In the sub-threshold characteristic of the sample, the threshold voltage is greatly reduced as compared with the initial value so that a clear threshold voltage is not observed, and a leaky collector current Ic flows at a gate voltage Vg lower than the standard.

  It was found that the cross section of the portion where leakage current flows at a low Vg of the sample whose subthreshold characteristics deteriorated after the thermal endurance test is in the state of the abnormal sample 100b shown in FIG.

  In the abnormal sample 100a of FIG. 1B, the second metal layer 12 is formed in a wedge shape by slits and voids existing on the surface of the first metal layer 10 above the connection holes h, and the second metal layer 12 The height of the lower point was lower than the height of the interlayer insulating film 9, and the lowest point of the second metal layer 12 entered the inside of the connection hole h formed in the interlayer insulating film 9. Further, in the sample 100b whose subthreshold characteristics deteriorated after the thermal endurance test of FIG. 2, the second metal layer 12 that has entered the inside of the connection hole h enters the inside in a state inclined with respect to the connection hole h. It was in contact with the interlayer insulating film 9 around the connection hole h.

  In the semiconductor device 100, the height of the lowest point of the second metal layer 12 is set higher than the height of the interlayer insulating film 9 as shown in FIG. As shown in b), there are the following two causes for the generation of the sample 100a in which the lowest point of the second metal layer 12 has entered the inside of the connection hole h. That is, the first metal layer 10 in the lower layer is not sufficiently embedded in the connection hole h formed in the interlayer insulating film 9, and the surface cleaning liquid is formed in the previous step of forming the upper second metal layer 12 by plating. It is considered that this is because the first metal layer 10 formed earlier is etched.

  Further, in the sample 100b in which the second metal layer 12 shown in FIG. 2 enters the inside in a state inclined with respect to the connection hole h, and the second metal layer 12 contacts the interlayer insulating film 9 around the connection hole h, The reason why the subthreshold characteristic is deteriorated as shown in FIG. 7 is considered as follows. That is, in the sample 100a in which the lowest point of the second metal layer 12 shown in FIG. 1B enters the inside of the connection hole h, the second metal layer 12 is indicated by a black arrow in the drawing by the cooling and heating cycle. The second metal layer 12 that moves in the direction horizontal to the substrate surface and enters the connection hole h is inclined with respect to the connection hole h during the cooling and heating cycle. If it moves further, the second metal layer 12 that contacts the interlayer insulating film 9 during the cooling / heating cycle exerts stress on the gate electrode 8 in the vicinity, thereby degrading the subthreshold characteristics as shown in FIG. It is done.

  Next, a screening method for the semiconductor device 100 of the present invention will be described.

  FIG. 3 is a diagram schematically showing a screening test of the semiconductor device 100. FIG. 4 is a diagram comparing the sub-threshold characteristics after the screening test with those of the samples whose sub-threshold characteristics have deteriorated as a result of the screening test of FIG. FIG. 5 is a diagram schematically showing the detection principle of the characteristic deterioration of FIG.

  The screening method for the semiconductor device 100 shown in FIG. 3 and FIG. 4 uses the characteristics of the sample 100a in FIG. 1B, in which the subthreshold characteristics deteriorate in the above-mentioned thermal endurance test. In the screening method shown in FIGS. 3 and 4, in the screening test of FIG. 3, the upper layer of the semiconductor device 100 is formed on the gate electrode 8 with respect to the current terminal electrode (emitter electrode) on the main surface side made of the second metal layer 12 by plating. After the negative predetermined (bias) potential Vs is applied for a predetermined time, the sub-threshold characteristic of FIG. 4 is measured, for example, and the quality of the semiconductor device 100 is determined. FIG. 5 shows a sample 100a in which the lowest point of the second metal layer 12 shown in FIG. 1B enters the inside of the connection hole h by applying a negative predetermined potential Vs to the gate electrode 8 for a predetermined time. Thus, cations i contained in the plating solution such as sodium ions (Na +) remaining in the vicinity of the lowest point of the second metal layer are attracted to the negative potential Vs of the gate electrode 8 and drawn into the gate insulating film 7. As a result, the subthreshold characteristic is degraded as shown in FIG.

  The initial state shown in FIG. 4 and the subthreshold characteristics after the screening test in FIG. 3 show similar tendencies to the initial state shown in FIG. 7 and the subthreshold characteristics after the thermal cycle. Therefore, the screening method shown in FIGS. 3 and 4 can screen the sample of FIG. 1B in which the lowest point of the second metal layer 12 penetrates into the connection hole h and the subthreshold characteristic is likely to deteriorate. it can. According to the above screening method, since it is not necessary to perform a thermal endurance test, the evaluation is completed in a short time, and there is no stock in the process.

  In the screening test of FIG. 3, the negative predetermined potential Vs applied to the gate electrode 8 of the semiconductor device 100 is preferably −5 [V] or less. As a result, the cation i contained in the plating solution remaining near the lowest point of the second metal layer 12 is easily drawn into the gate insulating film 7, promoting the deterioration of the subthreshold characteristics and further improving the screening result. The test time can be shortened while ensuring the reliability.

  On the other hand, in the screening test of FIG. 3, a negative predetermined potential Vs is applied to the gate electrode 8 of the insulated gate transistor, so that if the applied voltage is too large, the life of the gate electrode 8 is deteriorated. Therefore, in the above screening method, the negative predetermined potential Vs is preferably −30 [V] or higher, and particularly preferably −20 [V] or higher. Thereby, the lifetime deterioration of the gate electrode 8 by the said screening method can be suppressed.

  For example, when the semiconductor device 100 whose gate electrode 8 has a breakdown voltage of −10 [V] or less is used for the screening test, a negative potential Vs of −5 to −10 [V] may be applied to the gate electrode 8. In addition, the life deterioration of the gate electrode 8 can be suppressed. In particular, when the semiconductor device 100 whose gate electrode 8 has a breakdown voltage of −20 [V] or less is used for the screening test, a negative potential Vs of −10 to −20 [V] is applied to the gate electrode 8. In addition, it is possible to suppress the life deterioration of the gate electrode 8 and to reliably screen a deteriorated sample in a short time.

  In the screening test of FIG. 3, it is preferable to apply the negative predetermined potential Vs at a high temperature of not less than room temperature and not more than 200 [° C.]. This also facilitates the movement of cations i contained in the plating solution remaining in the vicinity of the lowest point of the second metal layer 12 to promote the deterioration of the subthreshold characteristics, making the screening result more reliable, Test time can be shortened. In particular, when the negative predetermined potential Vs is applied at a high temperature of 100 [° C.] or higher and 150 [° C.] or lower, the packaged semiconductor device 100 can be screened.

  As illustrated in FIGS. 3 and 4, in the above screening method, the application time of the negative predetermined potential Vs may be 10 [min] or less. By appropriately setting the negative potential applied to the gate electrode 8 and the ambient temperature, the lowest part of the second metal layer 12 shown in FIG. It is possible to surely screen the sample 100a in which the point penetrates into the connection hole h and the subthreshold characteristic is likely to deteriorate.

  Further, regarding the quality determination of the semiconductor device 100 in the screening method, the subthreshold characteristic of the semiconductor device 100 may be measured as shown in FIG. However, the present invention is not limited to this, and in order to shorten the measurement time, the positive predetermined potential Vg is applied at, for example, two potential values indicated by alternate long and short dash lines A and B in FIG. It is preferable to determine whether the device 100 is good or bad. As a result, it is possible to reliably screen in a short time a deteriorated sample of the subthreshold characteristic in which the leaked collector current Ic flows at a gate voltage Vg lower than the standard. In the pass / fail judgment, the pass / fail judgment is made with the two potentials and the detected current value, so even if there is some variation in the initial threshold voltage of the semiconductor device 100, only the deteriorated sample is reliably screened. be able to.

  On the other hand, when there is almost no variation in the initial threshold voltage of the semiconductor device 100, the positive predetermined potential Vg is applied at, for example, the potential value at one point indicated by the one-dot chain line A in FIG. By comparing the value with the reference current value to determine whether the semiconductor device 100 is good or bad, the time required for screening can be further shortened.

  As described above, the screening method for the semiconductor device 100 shown in FIGS. 3 and 4 is a screening method for a semiconductor device including an insulated gate transistor having a plated electrode, and is equivalent to the thermal durability test in a short time. This is a screening method capable of obtaining a screening result.

  In the embodiment and FIG. 1, an N-channel IGBT is shown, but a P-channel IGBT or MOS in which an N-type region and a P-type region are interchanged may be used. At that time, the sign of voltage application in the sentence is reversed. 3 and 4, the semiconductor device 100 is made of an IGBT and the evaluation portion is the emitter electrode that is the current terminal electrode on the main surface side. However, the evaluation portion is the current terminal electrode on the main surface side. There may be a certain source electrode and drain electrode. Thus, in the above-described screening method for a semiconductor device of the present invention, the screening target may be an arbitrary insulated gate transistor, and the evaluation portion may be an arbitrary current terminal electrode formed by plating on the main surface side. Further, although the gate electrode 8 of the semiconductor device 100 is a gate electrode having a trench structure, the screening method of the present invention can be applied to a semiconductor device having a gate electrode having a general planar structure.

FIG. 2 is a schematic cross-sectional view showing an internal structure of a semiconductor device 100 before a thermal endurance test, where (a) shows a state of a normal sample 100 in which subthreshold characteristics are not deteriorated by a thermal endurance test, and (b) shows a thermal endurance This is a state of the abnormal sample 100a in which the subthreshold characteristic is deteriorated by the test. It is typical sectional drawing which shows the state after the cooling-heat durability test of the abnormal sample 100b in which the subthreshold characteristic deteriorated. 3 is a diagram schematically showing a screening test of the semiconductor device 100. FIG. It is the figure which showed the subthreshold characteristic after the screening test compared with the initial stage about the sample which the subthreshold characteristic deteriorated as a result of the screening test of FIG. It is the figure which showed typically the detection principle of the characteristic degradation of FIG. 10 is a schematic cross-sectional view of a semiconductor device 90 disclosed in Patent Document 1. FIG. FIG. 7 is a diagram showing a sub-threshold characteristic of a sample in which a cooling endurance test is performed on a semiconductor device made of an IGBT having a plated electrode similar to the semiconductor device 90 of FIG. 6, using the number of cooling cycles as a parameter.

Explanation of symbols

100 Semiconductor device (normal sample)
100a Semiconductor device (abnormal sample)
100b Semiconductor device (abnormal sample with degraded subthreshold characteristics)
DESCRIPTION OF SYMBOLS 1 N + area | region 2 P + area | region 3 P- area | region 4 N- area | region 5 P area | region 6 Trench 7 Gate oxide film 8 Gate electrode 9 Interlayer insulating film 10 1st metal layer (emitter electrode)
11 Collector electrode 12 Second metal layer (emitter electrode)
i cations

Claims (15)

A gate electrode of an insulated gate transistor and an interlayer insulating film are formed on the gate electrode and the semiconductor substrate on the main surface side of the semiconductor substrate , and at least one current terminal electrode is formed on the interlayer insulating film. And
The main surface side current terminal electrode comprises a lower first metal layer and an upper second metal layer formed by plating,
In the vicinity of the gate electrode , the first metal layer is connected to a predetermined region adjacent to the gate electrode through a connection hole formed in an interlayer insulating film formed on the gate electrode, and the connection hole A method of screening a semiconductor device , wherein the height of the lowest point of the second metal layer above the upper portion is set higher than the height of the interlayer insulating film ,
After applying a negative predetermined potential to the gate electrode for a predetermined time with respect to the current terminal electrode on the main surface side, a positive predetermined potential is applied to the gate electrode to detect a current flowing through the current terminal electrode, A screening method for a semiconductor device, comprising: determining whether the height of the lowest point of the second metal layer is good or bad from a detected current value.   2. The method for screening a semiconductor device according to claim 1, wherein the predetermined negative potential is −5 [V] or less.   The method for screening a semiconductor device according to claim 2, wherein the negative predetermined potential is −30 [V] or more.   The semiconductor device screening method according to claim 3, wherein the predetermined negative potential is −20 [V] or more.   5. The method for screening a semiconductor device according to claim 1, wherein the negative predetermined potential is applied at a high temperature of room temperature to 200 ° C. 5.   6. The method of screening a semiconductor device according to claim 5, wherein the negative predetermined potential is applied at a high temperature of 100 [° C.] or higher and 150 [° C.] or lower.   7. The method for screening a semiconductor device according to claim 5, wherein the predetermined time is 10 [min] or less.   8. The quality determination is performed by applying the positive predetermined potential at two potential values, and determining the quality of the semiconductor device from each detected current value. A method for screening a semiconductor device as described in 1. above.   2. The quality determination is performed by applying the positive predetermined potential at a single potential value and comparing the detected current value with a reference current value to determine whether the semiconductor device is good or bad. 8. The method for screening a semiconductor device according to claim 7. A gate electrode of an insulated gate transistor and an interlayer insulating film are formed on the gate electrode and the semiconductor substrate on the main surface side of the semiconductor substrate , and at least one current terminal electrode is formed on the interlayer insulating film. And
The main surface side current terminal electrode comprises a lower first metal layer and an upper second metal layer formed by plating,
A semiconductor device in which the first metal layer is connected to a predetermined region adjacent to the gate electrode through a connection hole formed in an interlayer insulating film formed on the gate electrode in the vicinity of the gate electrode Because
The height of the lowest point of the second metal layer above the connection hole is set higher than the height of the interlayer insulating film,
The semiconductor device, wherein the gate electrode has a withstand voltage of −10 [V] or less.   The semiconductor device according to claim 10, wherein the gate electrode has a withstand voltage of −20 [V] or less.   The semiconductor device according to claim 10, wherein the first metal layer is made of aluminum or an aluminum alloy.   The semiconductor device according to claim 10, wherein the second metal layer is made of nickel or a nickel alloy. The insulated gate transistor is an IGBT;
The semiconductor device according to claim 10, wherein the main surface side current terminal electrode is an emitter electrode of the IGBT.   The semiconductor device according to claim 10, wherein the gate electrode is a gate electrode having a trench structure.

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