JPH09152463A - Method for testing degradation life of compound semiconductor device and method for evaluating reliability of compound semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correctly detect in a short time a change when a gate is deteriorated and broken, by repeatedly impressing a stress-impressing bias to a transistor and impressing a lower bias thereby measuring a deterioration characteristic until the gate is deteriorated. SOLUTION: A test apparatus consists of a CPU 1, a measuring device 2, an input device 3, a main memory device 4, etc. A semiconductor device is set to the measuring device 2. A stress bias is impressed to the semiconductor device and a characteristic of the semiconductor device is measured. When a stress is impressed, the stress bias is applied for a predetermined time to a transistor. When a deterioration characteristic is measured, a measuring circuit is switched, so that a deterioration characteristicmeasuring bias lower than the stress bias is applied between a gate and a drain of the transistor thereby measuring a gate current. The impressing of the stress and the measuring of the deterioration characteristic are repeatedly carried out until the gate is deteriorated. The dependency of the gate current and an accumulated time when the stress is impressed is obtained, which is displayed in a graph or the like at a display 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for testing the deterioration life of a compound semiconductor device, and more particularly to semi-insulating gallium arsenide (GaA).
s) HIGFET (Heterostructure In) formed on the substrate
sulated Gate Field-Effect Transistor: a technology effective when applied to the deterioration life test of a heterostructure insulated gate field effect transistor).

[0002]

2. Description of the Related Art A semiconductor device (semiconductor device) is subjected to a reliability test (reliability evaluation) such as screening after manufacturing in order to determine the quality of the product. Further, in order to know the deterioration life of the product, a deterioration life test for measuring the state until the product is broken is performed.

In the reliability test and the deterioration life test, the semiconductor device is tested by applying voltage stress. In the degradation life test, the breakdown life has a bias dependency, and the higher the stress application bias, the shorter the breakdown life time.Therefore, in order to shorten the test time, a large stress application bias is applied to the semiconductor device to perform the degradation life test. Etc. are being accelerated.

Regarding the reliability test, for example,
"Electronic Information and Communication Handbook" published by Ohmsha, March 1988
Issued 30 days, described in P973 to P975.

The environmental test method and durability test method for semiconductor integrated circuits are described in JIS-C-7022-1979.

Known semiconductor devices are those using a silicon substrate and those using a compound semiconductor substrate such as a semi-insulating gallium arsenide substrate.

A heterostructure insulated gate field effect transistor (HIGFET) is known as a semiconductor device using a semi-insulating gallium arsenide substrate. GaAsHIGF
ET is described in "Ultra High Speed Compound Semiconductor Devices", P120 and P121, published by Baifukan.

[0008]

The applicant of the present invention also
According to the conventional deterioration life test method described above, GaA
The gate reliability of sHIGFET is evaluated.

That is, when the reliability of the gate of the GaAs HIGFET is evaluated, in order to accelerate the voltage to the gate-drain voltage (Vdg) of the FET, the gate current (I) is applied while applying a large bias between the gate and the drain.
g) is monitored to evaluate the deterioration and breakdown of the gate.

In this case, in the graph showing the correlation between the stress applying bias and the breakdown life time shown in FIG. 8, the bias region a to be evaluated is a region where the stress applying bias is high, for example, the gate length (Lg) is 0.3 μm. GaA
In the case of sHIGFET, the deterioration life test is performed in the high bias region of 7 to 8V.

On the other hand, the present inventors have found that GaAs HIGFET
As a result of various analysis and examination in the voltage stress application test, the new characteristic deterioration phenomenon (degradation mode) was found.

This new degradation mode is characterized by the gate current (I) in the region where the gate-drain voltage (Vdg) is large.
g) is small, and the gate-drain voltage (Vd
It is characterized in that the change of the gate current (Ig) is large in the region where g) is small.

That is, the present inventors investigated the correlation between the gate-drain voltage (Vdg) and the gate current (Ig) before and after applying the stress application bias.

FIG. 9 shows Vdg-I obtained by the present inventors.
It is a graph which shows the correlation of g. As can be seen from this graph, it was found that the gate current greatly increases (for example, about several mA) in the low gate voltage region in the product in which the gate deterioration occurs. In this case, in the reliability test by the conventional high bias application in which the gate current (Ig) is monitored at the portion where the gate-drain voltage (Vdg) is high (for example, about 7 to 8 V), the change in the gate current is small, It can be seen that the detection of deterioration is difficult.

From the above, it is difficult to find the start of the gate deterioration by the conventional deterioration life test method in which the stress applying bias is set to a high bias, and the deterioration is performed until the gate is almost completely destroyed. It cannot be confirmed, and the deterioration life test requires a lot of time.

Therefore, the present inventor applies a high bias to the FET, and then detects the presence or absence of an increase in the gate current (Ig) at a low bias, which clearly shows the deterioration of the FET, whereby the gate is degraded at an early point. The present invention has been made on the basis that it is possible to know.

An object of the present invention is to provide a deterioration life test technique capable of accurately detecting the transition of gate deterioration / breakdown of a compound semiconductor field effect transistor.

Another object of the present invention is to provide a reliability evaluation method capable of detecting gate deterioration evaluation of a compound semiconductor field effect transistor in a short time.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0020]

The following is a brief description of an outline of typical inventions disclosed in the present application.

(1) A deterioration life test method for a compound semiconductor device, wherein a stress application bias is applied between a gate and a drain of a GaAs HIGFET and a gate current is monitored to perform a deterioration life test of the gate. A stress applying step of applying a bias for a predetermined time, a deterioration detecting step of switching a measurement circuit to measure a deterioration characteristic lower than the stress applying bias, and measuring a gate current by applying a bias between a gate and a drain of a transistor; The step of determining the dependency between the gate current and the cumulative stress application time is repeated by repeating the applying step and the deterioration characteristic measuring step until the gate is deteriorated. First, a deterioration characteristic measurement bias lower than the stress application bias is applied between the gate and the drain to detect the initial gate current, and then the stress application bias is applied to the transistor. A reverse voltage is applied to the gate as the stress application bias, and a reverse bias or a forward bias lower than the stress application bias is applied as the deterioration characteristic measurement bias.

(2) A reliability evaluation method for a compound semiconductor device, wherein a stress application bias is applied between the gate and the drain of a GaAs HIGFET and the gate current is monitored to evaluate the quality of the deterioration / destruction of the gate. A stress applying step of applying a stress applying bias for a predetermined time, and a deterioration characteristic measuring step of measuring a gate current by applying a deterioration detection bias lower than the stress applying bias between the gate and drain of the transistor,
An evaluation step of evaluating the quality of the field effect transistor from the gate current. A reverse voltage is applied to the gate as the stress application bias, and a reverse bias or a forward bias lower than the stress application bias is applied as the deterioration characteristic measurement bias.

According to the above-mentioned means (1), GaAsHI
After applying a stress applying bias between the gate and the drain of the GFET for a predetermined time, the measurement circuit is switched to apply a deterioration characteristic measuring bias lower than the stress applying bias between the gate and the drain of the transistor to measure the gate current, Moreover, since the dependency of the gate current and the cumulative time of stress application is obtained by repeating the stress applying step and the deterioration characteristic measuring step until the gate is deteriorated, the gate (gate insulating film The deterioration (deterioration) of () can be accurately measured.

According to the above-mentioned means (2), GaAsHI
After applying a stress applying bias between the gate and the drain of the GFET for a predetermined time, the measurement circuit is switched to apply a deterioration characteristic measuring bias lower than the stress applying bias between the gate and the drain of the transistor to measure the gate current, At this stage, the quality of the product can be evaluated based on whether or not the gate current has increased, so it is possible to evaluate the quality of the gate in a shorter time than the conventional reliability evaluation method that monitors the gate current while applying a high bias. Will be more likely.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

In all the drawings for explaining the embodiments of the invention, components having the same function are designated by the same reference numeral, and the repeated description thereof will be omitted.

FIG. 1 is a flow chart showing a deterioration life test method of a compound semiconductor device according to one embodiment of the present invention, and FIG. 2 is a correlation between a gate current and a cumulative stress application time obtained by the deterioration life test method of this embodiment. Showing the graph,
FIG. 3 is a block diagram showing the configuration of the test apparatus of this embodiment, FIG.
FIG. 5 is a circuit diagram when a deterioration characteristic measurement bias is used in the present embodiment, and FIG. 6 is a circuit diagram showing a bias applying circuit section in the present embodiment.

In this embodiment, the test apparatus shown in FIG. 3 is used. The test device is a central processing unit (CPU) 1,
It comprises a measuring instrument 2, an input device 3, a main storage device 4, an auxiliary storage device 5, and a display 6 and a printer 7 which are output devices, which are respectively connected to the CPU 1.

A semiconductor device is attached to a socket or the like, which is the measuring section of the measuring device 2, and a stress applying bias is applied. In addition, the characteristics of the semiconductor device when an applied bias is measured.

Measurement conditions and the like are input in advance by the input device 3. The measurement result is displayed on the display 6 and is printed out from the printer 7 if necessary.

The measuring device 2 has a bias applying circuit as shown in FIG. That is, the semiconductor device 9 to be measured, for example, a GaAs HIGFET (Q) having a gate length of 0.3 μm is attached to the measuring section 10 such as a socket.

The source (S) terminal 11S of the measuring section 10
Are connected to the ground 20 by the wiring 12.

Drain (D) terminal 11D of the measuring section 10
At the tip of the wire 13 connected to
Is connected. The changeover switch 14 has a wiring 13a for connecting the wiring 13 to the ground 20 or a wiring 13b in which a high power source 15 is incorporated by the switching.
Is to be connected to.

An ammeter 17 and a variable power supply 18 are incorporated between the wiring 16 between the gate (G) terminal 11G of the measuring section 10 and the ground 20.

GaAs is applied to such a bias applying circuit section.
The HIGFET 9 is attached and gate evaluation is performed.

The deterioration life test method of the present embodiment is carried out according to the flow chart shown in FIG. That is, the GaAs HIGFET 9 is attached to the measuring section 10 shown in FIG.

Next, the initial characteristics are measured as shown in the flow chart. For this initial characteristic, for example, as shown in the circuit diagram of FIG. 5, a low voltage (reverse voltage) is applied to only the gate (G) of the GaAs HIGFET 9 by the variable power source 18 to measure the gate current (Ig). The voltage is, for example, 2V. Further, in this case, the bias applied may be a forward voltage. In either case, the gate current (Ig) does not flow unless the gate is deteriorated or destroyed.

Next, in the GaAs HIGFET 9,
The stress is applied for a predetermined time, for example, several hours to several tens of hours (stress applying step).

That is, a high positive voltage is applied to the drain of the GaAs HIGFET 9 by the high power supply 15, and a low voltage (reverse voltage) is applied to the gate by the variable power supply 18. For example, 6V is applied by the high power source 15, and the variable power source 18
As a result, for example, 1V is applied, so a voltage of 7V is applied to the gate-drain voltage (Vdg).

Next, the measuring circuit is switched to measure the deterioration characteristic (deterioration characteristic measuring step).

That is, the variable power supply 18 is provided only to the gate of the GaAs HIGFET 9 by the circuit as shown in FIG.
A low voltage (reverse voltage) is applied to measure the gate current (Ig). The voltage is, for example, 2V. This voltage is set to a voltage range in which the deterioration is remarkable in the new deterioration mode found by the present inventors, that is, a voltage in the voltage range of the area b in FIG.

In this embodiment, the stress applying step and the deterioration characteristic measuring step are repeated until the element (transistor) is destroyed. Further, the gate current-stress application cumulative time dependency is obtained from the measurement result at the deterioration characteristic measuring stage.

FIG. 2 is a graph showing the correlation between the gate current (Ig) and the cumulative stress application time. This graph is displayed on the display 6 and the printer 7
Printed out from

According to this graph, it can be seen that the characteristic deterioration of the gate has started at time B. When the gate current at the time of measuring the initial characteristics is I _O , for example, the gate current increases to I _C and I _D as time passes C and D, and the gate current becomes I _P at time P, Will destroy.

By analyzing and examining this graph,
It is possible to accurately know the transition of deterioration and breakdown of the gate (gate insulating film).

According to the deterioration life test method of the present embodiment,
It is possible to confirm the transition of the characteristic deterioration life of the gate, which could not be confirmed by the conventional measurement method.

In the present embodiment, the gate current is measured by applying the reverse bias lower than the stress application bias to the gate in the deterioration characteristic measurement, but the forward current bias is applied to the gate to measure the gate current. You can

In the deterioration characteristic measurement, gate deterioration may be measured by measuring the gate voltage instead of detecting the gate current. Further, both the gate current and the gate voltage may be measured.

In this embodiment, the gate deterioration life test of the transistor is performed by repeating the stress application step and the deterioration characteristic measurement step until the gate deterioration occurs.
After applying stress for a predetermined time, deterioration characteristic measurement may be performed to perform a gate deterioration life test of the transistor.

FIG. 7 is a flowchart showing a reliability evaluation method for a compound semiconductor device according to another embodiment of the present invention.

In this embodiment, the gate current (I
This is a reliability evaluation method for screening compound semiconductor devices, which utilizes a graph showing the correlation between g) and the cumulative stress application time.

Since the characteristic deterioration phenomenon of the GaAs HIGFET can be clarified by the deterioration life test method of the compound semiconductor device, the aging time is set from the clarification result, and at the time, a gate current (threshold value) equal to or more than a constant gate deterioration is caused. A defective product in which the gate current has occurred is evaluated as a non-defective product in which gate deterioration does not occur.

In the graph of FIG. 2, in the GaAs HIGFET in the state where the application time D has elapsed, if the threshold value is I _C , it is possible to select and evaluate whether the product is a non-defective product or a defective product, even if the characteristic variation of the product is taken into consideration.

In the reliability evaluation method of this embodiment, after the GaAs HIGFET 9 is attached to the measuring section 10, the reliability evaluation is started as shown in the flowchart of FIG.

That is, the high bias is set to G by the same method as in the above embodiment, that is, the method shown in the circuit diagram of FIG.
A gate current (Ig) is measured by applying a low bias only to the gate as shown in the circuit diagram of FIG. 5, after applying a predetermined time (D time) between the gate and drain of the aAsHIGFET 9. Yes (degradation characteristic measurement stage). After that, a product having a measured gate current (Ig) of a threshold value (I _C ) or more is determined as a defective product, and a product of which the threshold current (Ig) does not reach the threshold value is determined as a good product, and the quality of the product is selected (evaluation stage).

As a result, the quality of products can be selected (screening) in a short time.

That is, in the conventional method, the presence or absence of gate deterioration cannot be determined until the time P has elapsed, and it takes a long time to evaluate the reliability. However, according to the present embodiment, the time P is not reached. Screening can be done at time D,
Increases productivity.

Also in this embodiment, the gate voltage may be measured instead of the gate current in the deterioration characteristic measurement.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say, for example, the present invention provides another field effect transistor using a semi-insulating gallium arsenide substrate, namely, an IG (Insulated Gat).
e) It can be similarly applied to the evaluation measurement of other field effect transistors such as FET and MES (Metal-Semiconductor) FET, and the same effect is obtained.

[0060]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

(1) After applying a stress applying bias between the gate and the drain of the GaAs HIGFET for a predetermined time, the measuring circuit is switched to apply a deterioration characteristic measuring bias lower than the stress applying bias between the gate and the drain of the transistor. A graph of the obtained gate current-cumulative stress application time obtained by measuring the gate current and determining the dependency of the gate current and cumulative stress application time by repeating the stress applying step and the deterioration characteristic measuring step until the gate is destroyed. Therefore, it is possible to accurately measure the transition of deterioration and breakdown of the gate (gate insulating film).

(2) After applying a stress applying bias between the gate and drain of the GaAs HIGFET for a predetermined time, the measuring circuit is switched to apply a deterioration characteristic measuring bias lower than the stress applying bias between the gate and drain of the transistor. Since the quality of the product can be evaluated by measuring the gate current and checking whether the gate current has increased or not at this stage, the gate quality can be evaluated in a short time compared to the conventional reliability evaluation method that monitors the gate current while applying a high bias. Can be evaluated and productivity will be increased.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a method for testing a deterioration life of a compound semiconductor device according to an embodiment of the present invention.

FIG. 2 is a graph showing a correlation between a gate current and a cumulative stress application time, which is obtained by the method of testing the deterioration life of the compound semiconductor device of the present embodiment.

FIG. 3 is a configuration block diagram of a test apparatus of this embodiment.

FIG. 4 is a circuit diagram when a stress application bias is applied in a deterioration life test of the compound semiconductor device of the present embodiment.

FIG. 5 is a circuit diagram when a deterioration characteristic measurement bias is applied in a deterioration life test of the compound semiconductor device of the present embodiment.

FIG. 6 is a circuit diagram showing a bias applying circuit section in a deterioration life test of the compound semiconductor device of the present embodiment.

FIG. 7 is a flowchart showing a reliability evaluation method of a compound semiconductor device according to another embodiment of the present invention.

FIG. 8 is a graph showing a correlation between a breakdown lifetime of a compound semiconductor device and a stress application bias.

FIG. 9 is a graph showing the correlation between the gate current and the gate-drain voltage in the compound semiconductor device before and after the stress application, which is found by the present inventors.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Central processing unit (CPU), 2 ... Measuring device, 3 ... Input device, 4 ... Main storage device, 5 ... Auxiliary storage device, 6 ... Display, 7 ... Printer, 9 ... Semiconductor device, 10 ... Measuring part,
11D ... Drain terminal, 11G ... Gate terminal, 11
S ... Source terminal, 12 ... Wiring, 13, 13a, 13b
… Wiring, 14… Changeover switch, 15… High power supply, 16…
Wiring, 17 ... Ammeter, 18 ... Variable power supply, 20 ... Ground.

Claims (6)

[Claims] 1. A deterioration life test method for a compound semiconductor device, comprising applying a stress applying bias between a gate and a drain of a field effect transistor formed in a compound semiconductor and monitoring a gate current to perform a gate deterioration life test. , A stress applying step of applying a stress applying bias to the transistor for a predetermined time, and a measuring circuit is switched to apply a deterioration characteristic measuring bias lower than the stress applying bias between the gate and the drain of the transistor to obtain a gate current or a gate voltage. A method of testing deterioration life of a compound semiconductor device, comprising: a deterioration detection step of measuring. 2. A deterioration life test method for a compound semiconductor device, wherein a stress application bias is applied between a gate and a drain of a field effect transistor formed in a compound semiconductor and a gate life is monitored to perform a deterioration life test of the gate. Then, a stress applying step of applying a stress applying bias to the transistor for a predetermined time and a measuring circuit are switched to apply a deterioration characteristic measuring bias lower than the stress applying bias between the gate and the drain of the transistor to obtain a gate current or a gate voltage. A deterioration detection stage for measuring
Degradation life of the compound semiconductor device, characterized in that the stress application step and the deterioration characteristic measurement step are repeated until the gate deterioration occurs, and the dependency of the gate current or / and the gate voltage and the cumulative time of stress application is obtained. Test method. 3. First, a deterioration characteristic measurement bias lower than the stress application bias is applied between the gate and the drain to detect an initial gate current or / and gate voltage,
Then, a stress application bias is applied to the transistor, and the deterioration life test method for a compound semiconductor device according to claim 1 or 2, is applied. 4. A reverse bias voltage is applied to the gate as the stress applying bias, and a reverse bias or a forward bias lower than the stress applying bias is applied as the deterioration characteristic measuring bias. 4. The deterioration life test method for a compound semiconductor device according to any one of 3 above. 5. A reliability evaluation method for a compound semiconductor device, comprising applying a stress application bias between a gate and a drain of a field effect transistor formed in a compound semiconductor and monitoring the gate current to evaluate the quality of the gate. A stress applying step of applying a stress applying bias to the transistor for a predetermined time, and a deterioration detection bias lower than the stress applying bias is applied between the gate and the drain of the transistor by switching the measurement circuit to a gate current or / and a gate voltage. And a reliability characteristic evaluation method for a compound semiconductor device, comprising: a deterioration characteristic measurement step for measuring the field effect transistor; and an evaluation step for evaluating the quality of the field effect transistor from the gate current and / or the gate voltage. 6. The compound according to claim 5, wherein a reverse voltage is applied to the gate as the stress applying bias, and a reverse bias or a forward bias lower than the stress applying bias is applied as the deterioration characteristic measuring bias. Semiconductor device reliability evaluation method.