JP6602519B1 - Semiconductor device, deterioration diagnosis device for semiconductor device, and deterioration diagnosis method for semiconductor device - Google Patents

Semiconductor device, deterioration diagnosis device for semiconductor device, and deterioration diagnosis method for semiconductor device Download PDF

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JP6602519B1
JP6602519B1 JP2019541209A JP2019541209A JP6602519B1 JP 6602519 B1 JP6602519 B1 JP 6602519B1 JP 2019541209 A JP2019541209 A JP 2019541209A JP 2019541209 A JP2019541209 A JP 2019541209A JP 6602519 B1 JP6602519 B1 JP 6602519B1
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semiconductor device
semiconductor chip
electrode
voltage
insulating resin
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JPWO2020225897A1 (en
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厚 山竹
厚 山竹
塩田 裕基
裕基 塩田
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Mitsubishi Electric Corp
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/12Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26Testing of individual semiconductor devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Abstract

絶縁基板(3)電極(4)を介して搭載された半導体チップ(2)が絶縁樹脂(8)により封止された半導体装置(1)であって、半導体チップの端部(2a)に対向した上方の絶縁樹脂(8)内で、半導体チップ(2)と離間して配置され、外部から電圧を印加可能な電極部(13)を備え、劣化診断時に、電極部(13)に電圧を印加した後に、半導体チップに対して逆方向電圧を印加し、半導体チップを流れるリーク電流を計測する。電極部(13)からの電界の影響で、半導体チップ(2)の耐圧が低下し、リーク電流が増加するので、劣化診断の感度が向上する。A semiconductor device (1) in which a semiconductor chip (2) mounted via an insulating substrate (3) electrode (4) is sealed with an insulating resin (8), facing the end (2a) of the semiconductor chip In the upper insulating resin (8), there is provided an electrode part (13) which is arranged apart from the semiconductor chip (2) and can apply a voltage from the outside. After the application, a reverse voltage is applied to the semiconductor chip, and a leak current flowing through the semiconductor chip is measured. Due to the influence of the electric field from the electrode section (13), the breakdown voltage of the semiconductor chip (2) is reduced and the leakage current is increased, so that the sensitivity of deterioration diagnosis is improved.

Description

本願は、半導体装置、半導体装置の劣化診断装置及び半導体装置の劣化診断方法に関するものである。   The present application relates to a semiconductor device, a deterioration diagnosis device for a semiconductor device, and a deterioration diagnosis method for a semiconductor device.

半導体パワーモジュール等の半導体装置において、劣化診断あるいは寿命予測を行うことで、半導体装置の交換時期の目安を知ることができる。そのため、半導体装置の故障発生前に交換することで、半導体装置の組み込まれた機器において半導体装置の故障による事故の発生を防止することが可能となる。   In a semiconductor device such as a semiconductor power module, by performing deterioration diagnosis or life prediction, it is possible to know a guideline for replacing the semiconductor device. Therefore, by replacing the semiconductor device before the failure occurs, it is possible to prevent an accident due to the failure of the semiconductor device in the device in which the semiconductor device is incorporated.

例えば、従来の半導体装置の劣化診断装置では、診断対象の半導体装置に逆方向電圧を印加した際のリーク電流を検出し、その結果から劣化度を評価している(例えば、特許文献1参照)。   For example, a conventional semiconductor device deterioration diagnosis apparatus detects a leakage current when a reverse voltage is applied to a semiconductor device to be diagnosed, and evaluates the degree of deterioration from the result (see, for example, Patent Document 1). .

一方、半導体装置の外部から電界を印加して耐圧の変動を測定する試験装置が知られている(例えば、特許文献2参照)。   On the other hand, there is known a test apparatus that measures the variation in breakdown voltage by applying an electric field from the outside of the semiconductor device (for example, see Patent Document 2).

特開2003−294807号公報JP 2003-294807 A 特開2010−66250号公報JP 2010-66250 A

しかし、特許文献1の方法では、半導体装置に直接逆方向電圧を印加するので、劣化が進んだ状態でないとリーク電流の変動量が小さい。また測定時の温度等の環境変動を受けやすいため小さなリーク電流の変動が劣化に起因するものか判断が難しいという問題があった。   However, in the method of Patent Document 1, since the reverse voltage is directly applied to the semiconductor device, the fluctuation amount of the leakage current is small unless the deterioration is advanced. In addition, since it is susceptible to environmental fluctuations such as temperature during measurement, there is a problem that it is difficult to determine whether small fluctuations in leakage current are caused by deterioration.

そこで、特許文献2の耐圧検査の方法を用いれば、診断対象の半導体装置に外部から電界を印加し半導体装置の耐圧を下げることが可能となり、劣化診断を行えることが期待される。   Therefore, if the withstand voltage test method disclosed in Patent Document 2 is used, an electric field can be applied to the semiconductor device to be diagnosed from the outside to lower the withstand voltage of the semiconductor device, and it is expected that deterioration diagnosis can be performed.

本願は、上記のような課題を解決するための技術を開示するものであり、診断対象の半導体装置に外部から電圧を印加することで、半導体装置の耐圧を下げて、リーク電流を検出し、半導体装置の劣化診断を行うことが可能な半導体装置、半導体装置の劣化診断装置及び劣化診断方法を提供することを目的とする。   The present application discloses a technique for solving the above-described problems, and by applying a voltage from the outside to the semiconductor device to be diagnosed, the breakdown voltage of the semiconductor device is lowered, and a leakage current is detected. An object of the present invention is to provide a semiconductor device capable of performing a deterioration diagnosis of a semiconductor device, a deterioration diagnosis device for a semiconductor device, and a deterioration diagnosis method.

本願に開示される半導体装置は、絶縁基板及び前記絶縁基板上の電極を介して搭載された半導体チップを有し、前記絶縁基板及び前記半導体チップが絶縁樹脂により封止された半導体装置であって、前記半導体チップの端部に対向した上方の前記絶縁樹脂内で、前記半導体チップと離間し電気的に絶縁されて配置され、外部から電圧を印加可能な電極部を備えたものである。 A semiconductor device disclosed in the present application includes a semiconductor chip mounted via an insulating substrate and an electrode on the insulating substrate, and the insulating substrate and the semiconductor chip are sealed with an insulating resin. In the upper insulating resin facing the end portion of the semiconductor chip, the semiconductor chip is provided so as to be separated from the semiconductor chip and electrically insulated , and provided with an electrode portion to which a voltage can be applied from the outside.

本願に開示される半導体装置の診断装置は、上述の電極部を備えた半導体装置の劣化診断を行う半導体装置の診断装置であって、前記電極部に電圧を印加する電源と、前記半導体チップに電圧を印加する電源と、前記半導体チップに流れる電流を計測する電流計と、を備えたものである。 A semiconductor device diagnostic device disclosed in the present application is a semiconductor device diagnostic device that performs a deterioration diagnosis of a semiconductor device including the above-described electrode unit, and includes a power source that applies a voltage to the electrode unit, and a semiconductor chip. A power source for applying a voltage; and an ammeter for measuring a current flowing through the semiconductor chip.

本願に開示される半導体装置の診断方法は、上述の電極部を備えた半導体装置を劣化診断する半導体装置の劣化診断方法であって、前記電極部に電圧を印加する第一ステップと、前記電極部に電圧を印加した状態で、前記半導体チップに逆方向電圧を印加する第二ステップと、前記半導体チップに流れる電流を計測する第三ステップと、計測された電流と予め取得された基準電流とを比較し、劣化診断を行う第四ステップと、を備えたものである。   A method for diagnosing a semiconductor device disclosed in the present application is a method for diagnosing deterioration of a semiconductor device including the above-described electrode unit, the first step of applying a voltage to the electrode unit, and the electrode A second step of applying a reverse voltage to the semiconductor chip in a state where a voltage is applied to the part, a third step of measuring a current flowing through the semiconductor chip, a measured current, and a reference current acquired in advance. And a fourth step of performing deterioration diagnosis.

本願によれば、半導体装置内の半導体チップの端部に対向して電極部を設け、この電極部に外部から電圧を印加することで、半導体装置の耐圧を一時的に下げて、リーク電流を検出しやすくしたので、半導体装置の劣化診断の感度が向上する。   According to the present application, an electrode portion is provided opposite to an end portion of a semiconductor chip in a semiconductor device, and a voltage is applied to the electrode portion from the outside, whereby the withstand voltage of the semiconductor device is temporarily reduced and leakage current is reduced. Since it is easy to detect, the sensitivity of the deterioration diagnosis of the semiconductor device is improved.

実施の形態1に係る半導体装置及び半導体装置の劣化診断装置の構成を示す図である。1 is a diagram illustrating a configuration of a semiconductor device and a deterioration diagnosis device for a semiconductor device according to a first embodiment. 実施の形態1に係る半導体装置の一部構成を示す斜視図である。1 is a perspective view showing a partial configuration of a semiconductor device according to a first embodiment. 実施の形態1に係る半導体装置の劣化診断方法を示すフローチャートである。3 is a flowchart showing a degradation diagnosis method for a semiconductor device according to the first embodiment. 半導体チップの電圧―電流特性における劣化変動を説明するための図である。It is a figure for demonstrating the degradation fluctuation | variation in the voltage-current characteristic of a semiconductor chip. 半導体チップの電圧―電流特性における印加電界の影響を説明するための図である。It is a figure for demonstrating the influence of the applied electric field in the voltage-current characteristic of a semiconductor chip. 実施の形態2に係る半導体装置の構成を示す図である。FIG. 4 is a diagram showing a configuration of a semiconductor device according to a second embodiment. 実施の形態2に係る比較例としての半導体装置の電界解析モデルを示す図である。FIG. 10 is a diagram showing an electric field analysis model of a semiconductor device as a comparative example according to the second embodiment. 実施の形態2に係る半導体装置の電界解析モデルを示す図である。6 is a diagram showing an electric field analysis model of a semiconductor device according to a second embodiment. FIG. 実施の形態3に係る半導体装置の構成を示す図である。FIG. 6 is a diagram showing a configuration of a semiconductor device according to a third embodiment. 実施の形態3に係る半導体装置の電界解析モデルを示す図である。6 is a diagram showing an electric field analysis model of a semiconductor device according to a third embodiment. FIG. 実施の形態3に係る半導体装置の別の構成を示す図である。FIG. 10 is a diagram showing another configuration of the semiconductor device according to the third embodiment. 実施の形態4に係る半導体装置の構成を示す図である。FIG. 6 is a diagram showing a configuration of a semiconductor device according to a fourth embodiment. 実施の形態4に係る半導体装置の構成を示す図である。FIG. 6 is a diagram showing a configuration of a semiconductor device according to a fourth embodiment. 実施の形態5に係る半導体装置の構成を示す図である。FIG. 10 is a diagram showing a configuration of a semiconductor device according to a fifth embodiment. 実施の形態5に係る半導体装置の一部構成を示す斜視図である。FIG. 10 is a perspective view showing a partial configuration of a semiconductor device according to a fifth embodiment. 実施の形態5に係る半導体装置の別の一部構成を示す斜視図である。FIG. 10 is a perspective view showing another partial configuration of the semiconductor device according to the fifth embodiment. 実施の形態5に係る半導体装置の別の一部構成を示す上面図である。FIG. 10 is a top view showing another partial configuration of the semiconductor device according to the fifth embodiment. 実施の形態6に係る半導体装置の一部構成を示す斜視図である。FIG. 10 is a perspective view showing a partial configuration of a semiconductor device according to a sixth embodiment. 実施の形態6に係る半導体装置の一部構成を示す上面図である。FIG. 10 is a top view showing a partial configuration of a semiconductor device according to a sixth embodiment. 実施の形態7に係る半導体装置の劣化診断装置の構成を示す図である。It is a figure which shows the structure of the deterioration diagnostic apparatus of the semiconductor device which concerns on Embodiment 7. FIG. 実施の形態7に係る半導体装置の劣化診断装置の別の構成を示す図である。FIG. 10 is a diagram showing another configuration of a semiconductor device degradation diagnosis apparatus according to a seventh embodiment. 実施の形態7に係る半導体装置の劣化診断装置のさらに別の構成を示す図である。It is a figure which shows another structure of the deterioration diagnostic apparatus of the semiconductor device which concerns on Embodiment 7. FIG. 実施の形態7に係る半導体装置の劣化診断装置のさらに別の構成を示す図である。It is a figure which shows another structure of the deterioration diagnostic apparatus of the semiconductor device which concerns on Embodiment 7. FIG.

以下、半導体装置、半導体装置の劣化診断装置及び劣化診断方法の実施の形態について図を参照して説明する。なお、各図中、同一符号は、同一または相当する部分を示すものとする。   Hereinafter, embodiments of a semiconductor device, a deterioration diagnosis device for a semiconductor device, and a deterioration diagnosis method will be described with reference to the drawings. In addition, in each figure, the same code | symbol shall show the part which is the same or it corresponds.

実施の形態1.
以下、実施の形態1に係る半導体装置について説明する。図1は、本実施の形態1に係る半導体装置及び半導体装置の劣化診断装置の構成の一例を示す図である。図1において、半導体装置1は、窒化アルミニウムまたはアルミナ等のセラミックからなる絶縁基板3と、絶縁基板3の上部に設けられた基板上部電極4を介してはんだ接合された半導体チップ2と、絶縁基板3の下部に設けられた基板下部電極5を介してはんだ接合された放熱板6と、半導体チップの端部2aの上方に外部電界を印加するための電極部13と、を有し、これらがケース7内に収納され、絶縁樹脂8で封止されて構成されている。
Embodiment 1 FIG.
The semiconductor device according to the first embodiment will be described below. FIG. 1 is a diagram illustrating an example of a configuration of a semiconductor device and a deterioration diagnosis device for a semiconductor device according to the first embodiment. In FIG. 1, a semiconductor device 1 includes an insulating substrate 3 made of a ceramic such as aluminum nitride or alumina, a semiconductor chip 2 solder-bonded via a substrate upper electrode 4 provided on the insulating substrate 3, and an insulating substrate. 3 has a heat sink 6 soldered via a substrate lower electrode 5 provided at the lower part of 3 and an electrode part 13 for applying an external electric field above the end part 2a of the semiconductor chip, It is housed in a case 7 and sealed with an insulating resin 8.

半導体チップ2は、例えばIGBT(Insulated Gate Bipolar Transistor)あるいはMOSFET(Metal Oxide Semiconductor Field Effect Transistor)等のパワー半導体素子からなるチップである。絶縁基板3は、セラミックに限ることなく、エポキシ樹脂等の絶縁性樹脂基板を用いてもよい。放熱板6は、半導体チップ2からの熱を外部に逃がすため熱伝導率の高い銅あるいはアルミニウム等の材料で構成されている。ケース7内を封止する絶縁樹脂8には、シリコーンゲルあるいはエポキシ樹脂等の絶縁樹脂が用いられる。半導体チップ2及び基板上部電極4には高電圧が印加されるため、その周囲を絶縁樹脂8により覆って絶縁性を保つ。半導体チップ2は、その上面および下面に電圧を印加する電極(エミッタ電極、コレクタ電極)を有する。基板上部電極4と半導体チップ2の上面電極9との間に電源10から電圧を印加することで、半導体チップ2に電圧を印加し、動作させる。なお、半導体チップ2の下面電極は図示してない。また、外部電界を印加するための電極部13は、半導体チップ2の端部2aの上方の絶縁樹脂中に、半導体チップ2等の部品から離間されて、埋められて配置される。
The semiconductor chip 2 is a chip made of a power semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The insulating substrate 3 is not limited to ceramic, and an insulating resin substrate such as an epoxy resin may be used. The heat radiating plate 6 is made of a material having high thermal conductivity such as copper or aluminum in order to release heat from the semiconductor chip 2 to the outside. For the insulating resin 8 that seals the inside of the case 7, an insulating resin such as silicone gel or epoxy resin is used. Since a high voltage is applied to the semiconductor chip 2 and the substrate upper electrode 4, the periphery is covered with an insulating resin 8 to maintain insulation. The semiconductor chip 2 has electrodes (emitter electrode, collector electrode) for applying a voltage to the upper and lower surfaces thereof. By applying a voltage from the power supply 10 between the substrate upper electrode 4 and the upper surface electrode 9 of the semiconductor chip 2, a voltage is applied to the semiconductor chip 2 to operate it. Note that the lower surface electrode of the semiconductor chip 2 is not shown. In addition, the electrode portion 13 for applying an external electric field is disposed in an insulating resin above the end portion 2a of the semiconductor chip 2 so as to be spaced apart from components such as the semiconductor chip 2 and the like.

次に、半導体装置1の劣化診断装置について説明する。半導体装置1内の電極部13には配線131を介して直流電源14が接続されている。劣化診断装置の動作時には、半導体装置1の内部の半導体チップ2に対し、逆方向電圧となるように、電源10から半導体チップの定格電圧が印加され、半導体チップ2を流れるリーク電流を半導体チップ2に接続された配線に設けられた電流計11により計測する。電極部13に対して直流電源14により電圧を印加することにより、半導体チップの端部2aに対して電極部13から電界が与えられる。この時の電極部13に印加する電圧は、絶縁樹脂8の絶縁破壊電圧以下に収める。   Next, a deterioration diagnosis apparatus for the semiconductor device 1 will be described. A DC power supply 14 is connected to the electrode portion 13 in the semiconductor device 1 through a wiring 131. During the operation of the deterioration diagnosis device, the rated voltage of the semiconductor chip is applied from the power supply 10 so that the reverse voltage is applied to the semiconductor chip 2 inside the semiconductor device 1, and the leakage current flowing through the semiconductor chip 2 is reduced to the semiconductor chip 2. It measures with the ammeter 11 provided in the wiring connected to. By applying a voltage to the electrode portion 13 from the DC power supply 14, an electric field is applied from the electrode portion 13 to the end portion 2a of the semiconductor chip. The voltage applied to the electrode part 13 at this time is kept below the dielectric breakdown voltage of the insulating resin 8.

ここで、半導体装置1内における電極部13の位置を説明する。図2は、半導体装置1内の半導体チップ2と電極部13との位置関係を示す斜視図である。図2に示すように、半導体チップ2の端部2aの上方に電極部13が設置されている。この電極部13は、絶縁樹脂8の中に埋め込まれるように設置され、また、周囲の上面電極9等の電極とは電気的に絶縁され、半導体装置1の外側と電気的に接続するための配線131を備える。   Here, the position of the electrode part 13 in the semiconductor device 1 will be described. FIG. 2 is a perspective view showing the positional relationship between the semiconductor chip 2 and the electrode portion 13 in the semiconductor device 1. As shown in FIG. 2, the electrode portion 13 is provided above the end portion 2 a of the semiconductor chip 2. The electrode portion 13 is installed so as to be embedded in the insulating resin 8, and is electrically insulated from surrounding electrodes such as the upper surface electrode 9, and is electrically connected to the outside of the semiconductor device 1. Wiring 131 is provided.

次に、本実施の形態1に係る半導体装置1の劣化診断方法についてフローチャートを用いて説明する。図3は、半導体装置の劣化診断方法を示すフローチャートである。
まず、ステップS1において、半導体装置1内の電極部13に直流電源14より直流電圧を印加する。
次に、ステップS2において、半導体チップ2に劣化診断を行うための試験電圧を印加する。試験電圧は、半導体チップに対し逆方向電圧を印加する。
ステップS3において、半導体チップ2に流れるリーク電流を電流計11により計測する。
リーク電流を計測した後、ステップS4において、電極部13及び半導体チップ2への電圧の印加を停止する。
ステップS5において、予め計測し取得しておいた正常時のリーク電流と計測されたリーク電流を比較し、劣化診断を実施する。劣化診断においては、正常時からのリーク電流の増加量により劣化の度合いを診断する。
Next, the deterioration diagnosis method for the semiconductor device 1 according to the first embodiment will be described with reference to a flowchart. FIG. 3 is a flowchart showing a method for diagnosing deterioration of a semiconductor device.
First, in step S <b> 1, a DC voltage is applied from the DC power supply 14 to the electrode unit 13 in the semiconductor device 1.
Next, in step S <b> 2, a test voltage for performing deterioration diagnosis is applied to the semiconductor chip 2. As the test voltage, a reverse voltage is applied to the semiconductor chip.
In step S <b> 3, the leak current flowing through the semiconductor chip 2 is measured by the ammeter 11.
After measuring the leakage current, application of voltage to the electrode unit 13 and the semiconductor chip 2 is stopped in step S4.
In step S5, a normal leakage current measured and acquired in advance is compared with the measured leakage current, and deterioration diagnosis is performed. In the deterioration diagnosis, the degree of deterioration is diagnosed by the amount of increase in leakage current from the normal time.

半導体チップ2の端部2aへ電界を与える効果について説明する。
図4A及び図4Bは、半導体チップの電圧―電流特性を示す図である。図4Aにおいて、正常時では電圧に対してリーク電流は直線状に増加している。半導体チップが劣化すると、電圧の増加に伴い直線状からはずれ、リーク電流は急激に増加する。本実施の形態では、正常時からのリーク電流の差分で劣化診断を行うが、試験電圧が図中のV1の場合では劣化時と正常時とではリーク電流の差分すなわち、劣化時のリーク電流の増加分が小さく、劣化状態を判断することができない。試験電圧をV2まで上げると、両者のリーク電流の差分が大きくなり、劣化診断を行うことが可能となる。しかし、試験電圧の増大は半導体チップの破壊あるいは劣化の原因となり得る。さらに、試験電圧は半導体チップの定格電圧を超えることができず、試験電圧の設定には制約があった。
The effect of applying an electric field to the end 2a of the semiconductor chip 2 will be described.
4A and 4B are diagrams showing voltage-current characteristics of the semiconductor chip. In FIG. 4A, the leakage current increases linearly with respect to the voltage under normal conditions. When the semiconductor chip is deteriorated, the leakage current increases sharply as the voltage increases, deviating from the linear shape. In this embodiment, the deterioration diagnosis is performed based on the difference in leakage current from the normal time. When the test voltage is V1 in the figure, the difference in leakage current between the deterioration time and the normal time, that is, the leakage current at the time of deterioration. The increment is small and the deterioration state cannot be determined. When the test voltage is increased to V2, the difference between the leakage currents of both increases, and deterioration diagnosis can be performed. However, an increase in test voltage can cause destruction or deterioration of the semiconductor chip. Furthermore, the test voltage cannot exceed the rated voltage of the semiconductor chip, and there is a restriction on the setting of the test voltage.

ところで、半導体チップは、内部の空乏層によって絶縁が保たれているが、外部からの電界を受け、内部の空乏層が縮まる等の現象により、耐圧が低下し、リーク電流の増加が引き起こされる。図4Bは、図4Aに劣化時の半導体チップに対し、劣化診断時に外部電界を生じさせたものを重ね合わせた図である。外部電界が印加されると、一時的に耐圧低下が生じ、図中矢印で示すようにリーク電流が増加する。これにより、定格電圧以下の試験電圧がV1であっても、正常時からのリーク電流の増加量を検出することができ、劣化診断を実施することが可能となる。   By the way, although the semiconductor chip is insulated by an internal depletion layer, a withstand voltage is reduced due to a phenomenon such as an internal depletion layer contracting due to an external electric field, and an increase in leakage current is caused. FIG. 4B is a diagram in which an external electric field generated at the time of deterioration diagnosis is superimposed on the semiconductor chip at the time of deterioration shown in FIG. 4A. When an external electric field is applied, the withstand voltage is temporarily reduced, and the leakage current increases as indicated by arrows in the figure. As a result, even if the test voltage equal to or lower than the rated voltage is V1, it is possible to detect the amount of increase in leakage current from the normal time and to perform deterioration diagnosis.

なお、上述では正常時のリーク電流を基準電流としてその差分の増大量で劣化診断を行うようにしたが、半導体チップの初期状態を正常時と見做すことができる場合、この初期状態のリーク電流を基準電流としてリーク電流の差分で判断するようにしてもよい。この場合、定期的あるいは半導体装置1の所定の運転時間毎にリーク電流を計測して履歴を記録しておけば、劣化の経緯あるいは劣化の予測も可能となる。   In the above description, the leakage diagnosis at the normal time is used as the reference current, and the deterioration diagnosis is performed with the increased amount of the difference. However, when the initial state of the semiconductor chip can be regarded as the normal state, this initial state leakage current is used. You may make it judge by the difference of leak current by making an electric current into a reference current. In this case, if the leakage current is measured periodically and recorded for every predetermined operating time of the semiconductor device 1, the history of deterioration or the prediction of deterioration can be made.

以上のように、本実施の形態1によれば、半導体装置1の内部であって、半導体チップ2の端部2aに対向した上方に電極部13配置して半導体装置1を構成し、電極部13に配線131を介して接続された直流電源14により、電圧を印加するように劣化診断装置を構成したので、半導体装置1の劣化診断時に、半導体チップ2に外部から電界を与えて、耐圧を低下させ、リーク電流を増大させることができ、半導体チップ2に印加する試験電圧を高くしなくてもリーク電流を検出しやすくなる。これにより、劣化診断の感度を向上させることができるとともに、劣化が進んでいない半導体チップにおいてもリーク電流から劣化状況を判断できるようになる。
また、電極部13は半導体装置1内で半導体チップ2の端部2aの上方に、他の電極から離間され、絶縁されて絶縁樹脂8に埋め込まれているので、半導体チップ2の端部2a以外に外部電界の影響を及ぼすことはない。
As described above, according to the first embodiment, the semiconductor device 1 is configured by disposing the electrode portion 13 inside the semiconductor device 1 and above the end portion 2a of the semiconductor chip 2. 13 is configured so that a voltage is applied by the DC power supply 14 connected to the wiring 13 via the wiring 131. Therefore, when the semiconductor device 1 is diagnosed for deterioration, an electric field is applied to the semiconductor chip 2 from the outside to reduce the withstand voltage. The leakage current can be increased and the leakage current can be easily detected without increasing the test voltage applied to the semiconductor chip 2. As a result, the sensitivity of deterioration diagnosis can be improved, and the deterioration state can be determined from the leakage current even in a semiconductor chip where deterioration has not progressed.
In addition, since the electrode portion 13 is separated from other electrodes above the end portion 2 a of the semiconductor chip 2 in the semiconductor device 1 and is insulated and embedded in the insulating resin 8, other than the end portion 2 a of the semiconductor chip 2. There is no influence of an external electric field.

実施の形態2.
以下に、実施の形態2に係る半導体装置の構成について説明する。
図5は、実施の形態2に係る半導体装置の構成を示す図である。電極部13が半導体装置1の絶縁樹脂8中の半導体チップ2の端部2aの上方に配置されている点は実施の形態1と同様であるが、電極部13が絶縁膜15で被覆されている点が、実施の形態1と相違する。実施の形態1では、電極部13が半導体チップ2の端部2aの上方に配置され、他の電極から離間されているが、他の電極及び配線部材(ワイヤ等)と近接する場合は、それら電極及び配線部材と電極部13との絶縁を確保することが重要となる。そこで、本実施の形態2では、電極部13を絶縁樹脂8よりも体積抵抗率の高い絶縁膜15を被覆することで、周囲と絶縁を確保する例について説明する。
Embodiment 2. FIG.
The configuration of the semiconductor device according to the second embodiment will be described below.
FIG. 5 is a diagram showing a configuration of the semiconductor device according to the second embodiment. Although the electrode part 13 is disposed above the end part 2a of the semiconductor chip 2 in the insulating resin 8 of the semiconductor device 1 as in the first embodiment, the electrode part 13 is covered with the insulating film 15. This is different from the first embodiment. In the first embodiment, the electrode portion 13 is disposed above the end portion 2a of the semiconductor chip 2 and is separated from other electrodes. However, when the electrode portion 13 is close to other electrodes and wiring members (wires, etc.), It is important to ensure insulation between the electrode and wiring member and the electrode portion 13. Therefore, in the second embodiment, an example will be described in which the electrode portion 13 is covered with an insulating film 15 having a volume resistivity higher than that of the insulating resin 8 to ensure insulation from the surroundings.

電極部13を絶縁膜15で被覆する場合、絶縁膜15の体積抵抗率がその周囲の絶縁樹脂8の体積抵抗率よりも大きいと、電極部13に直流電圧が印加された時、直列の電圧分担の関係により、高抵抗側に電位差が偏り、低抵抗側の電位差が小さくなる。その結果、低抵抗側の電界は低くなる。すなわち、絶縁樹脂8側の電界が弱まることになり、電極部13へ電圧を印加することで、半導体チップ2の耐圧を下げる効果が低下してしまう。そのため、本実施の形態2では、図5に示すように、電極部13の下部であって、半導体チップ2の端部2aに対向する領域には絶縁膜15は被覆しないものとする。このように構成することで、電極部13への電圧印加時に、絶縁樹脂8側の電界の低下が抑制され、半導体チップ2の耐圧を下げる効果を奏することが可能となる。   When the electrode part 13 is covered with the insulating film 15 and the volume resistivity of the insulating film 15 is larger than the volume resistivity of the surrounding insulating resin 8, a series voltage is applied when a DC voltage is applied to the electrode part 13. Due to the sharing relationship, the potential difference is biased toward the high resistance side, and the potential difference on the low resistance side is reduced. As a result, the electric field on the low resistance side is lowered. That is, the electric field on the insulating resin 8 side is weakened, and the effect of lowering the breakdown voltage of the semiconductor chip 2 is reduced by applying a voltage to the electrode portion 13. Therefore, in the second embodiment, as shown in FIG. 5, the insulating film 15 is not covered in a region below the electrode portion 13 and facing the end portion 2 a of the semiconductor chip 2. With this configuration, when a voltage is applied to the electrode portion 13, a decrease in the electric field on the insulating resin 8 side is suppressed, and an effect of reducing the breakdown voltage of the semiconductor chip 2 can be achieved.

次に、電極部13を絶縁膜15で被覆した場合の電界解析の結果について説明する。図6A及び図6Bは実施の形態2に係る半導体装置の電界解析モデルを示す図である。図6Aは電極部13の半導体チップ2側を全面的に絶縁膜15で被覆した比較例を、図6Bは半導体チップの端部2aに対向する領域には絶縁膜15は被覆しない電極部13の電界解析モデルを示している。図6A、6Bにおいて、電極部13の近傍は中央の点線を軸に軸対称とし、電極部13は直径dの円柱であり、電極部13には電圧HVが印加され、半導体チップの端部2aの上面から電極部13までの高さをh、絶縁膜15の厚みをt、絶縁膜15が被覆されていない領域を直径aの領域で示している。また、半導体チップの端部2a上の電極部13の直下の位置をAとしている。   Next, the result of electric field analysis when the electrode portion 13 is covered with the insulating film 15 will be described. 6A and 6B are diagrams illustrating an electric field analysis model of the semiconductor device according to the second embodiment. 6A shows a comparative example in which the semiconductor chip 2 side of the electrode portion 13 is entirely covered with the insulating film 15, and FIG. 6B shows the electrode portion 13 that does not cover the insulating film 15 in the region facing the end portion 2a of the semiconductor chip. An electric field analysis model is shown. 6A and 6B, the vicinity of the electrode portion 13 is axisymmetric with respect to the center dotted line, the electrode portion 13 is a cylinder having a diameter d, the voltage HV is applied to the electrode portion 13, and the end portion 2a of the semiconductor chip. The height from the upper surface to the electrode portion 13 is indicated by h, the thickness of the insulating film 15 is indicated by t, and the region not covered with the insulating film 15 is indicated by a region having a diameter a. A position immediately below the electrode portion 13 on the end portion 2a of the semiconductor chip is A.

この電界解析モデルにおいて、封止材である絶縁樹脂8を例えばシリコーンゲルとして体積抵抗率を1×1013Ωmとし、絶縁膜15を例えばポリイミドとして体積抵抗率を1×1014Ωmとし、電極部13の直径dを3mm、高さhを2mm、絶縁膜15の厚みtを0.1mm、電極部13下部の絶縁膜の穴の直径aを1mmとし、直流電圧印加時のA点の電界を直流場により解析した。
その結果、図6BにおけるA点の電界は、図6AにおけるA点の電界よりも約13%高い値となった。
また、図6Bにおいて電極部13下部の絶縁膜の穴の直径aを3mmとすると、すなわち電極部13下部には絶縁膜15を被覆せず、電極部13側面のみに絶縁膜15を被覆させた場合、図6BにおけるA点の電界は、図6Aの全面被覆状態と比較して約55%高い電界となった。
In this electric field analysis model, the insulating resin 8 as the sealing material is, for example, silicone gel, the volume resistivity is 1 × 10 13 Ωm, the insulating film 15 is, for example, polyimide, the volume resistivity is 1 × 10 14 Ωm, The diameter d of 13 is 3 mm, the height h is 2 mm, the thickness t of the insulating film 15 is 0.1 mm, the diameter a of the hole in the insulating film below the electrode portion 13 is 1 mm, and the electric field at point A when a DC voltage is applied is The analysis was performed using a DC field.
As a result, the electric field at point A in FIG. 6B was about 13% higher than the electric field at point A in FIG. 6A.
Further, in FIG. 6B, when the diameter a of the hole of the insulating film below the electrode part 13 is 3 mm, that is, the insulating film 15 is not covered at the lower part of the electrode part 13 and the insulating film 15 is covered only on the side surface of the electrode part 13. In this case, the electric field at point A in FIG. 6B was about 55% higher than that in the entire surface covering state in FIG. 6A.

絶縁樹脂8よりも体積抵抗率の高い絶縁膜15を電極部13に被覆する場合、絶縁膜15側に電圧降下が偏るため、それ以外の箇所の電界が下がる傾向がある。このため、半導体チップの端部2aに対向する領域には絶縁膜15が被覆されない方が、半導体チップ2へ与えられる電界の低下は抑制できる。
電極部13に絶縁樹脂8よりも体積抵抗率の高い絶縁膜15を被覆することにより、半導体チップの端部2a周辺の電極及び配線部材への電界の影響を抑制することが可能である。さらに、電極部13の半導体チップの端部2aに対向する部位に絶縁膜15を被覆すると半導体チップ2の耐圧を下げる効果も抑制されてしまうので、半導体チップの端部2a及びその周辺の電極及び配線部材との位置関係により、半導体チップの端部2aに対向する領域への絶縁膜15の被覆面積を変える等行い、半導体チップの端部2aに対向する領域への絶縁膜15の被覆を制限するのがよい。
When the electrode part 13 is covered with the insulating film 15 having a volume resistivity higher than that of the insulating resin 8, the voltage drop is biased toward the insulating film 15, and the electric field at other locations tends to decrease. For this reason, the fall of the electric field given to the semiconductor chip 2 can be suppressed when the region facing the end 2a of the semiconductor chip is not covered with the insulating film 15.
By covering the electrode portion 13 with the insulating film 15 having a volume resistivity higher than that of the insulating resin 8, it is possible to suppress the influence of the electric field on the electrode and the wiring member around the end portion 2a of the semiconductor chip. Furthermore, since the effect of lowering the breakdown voltage of the semiconductor chip 2 is suppressed when the insulating film 15 is coated on the part of the electrode part 13 that faces the end part 2a of the semiconductor chip, the end part 2a of the semiconductor chip and its surrounding electrodes and Depending on the positional relationship with the wiring member, the covering area of the insulating film 15 on the region facing the end 2a of the semiconductor chip is changed, and the covering of the insulating film 15 on the region facing the end 2a of the semiconductor chip is limited. It is good to do.

以上のように、本実施の形態2によれば、半導体装置1の内部であって、半導体チップ2の端部2aの上方に配置された電極部13の少なくとも側面部に絶縁樹脂8よりも体積抵抗率の高い絶縁膜15を被覆し、少なくとも半導体チップ2の端部2に対向する面の一部にはこの絶縁膜15を被覆しないようにしたので、半導体チップ2に外部から電界を与えても、半導体チップの端部2a周辺あるいは電極部13の周辺の電極及び配線部材への電界の影響は抑制され、絶縁が維持され、感度の高い劣化診断を行うことが可能となる。   As described above, according to the second embodiment, at least the side surface portion of the electrode portion 13 disposed inside the semiconductor device 1 and above the end portion 2 a of the semiconductor chip 2 has a volume larger than that of the insulating resin 8. Since the insulating film 15 having a high resistivity is covered and at least a part of the surface facing the end 2 of the semiconductor chip 2 is not covered with the insulating film 15, an electric field is applied to the semiconductor chip 2 from the outside. However, the influence of the electric field on the electrodes and wiring members around the end 2a of the semiconductor chip or around the electrode part 13 is suppressed, insulation is maintained, and a highly sensitive deterioration diagnosis can be performed.

実施の形態3.
以下に、実施の形態3に係る半導体装置の構成について説明する。
図7は、実施の形態3に係る半導体装置の構成を示す図である。電極部13が半導体装置1の絶縁樹脂8中の半導体チップ2の端部2aの上方に配置されている点は実施の形態1、2と同様であるが、電極部13が絶縁膜16で被覆されている点が、実施の形態1、2と相違する。
実施の形態2で述べたように、電極部13より印加される電界は、周囲の絶縁材料の体積抵抗率に影響される。本実施の形態3に示す半導体装置1の構造では、図7のように、電極部13の下部に絶縁膜16を被覆し、且つ絶縁膜16の体積抵抗率は、絶縁樹脂8の体積抵抗率よりも低いものとする。この構造により、絶縁膜16の被覆された電極部13の下部と対向する半導体チップの端部2aとの間の電界が強調される。
Embodiment 3 FIG.
The configuration of the semiconductor device according to the third embodiment will be described below.
FIG. 7 is a diagram showing a configuration of the semiconductor device according to the third embodiment. Although the electrode part 13 is arranged above the end part 2a of the semiconductor chip 2 in the insulating resin 8 of the semiconductor device 1 as in the first and second embodiments, the electrode part 13 is covered with the insulating film 16. This is different from the first and second embodiments.
As described in the second embodiment, the electric field applied from the electrode portion 13 is affected by the volume resistivity of the surrounding insulating material. In the structure of the semiconductor device 1 shown in the third embodiment, as shown in FIG. 7, the insulating film 16 is covered under the electrode portion 13, and the volume resistivity of the insulating film 16 is the volume resistivity of the insulating resin 8. Lower than. With this structure, the electric field between the lower part of the electrode part 13 covered with the insulating film 16 and the end part 2a of the semiconductor chip facing the surface is emphasized.

次に、電極部13の下部を絶縁膜16で被覆した場合の電界解析の結果について説明する。図8は実施の形態3に係る半導体装置の電界解析モデルを示す図である。モデルの基本構成は実施の形態2の図6A及び図6Bで説明したものと同様である。図8においては、絶縁膜16の厚みをtとする。
図8の電界解析モデルにおいて、絶縁樹脂8を例えばシリコーンゲルとして体積抵抗率を1×1013Ωm、絶縁膜16を例えばエポキシ樹脂として体積抵抗率を1×1012Ωmとし、電極部13の直径dを3mm、高さhを2mm、絶縁膜16を電極下面のみに被覆し、その厚みtを0.1mmとする。この図8の場合のA点の電界と絶縁膜が図8において絶縁膜16が被覆されていない場合のA点の電界を直流場の電界解析により比較した。その結果、絶縁膜16が被覆された図8の場合の電界は絶縁膜が被覆されていない場合の電界と比較して約6%高い電界となった。
Next, the result of the electric field analysis when the lower part of the electrode part 13 is covered with the insulating film 16 will be described. FIG. 8 is a diagram showing an electric field analysis model of the semiconductor device according to the third embodiment. The basic configuration of the model is the same as that described in FIGS. 6A and 6B of the second embodiment. In FIG. 8, the thickness of the insulating film 16 is t.
In the field analysis model of FIG. 8, the insulation volume resistivity of the resin 8 as e.g. silicone gel 1 × 10 13 [Omega] m, a volume resistivity of a 1 × 10 12 Ωm an insulating film 16 as, for example, an epoxy resin, the diameter of the electrode portions 13 d is 3 mm, height h is 2 mm, the insulating film 16 is covered only on the lower surface of the electrode, and the thickness t is 0.1 mm. The electric field at point A in FIG. 8 and the electric field at point A when the insulating film 16 is not covered with the insulating film in FIG. 8 were compared by electric field analysis of a DC field. As a result, the electric field in the case of FIG. 8 covered with the insulating film 16 was about 6% higher than the electric field in the case where the insulating film was not covered.

また、図7では、電極部13の下部から側面の一部に亘って絶縁膜16を設けた例を示したが、図9のように、絶縁膜16を電極部13の側面にのみ設けてもよい。図8で説明した電界解析モデルと同様の材料、パラメータ(物性値)を用い、図9で絶縁膜の厚みを0.1mmとした場合と絶縁膜16を被覆しない場合のA点の電界を比較した。その結果、0.1mmの厚さの絶縁膜16を側面に設けた電極部13の方が約2%高い電界となった。
さらに、電極部13の下面及び側面の両方に絶縁膜16を設けてもよい。この電極部13の下面および側面の両方に厚さが0.1mmの絶縁膜16を設けた場合のA点の電界は、絶縁膜を被覆しない場合のA点の電界に比べて約8%高くなった。
以上のことから、絶縁膜16を電極部13の表面全体に被覆してもよいが、絶縁膜16は絶縁樹脂8の体積抵抗率よりも低く、電極部13に印加された電圧からの電界の影響を強調するように作用するため、電極部13の周辺及び半導体チップ2の端部2aの周囲の電極及び配線部材等との絶縁性を考慮して設ける必要がある。
7 shows an example in which the insulating film 16 is provided from the lower part of the electrode portion 13 to a part of the side surface, but the insulating film 16 is provided only on the side surface of the electrode portion 13 as shown in FIG. Also good. Using the same materials and parameters (physical properties) as those in the electric field analysis model described in FIG. 8, the electric field at point A is compared when the insulating film thickness is 0.1 mm and when the insulating film 16 is not covered in FIG. did. As a result, the electrode portion 13 provided with the insulating film 16 having a thickness of 0.1 mm on the side surface has a higher electric field by about 2%.
Further, the insulating film 16 may be provided on both the lower surface and the side surface of the electrode portion 13. The electric field at point A when the insulating film 16 having a thickness of 0.1 mm is provided on both the lower surface and the side surface of the electrode portion 13 is about 8% higher than the electric field at point A when the insulating film is not covered. became.
From the above, the insulating film 16 may be covered on the entire surface of the electrode portion 13, but the insulating film 16 is lower than the volume resistivity of the insulating resin 8, and the electric field from the voltage applied to the electrode portion 13 is reduced. In order to act so as to emphasize the influence, it is necessary to provide in consideration of insulation between the electrode portion 13 and the electrodes and wiring members around the end portion 2a of the semiconductor chip 2.

以上のように、実施の形態3によれば、半導体装置1の内部であって、半導体チップ2の端部2aの上方に配置された電極部13の少なくとも下部に絶縁樹脂8よりも体積抵抗率の低い絶縁膜16を被覆したので、半導体チップ2に外部から電界を与えても、半導体チップの端部2a周辺あるいは電極部13の周辺の電極及び配線部材への電界の影響は強調せず、半導体チップ2に与えた電界を強めることができ、感度の高い劣化診断を行うことが可能となる。   As described above, according to the third embodiment, the volume resistivity is higher than that of the insulating resin 8 inside the semiconductor device 1 and at least below the electrode portion 13 disposed above the end portion 2 a of the semiconductor chip 2. Therefore, even if an electric field is applied to the semiconductor chip 2 from the outside, the influence of the electric field on the electrodes and wiring members around the end 2a of the semiconductor chip or around the electrode part 13 is not emphasized. The electric field applied to the semiconductor chip 2 can be strengthened, and a highly sensitive deterioration diagnosis can be performed.

実施の形態4.
以下、実施の形態4に係る半導体装置の構成について説明する。上述の実施の形態1から3では、半導体装置1の内部、半導体チップの端部2aの上方に電極部13を配置しているので、この電極部13が通常の半導体装置1の運転時にも存在することになる。半導体装置1の運転時には、基板上部電極4または半導体チップの上面電極9にかかる電圧によって、電極部13の周囲にも多少の電界が発生する。そのため、電極部13の周囲に発生する電界の大きさによっては電極部13にも長期的に課電されることになり、この影響で半導体装置1が劣化することも考えられる。本実施の形態では、電極部13を着脱可能な構成とし、劣化診断時に電極部13を半導体装置1内に設置し、劣化診断時以外は半導体装置1から取り外すことが可能な半導体装置1の構造を提供する。
Embodiment 4 FIG.
The configuration of the semiconductor device according to the fourth embodiment will be described below. In the above-described first to third embodiments, since the electrode portion 13 is disposed inside the semiconductor device 1 and above the end portion 2a of the semiconductor chip, the electrode portion 13 is also present during normal operation of the semiconductor device 1. Will do. During operation of the semiconductor device 1, a slight electric field is also generated around the electrode portion 13 due to the voltage applied to the substrate upper electrode 4 or the upper surface electrode 9 of the semiconductor chip. For this reason, depending on the magnitude of the electric field generated around the electrode portion 13, the electrode portion 13 is also charged for a long period of time, and the semiconductor device 1 may be deteriorated due to this influence. In the present embodiment, the structure of the semiconductor device 1 is configured such that the electrode portion 13 is detachable, the electrode portion 13 is installed in the semiconductor device 1 at the time of deterioration diagnosis, and can be detached from the semiconductor device 1 except at the time of deterioration diagnosis. I will provide a.

図10A及び図10Bは、実施の形態4に係る半導体装置の構成を示す図である。図10Aは、半導体装置1が運転中であり、電極部13が外部に取り外された状態、図10Bは劣化診断時であり電極部13が半導体装置1の内部に取り付けられた状態を示している。図10A及び図10Bにおいて、絶縁樹脂8には上方から開口された、電極部13を設置することが可能な差込み穴20が設けられている。   10A and 10B are diagrams illustrating the configuration of the semiconductor device according to the fourth embodiment. 10A shows a state in which the semiconductor device 1 is in operation and the electrode unit 13 is removed to the outside, and FIG. 10B shows a state in which the electrode unit 13 is attached to the inside of the semiconductor device 1 at the time of deterioration diagnosis. . 10A and 10B, the insulating resin 8 is provided with an insertion hole 20 that is opened from above and in which the electrode portion 13 can be installed.

半導体装置1の運転時である図10Aの状態では、その差込み穴20は矢印で示されるように直脱可能な蓋21により塞がれている。また、差込み穴20に対向するケース7の蓋22も矢印で示されるように着脱可能である。
劣化診断時には、着脱可能な蓋22がケースから外され、蓋21が絶縁樹脂8から外されて電極部13が点線矢印で示されるように差込み穴20に挿入される。劣化診断時は図10Bで示される状態となる。
In the state of FIG. 10A when the semiconductor device 1 is in operation, the insertion hole 20 is closed with a lid 21 that can be directly removed as indicated by an arrow. Further, the lid 22 of the case 7 facing the insertion hole 20 is also detachable as indicated by an arrow.
At the time of deterioration diagnosis, the detachable lid 22 is removed from the case, the lid 21 is removed from the insulating resin 8, and the electrode portion 13 is inserted into the insertion hole 20 as indicated by a dotted arrow. At the time of deterioration diagnosis, the state shown in FIG. 10B is obtained.

差込み穴20の形状は、電極部13を挿入できるクリアランスを持つ程度の電極部13とほぼ同じ形状が望ましい。また差込み穴20を設けることにより、差込み穴20を通して絶縁樹脂8へ水分が浸入し、半導体チップに対する吸湿劣化が促進される可能性がある。そのため、診断時以外は、差込み穴20は密着性の高い蓋21を用いて密閉しておくことが望ましい。また、図で示した蓋21でなく、差込み穴20の形状と同じ、すなわち電極部13と同じ形状で絶縁樹脂8と同材料の樹脂を着脱可能にすれば密閉性をより保つことが可能となる。   The shape of the insertion hole 20 is desirably substantially the same as that of the electrode portion 13 having a clearance that allows the insertion of the electrode portion 13. Further, by providing the insertion hole 20, moisture may enter the insulating resin 8 through the insertion hole 20, which may promote moisture absorption deterioration of the semiconductor chip. For this reason, it is desirable to seal the insertion hole 20 using a lid 21 with high adhesion except during diagnosis. In addition, if the resin of the same material as the insulating resin 8 is made detachable in the same shape as the insertion hole 20 instead of the lid 21 shown in the drawing, that is, the shape of the electrode portion 13, it is possible to further maintain the sealing performance. Become.

また、ケース7の着脱可能な蓋22も同様の理由で密閉性を担保できるように構成することが望ましい。   Moreover, it is desirable that the detachable lid 22 of the case 7 is configured so as to ensure sealing performance for the same reason.

以上のように、本実施の形態4によれば、実施の形態1から3と同様の効果に加え、電極部13を半導体装置1から着脱可能な構成としたので、半導体装置1の運転時には電極部13を取り外すことが可能となり、電極部13が設置されて長期的に課電されることによる劣化促進を抑制することができる。   As described above, according to the fourth embodiment, in addition to the same effects as those of the first to third embodiments, the electrode unit 13 is configured to be detachable from the semiconductor device 1. It becomes possible to remove the part 13, and the deterioration promotion by the electrode part 13 being installed and being charged for a long term can be suppressed.

実施の形態5.
以下、実施の形態5に係る半導体装置の構成について説明する。上述の実施の形態1から4では、半導体チップの端部2aの上方に配置された電極部13は半導体チップの端部2aの一部に対向するように配置されている。しかし、半導体チップの劣化発生について、全体が均一的に劣化するのではなく、半導体チップの端部の中でも部分的に劣化することもある。劣化発生部の直上に電極部13が配置されていない場合は、劣化診断の感度が低下する虞がある。本実施の形態5では、半導体チップの端部2aの領域に亘って、広く対向するように電極部13を配置する。
Embodiment 5 FIG.
Hereinafter, the configuration of the semiconductor device according to the fifth embodiment will be described. In the above-described first to fourth embodiments, the electrode portion 13 disposed above the end portion 2a of the semiconductor chip is disposed so as to face a part of the end portion 2a of the semiconductor chip. However, the occurrence of deterioration of the semiconductor chip is not uniformly deteriorated as a whole, but may be partially deteriorated in the end portion of the semiconductor chip. When the electrode part 13 is not disposed immediately above the deterioration occurrence part, there is a possibility that the sensitivity of deterioration diagnosis is lowered. In the fifth embodiment, the electrode portion 13 is arranged so as to face widely across the region of the end portion 2a of the semiconductor chip.

図11A及び図11Bは、実施の形態5に係る半導体装置の構成を示す図である。図11Aは側面図、図11Bは、半導体チップ2の周辺と電極部13の位置関係を示す斜視図である。電極部13は半導体チップ2の周囲の半導体チップの端部2aに対向するように配置される。電極部13の中央部は半導体チップ2の上面電極9に対向する領域であり、開口されている。そして、開口部を介して配線が行われる。このように半導体チップの端部2aの上部をカバーするように電極部13を配置する。   11A and 11B are diagrams illustrating the configuration of the semiconductor device according to the fifth embodiment. 11A is a side view, and FIG. 11B is a perspective view showing the positional relationship between the periphery of the semiconductor chip 2 and the electrode portion 13. The electrode portion 13 is disposed so as to face the end portion 2 a of the semiconductor chip around the semiconductor chip 2. The central portion of the electrode portion 13 is a region facing the upper surface electrode 9 of the semiconductor chip 2 and is opened. Then, wiring is performed through the opening. Thus, the electrode part 13 is arrange | positioned so that the upper part of the edge part 2a of a semiconductor chip may be covered.

図11Bのように、半導体チップの端部2aの上部をカバーするように電極部13を配置できない場合は、半導体チップの端部2aの一辺の上部をカバーするように配置すればよい。図12A及び図12Bは、実施の形態5に係る半導体装置を示す別の一部構成図である。図12Aは半導体チップ2の周辺と電極部13の位置関係を示す斜視図、図12Bは、半導体チップ2の周辺と電極部13の位置関係を示す上面図である。このように、半導体チップの端部2aの一辺の上部をカバーするように電極部13を配置すればよい。図12A及び図12Bでは、半導体チップの端部2aの一辺の上部をカバーするように電極部13を配置したが、電極部13を上面から見てL字状に配置して、隣り合う2辺をカバーするようにしてもよいし、矩形のU字状に配置して、隣り合う3辺をカバーするようにしてもよい。また、図12A及び図12Bで示された一辺に対応する電極をそれぞれの辺に設けて、半導体チップの端部2aの周辺をカバーするようにしてもよいし、L字状の電極部13を2つ組み合わせてもよい。   When the electrode part 13 cannot be arranged so as to cover the upper part of the end part 2a of the semiconductor chip as shown in FIG. 11B, it may be arranged so as to cover the upper part of one side of the end part 2a of the semiconductor chip. 12A and 12B are other partial configuration diagrams showing the semiconductor device according to the fifth embodiment. 12A is a perspective view showing the positional relationship between the periphery of the semiconductor chip 2 and the electrode portion 13, and FIG. 12B is a top view showing the positional relationship between the periphery of the semiconductor chip 2 and the electrode portion 13. Thus, the electrode part 13 should just be arrange | positioned so that the upper part of one side of the edge part 2a of a semiconductor chip may be covered. 12A and 12B, the electrode portion 13 is arranged so as to cover the upper portion of one side of the end portion 2a of the semiconductor chip. However, the electrode portion 13 is arranged in an L shape when viewed from the upper surface, and two adjacent sides are arranged. Or may be arranged in a rectangular U shape so as to cover three adjacent sides. Further, an electrode corresponding to one side shown in FIGS. 12A and 12B may be provided on each side so as to cover the periphery of the end portion 2a of the semiconductor chip, or the L-shaped electrode portion 13 may be provided. Two may be combined.

以上のように、実施の形態5によれば、半導体チップの端部2aの少なくとも一辺の領域に亘って対向するような電極部13の形状で、半導体チップの端部2aの上方に電極部13を配置したので、実施の形態1から3と同様の効果を奏するとともに、さらに劣化診断の精度が向上する。   As described above, according to the fifth embodiment, the electrode portion 13 is shaped so as to be opposed to at least one region of the end portion 2a of the semiconductor chip and above the end portion 2a of the semiconductor chip. Thus, the same effects as those of the first to third embodiments are obtained, and the accuracy of deterioration diagnosis is further improved.

実施の形態6.
以下、実施の形態6に係る半導体装置の構成について説明する。上述の実施の形態5では、少なくとも一辺の領域に亘って対向するような電極部13の形状で、半導体チップの端部2aの上方に1つの電極部13を配置したが、本実施の形態6では半導体チップの端部2aの一辺に対向するように複数の電極部13を配置する。
Embodiment 6 FIG.
The configuration of the semiconductor device according to the sixth embodiment will be described below. In Embodiment 5 described above, one electrode portion 13 is arranged above the end portion 2a of the semiconductor chip in the shape of the electrode portion 13 that is opposed over at least one side region. Then, the plurality of electrode portions 13 are arranged so as to face one side of the end portion 2a of the semiconductor chip.

図13A及び図13Bは、実施の形態6に係る半導体装置を示す一部構成図である。図13Aは半導体チップ2の周辺と電極部13の位置関係を示す斜視図、図13Bは、半導体チップ2の周辺と電極部13の位置関係を示す上面図である。半導体チップの端部2aの一辺の上部をカバーするように複数の電極部13が配置されている。複数の電極部13はそれぞれ配線131により直流電源14に接続される。   13A and 13B are partial configuration diagrams illustrating the semiconductor device according to the sixth embodiment. FIG. 13A is a perspective view showing the positional relationship between the periphery of the semiconductor chip 2 and the electrode portion 13, and FIG. 13B is a top view showing the positional relationship between the periphery of the semiconductor chip 2 and the electrode portion 13. A plurality of electrode portions 13 are arranged so as to cover an upper portion of one side of the end portion 2a of the semiconductor chip. Each of the plurality of electrode portions 13 is connected to the DC power supply 14 by a wiring 131.

このように配置された複数の電極部13のすべてに電圧を印加すれば、実施の形態5の図12A、12Bの例と同様に、半導体チップの端部2aの一辺に亘って電界が発生し、劣化診断を行うことが可能となる。この場合、電極部13間接続して電圧を印加するようにしてもよい。
また、複数の電極部13に順次電圧を印加することよりそれぞれの電極部13の対向する半導体チップの端部2a近傍の診断を行うことにより、劣化発生箇所の特定を行うことが可能となる。
If a voltage is applied to all of the plurality of electrode portions 13 arranged in this way, an electric field is generated over one side of the end portion 2a of the semiconductor chip, as in the example of FIGS. 12A and 12B of the fifth embodiment. Deterioration diagnosis can be performed. In this case, the electrodes 13 may be connected to apply a voltage.
In addition, by sequentially applying voltages to the plurality of electrode portions 13 and performing diagnosis in the vicinity of the end 2a of the semiconductor chip facing each of the electrode portions 13, it is possible to specify a degradation occurrence location.

上述の図13A及び図13Bでは、半導体チップの端部2aの一辺の上部をカバーするように複数の電極部13が配置されているが、隣り合う二辺の上部をカバーするようにL字状に複数配置してもよい。また、半導体チップの端部2aの隣り合う三辺の上部をカバーするように矩形のU字状に複数配置してもよいし、半導体チップの端部2aの周囲に亘って額縁状に複数配置してもよい。   In FIG. 13A and FIG. 13B described above, the plurality of electrode portions 13 are arranged so as to cover the upper portion of one side of the end portion 2a of the semiconductor chip, but are L-shaped so as to cover the upper portions of two adjacent sides. A plurality of them may be arranged. Further, a plurality of rectangular U-shapes may be arranged so as to cover the upper part of three adjacent sides of the end 2a of the semiconductor chip, or a plurality of frames are arranged around the periphery of the end 2a of the semiconductor chip. May be.

なお、上述の実施の形態5、6の構造を実施の形態4のように、着脱可能にするには、絶縁樹脂8に電極部13の形状に対応する差込み穴を設ければよい。   In order to make the structure of the above-described fifth and sixth embodiments detachable as in the fourth embodiment, an insertion hole corresponding to the shape of the electrode portion 13 may be provided in the insulating resin 8.

以上のように、実施の形態6によれば、半導体チップの端部2aの少なくとも一辺の領域に亘って対向するように複数の電極部13を配置したので、実施の形態5と同様の効果を奏する。また、複数の電極部13に順次電圧を印加することよりそれぞれの電極部13の対向する半導体チップの端部2a近傍の診断を行うことにより、劣化発生箇所の特定を行うことが可能となり、さらに劣化診断の精度が向上する。   As described above, according to the sixth embodiment, since the plurality of electrode portions 13 are arranged so as to face each other over at least one side region of the end portion 2a of the semiconductor chip, the same effect as that of the fifth embodiment is obtained. Play. In addition, it is possible to identify the location of deterioration by applying a voltage sequentially to the plurality of electrode portions 13 to diagnose the vicinity of the end 2a of the semiconductor chip facing each electrode portion 13, and The accuracy of deterioration diagnosis is improved.

実施の形態7.
以下、実施の形態7に係る半導体装置の劣化診断装置の構成について説明する。
半導体装置の劣化発生要因の一つとして、半導体装置の外部からの水分の侵入が挙げられる。封止樹脂である絶縁樹脂の外側の空気中から徐々に水分が侵入し、やがて半導体チップに到達すると、半導体チップの劣化が促進される。したがって、半導体チップ近傍の絶縁樹脂の吸水状態を検知することは、半導体チップ自体の劣化診断における有用なデータとなる。絶縁樹脂が吸水すると、体積抵抗率が低下する。そのため、絶縁樹脂を流れる電流を計測することで、樹脂の劣化変動を検知することができる。
Embodiment 7 FIG.
The configuration of the semiconductor device degradation diagnosis apparatus according to the seventh embodiment will be described below.
One of the causes of deterioration of a semiconductor device is the intrusion of moisture from the outside of the semiconductor device. When moisture gradually enters from the air outside the insulating resin, which is a sealing resin, and eventually reaches the semiconductor chip, deterioration of the semiconductor chip is promoted. Therefore, detecting the water absorption state of the insulating resin in the vicinity of the semiconductor chip is useful data in the deterioration diagnosis of the semiconductor chip itself. When the insulating resin absorbs water, the volume resistivity decreases. Therefore, by measuring the current flowing through the insulating resin, it is possible to detect the deterioration variation of the resin.

図14は、実施の形態7に係る半導体装置の劣化診断装置の構成を示す図である。図において、半導体装置1の半導体チップの端部2aの上方であって絶縁樹脂8中に電極部13が配置されている構成は実施の形態1から6と同様である。また、半導体チップ2の上面電極9には電流計11が接続されている。   FIG. 14 is a diagram showing a configuration of a semiconductor device deterioration diagnosis apparatus according to the seventh embodiment. In the figure, the configuration in which the electrode portion 13 is disposed in the insulating resin 8 above the end portion 2a of the semiconductor chip of the semiconductor device 1 is the same as in the first to sixth embodiments. An ammeter 11 is connected to the upper surface electrode 9 of the semiconductor chip 2.

図14の構成において、まず電極部13に高電圧を印加すると、図14中矢印で示されるように、電極部13から半導体チップ2の上面電極9へ向かう方向に微小な電流が流れる。電流計11では、この絶縁樹脂8を介して上面電極9へ流れた電流を計測する。この電流値を計測することにより、半導体チップ2近傍の絶縁樹脂8の吸水状態を把握することができる。すなわち、半導体装置1の初期から、絶縁樹脂8が徐々に水分が侵入すると絶縁劣化が進み、絶縁樹脂8中を流れ、電流計11で計測される電流が増加することになる。初期の電流を予め取得しておき、基準電流とし、計測された電流と比較することで劣化診断を行うことができる。なお、電極部13に印加される電圧は実施の形態1と同様に絶縁樹脂8の絶縁破壊電圧以下である。   In the configuration of FIG. 14, when a high voltage is first applied to the electrode portion 13, a minute current flows in a direction from the electrode portion 13 toward the upper surface electrode 9 of the semiconductor chip 2 as indicated by an arrow in FIG. 14. The ammeter 11 measures the current that has flowed to the upper surface electrode 9 through the insulating resin 8. By measuring this current value, it is possible to grasp the water absorption state of the insulating resin 8 in the vicinity of the semiconductor chip 2. That is, when the insulating resin 8 gradually enters moisture from the beginning of the semiconductor device 1, the deterioration of insulation progresses, flows through the insulating resin 8, and the current measured by the ammeter 11 increases. An initial current is acquired in advance, used as a reference current, and a deterioration diagnosis can be performed by comparing with a measured current. Note that the voltage applied to the electrode portion 13 is equal to or lower than the dielectric breakdown voltage of the insulating resin 8 as in the first embodiment.

図15は、実施の形態7に係る半導体装置の劣化診断装置の別の構成を示す図で、電流計11を基板上部電極4に接続した例である。また、図16は、実施の形態7に係る半導体装置の劣化診断装置のさらに別の構成を示す図で、電流計11を半導体チップ2の上面電極9及び基板上部電極4の両方に接続した例である。
図15の構成においては、図15中矢印で示されるように、電極部13から基板上部電極4へ向かう方向に流れる微小な電流を基板上部電極4に接続された電流計11で計測する。このとき水分が外側からチップ方向へ向けて横から侵入してきた場合、図15の構成は、図14の構成よりもチップ外側領域を流れる電流を計測するため、図14の構成よりも変動を早期に検知できる。図16の構成においては、図16中矢印で示されるように、電極部13から半導体チップ2の上面電極9へ向かう方向及び基板上部電極4へ向かう方向に流れる微小な電流を電流計11で計測する。電流の経路が広いため、図16の構成は、図14および図15の構成よりも変動量を検知しやすくなる。ただし、図15、図16は図14とは異なり、実施の形態6までに示した半導体チップの劣化診断時とは電流計の接続を変える必要がある。
FIG. 15 is a diagram illustrating another configuration of the deterioration diagnosis apparatus for a semiconductor device according to the seventh embodiment, in which the ammeter 11 is connected to the substrate upper electrode 4. FIG. 16 is a diagram showing still another configuration of the deterioration diagnosis device for a semiconductor device according to the seventh embodiment, in which an ammeter 11 is connected to both the upper surface electrode 9 and the substrate upper electrode 4 of the semiconductor chip 2. It is.
In the configuration of FIG. 15, as indicated by an arrow in FIG. 15, a minute current flowing in the direction from the electrode portion 13 toward the substrate upper electrode 4 is measured by an ammeter 11 connected to the substrate upper electrode 4. At this time, when moisture enters from the outside toward the chip direction from the outside, the configuration of FIG. 15 measures the current flowing in the chip outside region more than the configuration of FIG. Can be detected. In the configuration of FIG. 16, as indicated by an arrow in FIG. 16, the ammeter 11 measures a minute current flowing from the electrode portion 13 toward the upper surface electrode 9 of the semiconductor chip 2 and toward the substrate upper electrode 4. To do. Since the current path is wide, the configuration of FIG. 16 is easier to detect the variation than the configurations of FIGS. However, FIG. 15 and FIG. 16 differ from FIG. 14 in that the connection of the ammeter needs to be changed from the time of the semiconductor chip deterioration diagnosis shown in the sixth embodiment.

なお、絶縁樹脂8の電流を計測するのに、電極部13から半導体チップ2の周辺の電極に向かう電流を計測する例を示したが、これに限るものではない。例えば、実施の形態6で示した複数の電極部13を配置する例においては、電極部13間に流れる電流を計測してもよい。図17は、実施の形態7に係る半導体装置の劣化診断装置のさらに別の構成を示す図で、電流計11を電極部13の1つに接続している。図17に示されるように、一つの電極部13に電圧を印加し、電流計11の接続された別の電極部13に向かう電流を計測してもよい。   In addition, although the example which measures the electric current which goes to the electrode of the periphery of the semiconductor chip 2 from the electrode part 13 was shown in order to measure the electric current of the insulating resin 8, it does not restrict to this. For example, in the example in which the plurality of electrode portions 13 shown in the sixth embodiment are arranged, the current flowing between the electrode portions 13 may be measured. FIG. 17 is a diagram showing still another configuration of the semiconductor device deterioration diagnosis apparatus according to the seventh embodiment, in which the ammeter 11 is connected to one of the electrode sections 13. As shown in FIG. 17, a voltage may be applied to one electrode unit 13 and a current directed to another electrode unit 13 to which the ammeter 11 is connected may be measured.

以上のように、実施の形態7によれば、半導体装置1内の絶縁樹脂8中に配設された電極部13を用い、電極部13から半導体チップ2の上面電極9あるいは半導体チップの搭載された基板上部電極4等の半導体チップ2の周辺に向かう電流を計測することで、あるいは複数配設された電極部13間に流れる電流を計測することで、絶縁樹脂8の劣化を診断が可能となる。また、実施の形態1から6と合わせて半導体装置1として総合的な劣化診断を行うことが可能となり、劣化診断の精度が向上する。実施の形態1の図3のフローチャートにおいて、ステップS1の後、半導体チップ2に電圧を印加する前に絶縁樹脂8の劣化診断を行えばよい。   As described above, according to the seventh embodiment, the electrode portion 13 disposed in the insulating resin 8 in the semiconductor device 1 is used to mount the upper surface electrode 9 of the semiconductor chip 2 or the semiconductor chip from the electrode portion 13. The deterioration of the insulating resin 8 can be diagnosed by measuring the current flowing toward the periphery of the semiconductor chip 2 such as the substrate upper electrode 4 or by measuring the current flowing between the plurality of arranged electrode portions 13. Become. In addition, it is possible to perform comprehensive deterioration diagnosis as the semiconductor device 1 in combination with the first to sixth embodiments, and the accuracy of deterioration diagnosis is improved. In the flowchart of FIG. 3 of the first embodiment, after step S1, deterioration diagnosis of the insulating resin 8 may be performed before applying a voltage to the semiconductor chip 2.

上記実施の形態7では、半導体装置1内の絶縁樹脂8中に配設された電極部13を用い、絶縁樹脂8を流れる電流を計測することで、絶縁樹脂8の劣化診断を行うようにしたが、絶縁樹脂8中の劣化診断はこの方法に限るものではない。予め決められた絶縁樹脂の間の静電容量の変化を計測する方法もある。そこで、図17の構成において、電極部13に電流計11を接続するのではなく、電極部13間の外部経路に静電容量計を接続して、電極部13間の絶縁樹脂8の静電容量を計測する。上述した絶縁樹脂8の電流変化のように、半導体装置1の初期から、絶縁樹脂8が徐々に水分が侵入すると絶縁劣化が進み、絶縁樹脂8の静電容量が変動することになる。初期の状態を基準の静電容量とし、この静電容量の変動を評価することによって絶縁樹脂8の劣化状態を診断すればよい。   In the seventh embodiment, the deterioration of the insulating resin 8 is diagnosed by measuring the current flowing through the insulating resin 8 using the electrode portion 13 disposed in the insulating resin 8 in the semiconductor device 1. However, the deterioration diagnosis in the insulating resin 8 is not limited to this method. There is also a method of measuring a change in capacitance between predetermined insulating resins. Therefore, in the configuration of FIG. 17, the ammeter 11 is not connected to the electrode portion 13, but a capacitance meter is connected to the external path between the electrode portions 13, and the electrostatic resin 8 between the electrode portions 13 is electrostatically connected. Measure capacity. As in the case of the current change in the insulating resin 8 described above, when the insulating resin 8 gradually enters moisture from the initial stage of the semiconductor device 1, the deterioration of the insulation proceeds and the capacitance of the insulating resin 8 changes. The deterioration state of the insulating resin 8 may be diagnosed by setting the initial state as a reference capacitance and evaluating the fluctuation of the capacitance.

本開示は、様々な例示的な実施の形態及び実施例が記載されているが、1つ、または複数の実施の形態に記載された様々な特徴、態様、及び機能は特定の実施の形態の適用に限られるのではなく、単独で、または様々な組み合わせで実施の形態に適用可能である。
従って、例示されていない無数の変形例が、本願明細書に開示される技術の範囲内において想定される。例えば、少なくとも1つの構成要素を変形する場合、追加する場合または省略する場合、さらには、少なくとも1つの構成要素を抽出し、他の実施の形態の構成要素と組み合わせる場合が含まれるものとする。
Although this disclosure describes various exemplary embodiments and examples, various features, aspects, and functions described in one or more embodiments may be described in terms of particular embodiments. The present invention is not limited to the application, and can be applied to the embodiments alone or in various combinations.
Accordingly, countless variations that are not illustrated are envisaged within the scope of the technology disclosed herein. For example, the case where at least one component is deformed, the case where the component is added or omitted, the case where the at least one component is extracted and combined with the component of another embodiment are included.

1:半導体装置、 2:半導体チップ、 2a:半導体チップの端部、 3:絶縁基板、 4:基板上部電極、 5:基板下部電極、 6:放熱板、 7:ケース、 8:絶縁樹脂、 9:上面電極、 10:電源、 11:電流計、 13:電極部、 14:直流電源、 15、16:絶縁膜、 20:差込み穴、 21:蓋、 22:蓋   DESCRIPTION OF SYMBOLS 1: Semiconductor device, 2: Semiconductor chip, 2a: End part of semiconductor chip, 3: Insulating substrate, 4: Substrate upper electrode, 5: Substrate lower electrode, 6: Heat sink, 7: Case, 8: Insulating resin, 9 : Top electrode, 10: Power supply, 11: Ammeter, 13: Electrode section, 14: DC power supply, 15, 16: Insulating film, 20: Insertion hole, 21: Cover, 22: Cover

Claims (11)

絶縁基板及び前記絶縁基板上の電極を介して搭載された半導体チップを有し、前記絶縁基板及び前記半導体チップが絶縁樹脂により封止された半導体装置であって、
前記半導体チップの端部に対向した上方の前記絶縁樹脂内で、前記半導体チップと離間し電気的に絶縁されて配置され、外部から電圧を印加可能な電極部を備えた半導体装置。
A semiconductor device having a semiconductor chip mounted via an insulating substrate and an electrode on the insulating substrate, wherein the insulating substrate and the semiconductor chip are sealed with an insulating resin,
A semiconductor device comprising: an electrode portion which is disposed in the insulating resin above and facing the end portion of the semiconductor chip so as to be electrically insulated from the semiconductor chip and to which a voltage can be applied from the outside.
前記電極部の少なくとも側面は、前記絶縁樹脂の体積抵抗率よりも高い体積抵抗率を有する絶縁膜で覆われており、前記電極部の前記半導体チップと対向する面のうち少なくとも一部は前記絶縁膜で覆われていない請求項1に記載の半導体装置。   At least a side surface of the electrode portion is covered with an insulating film having a volume resistivity higher than the volume resistivity of the insulating resin, and at least a part of the surface of the electrode portion facing the semiconductor chip is the insulating material. The semiconductor device according to claim 1, which is not covered with a film. 前記電極部の前記半導体チップと対向する面のうち少なくとも一部は前記絶縁樹脂の体積抵抗率よりも低い体積抵抗率を有する絶縁膜で覆われている請求項1に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein at least a part of a surface of the electrode portion facing the semiconductor chip is covered with an insulating film having a volume resistivity lower than a volume resistivity of the insulating resin. 前記絶縁樹脂は上方から開口された差込み穴を有し、前記電極部は前記差込み穴に着脱可能に設けられた請求項1から3のいずれか一項に記載の半導体装置。   4. The semiconductor device according to claim 1, wherein the insulating resin has an insertion hole opened from above, and the electrode portion is detachably provided in the insertion hole. 5. 前記電極部は、前記半導体チップの端部の少なくとも一辺に沿って対向するように配置された請求項1から4のいずれか一項に記載の半導体装置。   5. The semiconductor device according to claim 1, wherein the electrode portion is disposed so as to face along at least one side of an end portion of the semiconductor chip. 6. 前記電極部は、前記半導体チップの端部に対向して複数配置された請求項1から4のいずれか一項に記載の半導体装置。   5. The semiconductor device according to claim 1, wherein a plurality of the electrode portions are arranged to face an end portion of the semiconductor chip. 請求項1から6のいずれか一項に記載の半導体装置の劣化診断を行う半導体装置の劣化診断装置であって、
前記電極部に電圧を印加する電源と、
前記半導体チップに電圧を印加する電源と、
前記半導体チップに流れる電流を計測する電流計と、を備えた半導体装置の劣化診断装置。
A deterioration diagnosis device for a semiconductor device that performs deterioration diagnosis on a semiconductor device according to any one of claims 1 to 6 ,
A power supply for applying a voltage to the electrode section;
A power source for applying a voltage to the semiconductor chip;
An apparatus for diagnosing deterioration of a semiconductor device, comprising: an ammeter that measures a current flowing through the semiconductor chip.
請求項1から5のいずれか一項に記載の半導体装置の劣化診断を行う半導体装置の劣化診断装置であって、
前記電極部に電圧を印加する電源と、
前記半導体チップに流れる電流を計測する電流計と、を備えた半導体装置の劣化診断装置。
A degradation diagnosis device for a semiconductor device that performs degradation diagnosis on a semiconductor device according to any one of claims 1 to 5 ,
A power supply for applying a voltage to the electrode section;
An apparatus for diagnosing deterioration of a semiconductor device, comprising: an ammeter that measures a current flowing through the semiconductor chip.
請求項6に記載の半導体装置と、
前記電極部に電圧を印加する電源と、
前記半導体チップに流れる電流を計測する電流計あるいは複数の前記電極部の1つに接続された電流計と、を備えた半導体装置の劣化診断装置。
A semiconductor device according to claim 6;
A power supply for applying a voltage to the electrode section;
An apparatus for diagnosing deterioration of a semiconductor device, comprising: an ammeter for measuring a current flowing through the semiconductor chip; or an ammeter connected to one of the plurality of electrode portions.
請求項1から6のいずれか一項に記載の半導体装置を劣化診断する半導体装置の劣化診断方法であって、
前記電極部に電圧を印加する第一ステップと、
前記電極部に電圧を印加した状態で、前記半導体チップに逆方向電圧を印加する第二ステップと、
前記半導体チップに流れる電流を計測する第三ステップと、
計測された電流と予め取得された基準電流とを比較し、劣化診断を行う第四ステップと、を備えた半導体装置の劣化診断方法。
A degradation diagnosis method for a semiconductor device for diagnosing degradation of the semiconductor device according to any one of claims 1 to 6,
A first step of applying a voltage to the electrode part;
A second step of applying a reverse voltage to the semiconductor chip with a voltage applied to the electrode portion;
A third step of measuring the current flowing through the semiconductor chip;
A degradation diagnosis method for a semiconductor device, comprising: a fourth step of comparing a measured current with a reference current acquired in advance and performing a degradation diagnosis.
前記第一ステップの後で、前記半導体チップに電圧を印加していない状態において、前記絶縁樹脂を流れる電流を計測するステップと、
計測された前記絶縁樹脂を流れる電流と予め取得された絶縁樹脂を流れる基準電流とを比較し、前記絶縁樹脂の劣化診断を行うステップとを備えた、請求項10に記載の半導体装置の劣化診断方法。
After the first step, in a state where no voltage is applied to the semiconductor chip, measuring a current flowing through the insulating resin;
The deterioration diagnosis of a semiconductor device according to claim 10, further comprising a step of comparing the measured current flowing through the insulating resin with a reference current flowing through the insulating resin acquired in advance to perform a deterioration diagnosis of the insulating resin. Method.
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