JP4582686B2 - Capacitor charging circuit integrated in a one-chip semiconductor device - Google Patents

Description

  The present invention relates to a capacitor charging circuit integrated in a one-chip semiconductor device, and more specifically, a circuit for charging a plurality of electric double layer capacitors connected in series, and a plurality of parallel monitor circuits for charging the capacitors equally. The present invention relates to a semiconductor device integrated with the above.

The electric double layer capacitor can be rapidly charged as compared with a secondary battery that takes time to charge. However, since the rated voltage of the electric double layer capacitor is as low as about 3V, usually a plurality of capacitors are connected in series to ensure a necessary voltage.
As described above, what is a problem when charging a plurality of large-capacity capacitors connected in series is non-uniform charging caused by a difference in capacitance between capacitors or self-charging or self-discharging.

For this measure, a charge equalization circuit called a parallel monitor is usually used (see, for example, Japanese Patent Laid-Open No. 2000-50495 (Patent Document 1)).
FIG. 3 shows the configuration of the conventional parallel monitor circuit. As can be seen from FIG. 3, the parallel monitor circuit is provided for each capacitor connected in series, and is provided inside the semiconductor device and partly externally. Since the parallel monitor circuits (monitor circuit + TR circuit) provided in the capacitors C1, C2, Cn all have the same configuration, the second parallel monitor circuit (the monitor circuit 2 and the monitor circuit 2) from the power source which is one of them. The TR circuit 2) will be described.

The TR circuit 2 includes an NPN transistor (TR2), a resistor (R21), and a resistor (R22).
A resistor (R22) is connected to the collector of the NPN transistor (TR2). The other end of the resistor (R22) is connected to the positive terminal of the capacitor (C2), and is further connected to the terminal (Cell1) of the semiconductor device. The emitter of the NPN transistor (TR2) is connected to the negative terminal of the capacitor (C2), and is further connected to the terminal (Cell2) of the semiconductor device. The base of the NPN transistor (TR2) is connected to the terminal (OUT2) of the semiconductor device via a resistor (R21).

In the semiconductor device, the drain and source of the Nch MOSFET (M21) are connected between the terminal (OUT2) and the terminal (Cell2), and the source and drain of the PchMOSFET (M22) are connected between the power supply (Vdd) and the terminal (OUT2). Is connected. The gate of the Nch MOSFET (M21) and the gate of the Pch MOSFET (M22) are connected in common. Further, an amplifier circuit (AMP2) for applying the control signal 2 to the gates of the Nch MOSFET (M21) and the Pch MOSFET (M22) is provided. The power supply of the amplifier circuit (AMP2) is the same as that of the semiconductor device.
When the control signal 2 is at a high level, the output voltage of the amplifier circuit (AMP2) is the power supply voltage (Vdd), so that the PchMOSFET (M22) is off, the NchMOSFET (M21) is on, and the base of the NPN transistor (TR2) NPN transistor (TR2) is off.
In this state, no bypass current flows and the capacitor (C2) is charged.

  When the voltage of the capacitor (C2) reaches full charge, the control signal 2 changes to a low level in response to an instruction from a control circuit (not shown). As a result, the output voltage of the amplifier circuit (AMP2) becomes 0 V (GND), so that the Pch MOSFET (M22) is turned on and the Nch MOSFET (M21) is turned off. When the PchMOSFET (M22) is turned on, the base current of the NPN transistor (TR2) is supplied from the power supply (Vdd) via the PchMOSFET (M22), the NPN transistor (TR2) is turned on, and the charging current of the capacitor (C2) To prevent overcharging. An example of a power supply device that can arbitrarily set a full charge or a charging voltage is disclosed in Japanese Patent Laid-Open No. 6-343225 (see Patent Document 2).

JP 2000-50495 A JP-A-6-343225

However, in the conventional circuit, when an N-type substrate is used as the substrate of the semiconductor device, the source of the Pch MOSFET (M22) is connected to the power supply (Vdd) which is the highest voltage. The drain of the Pch MOSFET (M22) is connected to the base of the NPN transistor (TR2). Since this configuration is the same for PchMOSFETs (M12 to Mn2 (not shown)) included in other monitor circuits, the drain voltage when the PchMOSFETs (M12 to Mn2) are ON is the power supply voltage (Vdd), and each NPN transistor (TR1 The voltage between the emitter and base resistance (R11 to Rn1) (between OUT1 and Cell1 to OUTn and Celln) differs for each monitor circuit. That is, the voltage between the emitter and base resistance of the NPN transistor (TR1) of the monitor circuit 1 of the capacitor (C1) closest to Vdd is the smallest, the base current of the NPN transistor (TR1) is reduced, and an NPN transistor that generates a bypass current (TR1) has the lowest collector current. The voltage between the emitter and base resistance of the NPN transistor (TRn) of the monitor circuit n closest to GND is the largest, the base current of the NPN transistor (TRn) increases, and the collector current of the NPN transistor (TRn) that generates the bypass current is Most often.
As a result, there is a problem that the bypass current differs for each capacitor and it becomes difficult to eliminate the uneven charging.

(the purpose)
An object of the present invention is to solve the above-described problems and provide a capacitor charging circuit integrated in a one-chip semiconductor device capable of making the bypass currents of all capacitors uniform.

  In order to achieve the above object, a capacitor charging circuit integrated in a one-chip semiconductor device of the present invention is (1) to apply a DC power source to a plurality of capacitors connected in series to charge the capacitors evenly. In addition, when the voltage of each of the capacitors exceeds a preset reference voltage, the parallel monitor circuit includes a parallel monitor circuit that bypasses a charging current in all the capacitors. In order to bypass the current, a PNP transistor in which an emitter is connected to the positive terminal of the capacitor via a resistor and a collector is connected to the negative terminal, and a base current of the PNP transistor is turned on or off. For this purpose, the drain is connected to the base of the PNP transistor via a resistor, and the source is connected to the capacitor. A first Nch MOSFET connected to the terminal on the side, and in order to turn on the first Nch MOSFET, the amplitude of the voltage applied to the gate of the first Nch MOSFET is set to the cell voltage of the capacitor. It is characterized by.

(2) A switching circuit is provided between the gate of the first Nch MOSFET and the positive terminal of the capacitor, the drain and source of the second Nch MOSFET being connected to the source and drain of the first Pch MOSFET, When the drain and source of the third Nch MOSFET are connected between the gate of the first Nch MOSFET and the negative terminal of the capacitor, and the first Nch MOSFET is turned on, the first Nch MOSFET is configured as the first switch circuit. A signal of a negative power supply voltage (hereinafter referred to as GND) level of the semiconductor device is given to the gates of the Pch MOSFET and the third Nch MOSFET, and the gate of the second Nch MOSFET constituting the switch circuit is given to the gate of the second Nch MOSFET. Apply a signal of the positive power supply voltage (hereinafter referred to as power supply) level of the semiconductor device. When turning off the first Nch MOSFET, a power level signal is given to the gates of the first Pch MOSFET and the third Nch MOSFET constituting the switch circuit, and the switch circuit is constructed. A GND level signal is applied to the gate of the second Nch MOSFET.
In this way, the capacitors can be charged uniformly.

(3) The PNP transistor described in (1) or (2) is replaced with an NPN transistor, the NchMOSFET is replaced with a PchMOSFET, the PchMOSFET is replaced with an NchMOSFET, and all the connections of these active elements to the power supply are reversed. It is also characterized in that active elements other than the transistors are integrated in a one-chip semiconductor device.
In this way, it is possible to manufacture an IC even on a P-type substrate.

  According to the present invention, since the amplitude of the gate voltage of the MOSFET driving the external bypass transistor is made equal to the voltage of one cell of the capacitor, the on-resistance of the driving MOSFET becomes uniform and the base current of the bypass transistor becomes uniform. As a result, the bypass current can be made uniform.

(First embodiment)
FIG. 1 is a configuration diagram of a capacitor charging circuit showing a first embodiment of the present invention.
In FIG. 1, since the configurations of the monitor circuits 1 to n and the TR circuits 1 to n are all the same, the second monitor circuit 2 and the TR circuit 2 will be described.
The TR circuit 2 includes a PNP transistor (TR2), a resistor (R21), and a resistor (R22). A resistor (R22) is connected to the emitter of the PNP transistor (TR2). The other end of the resistor (R22) is connected to the positive terminal of the capacitor (C2), and is further connected to the terminal (Cell1) of the semiconductor device. The collector of the PNP transistor (TR2) is connected to the negative terminal of the capacitor (C2), and is further connected to the terminal (Cell2) of the semiconductor device. The base of the PNP transistor (TR2) is connected to the terminal (OUT2) of the semiconductor device via the resistor (R21).

In the semiconductor device, the drain and the source of the Nch MOSFET (M21) are connected between the terminal (OUT2) and the terminal (Cell2). Between the gate and terminal (Cell1) of the Nch MOSFET (M21), a switch circuit is provided in which the drain and source of the Pch MOSFET (M23) are connected to the source and drain of the Nch MOSFET (M24). Further, the drain and source of the Nch MOSFET (M22) are connected between the gate of the Nch MOSFET (M21) and the terminal (Cell2).
The gate of the Pch MOSFET (M23) and the gate of the Nch MOSFET (M22) are connected in common and connected to the output of the inverter (INV2). The gate of the Nch MOSFET (M24) is connected to the input of the inverter (INV2). Note that since the power source of the inverter (INV2) is the same as that of the semiconductor device, the amplitude of the output voltage of the inverter (INV2) varies from the power source (Vdd) to GND. Further, a control signal 2 is applied to an input of the inverter (INV2) from a control circuit (not shown).

  When the control signal 2 is at the low level, the output of the inverter (INV2) is at the high level, so that the gate of the PchMOSFET (M23) constituting the switch is at the high level and the gate of the NchMOSFET (M24) is at the low level. The circuit is turned off. Further, since the gate of the Nch MOSFET (M22) is at a high level, the Nch MOSFET (M22) is turned on. For this reason, since the gate of the Nch MOSFET (M21) is at a low level (voltage on the negative side of the capacitor (C2)), the Nch MOSFET (M21) is turned off. When the Nch MOSFET (M21) is off, the base current of the PNP transistor (TR2) does not flow, so the PNP transistor (TR2) is turned off and the capacitor (C2) is charged.

  When charging of the capacitor (C2) proceeds and the voltage of the capacitor (C2) exceeds a predetermined voltage, the control signal 2 becomes high level. As a result, the output of the inverter (INV2) becomes low level, the gate of the PchMOSFET (M23) constituting the switch becomes low level, the gate of the NchMOSFET (M24) becomes high level, and the switch circuit is turned on. Further, since the gate of the Nch MOSFET (M22) is at a low level, the Nch MOSFET (M22) is turned off. For this reason, since the gate of the Nch MOSFET (M21) is at a high level (voltage on the positive side of the capacitor (C2)), the Nch MOSFET (M21) is turned on. When the Nch MOSFET (M21) is turned on, the base current of the PNP transistor (TR2) flows, the PNP transistor (TR2) is turned on, and the charging current of the capacitor (C2) is bypassed.

What is important here is that the gate voltage when the Nch MOSFET (M21) is turned on is the voltage on the positive side of the capacitor (C2) as described above. Since all the monitor circuits have the same configuration, the gate voltage when the Nch MOSFETs (M11 to n1) of other monitor circuits corresponding to the Nch MOSFET (M21) are turned on is also the same as the voltage for one capacitor cell.
That is, since the gate voltages when the Nch MOSFETs (M11 to n1) of the monitor circuit are turned on are all the same, the on resistances of the Nch MOSFETs (M11 to n1) are also the same. As a result, since the base currents of the PNP transistors (TR1 to TRn) are also the same, the collector currents of the PNP transistors (TR1 to TRn) are also the same, and the bypass current can be equalized.

(Second embodiment)
FIG. 2 is a block diagram showing the main part of a capacitor charging circuit according to the second embodiment of the present invention.
In the first embodiment, since the semiconductor device is configured using the N-type substrate, the case where the PNP transistor is used as the bypass element has been described. However, when the P-type substrate is used for the semiconductor device, FIG. As shown in FIG. 5, the same circuit configuration can be used by using an NPN transistor as the bypass transistor, changing the PchMOSFET to the NchMOSFET, changing the NchMOSFET to the PchMOSFET, and reversing the connection to the power source.
In the embodiment of FIGS. 1 and 2, a resistor (R21) is connected between the base of the transistor (TR2) and the terminal (OUT2), but this resistor limits the base current of the transistor (TR2). If the capacitor charging current is small, the resistor (R21) may be omitted.
Further, the resistor (R22) connected to the emitter of the transistor (TR2) may be connected to the collector side, but in this case, the base resistor (R21) cannot be omitted.

1 is a configuration diagram of a capacitor charging circuit showing a first embodiment of the present invention. FIG. It is a principal part block diagram of the capacitor charging circuit which shows the 2nd Example of this invention. It is a block diagram of the example of the conventional parallel monitor circuit.

Explanation of symbols

Vdd ... Power supply voltage, C1 ~ Cn ... Capacitor, Cell1 ~ Celln ... Capacitor positive / negative side connection terminal,
OUT1 to OUTn: Output terminal to bypass transistor,
TR1 to TRn: Bypass transistor, INV1 to INV2: Inverter, GND: Ground potential,
M21, M22, M24 ... Nch (Pch) MOSFET, M23 ... Pch (Nch) MOSFET,
R21, R22 ... resistance.

Claims (3)

In order to apply a DC power source to a plurality of capacitors connected in series and charge the capacitors evenly, a parallel monitor that bypasses the charging current when each voltage of the capacitors exceeds a preset reference voltage In a capacitor charging circuit in which a circuit is integrated in a one-chip semiconductor device provided in all the capacitors,
In order to bypass the charging current, the parallel monitor circuit includes a PNP transistor having an emitter connected to a positive terminal of the capacitor via a resistor and a collector connected to a negative terminal, and a base of the PNP transistor. A first Nch MOSFET having a drain connected to the base of the PNP transistor via a resistor and a source connected to a negative terminal of the capacitor in order to perform on / off control of the current;
In order to turn on the first NchMOSFET, the capacitor charging circuit, characterized in that the amplitude of the voltage applied to the gate of the first NchMOSFET, was set to full-charge voltage of one cell of the capacitor. The capacitor charging circuit according to claim 1,
A switch circuit is provided between the gate of the first Nch MOSFET and the positive terminal of the capacitor, the drain and source of the second Nch MOSFET being connected to the source and drain of the first Pch MOSFET,
Connecting the drain and source of a third NchMOSFET between the gate of the first NchMOSFET and the negative terminal of the capacitor;
When turning on the first Nch MOSFET, the power supply voltage (hereinafter referred to as GND) level on the negative side of the semiconductor device is applied to the gates of the first Pch MOSFET and the third Nch MOSFET constituting the switch circuit. And a signal of a power supply voltage (hereinafter referred to as a power supply) level on the positive side of the semiconductor device is applied to the gate of the second Nch MOSFET constituting the switch circuit,
When turning off the first Nch MOSFET, a power level signal is applied to the gates of the first Pch MOSFET and the third Nch MOSFET that constitute the switch circuit, and the switch circuit is configured. A capacitor charging circuit integrated in a one-chip semiconductor device, wherein a GND level signal is applied to a gate of a second Nch MOSFET. The capacitor charging circuit integrated in the one-chip semiconductor device according to claim 1 or 2,
The PNP transistor is replaced with an NPN transistor, the Nch MOSFET is replaced with a Pch MOSFET, and the Pch MOSFET is replaced with an Nch MOSFET.
And a capacitor charging circuit, characterized in that the connection to the power source was reversed positive and negative.

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