JP2003244859A - Method of charging electric double-layer capacitor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently control the charge of a plurality of electric double-layer capacitors connected in series. <P>SOLUTION: This system is constituted by connecting a capacitor module, where a charge balance circuit is connected in parallel with the electric double- layer capacitors connected in series, with a charger, and the charge balance circuit is constituted by connecting a terminal voltage detector, a comparator, a power NPN transistor, an upper limit voltage setter, a shunt regulator, and a resistor to each another, and the capacity of each capacitor can be utilized to its maximum and the energy consumed by the capacity dispersion among individuals is minimized, by detecting each terminal voltage and controlling the charge current so that all charge voltages agree with one another at charge. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charging device for a capacitor module in which a plurality of electric double layer capacitors (hereinafter abbreviated as capacitors) are connected in series.

[0002]

2. Description of the Related Art Electric double layer capacitors have dramatically higher capacities than conventional aluminum electrolytic capacitors, etc., are capable of rapid charging and large current discharge, and have a long cycle life. Besides being used, it is also being considered for use as an auxiliary power source for electric vehicles and fuel cell vehicles. Furthermore, by connecting multiple capacitors in series and parallel to form a large-capacity capacitor module,
It is also expected as a power storage device for solar power generation.

The rated voltage of these electric double layer capacitors depends on the decomposition voltage of the electrolytic solution and is as low as about 2.3 to 2.5 V. Therefore, when used as a power storage device, a plurality of them are excluded except for a part thereof. Increase the rated voltage by connecting capacitors in series,
It is generally used as a module (further, when a large capacity is required, these modules are used in parallel connection). However, when charging and discharging these modules connected in series, variations in the terminal voltage occur due to variations in the capacitance and leakage current of each capacitor, and when the capacitor voltage exceeds the rated voltage, the capacitors whose characteristics deteriorate Will occur.

When charging and discharging a module in which a plurality of capacitors are connected in series in consideration of the capacitance of each capacitor and the variation of leakage current, charging below the rated voltage is performed so that the capacitor voltage does not exceed the rated voltage. Must be set to voltage before use. However, the energy that can be stored in the electric double layer capacitor, because it is based on the relationship of W = CV ^2/2, the lower terminal voltage than the rated voltage, the charging energy with the square of the voltage becomes lower.
For example, when 2.0V is fully charged with respect to the rated voltage of 2.5V, only 64% of the chargeable energy can be charged.

In order to solve this problem, Japanese Patent Laid-Open No. 6-2
Japanese Patent No. 61452 discloses a parallel monitor circuit that detects each capacitor terminal voltage of an electric double layer capacitor connected in series, determines that the terminal voltage has reached a predetermined value, and limits charging of the capacitor. There is. FIG. 13 is an example of a charge control circuit when two capacitors described in the above publication are connected in series. Capacitors C1 and C2
Shunt regulators IC1 and IC1 are connected in parallel.
1, transistors Q1, Q11, resistors R1-4, R11
A parallel monitor circuit composed of 14 to 14 is connected to charge power source I.
Charging starts from 1. When either of the capacitors C1 and C2 reaches full charge, the parallel monitor circuit bypasses the current and limits the capacitor terminal voltage so that it does not exceed a predetermined value. However, in this method, if there are large variations in capacitance or variations in the initial state of charge of the individual capacitors connected in series, after the first capacitor reaches the rated voltage and the parallel monitor operates, all other It takes a relatively long time for the capacitor of No. 2 to be charged to the rated voltage. Moreover, since the electric power consumed by the parallel monitor is a large amount of heat generation represented by the terminal voltage × bypass current, there is a problem in that it is necessary to provide a circuit element and a heat dissipation mechanism corresponding to it.

Recently, in the use of an auxiliary power source for electric vehicles and fuel cell vehicles, it is necessary to increase the charging current required for a module in which a plurality of capacitors are connected in series to about 100 A. However, when the parallel monitor of the capacitor that has reached the rated voltage first in the module bypasses the charging current, the bypass current becomes the charging current itself. In case of charging current 100A, parallel monitor 1
If the rated voltage of the capacitor is 2.5V, the power consumed per unit becomes extremely large, 2.5V × 100A = 250W. Therefore, an electronic component having a power capacity and a current rating capable of bypassing these charging currents by 100% and a heat dissipation mechanism for keeping the same within a certain temperature are required, and an increase in capacity of the parallel monitor cannot be avoided.

Further, Japanese Unexamined Patent Publication No. 10-174283 discloses a charging method in which a terminal voltage of a module in which a plurality of capacitors are connected in series and individual capacitor terminal voltages are monitored and the charging current is reduced at a predetermined voltage. Has been done. When this method is used, the power consumed by the parallel monitor can be reduced by reducing the power consumption by reducing the charge current during the parallel monitor circuit operation, but the charge current is reduced before full charge. There was a problem that the charging time was long.

[0008]

Due to the above problems, when charging and discharging a plurality of capacitors connected in series, the power consumed by the charging current bypass monitor connected in parallel to each capacitor. There has been a demand for a charging device in which circuit elements such as transistors and a heat dissipation mechanism are miniaturized, and a charging method with a shorter charging time.

[0009]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and when charging and discharging a plurality of capacitors connected in series, the characteristics of each capacitor must be taken into consideration. By setting the capacitor allowable voltage range so that the terminal voltages match during charging, and controlling the charging current of each capacitor so that it does not exceed this range, it is consumed by the charging current bypass transistor connected in parallel with each capacitor. It is an object of the present invention to provide a charging device in which circuit power such as a transistor is minimized and a heat dissipation mechanism is miniaturized, and a charging method with a shorter charging time.

That is, in an electric double layer capacitor charging device constituted by connecting a charging device and a capacitor module in which a charge balance circuit is connected in parallel to an electric double layer capacitor connected in series, Reference setting means for setting the capacitor voltage allowable range at each average voltage during charging progress from the average voltage, the charge setting voltage of each capacitor and the variation of the capacitance of each capacitor, or the tolerance of the variation of capacitance and the variation of leakage current. And charging control means for comparing each capacitor voltage value with the capacitor voltage allowable range and conducting a charging balance circuit connected in parallel to the capacitor to limit the charging current when exceeding the capacitor voltage value. This is a method of charging a double layer capacitor.

Further, the difference between the combined capacitance of the electric double layer capacitors and the combined capacitance when assuming that there is no capacitance variation among the capacitors is obtained, and the resistance is adjusted by the difference to correct the average voltage of the capacitors. It is a method of charging an electric double layer capacitor.

Further, the difference between the average capacitance of the electric double layer capacitor and the average capacitance on the assumption that there is no capacitance variation among the capacitors is obtained, and the average voltage of the capacitor is corrected. This is a method of charging a double layer capacitor.

The charge balance circuit has a minimum voltage detector and a maximum voltage detector, detects the minimum voltage and the maximum voltage of all capacitors, obtains an average value by an arithmetic unit, and calculates the average value. A method of charging an electric double layer capacitor, which is characterized in that the average voltage of the capacitor is used.

Further, in an electric double layer capacitor charging device constructed by connecting a charging module and a capacitor module in which a charging balance circuit is connected in parallel with an electric double layer capacitor connected in series, the minimum voltage of all capacitors is detected. Then, this is set as a lower limit reference value, and reference setting means for setting the capacitor voltage allowable range by an upper limit voltage setting device that adds voltage variation set by the tolerance of capacitance variation and leakage current variation to the lower limit reference value. ,
Comparing each capacitor voltage value and the capacitor voltage allowable range by a comparator, and when the capacitor voltage value is high,
A charging control means for conducting a charging balance circuit connected in parallel with the capacitor to limit a charging current, is a method of charging an electric double layer capacitor.

Further, in the above electric double layer capacitor charging device, the allowable range of the capacitor voltage converges to 0 as the capacitor average voltage approaches the capacitor charging set voltage during charging, and the charging method of the electric double layer capacitor. Is.

In the above electric double layer capacitor charging device, a charging change point is provided at a voltage value lower than the charging set voltage of the capacitor module, and when the capacitor module voltage exceeds the charging change point, constant current charging to constant voltage charging is performed. It is an electric double layer capacitor charging method characterized by adopting a charging control method of shifting to.

Further, in the electric double layer capacitor charging device, reference setting means for setting a capacitor voltage allowable range during charging progress, and each capacitor voltage value is compared with the capacitor voltage allowable range and charging is performed when the value exceeds the allowable range. The electric double layer capacitor charging method is characterized in that the charging control means for limiting the current is performed by software control by a microprocessor.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION As shown in FIG. 1, an electric double layer capacitor charging device includes a capacitor module in which a charge balance circuit is connected in parallel with an electric double layer capacitor connected in series, a current detector, and a charge control circuit. And are connected to a charging device. As shown in FIGS. 2 and 7, the charge balance circuit is configured by connecting a terminal voltage detector, a comparator, a power NPN transistor, an upper limit voltage setting device, a shunt regulator and a resistor. Here, as shown in FIGS. 8 and 9, a maximum voltage detector and / or a minimum voltage detector, a calculator and / or a multiplier are provided between the terminal voltage detector and the upper limit voltage setter of the charge balance circuit. You may connect the circuit comprised by. The charge control circuit is configured by connecting a terminal voltage detector, a charge current detector, a charge current controller and a full charge detector as shown in FIG. With the electric double layer capacitor charging device described above, the capacitor at each average voltage at the time of charging progress is calculated from the average voltage of the electric double layer capacitor, the charge setting voltage of each capacitor, the variation in the capacitance of each capacitor, or the tolerance of the variation in leakage current. Reference setting means for setting a voltage allowable range, and charge control means for comparing each capacitor voltage value with the capacitor voltage allowable range and conducting a current balance circuit connected in parallel to the capacitor to limit the charging current when exceeding the capacitor voltage value. And are used to charge the electric double layer capacitor. Further, the difference between the combined capacity of the electric double layer capacitor and the combined capacity assuming that there is no capacity variation among the capacitor cells is obtained, and the average voltage of the capacitor is corrected by the difference. Further, the difference between the average capacity of the electric double layer capacitor and the average capacity assuming that there is no capacity variation among the capacitors is calculated, and the average voltage of the capacitor is corrected.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. An embodiment of the electric double layer capacitor charging device according to the present invention is shown in FIG. In FIG. 1, the capacitor module 3 includes a plurality of capacitors 1 connected in series and a charge balance circuit 2 connected in parallel with the capacitors 1. The charging device 6 supplies electric power to the capacitor module 3 using a combination of a commercial power supply and a voltage converting means by an inverter, or a direct current power supply such as a solar cell, and the charging control circuit 4 charges the terminal voltage of the capacitor module 3 with the terminal voltage. The current is detected and charging is controlled.

FIG. 2 shows an example of a capacitor module in which two capacitors are connected in series, which is composed of capacitors C1 and C2 connected in series and a charge balance circuit 2 connected in parallel with them. Of the voltages input to the upper limit voltage setting device 7, the voltage at the point A is, for example, resistance R1 = 11 kΩ,
By setting the resistance R2 = 9 kΩ, 0.45 × (capacitor module voltage) = 0.9 × (capacitor average voltage Vave) can be obtained from capacitor average voltage = capacitor module voltage / 2. The voltage at the point B can be obtained by, for example, the shunt regulator μPC1944 in the control IC1.
(Manufactured by NEC) is used to control the voltage at point D to 1.25 V, and R5 = 10 kΩ and R6 = 2.5 kΩ are set to R5, R
It is possible to obtain 0.25 V with a resistance partial voltage of 6. A, B
The point voltage is added by the upper limit voltage setting unit 7 and the upper limit voltage is 0.9 ×
It is output as Vave + 0.25, and compared with each capacitor terminal voltage in the comparator 9, the power NPN in the capacitor in which the capacitor terminal voltage is higher than the upper limit curve voltage.
The transistor 10 is turned on to limit the charging current,
If the capacitor terminal voltage does not exceed the upper limit voltage, charging proceeds without limiting the charging current. Note that the terminal voltage of the capacitor C2 has the same voltage reference as that of the upper limit voltage setting unit 7, so that the capacitor terminal voltage detector is not necessary.

FIG. 3 shows the terminal voltages of the capacitors C1 and C2 during the charge / discharge cycle when the charge setting voltage of each capacitor in the capacitor module of FIG. 2 is 2.5V. Now, the tolerance due to the variation in capacitance is set to ± 10%, and the capacitor C1 is
Consider the case where the 0% capacity is small. Capacitors C1 and C2
, Both start to discharge from full charge of 2.5V,
The C1 terminal voltage drops 20% faster than C2. When the discharge progresses for a certain period of time and then switches to charging, the C1 terminal voltage is 20% lower than C2.
Since the terminal voltage rises at a fast speed, the depth of discharge and the charging speed eventually cancel each other out, and the charge fully matches again.
As described above, when the discharging is started from the full charge and the charging is performed again, the effects of the depth of discharge and the charging speed in the capacitors C1 and C2 are canceled out, so that the charging balance circuit 2 does not need to limit the charging current. . Here, the cell voltage allowable range is a range in which variations in the terminal voltage of each capacitor during the progress of charging are canceled by the relationship between the depth of discharge and the charging speed when fully charged.

The allowable capacitor voltage range during charging progress is set based on the average voltage of the capacitors, the charge setting voltage, and the capacitance variation tolerance. In order to match the terminal voltages of the capacitors C1 and C2 with full charge, the charging speed due to the capacitance variation ΔC ₀ with respect to the voltage difference (Vtar−Vave) between the charging setting voltage Vtar and the average voltage Vave at the average voltage Vave. Considering the difference, (Vtar-Vave) × ΔC
_It is necessary to control so that the terminal voltages of the capacitors C1 and C2 fall within the range of ₀ . The capacitor voltage allowable range ΔVc allowed at the average voltage Vave for matching the capacitors C1 and C2 at the charging setting voltage Vtar is calculated by the following equation (1).

ΔVc = Vave + (Vtar−Vave) × ΔC ₀ (1)

In FIG. 2, charge set voltage Vtar = 2.
5V, capacitance variation ΔC ₀ is ± 10%, and this is substituted into the equation (1),

[0025] ΔVc = Vave + (2.5−Vave) × (± 0.1) (2)

When this is expressed as the upper limit voltage Vh of the capacitor cell voltage allowable range, the following equation is obtained.

[0027] Vh = 0.9 × Vave + 0.25 (3)

When expressed as the lower limit voltage Vl, the following equation is obtained.

[0029] Vl = 1.1 × Vave-0.25 (4)

If there is a capacitor terminal voltage lower than the lower limit voltage Vl, it is impossible to increase the charging current. Therefore, the charging balance circuit 2 continues charging without limiting the charging current. On the contrary, when there is a capacitor terminal voltage exceeding the upper limit voltage Vh, the charging balance circuit 2 limits the charging current of the corresponding capacitor, and the charging proceeds with the charging current falling within the voltage allowable range. in this way,
The effect of offsetting the difference in depth of discharge and the difference in charge speed is obtained in the case corresponding to the second and subsequent charging / discharging.

FIG. 4 shows terminal voltages of the capacitors C1 and C2 at the time of initial charging in the capacitor module of FIG. The initial charging starts from 0 V for both capacitors C1 and C2. Until the terminal voltage of the capacitor C1 reaches 1.25 V, the terminal voltage of the capacitors C1 and C2 falls within the previously set voltage allowable range, so that the charging balance circuit 2 does not limit the charging current. However, when the capacitance of the capacitor C1 exceeds 1.25 V, the allowable range is exceeded. Therefore, only the capacitor C1 limits the charging current by the charging balance circuit 2 and reduces the charging speed to perform charging. The charging current of the capacitor C1 is equal to the charging current limit (20) for matching the charging speed with the capacitor C2.
%) And the voltage difference between the capacitors C1 and C2 opened until the capacitor C1 is charged to 1.25 V (0.25 V)
The charging current of 33% in total of the compensation amount (13%) is limited to charge. Therefore, the capacitor C1 is 1.25V
After exceeding, the charging current of only capacitor C1 is 33%.
By limiting the charging and continuing the charging, and charging the capacitor C2 without limiting the charging current, the terminal voltages of the capacitors C1 and C2 can be matched at the charging setting voltage of 2.5V. As described above, when a canceling relationship cannot be obtained between the depth of discharge and the charging speed due to spontaneous discharge at the time of initial charging or after being left for a long time, the terminal voltages of the capacitors C1 and C2 exceed the capacitor voltage allowable range during the progress of charging. For,
The charging balance circuit 2 limits the charging current and advances charging.

According to Japanese Unexamined Patent Publication No. 6-261452, a charging method in which the charging current is limited when the capacitor voltage reaches the charging set voltage, and a charging current when the capacitor voltage exceeds the allowable capacitor voltage range according to the present invention Will be compared with the charging method that is limited at the time of the first charge. Capacitance C
Consider the case where 1 is 20% smaller in capacity than C2. In the charge limiting circuit of FIG. 13, the capacitor C1 is 2.
When 5V is reached, the capacitor C2 is only 2.0V, so the capacitor C1 bypasses all the charging current to the parallel monitor side, and waits until the capacitor C2 reaches 2.5V. At this time, the capacitor C1
Reaches the charge set voltage and then continues to bypass all charge currents as much as 20% of the total charge time. On the other hand, in the charge control circuit of FIG.
Time from 5V to 2.5V (6 of total charging time)
0%), 33% of the charging current is bypassed by the power NPN transistor 10 so that the capacitor C
The terminal voltages of 1 and C2 can be made to coincide with each other when fully charged. Therefore, in the charge control circuit of FIG.
Since a small current capacity can be selected as 0 and the power consumption of the charge balance circuit 2 (bypass current × capacitor terminal voltage) can be reduced, the heat dissipation device can be downsized.

The capacitor voltage allowable range (1) used in the charging / discharging cycle examples of FIGS. 3 and 4 considers only the capacitance variation tolerance of each capacitor. Generally, the variation of the leakage current of the capacitor is smaller than that of the variation of the electrostatic capacity. However, when the tolerance ΔL of the variation of the leakage current of each capacitor is also considered in the formula (1), the variation of the tolerance of the entire capacitor is (ΔC + ΔL). As (1)
When replaced with ΔC _{0 in the} equation, the capacitor voltage allowable range is given by equation (5).

[0034] ΔVc ′ = Vave + (Vtar−Vave) × (ΔC ′ + ΔL) (5)

As described above, when the capacitance variation and the leakage current variation are also considered together, the respective tolerance variations may be added together and substituted into the equation (5),
The upper and lower limit voltages of the capacitor voltage allowable range corresponding to the expressions (3) and (4) can be easily derived.

Next, consider a capacitor module in which five capacitors are connected in series. In order to simplify the case, it is assumed that only the capacitance variation occurs in the following description. When considering both the capacitance variation and the leakage current variation, as in equation (5),
The allowable range of the capacitor voltage may be set by adding the respective variations. When the variations in the capacitance of the five capacitors cancel each other out and the variation in the combined capacitance of the capacitors is 0, the average voltage is located in the middle of the charge / discharge curve of each capacitor, and thus the capacitor 2 of FIG.
It is possible to set a capacitor voltage allowable range similar to that of a capacitor module in which pieces are connected in series. However, when the average capacitance of the capacitors varies depending on whether the electrostatic capacitance is on the plus side or the minus side, the charging current control by the upper limit voltage shown in FIG. 2 may not be effectively performed. Now, as an example in which the capacitance value is large, one of + 10% of the five capacitors is -1,
Consider the case where there are four 0% capacitors. FIG. 5 shows the capacitor terminal voltage at the time of initial charging by the capacitor C1 (4 pieces) of −10% and the capacitor C2 (1 piece) of + 10%. Since the average voltage is biased to the capacitor C1 side, the upper limit voltage of the capacitor voltage allowable range expressed by the equation (3) is also biased to the C1 side. The voltage of the capacitor C1 is V
When it is 1, the voltage of the capacitor C2 is 0.8 × V1. At this time, the capacitor average voltage Vave is (6)
It is calculated by the formula.

[0037] Vave = (4 × V1 + 0.8 × V1) / 5      = 0.96 x V1 (6)

Substituting Vave in equation (6) into equation (3),
When the capacitor voltage V1 that exceeds the upper limit curve formula is obtained in FIG. 5, V1 = 1.84 V, which is 1.
It is about 0.6V higher than 25V. Therefore, the terminal voltage of the capacitor C1 is from 1.84V to 2.5.
Until reaching V, the charging current of the capacitor C1 is limited by the charging current (20%) for matching the charging speed with the capacitor C2 and the capacitor C1 opened by the time the capacitor C1 is charged to 1.84V, A total of 49% of the compensation (29%) of the voltage difference (0.37V) of C2
The charging current will be limited and charging will proceed. Even in the second and subsequent charging / discharging situations, the charging current cannot be effectively limited. In FIG. 6, capacitors C1 and C2
Should be discharged from the fully charged 2.5 V, C2 should be the discharge curve a, but since the average voltage is biased toward the capacitor C1 side, C2 exceeds the upper limit voltage, and the capacitor C2 is discharged. Then, the current of 4% is bypassed to the charge balance circuit side, and the discharge is performed at the discharge curve b. Also during the second and subsequent charges, the relationship between the depth of discharge of the capacitors C1 and C2 and the charging speed becomes unbalanced due to the 4% bypass current during the previous discharge, and the terminal voltage of the capacitors C1 and C2 at the intersection point d. Will match, so
From the intersection point d to the charge setting voltage 2.5V, the capacitor C1
It is necessary to limit the charging current of 20% to proceed with charging.
As another example in which the capacitance value is large, out of 5 capacitors, + 10% is 4 capacitors, −
Consider the case where there is one 10% capacitor. Although illustration is omitted, in this case, since the average voltage is biased toward the C2 side, the voltage at which the capacitor C1 exceeds the upper limit voltage at the time of the initial charge is sufficiently smaller than 1.25V, and the voltage gradually decreases from the time when the charge does not proceed so much. It is possible to limit the charging current on the side of the capacitor C1. In addition, there is no capacitor voltage exceeding the upper limit voltage during the second and subsequent charging / discharging operations, and there is no need to limit the charging current.

FIG. 7 shows an example of a capacitor module in which five capacitors are connected in series. Of the voltages input to the upper limit voltage setting unit 7, the voltage at the point A is, for example, the resistance R1 = 41.
By setting kΩ and resistance R2 = 9 kΩ, capacitor average voltage Vave = capacitor module voltage / 5,
0.18 x (capacitor module voltage) = 0.9 x
(Capacitor average voltage Vave) can be obtained. B
The point voltage is, for example, IC1 shunt regulator μPC
Use 1944 (made by NEC) to set the D point voltage to 1.25V
R5 = 10kΩ, R6 = 2.5kΩ
It is possible to obtain 0.25V with a resistance partial pressure of 5 or 6.
The A and B point voltages are added by the upper limit voltage setting unit 7 and output as the upper limit curve voltage 0.9 × Vave + 0.25, and the capacitor terminal voltage is compared with each capacitor terminal voltage by the comparator 9, In a capacitor higher than the voltage, the power NPN transistor 10 is turned on to limit the charging current, and when the capacitor terminal voltage does not exceed the upper limit voltage, charging proceeds without limiting the charging current.

As shown in the above-mentioned series connection of the five capacitors, when there is a bias in the average voltage of the capacitors due to variations in capacitance, it is necessary to correct the upper limit voltage in FIGS. For example, it is possible to measure the combined capacitance of the capacitor modules, compare it with the combined capacitance on the assumption that there is no capacitance variation, obtain the difference, and correct the capacitor average voltage using the difference in the combined capacitance. Table 1 shows that when the five capacitors in FIG. 5 are connected in series, the capacitance variation of each capacitor is assumed to be + 10% or −10%, and the capacitance variation of the capacitors is calculated based on the average capacitance of the capacitors. It shows the relationship.

[0041]

[Table 1]

In Table 1, it can be seen that the inversion of the sign of the capacitor combined capacitance variation is almost equal to the capacitor average voltage variation. Therefore, the combined capacitance of the capacitor module is measured to obtain the combined capacitance of the capacitors, and this is used as the value of the average voltage of the capacitor to correct Vave at the voltage at point A in FIG. The average voltage curve is the capacitor C
It can be placed near the middle of the charge and discharge curves of C1 and C2.
For example, -10% C1 (4 pieces) and +10 in Table 1
When C2 (1 piece) is used, + 6% is obtained from the average voltage from Table 1, and the resistance of R2 is adjusted by using a variable resistor as shown in FIG. × Vave
Is corrected by reducing 6%, the average voltage curves of FIGS. 5 and 6 can be corrected with an error of 0.6%.

When the average voltage is corrected more accurately, the capacitance of each capacitor is measured and the average capacitance is calculated, and the average capacitance is compared with the average capacitance when there is no capacitance variation. By adjusting the resistance of R2 in FIG. 7 and correcting the voltage at the point A of 0.9 × Vave, the average voltage of FIGS. 5 and 6 can be plotted at the midpoint of the charge / discharge curves of C1 and C2. .

As a method that does not require correction of the average voltage, a method of obtaining the minimum terminal voltage and the maximum terminal voltage of each capacitor voltage and using this average as the average voltage Vave will be described. Of the capacitor voltages in FIG. 8, for each capacitor voltage detected by the terminal voltage detector 8, the minimum voltage detector 11 and the maximum voltage detector 12 determine the minimum / maximum terminal voltage, and the calculator 13 calculates the maximum voltage value. + Minimum voltage value) / 2 is calculated. Then, the multiplier 14 multiplies the output of the calculator 13 by 0.9 to obtain the voltage at the point A (0.9
XVave) is obtained. The A point voltage obtained by the multiplier 14 is added to the B point voltage by the upper limit voltage setting unit 7 and output as the upper limit curve voltage 0.9 × Vave + 0.25,
Used to compare with each capacitor terminal voltage. Since the subsequent steps are the same as in the example of FIG. 7, description thereof will be omitted. Figure 8
Vave in is not the average value of all the capacitor voltages but the average of the maximum voltage value and the minimum voltage value, but it is originally required without being affected by the voltage bias due to the variation in capacitance or the variation in leakage current. An average voltage curve can be plotted at the midpoint of the charge / discharge curve of each capacitor.

As another method that does not require correction of the average voltage, the minimum voltage of the capacitor voltages is detected and this is set as the lower limit reference value, and the capacitance variation of each capacitor and the leakage current variation are set to this value. A method of setting the capacitor voltage allowable range by adding the voltage variations set by the tolerance will be described. If Vave is deleted from the equations (3) and (4) of the upper and lower limit voltages obtained above, the next upper limit voltage can be obtained.

[0046] Vh = 0.82 × Vl + 0.45 (Formula 7)

The value of the upper limit voltage is obtained by substituting the minimum capacitor terminal voltage for Vl in this equation. This will be specifically described with reference to the circuit diagram of FIG. Among the capacitor voltages in FIG. 9, for each capacitor voltage detected by the terminal voltage detector 8, the minimum voltage detector 11 calculates the minimum terminal voltage, and the multiplier 14 multiplies the output of the calculator 13 by 0.82. Thus, the voltage at point A (0.82 × Vl) is obtained. The voltage at the point A obtained from the multiplier 14 is added to the voltage at the point B by the upper limit voltage setting unit 7 and output as the upper limit voltage 0.82 × Vl + 0.45, which is used for comparison with each terminal voltage. Later,
Since it is similar to the example of FIGS. 7 and 8, description thereof will be omitted. As described above, in the method shown in the circuit diagram of FIG. 9, the capacitance variation and the leakage current variation tolerance are added based on the minimum voltage value. The capacitor voltage permissible range can be set without being affected by.

In the charge balance circuits of FIGS. 2, 7, 8 and 9 of the above embodiment, the power NPN is used for the comparator.
Although a transistor is used as a connection, a power PNP transistor, an IGBT, an FET, or the like can be used instead.

In the electric double layer capacitor charging device of FIG. 2, a charge change point is provided at a voltage value lower than the charge set voltage of the entire capacitor module, and when the capacitor module voltage exceeds the charge change point, the constant current charge changes to the constant voltage. By adopting the charging control method of shifting to charging, more effective charging control can be performed. In FIG. 10, the electric double layer capacitor charging device is configured by connecting the capacitor module 3, the charging control circuit 4, and the charging device 6. The capacitor module 3 includes a plurality of capacitors 1 connected in series and a charge balance circuit 2 connected in parallel with the capacitors 1. Further, as the charging device 6, as in the case of FIG. 2, a commercial power source and a combination of voltage converting means by an inverter, or a DC power source such as a solar cell can be used.

The charging control circuit 4 switches from constant current charging to constant voltage charging in the following manner. When the capacitor module 3 of FIG. 10 is configured by connecting five capacitors having a rating of 2.5V in series, the charging set voltage of the capacitor module becomes 12.5V, and switching from constant current charging to constant voltage charging is performed. The charge change point voltage to be performed is set to around 12V. The terminal voltage detector 15 compares the terminal voltage of the capacitor module 3 with the charge change point voltage of 12V, and when the voltage exceeds the charging change point voltage of 12V, the difference between the terminal voltage and 12V is compared and amplified by the differential amplifier 19, and the voltage difference between the transistor 20 and the transistor 20. A voltage is output across the resistor R7 via the photocoupler 21. In addition, the charging current detector 16 extracts the charging current of the capacitor module 3 as the voltage across the resistor R8,
It is amplified by the differential amplifier 22, and a voltage is output across the resistor R7 via the transistor 23 and the photocoupler 24. Therefore, a voltage output obtained by adding the amplified output proportional to the difference between the capacitor module terminal voltage and the charging change point voltage 12V and the amplified output proportional to the charging current is obtained across the resistor R7. Further, in the charging current controller 17,
Vref voltage and resistance R set by converting charging current value into voltage
The drive transistor 26 is feedback-controlled so that the voltage between both ends of 7 is always equal to charge the capacitor module 3 from the charging device 6.

The terminal voltage of the capacitor module 3 is 12
When it is lower than V, the voltage output to the resistor R7 is only the output from the charging current detector 16, and there is no output from the terminal voltage detector 15. Therefore, the capacitor module 3
A constant current is charged at the charging current value set by the voltage Vref. On the other hand, when the terminal voltage of the capacitor module 3 exceeds 12V, a voltage obtained by amplifying the difference between the terminal voltage and 12V by the terminal voltage detector 15 is output to the resistor R7. Terminal voltage detector 15 and charging current detector 16
Since the output to the resistor R7 due to is constant at Vref, the output of the charging current detector 16 is reduced by the amount of increase in the output by the terminal voltage detector 15.

FIG. 11 shows the charging voltage-charging current characteristics when charged by the electric double layer capacitor charging device of FIG.
The charging current gradually decreases from 12 V, and the charging current is reduced to 0.5 A of 12.5 V to perform charging.
The charging current of 0.5 A at this time corresponds to a supplementary current for equalizing the charging density inside each capacitor. Then, the full charge detector 18 detects that the terminal voltage of the capacitor module exceeds 12.5 V, and stops charging by the charging device 6.

At the charge change point voltage of 12 V of the capacitor module which starts to shift from constant current charging to constant voltage charging, 5
Since all of the two capacitors are in the error variation of 2.4 V ± 10 mV, even if the charging current is reduced, it does not delay the full charge of a certain capacitor. In addition, each capacitor is 2.
Even if the voltage reaches 5V, it is necessary to perform supplementary charging for equalizing the charging density for a certain period of time, and by performing charging with the charging device shown in FIG. 10, efficient switching from constant current charging to constant voltage charging is performed. You can

In the electric double-layer capacitor charging device of FIG. 2, setting of the capacitor voltage allowable range at the time of charging and comparison of each capacitor voltage value with the capacitor voltage allowable range and charge control for limiting the charging current when exceeding the capacitor voltage allowable range FIG. 12 shows an example in which the above is performed by software control by a microprocessor. In the capacitor module in FIG. 12, five capacitors are connected in series. The potential of each connection point of the capacitors connected in series is calculated by the A / D converter 31.
Is detected and transmitted to the CPU, and the CPU calculates and calculates each terminal voltage. In the EEPROM 30, reference setting means for setting a capacitor voltage allowable range at each average voltage at the time of charging, and a program for comparing each capacitor voltage value with an upper limit voltage value and outputting a signal for limiting the charging current when exceeding the upper limit voltage value Is written in advance. And A-
Each terminal voltage and EEPR input from the D converter 31
CP based on the control program written in OM30
In U29, the upper limit set voltage is calculated and compared with each capacitor terminal voltage, and if each terminal voltage exceeds the upper limit set voltage, the power NPN transistor 10 connected in parallel to each capacitor through the DA converter 32 is controlled to conduct. Then, by controlling the charging of each capacitor in real time, all the capacitors are made fully charged at the charging set voltage. At this time, the upper limit setting voltage formula described in the EEPROM 30 may be calculated as (0.9 × Vave + 0.25) from the capacitor voltage in which the upper limit setting voltage Vave is connected in series, or the maximum voltage and the minimum voltage of all capacitors. May be detected and the average value thereof may be input. Further, the upper limit setting voltage formula ΔVh = (0.82 × Vl + 0.45) of the formula (7) described by the minimum voltage Vl of all capacitors may be used. Further, the capacitance of each capacitor connected to the microprocessor 28 is measured, the average voltage is corrected based on the average capacitance variation, and then the EEPRO is corrected.
The control program can also be written using the program write port 33 of M30.

[0055]

As described above, according to the present invention, in a capacitor module in which a plurality of electric double layer capacitors are connected in series, each capacitor terminal voltage is detected so that all the capacitor voltages match with full charge. By setting the allowable capacitor voltage range and performing charge control,
The power consumption of the charging current control transistor connected in parallel with the capacitor can be reduced, and the heat dissipation device can be downsized. Also, when charging progresses, the minimum voltage capacitor advances charging without limiting the charging current, and by limiting the charging current for other capacitors, without slowing down the charging speed when looking at the entire capacitor module, All capacitors can be fully charged in the shortest time. Further, by providing a charge change point at a voltage value lower than the charge set voltage of the capacitor module, and by adopting a charge control method that shifts from constant current charge to constant voltage charge when the capacitor module voltage exceeds the charge change point, It is possible to equalize the charge densities inside the capacitors by suppressing the progress of the charge beyond the charge set voltage and performing the supplementary charge near the full charge. Further, in a charge balance circuit connected to capacitors connected in series, means for setting a capacitor voltage allowable range based on the average voltage of the capacitors and comparing each capacitor voltage value with the capacitor voltage allowable range to limit the charging current. By performing signal output by software control by a microprocessor, the charge balance circuit can be downsized.

[Brief description of drawings]

FIG. 1 is an electric double layer capacitor charging device according to an embodiment of the present invention.

FIG. 2 is an example of a capacitor module in which two electric double layer capacitors are connected in series.

3 is a change with time of the terminal voltage of the electric double layer capacitors C1 and C2 in the capacitor module of FIG.

4 is a terminal voltage of capacitors C1 and C2 at the time of initial charging in the capacitor module of FIG.

FIG. 5 shows terminal voltages of capacitors C1 and C2 at the time of initial charging in a capacitor module in which five capacitors are connected in series.

FIG. 6 shows terminal voltages of C1 and C2 in a capacitor module in which five capacitors are connected in series.

FIG. 7 is another embodiment of a capacitor module in which five capacitors are connected in series.

FIG. 8 is another embodiment of a capacitor module in which five capacitors are connected in series.

FIG. 9 is another embodiment of a capacitor module in which five capacitors are connected in series.

FIG. 10 illustrates a main part of a charge control circuit of an electric double layer capacitor charging device according to an exemplary embodiment of the present invention.

11 is a diagram describing the charging voltage-charging current characteristics of a capacitor module by the electric double layer capacitor charging device of FIG.

FIG. 12 is another embodiment of a capacitor module in which five capacitors are connected in series.

FIG. 13 is a conventional example in which two electric double layer capacitors are connected in series.

[Explanation of symbols]

1 Electric double layer capacitor 2 Charge balance circuit 3 Capacitor module 4 Charge control circuit 5 Current detector 6 charger 7 Upper limit voltage setting device 8-terminal voltage detector 9 comparator 10 power NPN transistor 11 Minimum voltage detector 12 Maximum voltage detector 13 arithmetic unit 14 Multiplier 15 terminal voltage detector 16 Charge current detector 17 Charge current controller 18 Full charge detector 19 Comparison / differential amplifier 20 transistors 21 Photo coupler 22 Differential amplifier 23 transistor 24 Photocoupler 25 differential amplifier 26 transistors 27 comparator 28 microprocessors 29 CPU 30 EEPROM 31 A-D converter 32 DA converter 33 EEPROM writing terminal

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[Procedure amendment]

[Submission date] March 1, 2002 (2002.3.1)

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Title of invention

[Correction method] Change

[Correction content]

Title: Electric double layer capacitor charging method

Claims (8)

[Claims] 1. An electric double layer capacitor charging device configured by connecting a charging module and a capacitor module in which a charge balance circuit is connected in parallel to an electric double layer capacitor connected in series, wherein Reference setting means for setting the capacitor voltage allowable range at each average voltage during charging progress from the average voltage, the charge setting voltage of each capacitor and the variation of the capacitance of each capacitor, or the tolerance of the variation of capacitance and the variation of leakage current. And charging control means for comparing each capacitor voltage value with the capacitor voltage allowable range and conducting a charging balance circuit connected in parallel to the capacitor to limit the charging current when exceeding the capacitor voltage value. Double-layer capacitor charging method. 2. The difference between the combined capacitance of the electric double layer capacitors and the combined capacitance assuming that there is no capacitance variation among the capacitors is obtained, and the resistance is adjusted based on the difference to correct the average voltage of the capacitors. The method for charging an electric double layer capacitor according to claim 1, wherein 3. An average voltage of the capacitor is corrected by obtaining a difference between an average capacity of the electric double layer capacitor and an average capacity assuming that there is no capacity variation among the capacitors. Item 2. A method for charging an electric double layer capacitor according to Item 1. 4. The charge balance circuit has a minimum voltage detector and a maximum voltage detector, detects the minimum voltage and the maximum voltage of all capacitors, obtains an average value by an arithmetic unit, and calculates the average value. The method for charging an electric double layer capacitor according to claim 1, wherein the average voltage of the capacitor is used. 5. An electric double layer capacitor charging device configured by connecting a charging device and a capacitor module in which a charging balance circuit is connected in parallel to an electric double layer capacitor connected in series, and detecting the minimum voltage of all capacitors. Then, this is set as a lower limit reference value, and reference setting means for setting the capacitor voltage allowable range by an upper limit voltage setting device that adds voltage variation set by the tolerance of capacitance variation and leakage current variation to the lower limit reference value. Comparing each capacitor voltage value with the above-mentioned capacitor voltage allowable range by a comparator, and when the capacitor voltage value is high, it has a charging control means for conducting a charging balance circuit connected in parallel with the capacitor to limit the charging current. A method of charging an electric double layer capacitor, comprising: 6. The electric double layer capacitor charging device according to claim 1, wherein the capacitor voltage allowable range converges to 0 as the capacitor average voltage approaches the capacitor charging set voltage during charging. Electric double layer capacitor charging method. 7. The electric double layer capacitor charging device, wherein a charging change point is provided at a voltage value lower than a charging set voltage of the capacitor module, and when the capacitor module voltage exceeds the charging change point, constant current charging to constant voltage charging. 2. A charging control system for shifting to the above is adopted.
~ The method for charging an electric double layer capacitor as described in 6 above. 8. In the electric double layer capacitor charging device, reference setting means for setting a capacitor voltage allowable range during charging progress, and comparing each capacitor voltage value with the capacitor voltage allowable range and charging when exceeding the capacitor voltage allowable range. The charging control means for limiting the current is performed by software control by a microprocessor.
7. The electric double layer capacitor charging method according to 7.