JP2001025162A - Uniformly charging equipment for electric double-layer capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide uniformly charging equipment for an electric double-layer capacitor, which prevents deterioration of the cell by preventing the overcharge of becoming over breakdown strength as to each cell, and enables maximum utilization of the cell capacity, in charging equipment which is used for a plurality of electric double-layer capacitor cells which are connected in series. SOLUTION: This uniformly charging equipment 1 for an electric double-layer capacitor is used for a plurality of electric double-layer capacitors cells 6 connected in series. Equalizing means 5, which operate receiving the signals from an equalizing charge control means 4, are connected in parallel to each cell 6, and each equalizing means 5 has a means for charging the cell, without letting the charging current bypass as to the cell under the specified voltage, when equalizing the voltage of each cell 6 on the one hand, while for either letting the charge current bypass it or discharging the cell as to the cell over the specified voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention is used for a plurality of electric double layer capacitor cells connected in series,
The present invention relates to a uniform charging device for an electric double-layer capacitor that prevents overcharge of each cell beyond a withstand voltage to prevent cell deterioration and enables maximum utilization of cell capacity.

[0002]

2. Description of the Related Art Electric double-layer capacitors have a farad-class large capacity and excellent charge-discharge cycle characteristics, and are therefore used as backup power supplies for electronic equipment and batteries for various transport vehicles such as automobiles. Besides
From the viewpoint of effective use of energy, use in applications such as storage of nighttime power is also being considered.

[0003] Among these applications, in applications requiring a large amount of current, such as for an automobile, a plurality of electric double layer capacitor cells (hereinafter, referred to as "cells") connected in series are further provided. It is common that modules are assembled and used by connecting them in parallel. When this module is charged and discharged, a difference occurs in the voltage between terminals of each cell due to variations in characteristics such as the capacitance and leakage resistance of each cell in the series connection of the capacitors in the module, and the cell voltage becomes higher than the withstand voltage. As a result, the cells whose life is degraded are generated.

In order to solve this problem, Japanese Patent Publication No. Sho 62
Japanese Patent Publication No. 4848 discloses a method of connecting a bleeder resistor in parallel to each cell to equalize cell voltages. Japanese Utility Model Laid-Open Publication No. 4-26522 discloses a method of limiting a charging voltage by a voltage clamp. Further, Japanese Patent Laid-Open No. Hei 10-174283 discloses a charging method for monitoring a voltage and reducing a charging current at a predetermined voltage.

[0005]

However, the method disclosed in Japanese Patent Publication No. 62-4848 has a problem that the current flowing through the bleeder resistor becomes a leakage current for the cell, and the voltage holding time is shortened.

In addition, when the method described in Japanese Utility Model Laid-Open No. 4-26522 is used, when one of the cells connected in series reaches the clamp voltage, the charging current is bypassed to the clamp circuit. Here, in the bypass circuit, power corresponding to (cell voltage × bypass current) is consumed. Therefore, for example, in the case of a hybrid electric vehicle that is charged with a regenerative current or the like, the current is large, so that the power consumption becomes excessive and a problem arises in that the radiator must be increased.

On the other hand, when the method described in Japanese Patent Application Laid-Open No. H10-174283 is used, the charging current is reduced during the operation of the equalizing circuit to reduce the power consumption. This causes a problem of increased power consumption. In addition, since the cells that have not reached the full charge voltage are equalized by continuing charging,
If the charging current is reduced, there is an inherent problem that charging is terminated in the middle of equal charging during braking. That is, there is a problem that the cell voltage cannot be equalized unless the charging circuit operates.

[0008]

Means for Solving the Problems The present invention has been made in view of the above-mentioned problems of the prior art, and has an object to reduce the charging voltage of each cell connected in series to a withstand voltage or less. It is an object of the present invention to provide a uniform charging device for an electric double layer capacitor, which suppresses and equalizes the battery while taking safety measures in charge and discharge.

That is, according to the present invention, a uniform charging device for an electric double layer capacitor used for a plurality of electric double layer capacitor cells connected in series, which operates upon receiving a signal from a uniform charging control means. The equalization means
Connected in parallel to each of the cells, the equalization means comprises:
When equalizing the voltage of each of the cells, the cells below the predetermined voltage are charged without bypassing the charging current, while the cells exceeding the predetermined voltage are charged.
A uniform charging device for an electric double layer capacitor is provided, which has means for bypassing a charging current or discharging the cell.

In such an equalizing device for an electric double layer capacitor of the present invention, it is preferable that a means for bypassing a charging current or discharging a cell is provided with a means for limiting a discharging current. In addition, it is also preferable that the bypass of the charging current or the discharging of the cell be performed once or more than once.
It is also preferable to use such a method.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings, wherein an equivalent charging circuit as an equivalent charging device for an electric double layer capacitor, an equivalent charging timing control circuit as an equivalent charging control means, Description will be made by using an equalizing circuit as an equalizing means that operates in response to a signal from the charging timing control circuit.
However, it goes without saying that the present invention is not limited to the following embodiments.

The equalizing charge circuit according to the present invention is used for a series connection of cells in a module in which a plurality of electric double layer capacitor cells (cells) are connected in series and parallel. FIG. 1 is an explanatory diagram showing a schematic configuration of the equalizing charging circuit 1. The main components of the equalizing charging circuit 1 are a charging circuit 2, a voltage detecting circuit 3, and an equalizing charging timing control circuit (hereinafter, referred to as a “charging circuit”).
It is called "timing circuit". 4) An equalizing circuit 5 and a cell 6, wherein one equalizing circuit is connected in parallel to one cell. Note that, of course, the number of cells connected in series is not limited to four as shown in FIG.

In general, when charging and discharging are repeatedly performed on a module including a plurality of cells, a voltage balance between cells is caused due to a variation in electric characteristics such as capacitance and leakage resistance of each cell. Collapses. However, once the voltage of the cell is adjusted to an arbitrary voltage, the voltage difference in the subsequent charge / discharge cycle tends to fall within an allowable range.

Therefore, in the present invention, first, the voltages of the cells 6 are once adjusted to an arbitrary voltage lower than the voltage at the time of full charge. Specifically, cell 6
A predetermined voltage value to be equalized is determined in advance, and the total voltage value applied between all the cells 6 when the charging circuit 2 is operating is monitored by the voltage detection circuit 3, and the total voltage value of the cell to be equalized is determined. When the value obtained by the product of the predetermined voltage and the cell is reached, a timing signal is sent from the timing circuit 4 to each equalizing circuit 5 to operate the equalizing circuit 5.

The equalizing circuit 5 determines whether to perform charging or discharging in accordance with the state of charge (voltage value) of the connected cells 6, and equalizes the voltages of all the cells 6. Then, when the equalization is completed, the operation of the equalization circuit 5 is stopped. The charging by the charging circuit 2 is started again from the time when the equalization is completed. However, if the voltage detection circuit 3 is designed to have a function of detecting the fully charged state of the cell 6 as well, the voltage detection While monitoring the total voltage of the cell 6, the circuit 3 sends a signal to the charging circuit 2 at the time of reaching the full charge, the operation of the charging circuit 2 stops, and the charging of the cell 6 ends.

Here, the bypass of the charging current or the discharging of the cell 6 does not always need to be performed in a required amount (current amount) once. That is, it may be executed once or may be executed a plurality of times (a plurality of cycles).

FIG. 5 is an explanatory diagram showing an example in which equalizing charging is performed by operating the equalizing circuit 5 over a plurality of cycles. The two broken lines in FIG. 5 indicate a change in voltage due to charging / discharging of two cells (referred to as a cell 6A and a cell 6B) whose voltages are not uniform. In the first cycle, the charged voltage of the charged cell 6A becomes constant when the equalizing circuit 5 operates (Step 101 in FIG. 5), and during this time, the charged voltage of the delayed cell 6B increases. . However, in this example, before the charging voltage of the cell 6B becomes the same as that of the cell 6A, the operation of the equalizing circuit 5 is stopped, and the charging of the cell 6A is started again, and the voltage difference between the cell 6A and the cell 6B. Is left.

Next, in the second cycle, the cell 6
As for A, the equalizing circuit 5 operates in the same manner as in the first cycle, and the voltage is constant in step 102. On the other hand, during this time, the voltage of the cell 6B has risen. Thus, after the operation of the equalizing circuit 5 for the cell 6A is completed, the voltages of the cells 6A and 6B can be made uniform.

Here, FIG. 2 shows an equalizing circuit 5 A which is an embodiment of a more detailed circuit configuration of the equalizing circuit 5,
Regarding the operation of the above-described equalization charging circuit 1, the process of equalization after the timing signal from the timing circuit 4 is supplied to the equalization circuit 5A will be described in further detail.
In FIG. 2, the cell 6 is divided into a capacitance C and an equivalent internal resistance R. As shown in FIG. 2, as the timing circuit 4, specifically, a photocoupler PC
1 can be used. When a timing signal is input to the diode of the photocoupler PC1, the photocoupler P1
The output transistor of C1 conducts, which activates the equalizing circuit 5A.

That is, when the output transistor of the photocoupler PC1 is turned on, the transistor TR3 is turned on, and the equalizing voltage / reference voltage generating constant voltage diode (hereinafter, referred to as “constant voltage diode”) ZD1 through the resistor R2.
And the equalizing circuit 5A starts operating.
As shown in FIG. 2, the terminal voltage VC of the cell 6 is divided by the resistors R4 and R5 and input to the constant voltage diode ZD1, so that the constant voltage diode ZD1 , The base current of the transistor TR1 is adjusted so that

When the cell 6 is higher than the equalized voltage at this time, the transistor TR1 is turned on to turn on the bypass transistor TR4, and the transistor TR1 is turned on.
Discharge occurs, and the terminal voltage VC of the cell 6 starts to decrease. Then, when the terminal voltage VC reaches the equalized voltage, the transistor TR1 does not conduct, so that the transistor TR4 also does not conduct, the bypass operation is terminated, and the cell 2 is held at the equalized voltage.

On the other hand, if the terminal voltage VC of the cell 6 is less than the equalized voltage at the start of the operation of the constant voltage transistor ZD1, the transistor TR1 does not conduct, and the transistor TR4 does not conduct. The cell 6 is charged by this current, and the terminal voltage rises. Terminal voltage V
When C reaches the equalized voltage, the transistor TR1 conducts, so that TR4 also conducts, bypassing the charging current,
The terminal voltage VC is kept constant so that the terminal voltage VC does not become higher than the equalized voltage.

In this way, the terminal voltages of all the cells 6 in FIG. 1 can be made equalized voltages, and further charging is performed from this state, so that the terminal voltage difference between the cells 6 becomes small enough to fall within an allowable range. It is possible to do.

When the terminal voltage of the cell 6 is higher than the equalized voltage at the start of the operation of the equalizing circuit 5A, the cell 6 is discharged as described above. Short-circuit current flows to TR4. Therefore, this short-circuit current is detected by the resistor R1, and the transistor TR2 operates so that the current does not exceed a current value determined by the resistor R1 and the base-emitter voltage of the transistor TR2, and adjusts the base-emitter voltage of the transistor TR4. , The current value flowing through the transistor TR4 is limited. Thus, the discharge circuit is protected.

When there is no input from the photocoupler PC1 to the equalizing circuit 5A, the transistor TR3 does not operate, and no voltage is applied to the constant voltage diode ZD1, so that the transistor TR1 remains non-conductive.
The charging operation is continuously performed.

Next, another embodiment of the present invention will be described. FIG. 3 is an explanatory diagram showing an equalizing circuit 5B as another embodiment of the equalizing circuit 5 in FIG. 1, in which the form of the circuit portion 10 shown by a dotted frame in FIG. 2 is different. . Therefore, the equalizing circuit 5B naturally has the functions of the parts other than the circuit part 10 in the equalizing circuit 5A shown in FIG. 2, and the parts other than the circuit part 10 are the same as those in the case of the equalizing circuit 5A. To work.

In the equalizing circuit 5B, a current limiting resistor R10 is inserted on the collector side of the discharging transistor TR4. When the voltage of the cell 6 is higher than the set voltage, T
R4 conducts, but its current is limited by the current limiting resistor R10, thereby protecting the discharge circuit. For example, assuming that the current limiting resistor R10 is 1Ω and the set voltage for equalization is 2.5V, the terminal value of the cell 6 is high and the current value is 2. It will be limited to 5/1 of 2.5A.

FIG. 4 shows another equalizing circuit 5.
The explanatory view of C was shown. This equalizing circuit 5C is shown in the same manner as the equalizing circuit 5B shown in FIG. 3, and therefore, the equalizing circuit 5C also has a circuit portion other than the circuit portion 10 in FIG.

In the equalizing circuit 5 C, a thermistor THR having a positive temperature characteristic is provided on the emitter side of the discharging transistor TR 4.
Insert With such a configuration, when the discharge current increases, the thermistor THR generates heat and the resistance value increases, and the emitter voltage of the transistor TR4 increases to decrease the base current, so that the discharge current can be suppressed. become. The transistor TR2 in the equalizing circuit 5A is not required in the equalizing circuit 5C.

By the way, it is easily considered that the equalization using the equalizing device for an electric double layer capacitor of the present invention described above is not limited to only at the time of charging, and can be performed at the time of discharging or at rest. Can be For example, the terminal voltage of the cell can be equalized by operating the equalizing circuit at the time of suspension or immediately after the end of discharging, and the charging circuit can be operated as necessary.

[0031]

As described above, according to the equalizing device for an electric double layer capacitor of the present invention, the cells can be equalized at any time, not only at the time of charging, and can be equalized with a small current. Low heat value for adjustment. As a result, there is an excellent effect that the circuit components of the power semiconductor and the heat radiating device can be easily reduced in size and weight can be easily reduced.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing a configuration of a uniform charging device for an electric double layer capacitor of the present invention.

FIG. 2 is an explanatory diagram showing an embodiment of a circuit configuration of an equalizing circuit used in the electric double layer capacitor equalizing charging device of the present invention.

FIG. 3 is an explanatory diagram showing another embodiment of the circuit configuration of the equalizing circuit used in the electric double layer capacitor equalizing charging device of the present invention.

FIG. 4 is an explanatory diagram showing still another embodiment of the circuit configuration of the equalizing circuit used in the electric double layer capacitor equalizing charging device of the present invention.

FIG. 5 is an explanatory diagram showing an operation of performing an equalizing operation over several cycles in an equalizing circuit used in the electric double layer capacitor equalizing charging device of the present invention.

[Explanation of symbols]

1 ... Equal charging circuit, 2 ... Charging circuit, 3 ... Voltage detecting circuit,
4 ... Equalization charging timing control circuit, 5.5A to 5C ... Equalization circuit, 6 ... Cell, 10 ... Circuit part, 101/102
... Step, PC1 photocoupler, ZD1 constant voltage diode, TR1 to TR4 transistor, R1 bypass current value detection resistor, R10 current limiting resistor, R2
R4, R5: resistance, THR: thermistor.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yasuhisa Sakurai 2-56, Suda-cho, Mizuho-ku, Nagoya-shi, Aichi Japan Insulator Co., Ltd. No. 6 F-term in Okamura Laboratory Co., Ltd. (reference) 5G065 BA01 BA02 DA04 GA02 HA04 HA17 LA01 MA07 NA01 NA02 NA04 5H030 AA03 AS18 BB03 FF43

Claims (3)

[Claims] 1. An equalizing device for an electric double layer capacitor used for a plurality of electric double layer capacitor cells connected in series, wherein the equalizing means which operates upon receiving a signal from the equalizing charge control means includes: The equalizing unit is configured to charge the cell without bypassing a charging current for a cell that does not reach a predetermined voltage when equalizing the voltage of the cell. A charge current bypassing means for a cell having a voltage exceeding the above voltage or a means for discharging the cell. 2. The equalizing charging device for an electric double layer capacitor according to claim 1, wherein the means for bypassing the charging current or discharging the cell is provided with means for limiting a discharging current. . 3. The uniform charging device for an electric double layer capacitor according to claim 2, wherein the charging current can be bypassed or the cell can be discharged one or more times.