JP2000050495A - Monitoring and control apparatus for charging of capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a heat loss due to initialization of a capacitor by a method wherein a reference voltage is set at a voltage at several fractions of a fully charged voltage and initialization of a charging operation is corrected. SOLUTION: Respective capacitors are discharged completely. The designated signal SHn of a maximum capacitor, e.g. Cn, is set at 'H', and flip-flop 12i and a flip-flop 13i are reset. Thereby, selection signals S11,... Sn1 of a changeover switch at a parallel monitor are set at 'L', and selection signals S12,... Sn2 are set at 'H'. As a result, a reference voltage at a low voltage used to correct initialization of a charging operation is connected to respective comparison terminals. When the charging operation is started, the charging voltage of the respective capacitors is raised so as to reach the reference voltage sequentially. The output of a comparator CMP1 is set at 'H', the selection signals S11,... Sn1 are set at 'H', and the selection signals S12,... Sn2 are inverted to 'L'. Consequently, a finish signal SB which corrects the initialization as the output of an OR gate 17 is set at 'H', all the flip-flops are reset, the output is returned to 'H', and the correction of the initialization of the charging operation is finished.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor charge monitoring and control device which is connected in parallel to a plurality of capacitors constituting a power storage device, monitors the voltage of the capacitors, and controls charging.

[0002]

2. Description of the Related Art FIG. 6 is a diagram showing a circuit configuration of a parallel monitor.
FIG. 7 is a diagram for explaining the charge / discharge waveform with the parallel monitor and the operation without the parallel monitor. In the figure, C is an electric double layer capacitor, CMP is a comparator, D is a diode, T
r indicates a transistor, and Vr indicates a reference voltage.

[0003] Combining a plurality of large capacity capacitors,
An indispensable condition for a power storage device is a problem of equalization of burden voltage that occurs when capacitors are connected in series.
The present inventors have proposed a power storage device called an ECS (Energy Capacitor System) using an electric double layer capacitor (for example, electronic technology, 1994-12, p1 to p1).
3, Denki Kagaku B, Vol. 115, No. 5, 1995, p.
10). In the ECS, a parallel monitor as a voltage monitoring and control device is connected to individual capacitors connected in series so that the maximum charge can be performed within the withstand voltage range of the capacitors.

[0004] The parallel monitor uses a comparator CMP to change the voltage of the capacitor C to a reference voltage Vr as shown in FIG.
Is monitored by comparing with the reference voltage Vr.
Exceeds the set value, the transistor Tr is turned on to bypass the charging current. By this operation, the charging voltage of the capacitor C is maintained at the set value as shown in FIG. 7, and the constant voltage is relaxed until the other capacitors connected in series reach full charge and start the next discharge. The charging mode is set. As described above, in the ECS, the problem that the voltage distribution of the capacitor becomes as shown in the circle of FIG. 7 due to the variation in the individual capacitance and the difference in the voltage at the start of charging is suppressed to the upper limit of the charging voltage in terms of The problem was solved by initializing (clamping) the voltage at the upper limit and charging / discharging with the voltage as a starting point.

[0005]

However, since the above-mentioned configuration can be realized simply and at low cost and the operation is reliable, it has played a large role in putting the ECS into practical use. The problem is that the charging energy during the period when the monitor is turned on becomes heat. That is, in the parallel monitor shown in FIG. 6, when the set voltage is reached, the transistor Tr is operated to form a bypass circuit so that the voltage does not rise any more, and the "voltage clamp" of the electronic circuit is prevented. Created a state, but for that,
In the bypass circuit, a loss corresponding to the charging current × the full charging voltage occurs and heat is generated.

In the case of a secondary battery, heat is generated every time a charge / discharge cycle occurs. However, in a capacitor, heat is generated only once at first, and thereafter, the set value of full charge, It is characterized in that it starts discharging from the potential and discharges downward as shown in FIG. Therefore, it is possible to reduce the power loss generated by reducing the charging current only in the case of initialization, but this increases the time required for initialization, but the amount of power required for initialization cannot be reduced. It has the same value. Also, "In order to reduce the power loss to make the charging voltage uniform, it is better to perform initialization at a low voltage stage." However, if clamping is performed at a low voltage stage, charging will not proceed and which capacitor will charge faster. Or is indistinguishable.

[0007]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to reduce heat loss due to initialization of a capacitor connected in series and used as a power storage device.

For this purpose, the present invention provides a capacitor charge monitoring and control device which is connected in parallel to each of a plurality of capacitors constituting a power storage device, monitors the voltages of the plurality of capacitors and controls charging, and A plurality of bypass means for bypassing a charging current of the capacitor, a voltage setting means for setting a reference voltage to a voltage lower than a full charge voltage of the plurality of capacitors, and a charging voltage of the plurality of capacitors set by the voltage setting means. A plurality of first control means for controlling the bypass means to a bypass operation mode by judging that the bypass voltage has reached the reference voltage by comparing with the reference voltage, and controlling each of the bypasses controlled to the bypass operation mode. Charging initialization correction by maintaining the operation of the means until each charging voltage of the plurality of capacitors reaches the reference voltage Performed, and is characterized in that a second control means for controlling so as to charge up thereafter the full charge voltage of the plurality of capacitors to cancel the bypass mode of operation of the bypass means.

Further, the reference voltage is a fraction of a full charge voltage, and the second control means determines whether or not the charge voltage of a predetermined capacitor or all the capacitors reaches the reference voltage. During this time, the operation in the bypass mode is continued, and the constant current charging up to that time is terminated on condition that any one of the charging voltages of the plurality of capacitors has reached the full charging voltage.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an embodiment of a capacitor charge monitoring and control device according to the present invention, FIG. 2 is a diagram for explaining the operation of the capacitor charge monitor and control device according to the present invention, and FIG. FIG. 7 is a diagram for explaining the operation of the present invention when connected in series. In the figure,
1 _1, 1 ₂ comparator, 2 is a switch control circuit, C
₁ and C ₂ are capacitors, D ₁ and D ₂ are diodes, Tr
_1, Tr ₂ are _{transistors, S 1 1, S 1 2} , S 2 1, S 2 2 is changeover _{switch, Vr 1 1, Vr 1 2} , Vr 2 1, Vr 2 2 denotes a reference voltage.

In FIG. 1A, capacitors C ₁ and C
₂ is an electric double layer capacitor constituting the power storage device connected to the serial-parallel, the transistor Tr _1, Tr ₂ is a bypass means for bypassing the charging current of the capacitor C _1, C _2. Comparator ₁ 1, 1 _2, the capacitors C _1, the reference voltage Vr ₁ 1 charging voltage of C _2, Vr
₁ 2, Vr ₂ 1, monitors compared to Vr 2 _2, transistor Tr ₁ determines that the charging voltage reaches the reference voltage,
Tr ₂ is operated in the bypass mode. Changeover switch S ₁ 1, S ₁ 2, S ₂ 1, S ₂ 2, the comparators ₁ 1, 1 ₂ the reference voltage Vr ₁ 1 for comparing the charging voltage of the capacitor C _1, C _2, Vr ₁ 2, Vr ₂ 1, which switches the Vr 2 _2, the switch control circuit 2, the changeover switch S ₁ 1 based on the determination output of the comparators 1 _1, 1 _2,
And controls the switching of _{S 1 2, S 2 1,} S 2 2.

[0012] In the capacitor charge monitoring and control device according to the present invention, in the above configuration, at a very early stage of charging a voltage that is a fraction of the full charge voltage, first, charging of the capacitor that has reached the predetermined voltage first. When the current is bypassed and another capacitor reaches the predetermined voltage with a delay, the bypass mode of the previous capacitor is released and charging is performed up to the full charge voltage.
For example, capacitors C ₁ = 1000F, C ₂ = 800F,
A case will be described where the full charge voltage is 3 V, the initialization is corrected at the stage of 0.8 V at a charge current of 10 A, and the charging is performed until the total voltage reaches 6 V. FIG. 2 shows a voltage waveform between the terminals of the _two capacitors C ₁ and C ₂ at this time. First, set the 3V reference voltage _{Vr 1 2, Vr 2 2 0.8V} , the reference voltage Vr ₁ 1, Vr ₂ 1, the comparator ₁ 1,
Selecting Vr ₁ 2, Vr 2 ₂ to the reference voltage connected to one _second comparison terminals. When starting the charging from the initial zero voltage, it is more smaller capacitors C ₂ capacity is charged more rapidly than the capacitor C ₁ as shown in FIG. Therefore,
0 charge voltage of capacitor C ₂ is a set value is first at A.
Reaching 8V, the the output of the comparator 1 ₂ to turn on the transistor Tr _2, a capacitor C ₂ with a time constant determined by the resistance components R1, R2 of the circuit including the transistor Tr ₂ starts to discharge (bypass mode of operation).
When the charging voltage of the other capacitors C ₁ and to sustain the discharge is the time B to reach 0.8V setting to cancel the bypass mode of operation, the reference voltage connected to the comparator terminal of the comparator 1 _1, 1 ₂ to 3V full charge voltage respectively switched to Vr _{1 1,} Vr _{2 1,} is charged up to a total voltage reaches 6V.

Further, when three or more capacitors are connected in series, as shown in FIG. 3, the largest capacitor among them, that is, the last capacitor reaches this low voltage reference voltage, and B is Become. The voltage fluctuation waveform shown in FIG. 3 decreases the capacitance from 1000 F in steps of 5%.
An operation example in the case where it is changed to 20% is shown.

[0014] The reference voltage Vr as described above ₁ 1, Vr ₂ 1 3
To full charge voltage and V, when performing initialization corrected by the reference voltage Vr _{1 2,} Vr 2 2 at the stage of just 0.8V to align the charging voltage, only 7% in power. However, reducing the reference voltage Vr _{1 2,} Vr 2 2, transistor Tr
_Although the power loss when the ₂ turns on and discharge can be further reduced, when the variation of the capacitor is large, the discharge voltage reaches the bottom at the point B, and accurate correction cannot be performed. As described above, in the case of a capacitor having a capacitance of 1000 F and a full charge voltage of 3 V, when the reference voltage at the time of initialization correction is set to 0.8 V, it is possible to correct the variation of the capacitor capacitance within -20%. In this case, even if the power is discharged from 0.8 V to zero, only 7% of the power is required. Therefore, as described above with reference to FIG. Obviously it is big. Of course, in the case of a capacitor having a larger variation, if the reference voltage is increased, the loss increases accordingly, but the range that can be corrected can be expanded.

Next, an example of a switch control circuit for switching the reference voltage will be described. FIG. 4 is a diagram illustrating a configuration example of a circuit that controls a changeover switch based on a selected state of a reference voltage and an output of a comparator, and includes 11 _i , 14 _i , 16-1 to 1.
6-n and 18 are AND gates, 12 _i and 13 _i are flip-flops, and 15 _i and 17 are OR gates.

FIG. 4A shows an example of the configuration of a circuit for controlling a changeover switch for selecting a reference voltage of a comparator corresponding to the parallel monitoring of each capacitor. FIG. 4B and 4C show an example of the configuration of a common circuit for canceling the operation mode of the parallel monitor.

In FIG. 4A, an AND gate 11 _i
The output CM of the comparator 1 ₁ and 1 ₂ of FIG. 1
P _i selected, the reference voltage _{Vr 1 1, Vr 1 2,} Vr 2 1, the changeover switch S ₁ 1 to select switching the Vr ₂ 2 any, S ₂ 1 of the selection signals S1 _i, on whether the reference voltage or ground potential is intended for calculating a logical product of the switch S _{1 2,} S 2 2 of the selection signals S2 _i for switching. Here, the comparator 1
_1, 1 ₂ of the output CMP _i, the voltage comparison voltage of the capacitor, or "H" to reach the reference voltage, the selection signal S1 _i is changeover switch S ₁ 1, S ₂ 1 is the reference voltage of the full-charge voltage when in the position to select the "H", "L" when in the position for selecting the reference voltage of the low voltage for initializing the correction, the selection signal S2 _i is changeover switch S _{1 2,} S 2 2 the reference It is "H" when in the position for selecting the voltage side, and "L" when in the position for selecting the ground side. Therefore, the AND gate 11
_i is the reference voltage of the low voltage to initialize the correction is connected to the comparison terminal of the comparator 1 _1, 1 _2, becomes "H" when the voltage of the capacitor reaches the reference voltage.

The flip-flop 12 _i is configured to output a selection signal S _i 1 of the switch S _{1 1,} S _{2 1,} reset by inputting a reset pulse inputted during initialization to the R terminal And outputs “L”.
It becomes “H” together with the “H” output of the AND gate 11 _i input to the terminal. Flip-flop 13 _i is for outputting a changeover switch S _{1 2,} S 2 2 of the selection signals S _i 2, a reset pulse or initialization correction of the end signal is input at the start initialization through the OR gate 15 _i by being reset outputs "H" by inputting a S _B to the R terminal, entering through the aND gate 14 _i designation signal SL _i of the output and the capacitor of the aND gate 11 to the S terminal, designation signal SL _i Is "L", the output becomes "L" together with the "H" output of the AND gate _11i . Designation signal SL _i is set to "H" only for the largest capacitor mentioned above, for other capacitor is for setting the "L". Therefore, in a series connection circuit of a plurality of capacitors, “H” is set only for one of the capacitors. The end signal S _B initialization correction serves as a "H" when it reaches the reference voltage of the low voltage that the maximum capacitor performs last initialized correction, a configuration example of the signal generating circuit Figure 4 shows
(B). According to the circuit shown in FIG. 4 (B), only one of the designation signals SL ₁ , SL ₂ ,..., SL _n is set to “H” and all the others are set to “L”. , Comparator outputs CMP ₁ , CMP ₂ ,..., C
Even when the MP _n has become "H", the specified signal is set to "H" SL _1, SL _2, ......, the AND gate 16-1 and 16-2 of the SL _n, ......, of the 16-n Only the output becomes “H”, and the other AND gate 16-1,
The outputs of 16-2, ..., 16-n always remain "L".

Next, the operation will be described. First, each capacitor is fully discharged, resetting the largest capacitors, for example, a C _n of the designation signal SL _n is set to "H" flip-flop 12 by the reset pulse _i, 13 _i. Thus, the selection signal S _{1 1,} S _{2 1} of the changeover switch of the parallel monitor of each capacitor, ......, S _n 1 is "L", S
_{1 2, S 2 2, ......} , since S _n 2 becomes "H", as shown in FIG. 1
As shown in (A), the comparison terminals of the respective comparators have low-voltage reference voltages Vr ₁₂ and Vr for performing initialization correction.
_{2 2,} ...... Vr _{n 2} are connected. Next, when starting the charging, rises the charging voltage of each capacitor, each sequentially reference voltage Vr _{1 2,} Vr 2 2, since reaching ..., the output of the comparator CMP _1, CMP _2, the output of ... is becomes "H", the selection signal _{S 1 1, S 2 1,} ...... is "H", the selection signal S
_{1 2,} S 2 2, ...... is inverted to "L". At this time, the changeover switch is in the connection state shown in FIG. The reference charging voltage of the last capacitor C _n voltage Vr _n
When it reaches 2, the output CMP _{n of} the comparator becomes “H”. At this time, since the designating signal SL _n is set to "H", the output of the AND gate 16-n shown in FIG. 4 (B) becomes "H". Also, the AND gate 14 _n (FIG. 4)
Since the output of 14 _i ) shown in (A) remains at “L”, the flip-flop 13 _n is not set.
Therefore, end signal S _B of which is the output initialization correction of the OR gate 17 becomes "H", the flip-flop 13 _i
Are all reset, the output returns to "H", and the initialization correction ends. After that, the changeover switch is turned on as shown in FIG.
Since the connection state shown in each of the capacitor and the reference voltage Vr _{1 1,} Vr _{2 1,} is charged toward the full charge voltage determined by ...... Vr _n 1.

As the number of capacitors increases, it becomes more troublesome to identify the largest capacitor.
Without specifying a capacitor, a configuration example of a circuit in which the last capacitor is so as to generate an end signal S _B of the detection to initialize the correction that has reached the reference voltage of the low voltage to perform a predetermined initialization correction FIG. 4C shows this. In this case, eliminating the designation signal SL _i and an AND gate 14 in FIG. 4 (A), the coupled output of the AND gate 11 to the S terminal of the direct flip-flop. Then, the AND gate 18, all of the selection signals _{S 1 1, S 2 1,} ......, S
_By setting _n 1, that is, the output “H” as a logical product when the flip-flop 12 is set, the circuit is configured to reset all the flip-flops 13.

FIG. 5 is a diagram showing another embodiment of the capacitor charge monitoring and control device according to the present invention. In the above embodiment, the reference voltage Vr _i 2 undervoltage initializes correction capacitors, then, the reference voltage Vr _i 1 to the full-charge voltage
Is switched to charge the battery until the battery is fully charged. However, when it is detected that one of the batteries has been charged to the full charge voltage, the constant current charging up to that point is terminated, and the next discharge (FIG. ) May be configured to control to the constant voltage relaxation charging mode. FIG. 5 shows the embodiment. In the embodiment shown in FIG.
Insert connecting the switch S _i 3 switching between the _i output and the gate of the transistor Tr _i, the initialization correction is completed, the detection signal F _i of full charge voltage output from the comparator 1 _i from the gate of the transistor Tr _i Output terminal. Detection signals F _i of the full charge voltage, 5
As shown in (B), the detection signal F ₁ of the full charge voltage of each capacitor is supplied to the OR gate 19 that performs the OR operation.
F _2, ......, input as F _n, and sends a charging completion signal for switching the constant current charging from the OR gate 19 to it to mitigate charging mode of constant voltage.

In order to generate a charge end signal,
The comparator 1 _i to have a separate comparator (not shown), thereby may select one or several of the plurality of capacitors as a representative so as to monitor the charging voltage. In this case, switch S _i 3 switched as shown in FIG. 5 (C), the initialization correction is completed, may be the output of the comparator 1 _i to decouple from the gate of the transistor Tr _i. When the charging voltage of the capacitor reaches the low reference voltage, the transistor Tr
_{When the} capacitor is discharged with a predetermined time constant by turning on _i , the comparison terminal of the comparator 1 _i is connected to the ground potential. Of course, as shown by the dotted line in FIG. It may be configured to be connected.

Incidentally, there are two causes of the variation in the burden voltage of the capacitor: the variation in the capacitance and the variation in the leakage current. According to the above embodiment, the variation can be solved, but a large variation may be accumulated by the charge / discharge cycle, and may further grow to an extreme variation. In particular, the leakage current due to the self-discharge of the capacitor shows a much larger distribution than the capacity error and the like, and it is difficult to control the quality of the distribution over the entire life span. In the present invention, such a problem can be solved by performing the same initialization by performing a full discharge on the contrary. That is, the capacitor is completely discharged and further charged with a small current in the opposite polarity until the diode D connected in anti-parallel with the transistor Tr is turned on. By keeping this state for a time constant unique to the capacitors until the diodes D connected to all the capacitors are turned on, all the residual voltages can be made uniform.

In the case of the embodiment shown in FIG. 5, a conventional parallel monitor in which a rise in a voltage higher than a set value (full charge voltage) is forcibly suppressed by turning on a transistor Tr is described. Then, the voltage is not forcibly suppressed as shown in FIG. Therefore, the transistor is not used in the charge and discharge after the initialization correction is performed, so that the conventional heat loss during the normal charge and discharge can be eliminated, and the comparator and the transistor can be replaced with the defective capacitor as necessary. It may be commonly used to monitor the charging voltage for monitoring a short circuit, an increase in variation, or for other purposes.

It should be noted that the present invention is not limited to the above embodiment, and various modifications are possible. For example, in the above-described embodiment, the comparison terminal of the comparator is connected to the ground potential in the bypass operation mode for performing the initialization correction. However, the bypass operation mode is held by another circuit, and the initialization operation is terminated. A circuit configuration in which the control logic is released by a signal may be employed, or such control logic may be incorporated by software. Of course, the present invention is not limited to the circuit configurations shown in FIG. 1, FIG. 4, and FIG. Although the end signal of the initialization correction is generated by monitoring the voltage of the last capacitor, an appropriate capacitor is selected, the voltage is monitored, and after the charging voltage reaches a predetermined voltage, a predetermined time is reached. May be configured to be released on condition that the time has elapsed. Further, although the reference voltage is prepared and connected to each of the comparators corresponding to the parallel monitoring of the respective capacitors, these may be connected in common.

[0026]

As is apparent from the above description, according to the present invention, the reference voltage is set to a fraction of the full charge voltage, and the charge voltage of the capacitor is used as the correction for initializing the charge. When the voltage reaches the voltage, the bypass operation mode is maintained, and after the charging voltage of the other capacitors reaches the reference voltage,
Since the operation in the bypass mode is canceled to perform the charging and discharging up to the full charge voltage, correction based on the variation of the capacitor can be performed in the initial stage of the low voltage, and the heat loss during initialization can be reduced. Moreover, by using the comparator and the transistor that bypasses the charging current only for the initialization correction, the comparator and the transistor can be shared for various types of monitoring of the capacitor after the initialization correction. Can monitor and control the capacitor.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of a capacitor charge monitoring and control device according to the present invention.

FIG. 2 is a diagram for explaining the operation of the capacitor charge monitoring and control device according to the present invention.

FIG. 3 is a diagram for explaining the operation of the present invention when three or more capacitors are connected in series;

FIG. 4 is a diagram illustrating a configuration example of a circuit that controls a changeover switch based on a selection state of a reference voltage and an output of a comparator.

FIG. 5 is a diagram showing another embodiment of the capacitor charge monitoring and control device according to the present invention.

FIG. 6 is a diagram showing a circuit configuration of a parallel monitor.

FIG. 7 is a diagram for explaining a charge / discharge waveform with a parallel monitor and an operation without a parallel monitor.

[Explanation of symbols]

1 ₁ , 1 ₂ … Comparator, 2… Switch control circuit, C
₁ , C ₂ ... capacitor, D ₁ , D ₂ ... diode, Tr
_1, Tr ₂ ... _{transistors, S 1 1, S 2 1} , S 2 2 ... changeover _{switch, Vr 1 1, Vr 1 2} , Vr 2 1, Vr 2 2 ... reference voltage

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Dio Okamura 2-19-6 Minamiota-cho, Minami-ku, Yokohama-shi, Kanagawa Prefecture (72) Inventor Akinori Mogami 3-1-2 Musashino, Akishima-shi, Tokyo Japan Electronics F term in the company (reference) 5G065 AA01 DA04 EA01 FA05 HA01 HA16 JA02 KA02 KA05 LA01 MA09 MA10 NA01 PA01

Claims (5)

[Claims] 1. A capacitor charge monitoring and control device connected to each of a plurality of capacitors constituting a power storage device in parallel to monitor voltages of the plurality of capacitors and control charging, wherein a charge current of the plurality of capacitors is controlled. A plurality of bypass means for bypassing, a voltage setting means for setting a reference voltage to a voltage lower than the full charge voltage of the plurality of capacitors, and a reference voltage set by the voltage setting means to charge the plurality of capacitors. A plurality of first control means for controlling the bypass means to a bypass operation mode by determining that the reference voltage has been reached, and controlling the operation of each bypass means controlled to the bypass operation mode. The initialization of the charging is corrected by maintaining each charging voltage of the plurality of capacitors until the charging voltage reaches the reference voltage. A second control unit for releasing the bypass operation mode of the bypass unit and controlling the plurality of capacitors to be charged to the full charge voltage. 2. The reference voltage is a fraction of a full charge voltage.
2. The capacitor charge monitoring and control device according to claim 1, wherein 3. The capacitor charging monitor according to claim 1, wherein said second control means keeps said bypass operation mode until a charging voltage of a capacitor designated in advance reaches said reference voltage. Control device. 4. The capacitor charge monitoring control according to claim 1, wherein said second control means keeps operating in said bypass mode until charging voltages of all capacitors reach said reference voltage. apparatus. 5. The constant current charging according to claim 2, wherein the second control means terminates constant current charging on condition that one of the charging voltages of the plurality of capacitors reaches a full charging voltage. 2. The capacitor charge monitoring and control device according to claim 1.