TWI360297B - I/o circuit - Google Patents

I/o circuit Download PDF

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Publication number
TWI360297B
TWI360297B TW097105883A TW97105883A TWI360297B TW I360297 B TWI360297 B TW I360297B TW 097105883 A TW097105883 A TW 097105883A TW 97105883 A TW97105883 A TW 97105883A TW I360297 B TWI360297 B TW I360297B
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Taiwan
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nmos
control signal
input
output
driver
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TW097105883A
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Chinese (zh)
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TW200836487A (en
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Teruo Suzuki
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Fujitsu Semiconductor Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)

Description

1360297 九、發明說明： 相關申請案之對照參考資料 本申請案係根據並主張2007年2月20日提申的習知日 本專利申請案第2007_038959號之優先權，其全部内容被併 5 入在此供參考。 【發^明所屬技_撕&quot;&gt;^域^】 發明領域 本揭露有關一種輸入/輸出電路，其中一驅動器電路係 與一 ESD保護電路分開路電壓。 10 【先前技術】 相關技藝說明 根據一揭露於James W. Miller，Michael G. Khazhinsky 及 James C· Weldon 的 “ ECNMOS Output Buffer for Maximum Vtl” ，第22屆EOS/ESD研討會論文，p_308-317， I5 所卸的是’若分隔一主動區之一第一NMOS驅動器10與一 第二NM0S驅動器11被串聯連接如第5圖所示，一 ESD崩潰 電壓被提升。 另外，如第6圖所示，在ESD電壓的研究係完成關於一 驅動器電路21其中一第一NM0S驅動器10的一閘極及一第 20 二NM0S驅動器11的一閘極二者被連接至一地電位VSS，且 一第二NM0S驅動器11的一閘極被連接至一輸入/輸出（1/〇) 墊、及一驅動器電路203其中一第一NM0S驅動器1〇的一閘 及被連接至一L0墊，且一第二NM0S驅動器11的一閘極被 連接至一地電位VSS、及一驅動器電路204其中一第一 5 1360297 NMOS電晶體ι〇的一閘及與一第：NM〇s驅動器丨丨的一閘 極二者被連接至一 I/O墊。 第7圖顯示在該等驅動器電路201到204之ESD耐電壓 上的研究之結果，該曲線圖中顯示該等電路之各個特性的 5到達點分別指示該等電路的ESD崩潰電壓與崩潰電流。當 該驅動器電路202與該驅動器204在近8.2V崩潰時，該驅動 器電路201與該驅動器電路2〇3維持一對抗ESD崩潰的容忍 度上至近16V。 在該驅動器電路201與該驅動器電路2〇3之間的共同點 10疋s亥第一NMOS驅動器11的閘極被連接至該地電位vss。於 是，清楚的是，該ESD崩潰電壓，藉由將在它的源極被連 接至該地電位VSS之側的第二NMOS驅動器11之閘極連接 至該地電位’被提升於該具有顯示於“ECNMOS Output Buffer for Maximum Vtl”之串聯結構的驅動器電路。第8 15圖顯示一傳統I/O電路其中一電容器25被社在該第二NMOS 驅動器11的一閘極端C與該地電位之間，且該第二NM0S驅 動器11之閘極端C被保持在該地電位。 此外’另一相關技術被揭露於PCT國際專利公報第 2003-510827號的公開日本翻譯。 2〇 【發明内容】 發明概要 根據本發明一實施例的一個觀點，一種輸入/輸出（I/O) 電路被提供，其包含有：一第一NM0S驅動器，其具有一 連接至一輸入/輸出墊的汲極；一第二NM0S驅動器，其被 6 1360297 佈局在一不同於該第一nmos驅動器的主動區中，該第二 NMOS驅動H具有—連接至該帛__NM〇s驅動_之源極的 汲極以及一連接至一地電位的源極；一具有一閂鎖結構之 位準轉換盗’該位準轉換器係適於接收在一與一電源電位 5分開之内部電源電位下被驅動的一第一控制信號及一互補 於該第一控制信號的信號，並將該第一控制信號與該互補 於該第一控制信號之信號轉換成與該第一控制信號同相位 且在該電源電位下被驅動的一第二控制信號及一互補於該 第二控制信號的信號；及一第—NM〇s電晶體，其具有— 10連接至該位準轉換器的一輸出端的汲極，該第二控制信號 係輸出自該位準轉換器之該輸出端、一連接至一地電位的 源極、及一連接至該位準轉換器中一互補於該第二控制信 號之信號的一輸出端的閘極；其中該第一 NM0S電晶體之 汲極被連接至該第二NM0S驅動器的一閘極。 15 圖式簡單說明 第1圖是一顯示根據本實施例的一種I/O電路結構之電 路圖； 第2圖是一顯示在一 ESD測試電壓被施加至一 I/O墊之 情況下的PMOSESD保護元件的橫截面圖； 20 第3圖是一顯示該ESD保護元件之結構的橫截面圖； 第4圖是一顯示該ESD保護元件之Ι·ν特性的特性圖； 第5圖是一顯示在一串聯結構中NM0S驅動器的一結 構之佈局圖； 第6圖是一顯示在具有不同結構之驅動器電路之連接 7 1360297 的電路圖； 第7圖是一顯示該等具有不同結構之驅動器電路 ESD耐電壓特性之特性圖；及 的 第8圖是—顯示一傳統I/O電路之結構的電路圖。 5 【實施方式】 較佳實施例之詳細說明 將該第二NMOS驅動器11之閘極端C保持在該地電位 需要使用一具有一大電容值的電容器，具有一大電容值之 電谷器的使用產生一問題是該佈局表面被增加。若在該閑 10 極端之信號位準’在該第二NMOS驅動器11係成為導電 時，從一地電位轉移至一 “H”位準，則該電容器需要時間 充電，其產生一問題是該轉移時間變長。同樣地，發生的 問題是，當該電容器被使用且經由一PMOS電晶體17被充電 時，在該第二NMOS驅動器11之閘極端的電位增加。 15 提供的是一種I/O電路其包含串聯連接的NMOS驅動 器，其中在地側的該等NMOS驅動器具有一小區域，起動 該等在該地側的NMOS驅動器之轉移時間是短的，並且在 該地側之該等NMOS驅動器之該等閘極電壓被更可靠地設 定至該地電位。 20 一 I/O電路的一實施例將參考第1圖到第4圖被詳細說 明在下。</ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> This is for reference. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input/output circuit in which a driver circuit separates a circuit voltage from an ESD protection circuit. 10 [Prior Art] The related art is based on "ECNMOS Output Buffer for Maximum Vtl" by James W. Miller, Michael G. Khazhinsky and James C. Weldon, 22nd EOS/ESD Symposium Paper, p_308-317, I5 is unloaded. 'If one of the active regions is separated, the first NMOS driver 10 and a second NMOS driver 11 are connected in series as shown in FIG. 5, and an ESD collapse voltage is boosted. In addition, as shown in FIG. 6, the research on the ESD voltage is completed with respect to a driver circuit 21, wherein a gate of a first NMOS driver 10 and a gate of a 20 NAND driver 11 are connected to one. a ground potential VSS, and a gate of a second NMOS driver 11 is connected to an input/output (1/〇) pad, and a driver circuit 203 of a first NMOS driver 1 〇 is connected to a gate An L0 pad, and a gate of a second NMOS driver 11 is connected to a ground potential VSS, and a driver circuit 204, a first 5 1360297 NMOS transistor ι〇 and a 1:NM〇s driver Both of the gates of the turns are connected to an I/O pad. Figure 7 shows the results of a study of the ESD withstand voltages of the driver circuits 201 to 204, which show the 5 arrival points of the various characteristics of the circuits indicating the ESD collapse voltage and the breakdown current of the circuits, respectively. When the driver circuit 202 and the driver 204 collapse at nearly 8.2V, the driver circuit 201 and the driver circuit 2〇3 maintain a tolerance against ESD collapse up to approximately 16V. At the common point between the driver circuit 201 and the driver circuit 2〇3, the gate of the first NMOS driver 11 is connected to the ground potential vss. Thus, it is clear that the ESD breakdown voltage is connected to the ground potential by the gate of the second NMOS driver 11 whose source is connected to the ground potential VSS. A driver circuit of a series structure of "ECNMOS Output Buffer for Maximum Vtl". Figure 8 15 shows a conventional I/O circuit in which a capacitor 25 is placed between a gate terminal C of the second NMOS driver 11 and the ground potential, and the gate terminal C of the second NMOS driver 11 is held at The ground potential. Further, another related art is disclosed in the Japanese Japanese translation of PCT International Patent Publication No. 2003-510827. SUMMARY OF THE INVENTION According to an aspect of an embodiment of the present invention, an input/output (I/O) circuit is provided, comprising: a first NMOS driver having a connection to an input/output a drain of the pad; a second NMOS driver arranged by the 6 1360297 in an active region different from the first nmos driver, the second NMOS driver H having a source connected to the 帛__NM〇s driver a pole of a pole and a source connected to a ground potential; a level shifting thief having a latching structure adapted to receive an internal power supply potential separated from a power supply potential 5 Driving a first control signal and a signal complementary to the first control signal, and converting the first control signal and the signal complementary to the first control signal into phase with the first control signal and a second control signal driven at a power supply potential and a signal complementary to the second control signal; and a first NM〇s transistor having a drain connected to an output of the level converter The second control letter The output is output from the output of the level converter, a source connected to a ground potential, and a gate connected to an output of the level converter complementary to the signal of the second control signal Wherein the drain of the first NMOS transistor is connected to a gate of the second NMOS driver. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram showing an I/O circuit structure according to the present embodiment; Fig. 2 is a diagram showing PMOS ESD protection in the case where an ESD test voltage is applied to an I/O pad. Cross-sectional view of the component; 20 Figure 3 is a cross-sectional view showing the structure of the ESD protection element; Figure 4 is a characteristic diagram showing the Ι·ν characteristic of the ESD protection element; Figure 5 is a A layout diagram of a structure of a NMOS driver in a series configuration; FIG. 6 is a circuit diagram showing a connection 7 1360297 of a driver circuit having a different structure; and FIG. 7 is a circuit showing ESD withstand voltage of the driver circuit having different structures A characteristic diagram of the characteristics; and Fig. 8 is a circuit diagram showing the structure of a conventional I/O circuit. [Embodiment] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The holding of the gate terminal C of the second NMOS driver 11 at the ground potential requires the use of a capacitor having a large capacitance value, and the use of a battery having a large capacitance value. A problem is that the layout surface is increased. If the signal level at the idle 10 extreme is shifted from a ground potential to an "H" level when the second NMOS driver 11 is conductive, the capacitor needs time to charge, which causes a problem that is the transfer. Time is getting longer. Similarly, a problem occurs in that when the capacitor is used and charged via a PMOS transistor 17, the potential at the gate terminal of the second NMOS driver 11 increases. Provided is an I/O circuit comprising NMOS drivers connected in series, wherein the NMOS drivers on the ground side have a small area, and the transition time of starting the NMOS drivers on the ground side is short, and The gate voltages of the NMOS drivers on the ground side are more reliably set to the ground potential. An embodiment of an I/O circuit will be described in detail below with reference to Figs. 1 through 4.

第1圖是一顯示根據本實施例的一種1/0電路1之結構 之電路圖。該I/O電路1係設有一第—NM〇s驅動器10及一第 二NMOS驅動器11，該第一NMOS驅動器10與該第二NMOS 8 1360297 驅動器11安排以使得一種主動區被分割在其間如第5圖所 示’這些驅動器被一保護環34 (—背閘極的一井塞）圍繞在 其周圍，該第一NMOS驅動器10的一源極與該第二NMOS 驅動器的一汲極係在一配線層中被互相連接。Fig. 1 is a circuit diagram showing the structure of a 1/0 circuit 1 according to the present embodiment. The I/O circuit 1 is provided with a first NM〇s driver 10 and a second NMOS driver 11, and the first NMOS driver 10 and the second NMOS 8 1360297 driver 11 are arranged such that an active region is divided therebetween. Figure 5 shows that these drivers are surrounded by a guard ring 34 (a well plug of the back gate), a source of the first NMOS driver 10 and a drain of the second NMOS driver are A wiring layer is connected to each other.

5 如所說明的，該第一NMOS驅動器10與該第二NMOS 驅動器11每一個被一降低通過一主體層的電性干擾之保護 層34圍繞在其周圍，因此使得可能進一不增加該ESd抗電 壓。 回到第1圖，該I/O電路1係設有一NMOS電晶體12，其 10 具有一連接至該VSS的閘極以及一與該NMOS電晶體12串 聯連接的矽化物區塊13，其當作一ESD保護電路。該I/O電 路1亦設有一具有一連接至一外部電源VDE之閘極的pm〇S 電晶體14、及一PM0S電晶體15其連同該第一NMOS驅動器 10形成一反相器，其當作一ESD保護電路。由該PM0S電晶 15 體15與該第一NMOS驅動器10構成的反相器被一輸出自一 内部電路16的信號所驅動。 另外，該I/O電路1亦設有一具有一連接至一外部電源 VDE的源極與一連接至另一反相輸出端XQ之PM0S電晶體 17，一具有一連接至該地電位VSS之源極、一連接至該 20 PM0S電晶體17之汲極、及一當作一反相輸入端XA的閘極 之NMOS電晶體18，一具有一連接至該外部電源VDE之源 極及一連接至一個輸入端Q之閘極的PM0S電晶體19，及一 具有一連接至該地電位VSS之源極、一連接至該PM0S電晶 體19之汲極的汲極 '及一當作一輸入端A之閘極的NMOS電 9 13602975, as illustrated, the first NMOS driver 10 and the second NMOS driver 11 are each surrounded by a protective layer 34 that reduces electrical interference through a body layer, thereby making it possible to increase the ESd resistance. Voltage. Returning to Fig. 1, the I/O circuit 1 is provided with an NMOS transistor 12 having a gate connected to the VSS and a germanide block 13 connected in series with the NMOS transistor 12. Make an ESD protection circuit. The I/O circuit 1 is also provided with a pm 〇S transistor 14 having a gate connected to an external power source VDE, and a PMOS transistor 15 forming an inverter together with the first NMOS driver 10, Make an ESD protection circuit. The inverter constituted by the PMOS transistor 15 and the first NMOS driver 10 is driven by a signal output from an internal circuit 16. In addition, the I/O circuit 1 is also provided with a PMOS transistor 17 having a source connected to an external power source VDE and a NMOS transistor 17 connected to another inverting output terminal XQ, one having a source connected to the ground potential VSS. a NMOS transistor 18 connected to the gate of the 20 PM0S transistor 17 and a gate as an inverting input terminal XA, one having a source connected to the external power supply VDE and one connected to a PMOS transistor 19 having a gate of the input terminal Q, and a drain having a source connected to the ground potential VSS, a drain connected to the drain of the PMOS transistor 19, and an input terminal A The gate of the NMOS electric 9 1360297

晶體20。該PMOS電晶體17、NMOS電晶體18、PM〇s, B 曰曰 體19及NMOS電晶體20當作一適於將—内部電源vdi的一 信號位準轉變至該外部電源VDE的一信號位準之位準轉換 器。同樣地，該I/O電路1包含有一具有一連接至一反相輪 5入端XQ之閘極 '一連接至一輸入端Q之汲極及一連接至該 地電位VSS之源極的NM0S電晶體26。該位準轉換器之輪出 端Q與該第二NM0S驅動器11之閘極端c被連接。 該I / 0電路1係更設有構成一被該内部電源V DI所驅動 之反相器的一PM0S電晶體21及一NM0S電晶體22，及構成 10 一由該内部電源VDI所驅動之反相器的一pm〇S電晶體23 及一NM0S電晶體24。構成該反相器之該PM0S電晶體23與 該NM0S電晶體24接收一控制該第二NM0S驅動器11的閘 極端C之控制信號CNT。 當使用一正極，至該I/O墊32的ESD被摧毀時，利用設 15 定為一基礎之VSS，一電壓亦從一寄生二極體14Di，經由 該PM0S電晶體14的一汲極14D與該I/O墊32、及該PM0S電 晶體14的一背閘極14BG與該寄生二極體14Di，被施加至該 外部電源。 由該PMOS電晶體21與該NM0S電晶體22組成的反相 20 器之輸出與由該PM0S電晶體23與該NM0S電晶體24組成 的反相器之輸出係在一寄生電容被放電的之狀態，並且因 此，該等輸出是一地電位。於是，該位準轉換器之該輸入 端A與該反相輸入端XA二者接收一地電位。在該位準轉換 器中，為了一ESD測試電壓被施加前，該輸出端Q與該反相 10 1360297 輸出端XQ是在一地電位’然而’當為了一 ESD測試一電壓 被施加時，該PMOS電晶體17與該PM0S電晶體19變成導通 的並且在該輸出端Q與該反相輸出端又卩的該等電位被提 升。若該反相輸出端XQ的電位超過該NMOS電晶體26的一 5門檻電壓，則該NM〇S電晶體26係成為導通的。當該NM〇s 電晶體26係成為導通時，該輸出端q與該閘極端c的信號位 準變成一地電位。結果，該PMOS電晶體19變成完全導通， 且該反相輸出端XQ之位準轉移至一 “H”位準。結果，該 PMOS電晶體17變成不導通，且該反相輸出端Xq被維持在 10 Η位準，而s亥輸出端Q被維持在一地電位狀態（閂鎖操 作）。 接著，將給予在該ESD保護電路的一說明，其中該石夕 化物Q塊13與s亥NMOS電晶體12係串聯連接自該1/〇塾32。 第3圖是一顯示該ESD保護元件之結構的橫截面圖。因為連 15接至該1/0墊32之NMOS電晶體12的汲極通過該矽化物區塊 13，所以该NMOS電晶體12藉由一主體.係與該ι/Q塾32連 接。該NMOS電晶體12的汲極12D (η+)、該NMOS電晶體12 的主體(Ρ-)及該NMOS電晶體12之源極構成一寄生ΝΡΝ電 晶體12TR。該寄生ΝρΝ電晶體12111在一低電壓下不會變成 20 導通的’然而，當該I/O墊32之電位大概達到9V由於一漏電 流等時，它變成導通的。在其為一顯示該ESD保護電路之ι_ν 特性之特性圖的第4圖中，若該寄生ΝΡΝ電晶體12TR係做出 導通一次，則該電晶體回抓且該電壓下降至一保持電壓（大 概6V)’因此允許一對應隨後要飛升之電壓的大電流。藉由 11 1360297 比較，根據對於該機器模式之ESD抗電壓之該等標準，若 一上至3.0A之電流（由虛線所示）係能飛升，該抗電壓能被期 望變成等於或高於200V。 在根據本實施例之I/O電路1中，因為該第二NM〇s驅動 5器11之閘極端C，藉由一閂鎖操作，被保持在一地位準，所 以一由該第一NMOS驅動器10與該第：NM〇s驅動器以構 成的驅動器電路具有一等於或高於大概9V的一 ESD抗電 壓，且該ESD抗電壓能被維持於由該第—NM〇s驅動器1〇 與s亥第一 NMOS驅動器11構成之該串聯連接的驅動器電 10路，直到該ESD保護電路的寄生NPN電晶體12TR變成導通。 在本實施利之I/O電路1中，在該第二NM0S驅動器之閘 極端C的地位準被維持，不需用—電容器。因為不使用一電 容器，所以該I/O電路1的全部的佈局面，比起使用一電容 器的傳統電路，能被做成更精簡。 15 因為該傳統1/0電路100使用一大電容的電容器25，所 以從一地電位至一 “H”位準的轉移時間，甚至在該内部電 源VDI被連接與該閘極端c總被控制的情況下，是緩慢的。 然而，因為本實施例之I/O電路丨不使用一電容器，所以從 一地電位至一 Η位準的轉移操作能被快速完成。Crystal 20. The PMOS transistor 17, the NMOS transistor 18, the PM〇s, the B body 19 and the NMOS transistor 20 serve as a signal bit suitable for converting a signal level of the internal power source vdi to the external power source VDE. Quasi-level converter. Similarly, the I/O circuit 1 includes a gate having a gate connected to an input terminal XQ of the inverting wheel 5, a gate connected to an input terminal Q, and a NM0S connected to the source of the ground potential VSS. Transistor 26. The wheel terminal Q of the level shifter is connected to the gate terminal c of the second NMOS driver 11. The I / 0 circuit 1 is further provided with a PMOS transistor 21 and an NMOS transistor 22 constituting an inverter driven by the internal power supply V DI , and a composition 10 is driven by the internal power supply VDI. A pm 〇S transistor 23 and an NMOS transistor 24 of the phaser. The PMOS transistor 23 and the NMOS transistor 24 constituting the inverter receive a control signal CNT for controlling the gate terminal C of the second NMOS driver 11. When a positive electrode is used, when the ESD of the I/O pad 32 is destroyed, the VSS is set to a base VSS, and a voltage is also applied from a parasitic diode 14Di through a drain 14D of the PMOS transistor 14. The I/O pad 32, and a back gate 14BG of the PMOS transistor 14 and the parasitic diode 14Di are applied to the external power source. The output of the inverting 20 composed of the PMOS transistor 21 and the NMOS transistor 22 and the output of the inverter composed of the PMOS transistor 23 and the NMOS transistor 24 are discharged in a parasitic capacitance. And, therefore, the outputs are a ground potential. Thus, both the input terminal A of the level shifter and the inverting input terminal XA receive a ground potential. In the level converter, before an ESD test voltage is applied, the output terminal Q and the inverting 10 1360297 output terminal XQ are at a ground potential 'however' when a voltage is applied for an ESD test, The PMOS transistor 17 and the PMOS transistor 19 become conductive and the equipotential at the output terminal Q and the inverted output terminal are boosted. If the potential of the inverting output terminal XQ exceeds a threshold voltage of the NMOS transistor 26, the NM〇S transistor 26 is turned on. When the NM〇s transistor 26 is turned on, the signal level of the output terminal q and the gate terminal c becomes a ground potential. As a result, the PMOS transistor 19 becomes fully turned on, and the level of the inverted output terminal XQ shifts to an "H" level. As a result, the PMOS transistor 17 becomes non-conductive, and the inverted output terminal Xq is maintained at the 10 Η level, and the sigma output terminal Q is maintained at a ground potential state (latch operation). Next, an explanation will be given of the ESD protection circuit in which the lithium Q block 13 and the NMOS NMOS transistor 12 are connected in series from the 1/〇塾32. Figure 3 is a cross-sectional view showing the structure of the ESD protection element. Since the drain of the NMOS transistor 12 connected to the 1/0 pad 32 passes through the germanide block 13, the NMOS transistor 12 is connected to the ι/Q 塾 32 by a body. The drain 12D (n+) of the NMOS transistor 12, the body (Ρ-) of the NMOS transistor 12, and the source of the NMOS transistor 12 constitute a parasitic germanium transistor 12TR. The parasitic Ν Ν transistor 12111 does not become 20-conducted at a low voltage. However, when the potential of the I/O pad 32 reaches approximately 9 V due to a leakage current or the like, it becomes conductive. In FIG. 4, which is a characteristic diagram showing the characteristics of the ESD protection circuit of the ESD protection circuit, if the parasitic germanium transistor 12TR is turned on once, the transistor is grasped and the voltage is lowered to a holding voltage (probably 6V) 'So allows a large current corresponding to the voltage to be subsequently boosted. With the comparison of 11 1360297, according to these standards for the ESD voltage resistance of the machine mode, if the current up to 3.0A (shown by the dashed line) can fly, the anti-voltage can be expected to become equal to or higher than 200V. . In the I/O circuit 1 according to the present embodiment, since the second NM〇s drives the gate terminal C of the device 11, by a latch operation, it is held in a positional state, so that the first NMOS is The driver 10 and the first:NM〇s driver form a driver circuit having an ESD voltage equal to or higher than approximately 9V, and the ESD voltage can be maintained by the first NM〇s driver 1〇 and s The first NMOS driver 11 is configured to electrically connect the serially connected drivers until the parasitic NPN transistor 12TR of the ESD protection circuit becomes conductive. In the I/O circuit 1 of the present embodiment, the position of the gate terminal C of the second NMOS driver is maintained, and no capacitor is required. Since a capacitor is not used, the entire layout of the I/O circuit 1 can be made more compact than the conventional circuit using a capacitor. 15 Since the conventional 1/0 circuit 100 uses a capacitor 25 of a large capacitance, the transition time from a ground potential to an "H" level, even when the internal power supply VDI is connected and the gate terminal c is always controlled In the case, it is slow. However, since the I/O circuit of the present embodiment does not use a capacitor, the transfer operation from a ground potential to a level can be quickly completed.

20 在該傳統1/0電路1中一電容器25被用來將該閘極端C 保持在一地電位。於是，發生一問題係該電容器經由該導 致在電位上增加的PMOS電晶體17被充電晶體。相反於此， 在本實施例之I/O電路1中，該地電位，經由該閂鎖操作， 被維持’其消除了在該閘極端C之電位上升的危險。 12 1360297 本揭露並不限於上述實施例，並且不用說，其不同改 良與修改在不離開該揭露之範圍下能被執行。 舉例說’雖然給予了該具有一個階段結構之第— NMOS驅動器1〇之輸出是一反相器的情況之本實施例的說 5明，可是具有相同如該第一NMOS驅動器10之多數個驅動 器可被串聯連接。舉例說，若該輸出驅動器具 結構’則一具有相同如該第一NMOS驅動器10之結構的電 晶體可是一個階段串聯連接。 雖然本實施例中該輸入端A與該反相輸入端X A係經由 10該兩個反相器被控制’一個係由該PMOS電晶體21與該 NMOS電晶體22構成，且另一個係由該pm〇S電晶體23與該 NMOS電晶體24構成，該PMOS電晶體21與該NMOS電晶體 22可被除去以使得該輸入端a可直接被一未示的控制信號 所控制。 15 該NMOS電晶體26當作一第一NMOS電晶體的一個範 例，該NMOS電晶體12當作一第二NMOS電晶體的一個範 例，該PMOS電晶體14當作一第一PMOS電晶體的一個範 例’且該PMOS電晶體15當作一第二PMOS電晶體的一個範 例。同樣地，該PMOS電晶體17當作一第三PMOS電晶體的 20 一個範例，該PMOS電晶體19當作一第四電晶體的一個範 例，該NMOS電晶體18當作一第三NMOS電晶體的一個範 例，且該NMOS電晶體20當作一第四NMOS電晶體的一個範 例。另外，該PMOS電晶體21與該NMOS電晶體22當作一第 一反相器的一個範例，且該PMOS電晶體23與該NMOS電晶 13 1360297 體24當作一第二反相器的一個範例。 在本實施例中’當ESD被施加至一塾時，一位準轉換 器的輸出被設定至一中點電位。結果’該第一NMOS電晶 體係成為導通，且該第二NMOS驅動器的閘極被設定至一 5 地電位。於是，是有可能防止因施加ESD至該第一NMOS 驅動器與該第二NMOS驅動器之該等墊所導致的崩潰。 根據本揭露，是有可能提供一種包含有串聯連接的 NMOS驅動器之I/O電路，其中在該地側的該等NMOS驅動 器具有一區域，在該地側至該等NMOS驅動器的一主動狀 10 態之轉移時間是短的，且在該地側的該等NMOS驅動器之 閘極電壓被可靠地保持在一地電位。 【阖式簡單説明】 第1圖是一顯示根據本實施例的一種I/O電路結構之電 路圖； 15 第2圖是一顯示在一 ESD測試電壓被施加至一 I/O墊之 情況下的PM0SESD保護元件的橫截面圖； 第3圖是一顯示該ESD保護元件之結構的橫截面圖； 第4圖是一顯示該ESD保護元件之i_v特性的特性圖； 第5圖是一顯示在一串聯結構中NM〇S驅動器的一結 20 構之佈局圖； 第6圖疋—顯示在具有不同結構之驅動器電路之連接 的電路圖； 第7圖是一顯示該等具有不同結構之驅動器電路的 ESD耐電壓特性之特性圖；及 14 1360297 第8圖是一顯示一傳統I/O電路之結構的電路圖 【主要元件符號說明】 1...I/O 電路 24... NMOS電晶體 10…第一NMOS驅動器 25...電容器 11...第二NMOS驅動器 26... NMOS電晶體 12...NMOS電晶體 31...VDE 12D···汲極 32·· .1/0 墊 12TR...寄生NPN電晶體 33...VSS 34…保護環 13...矽化物區塊 100…傳統I/O電路 14...PMOS電晶體 201-204…驅動器電路 14D···汲極 C. · 閘極端 14Di...寄生二極體 A，Q...輸入端 14BG…背閘極 XQ...反相輸出端 15...PMOS電晶體 XA··.反相輸入端 16...内部電路 VSS...地電位 17...PM0S電晶體 VDE...外部電源 18... NMOS電晶體 VDI...内部電源 19...PMOS電晶體 CNT...控制信號 20...NMOS電晶體 23...PMOS電晶體 1520 In this conventional 1/0 circuit 1, a capacitor 25 is used to maintain the gate terminal C at a ground potential. Thus, a problem occurs in that the capacitor is charged to the crystal via the PMOS transistor 17 which causes the potential to increase. On the contrary, in the I/O circuit 1 of the present embodiment, the ground potential is maintained by the latch operation, which eliminates the risk of the potential rising at the gate terminal C. 12 1360297 The present disclosure is not limited to the above embodiments, and it is needless to say that different modifications and modifications can be performed without departing from the scope of the disclosure. For example, although the embodiment in which the output of the NMOS driver 1 is an inverter is given, the plurality of drivers having the same as the first NMOS driver 10 are provided. Can be connected in series. For example, if the output driver structure is, then a transistor having the same structure as the first NMOS driver 10 may be connected in series in one stage. In this embodiment, the input terminal A and the inverting input terminal XA are controlled via the two inverters. One is composed of the PMOS transistor 21 and the NMOS transistor 22, and the other is composed of The pm〇S transistor 23 is formed with the NMOS transistor 24, and the PMOS transistor 21 and the NMOS transistor 22 can be removed such that the input terminal a can be directly controlled by an unillustrated control signal. The NMOS transistor 26 is taken as an example of a first NMOS transistor. The NMOS transistor 12 is an example of a second NMOS transistor. The PMOS transistor 14 is regarded as a first PMOS transistor. The example 'and the PMOS transistor 15 serves as an example of a second PMOS transistor. Similarly, the PMOS transistor 17 is taken as an example of a third PMOS transistor 19, which is taken as an example of a fourth transistor, and the NMOS transistor 18 is regarded as a third NMOS transistor. An example of this, and the NMOS transistor 20 serves as an example of a fourth NMOS transistor. In addition, the PMOS transistor 21 and the NMOS transistor 22 are regarded as an example of a first inverter, and the PMOS transistor 23 and the NMOS transistor 13 1360297 body 24 are regarded as one of a second inverter. example. In the present embodiment, when the ESD is applied to one turn, the output of the one-bit converter is set to a midpoint potential. As a result, the first NMOS transistor system is turned on, and the gate of the second NMOS driver is set to a ground potential. Thus, it is possible to prevent the collapse caused by the application of ESD to the pads of the first NMOS driver and the second NMOS driver. According to the present disclosure, it is possible to provide an I/O circuit including an NMOS driver connected in series, wherein the NMOS drivers on the ground side have an area on the ground side to an active 10 of the NMOS drivers The transition time of the states is short, and the gate voltages of the NMOS drivers on the ground side are reliably maintained at a ground potential. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing an I/O circuit structure according to the present embodiment; 15 FIG. 2 is a view showing an case where an ESD test voltage is applied to an I/O pad. A cross-sectional view of the PM0SESD protection element; Fig. 3 is a cross-sectional view showing the structure of the ESD protection element; Fig. 4 is a characteristic diagram showing the i_v characteristic of the ESD protection element; A layout diagram of a junction 20 of a NM〇S driver in a series configuration; FIG. 6 is a circuit diagram showing connections of driver circuits having different structures; and FIG. 7 is an ESD showing driver circuits having different structures. Characteristic diagram of withstand voltage characteristics; and 14 1360297 Fig. 8 is a circuit diagram showing the structure of a conventional I/O circuit [Major component symbol description] 1...I/O circuit 24... NMOS transistor 10... An NMOS driver 25...capacitor 11...second NMOS driver 26... NMOS transistor 12...NMOS transistor 31...VDE 12D···汲32·· .1/0 pad 12TR ...parasitic NPN transistor 33...VSS 34...protection ring 13...halide block 100...traditional I/ O circuit 14... PMOS transistor 201-204... driver circuit 14D··· drain C. · Gate terminal 14Di... Parasitic diode A, Q... Input terminal 14BG... Back gate XQ.. Inverting output terminal 15... PMOS transistor XA··. Inverting input terminal 16... Internal circuit VSS... Ground potential 17...PM0S transistor VDE... External power supply 18... NMOS Transistor VDI...Internal power supply 19...PMOS transistor CNT...Control signal 20...NMOS transistor 23...PMOS transistor 15

Claims (1)

1360297 第097105883號申請案申請專利範圍替換本 1(^.1^25日修正本 十、申請專利範圍： -：一- 1. 一種輸入/輸出電路，包含有： 一第一 η通道金氧半導體(NMOS)驅動器，其具有一 連接至一輸入/輸出墊的汲極； 5 一第二NMOS驅動器，其被佈局在一不同於該第一 NMOS驅動器的主動區中，該第二NMOS驅動器具有一 連接至該第一 NMOS驅動器之源極的汲極以及一連接至 I 一地電位的源極； 一具有一閂鎖結構之位準轉換器，該位準轉換器係適 10 於接收在一與一電源電位分開之内部電源電位下被驅動 的一第一控制信號及一互補於該第一控制信號的信號， 並將該第一控制信號與該互補於該第一控制信號之信號 轉換成與該第一控制信號同相位且在該電源電位下被驅 動的一第二控制信號及一互補於該第二控制信號的信 15 號；及 一第一 NMOS電晶體，其具有一連接至該位準轉換 器的一輸出端的汲極，該第二控制信號係輸出自該位準 轉換器之該輸出端、一連接至該地電位的源極、及一連 接至該位準轉換器中該互補於該第二控制信號之信號的 20 一輸出端的閘極； 其中該第一 NMOS電晶體之汲極被連接至該第二 NMOS驅動器的一閘極。 2. 如申請專利範圍第1項所述之輸入/輸出電路，更包含有 一配置在該輸入/輸出墊與該地電位之間的靜電放電 16 1360297 第097105883號申請案申請專利範圍替換本 100.10.25 (ESD)保護電路。 3.如申請專利範圍第2項所述之輸入/輸出電路，其中該 ESD保護電路係由串聯連接的一矽化物區塊與一第二 NMOS電晶體形成。 5 4.如申請專利範圍第1項所述之輸入/輸出電路，更包含有 一具有一連接至該輸入/輸出墊之汲極與一連接至該電源 電位之源極及閘極的第一 p通道金氧半導體(PMOS)電晶 體。 5. 如申請專利範圍第1項所述之輸入/輸出電路，更包含有： 10 一第二PMOS電晶體，其具有一連接至該輸入/輸出 墊之汲極、一連接至該電源電位之源極、及一連接至該 第一 NMOS驅動器之閘極的閘極，並且其中該第一 NMOS驅動器係由一 NMOS電晶體構成。 6. 如申請專利範圍第1項所述之輸入/輸出電路，其中該第 15 一 NMOS驅動器的一佈局與該第二NMOS驅動器的一佈 局二者被一背閘極的一防護環所包圍。 7. 如申請專利範圍第1項所述之輸入/輸出電路，其中該位 準轉換器更包含有： 一第三NMOS電晶體，其具有一連接至該第二控制 20 信號的一輸出端之汲極、一連接至該地電位的源極、及 一連接至該第一 NMOS驅動器中該互補於該第一控制信 號之信號的一輸入端之閘極； 一第四NMOS電晶體，其具有一連接至該互補於該 第二控制信號之信號的該輸出端之汲極、一連接至該地 17 1360297 第097105883號申請案申請專利範圍替換本 100.10. 25 電位的源極、及一連接至該第一 NMOS驅動器中該第一 控制信號的一輸入端之閘極； 一第三PMOS電晶體，其具有一連接至該第二控制 信號的該輸出端之汲極、一連接至該電源電位的源極、 5 及一連接至該互補於該第二控制信號之信號的該輸出端 之閘極；及 一第四PMOS電晶體，其具有一連接至該互補於該 第二控制信號之信號的該輸出端之汲極、一連接至該電 源電位的源極、及一連接至該第二控制信號的該輸出端 10 之閘極。 8.如申請專利範圍第1項所述之輸入/輸出電路，更包含有： 一第一反相器，其被驅動在該内部電源電位，該第一 反相器具有一連接至該位準轉換器中該第一控制信號的 一輸入端之輸出端；及 15 —第二反相器，其被驅動在該内部電源電位，該第二 反相器具有一連接至該位準轉換器中該互補於該第一控 制信號之信號的一輸入端與該第一反相器的一輸入端之 輸出端。 181360297 Application No. 097105883 Application for Patent Replacing This Part 1 (^.1^25 Revision Amendment 10, Patent Application Range: -: 1 - 1. An input/output circuit comprising: a first n-channel MOS An (NMOS) driver having a drain connected to an input/output pad; 5 a second NMOS driver disposed in an active region different from the first NMOS driver, the second NMOS driver having a a drain connected to a source of the first NMOS driver and a source connected to a ground potential; a level converter having a latch structure adapted to receive a a first control signal driven by an internal power supply potential separated by a power supply potential and a signal complementary to the first control signal, and converting the first control signal and the signal complementary to the first control signal into a second control signal that is in phase and driven at the power supply potential and a signal 15 that is complementary to the second control signal; and a first NMOS transistor having a connection to the a drain of an output of the level converter, the second control signal being output from the output of the level converter, a source connected to the ground potential, and a connection to the level converter a gate complementary to a signal of the signal of the second control signal; wherein a drain of the first NMOS transistor is connected to a gate of the second NMOS driver. 2. According to claim 1 The input/output circuit further includes an electrostatic discharge disposed between the input/output pad and the ground potential. 16 1360297 Application No. 097105883 The patent application scope replaces the 100.10.25 (ESD) protection circuit. The input/output circuit of claim 2, wherein the ESD protection circuit is formed by a germanide block connected in series and a second NMOS transistor. 5 4. As described in claim 1 The input/output circuit further includes a first p-channel metal oxide semiconductor (PMOS) transistor having a drain connected to the input/output pad and a source and a gate connected to the power supply potential. If you apply for a special The input/output circuit of claim 1, further comprising: a second PMOS transistor having a drain connected to the input/output pad, a source connected to the power supply potential, and a a gate connected to a gate of the first NMOS driver, and wherein the first NMOS driver is formed by an NMOS transistor. 6. The input/output circuit of claim 1, wherein the 15th Both a layout of an NMOS driver and a layout of the second NMOS driver are surrounded by a guard ring of a back gate. 7. The input/output circuit of claim 1, wherein the level converter further comprises: a third NMOS transistor having an output connected to the second control 20 signal a drain, a source connected to the ground potential, and a gate connected to an input of the first NMOS driver complementary to the signal of the first control signal; a fourth NMOS transistor having a source connected to the output of the signal complementary to the second control signal, a source connected to the ground, and the source of the application of the 100.10.25 potential, and a connection to a gate of an input terminal of the first control signal in the first NMOS driver; a third PMOS transistor having a drain connected to the output terminal of the second control signal, and a connection to the power supply potential a source, a gate connected to the output terminal of the signal complementary to the second control signal; and a fourth PMOS transistor having a signal coupled to the second control signal The A drain of the output terminal, a source coupled to the power supply potential, and a gate coupled to the output terminal 10 of the second control signal. 8. The input/output circuit of claim 1, further comprising: a first inverter driven at the internal power supply potential, the first inverter having a connection to the level conversion An output of an input of the first control signal; and 15 - a second inverter driven at the internal power supply potential, the second inverter having a complementary connection to the level converter An input of the signal of the first control signal and an output of an input of the first inverter. 18
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